lpfc_sli.c 84 KB

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  1. /*******************************************************************
  2. * This file is part of the Emulex Linux Device Driver for *
  3. * Fibre Channel Host Bus Adapters. *
  4. * Copyright (C) 2004-2006 Emulex. All rights reserved. *
  5. * EMULEX and SLI are trademarks of Emulex. *
  6. * www.emulex.com *
  7. * Portions Copyright (C) 2004-2005 Christoph Hellwig *
  8. * *
  9. * This program is free software; you can redistribute it and/or *
  10. * modify it under the terms of version 2 of the GNU General *
  11. * Public License as published by the Free Software Foundation. *
  12. * This program is distributed in the hope that it will be useful. *
  13. * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
  14. * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
  15. * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
  16. * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
  17. * TO BE LEGALLY INVALID. See the GNU General Public License for *
  18. * more details, a copy of which can be found in the file COPYING *
  19. * included with this package. *
  20. *******************************************************************/
  21. #include <linux/blkdev.h>
  22. #include <linux/pci.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/delay.h>
  25. #include <scsi/scsi.h>
  26. #include <scsi/scsi_cmnd.h>
  27. #include <scsi/scsi_device.h>
  28. #include <scsi/scsi_host.h>
  29. #include <scsi/scsi_transport_fc.h>
  30. #include "lpfc_hw.h"
  31. #include "lpfc_sli.h"
  32. #include "lpfc_disc.h"
  33. #include "lpfc_scsi.h"
  34. #include "lpfc.h"
  35. #include "lpfc_crtn.h"
  36. #include "lpfc_logmsg.h"
  37. #include "lpfc_compat.h"
  38. /*
  39. * Define macro to log: Mailbox command x%x cannot issue Data
  40. * This allows multiple uses of lpfc_msgBlk0311
  41. * w/o perturbing log msg utility.
  42. */
  43. #define LOG_MBOX_CANNOT_ISSUE_DATA( phba, mb, psli, flag) \
  44. lpfc_printf_log(phba, \
  45. KERN_INFO, \
  46. LOG_MBOX | LOG_SLI, \
  47. "%d:0311 Mailbox command x%x cannot issue " \
  48. "Data: x%x x%x x%x\n", \
  49. phba->brd_no, \
  50. mb->mbxCommand, \
  51. phba->hba_state, \
  52. psli->sli_flag, \
  53. flag);
  54. /* There are only four IOCB completion types. */
  55. typedef enum _lpfc_iocb_type {
  56. LPFC_UNKNOWN_IOCB,
  57. LPFC_UNSOL_IOCB,
  58. LPFC_SOL_IOCB,
  59. LPFC_ABORT_IOCB
  60. } lpfc_iocb_type;
  61. struct lpfc_iocbq *
  62. lpfc_sli_get_iocbq(struct lpfc_hba * phba)
  63. {
  64. struct list_head *lpfc_iocb_list = &phba->lpfc_iocb_list;
  65. struct lpfc_iocbq * iocbq = NULL;
  66. list_remove_head(lpfc_iocb_list, iocbq, struct lpfc_iocbq, list);
  67. return iocbq;
  68. }
  69. void
  70. lpfc_sli_release_iocbq(struct lpfc_hba * phba, struct lpfc_iocbq * iocbq)
  71. {
  72. size_t start_clean = (size_t)(&((struct lpfc_iocbq *)NULL)->iocb);
  73. /*
  74. * Clean all volatile data fields, preserve iotag and node struct.
  75. */
  76. memset((char*)iocbq + start_clean, 0, sizeof(*iocbq) - start_clean);
  77. list_add_tail(&iocbq->list, &phba->lpfc_iocb_list);
  78. }
  79. /*
  80. * Translate the iocb command to an iocb command type used to decide the final
  81. * disposition of each completed IOCB.
  82. */
  83. static lpfc_iocb_type
  84. lpfc_sli_iocb_cmd_type(uint8_t iocb_cmnd)
  85. {
  86. lpfc_iocb_type type = LPFC_UNKNOWN_IOCB;
  87. if (iocb_cmnd > CMD_MAX_IOCB_CMD)
  88. return 0;
  89. switch (iocb_cmnd) {
  90. case CMD_XMIT_SEQUENCE_CR:
  91. case CMD_XMIT_SEQUENCE_CX:
  92. case CMD_XMIT_BCAST_CN:
  93. case CMD_XMIT_BCAST_CX:
  94. case CMD_ELS_REQUEST_CR:
  95. case CMD_ELS_REQUEST_CX:
  96. case CMD_CREATE_XRI_CR:
  97. case CMD_CREATE_XRI_CX:
  98. case CMD_GET_RPI_CN:
  99. case CMD_XMIT_ELS_RSP_CX:
  100. case CMD_GET_RPI_CR:
  101. case CMD_FCP_IWRITE_CR:
  102. case CMD_FCP_IWRITE_CX:
  103. case CMD_FCP_IREAD_CR:
  104. case CMD_FCP_IREAD_CX:
  105. case CMD_FCP_ICMND_CR:
  106. case CMD_FCP_ICMND_CX:
  107. case CMD_FCP_TSEND_CX:
  108. case CMD_FCP_TRSP_CX:
  109. case CMD_FCP_TRECEIVE_CX:
  110. case CMD_FCP_AUTO_TRSP_CX:
  111. case CMD_ADAPTER_MSG:
  112. case CMD_ADAPTER_DUMP:
  113. case CMD_XMIT_SEQUENCE64_CR:
  114. case CMD_XMIT_SEQUENCE64_CX:
  115. case CMD_XMIT_BCAST64_CN:
  116. case CMD_XMIT_BCAST64_CX:
  117. case CMD_ELS_REQUEST64_CR:
  118. case CMD_ELS_REQUEST64_CX:
  119. case CMD_FCP_IWRITE64_CR:
  120. case CMD_FCP_IWRITE64_CX:
  121. case CMD_FCP_IREAD64_CR:
  122. case CMD_FCP_IREAD64_CX:
  123. case CMD_FCP_ICMND64_CR:
  124. case CMD_FCP_ICMND64_CX:
  125. case CMD_FCP_TSEND64_CX:
  126. case CMD_FCP_TRSP64_CX:
  127. case CMD_FCP_TRECEIVE64_CX:
  128. case CMD_GEN_REQUEST64_CR:
  129. case CMD_GEN_REQUEST64_CX:
  130. case CMD_XMIT_ELS_RSP64_CX:
  131. type = LPFC_SOL_IOCB;
  132. break;
  133. case CMD_ABORT_XRI_CN:
  134. case CMD_ABORT_XRI_CX:
  135. case CMD_CLOSE_XRI_CN:
  136. case CMD_CLOSE_XRI_CX:
  137. case CMD_XRI_ABORTED_CX:
  138. case CMD_ABORT_MXRI64_CN:
  139. type = LPFC_ABORT_IOCB;
  140. break;
  141. case CMD_RCV_SEQUENCE_CX:
  142. case CMD_RCV_ELS_REQ_CX:
  143. case CMD_RCV_SEQUENCE64_CX:
  144. case CMD_RCV_ELS_REQ64_CX:
  145. type = LPFC_UNSOL_IOCB;
  146. break;
  147. default:
  148. type = LPFC_UNKNOWN_IOCB;
  149. break;
  150. }
  151. return type;
  152. }
  153. static int
  154. lpfc_sli_ring_map(struct lpfc_hba * phba, LPFC_MBOXQ_t *pmb)
  155. {
  156. struct lpfc_sli *psli = &phba->sli;
  157. MAILBOX_t *pmbox = &pmb->mb;
  158. int i, rc;
  159. for (i = 0; i < psli->num_rings; i++) {
  160. phba->hba_state = LPFC_INIT_MBX_CMDS;
  161. lpfc_config_ring(phba, i, pmb);
  162. rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
  163. if (rc != MBX_SUCCESS) {
  164. lpfc_printf_log(phba,
  165. KERN_ERR,
  166. LOG_INIT,
  167. "%d:0446 Adapter failed to init, "
  168. "mbxCmd x%x CFG_RING, mbxStatus x%x, "
  169. "ring %d\n",
  170. phba->brd_no,
  171. pmbox->mbxCommand,
  172. pmbox->mbxStatus,
  173. i);
  174. phba->hba_state = LPFC_HBA_ERROR;
  175. return -ENXIO;
  176. }
  177. }
  178. return 0;
  179. }
  180. static int
  181. lpfc_sli_ringtxcmpl_put(struct lpfc_hba * phba,
  182. struct lpfc_sli_ring * pring, struct lpfc_iocbq * piocb)
  183. {
  184. list_add_tail(&piocb->list, &pring->txcmplq);
  185. pring->txcmplq_cnt++;
  186. if (unlikely(pring->ringno == LPFC_ELS_RING))
  187. mod_timer(&phba->els_tmofunc,
  188. jiffies + HZ * (phba->fc_ratov << 1));
  189. return (0);
  190. }
  191. static struct lpfc_iocbq *
  192. lpfc_sli_ringtx_get(struct lpfc_hba * phba, struct lpfc_sli_ring * pring)
  193. {
  194. struct list_head *dlp;
  195. struct lpfc_iocbq *cmd_iocb;
  196. dlp = &pring->txq;
  197. cmd_iocb = NULL;
  198. list_remove_head((&pring->txq), cmd_iocb,
  199. struct lpfc_iocbq,
  200. list);
  201. if (cmd_iocb) {
  202. /* If the first ptr is not equal to the list header,
  203. * deque the IOCBQ_t and return it.
  204. */
  205. pring->txq_cnt--;
  206. }
  207. return (cmd_iocb);
  208. }
  209. static IOCB_t *
  210. lpfc_sli_next_iocb_slot (struct lpfc_hba *phba, struct lpfc_sli_ring *pring)
  211. {
  212. struct lpfc_pgp *pgp = &phba->slim2p->mbx.us.s2.port[pring->ringno];
  213. uint32_t max_cmd_idx = pring->numCiocb;
  214. IOCB_t *iocb = NULL;
  215. if ((pring->next_cmdidx == pring->cmdidx) &&
  216. (++pring->next_cmdidx >= max_cmd_idx))
  217. pring->next_cmdidx = 0;
  218. if (unlikely(pring->local_getidx == pring->next_cmdidx)) {
  219. pring->local_getidx = le32_to_cpu(pgp->cmdGetInx);
  220. if (unlikely(pring->local_getidx >= max_cmd_idx)) {
  221. lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
  222. "%d:0315 Ring %d issue: portCmdGet %d "
  223. "is bigger then cmd ring %d\n",
  224. phba->brd_no, pring->ringno,
  225. pring->local_getidx, max_cmd_idx);
  226. phba->hba_state = LPFC_HBA_ERROR;
  227. /*
  228. * All error attention handlers are posted to
  229. * worker thread
  230. */
  231. phba->work_ha |= HA_ERATT;
  232. phba->work_hs = HS_FFER3;
  233. if (phba->work_wait)
  234. wake_up(phba->work_wait);
  235. return NULL;
  236. }
  237. if (pring->local_getidx == pring->next_cmdidx)
  238. return NULL;
  239. }
  240. iocb = IOCB_ENTRY(pring->cmdringaddr, pring->cmdidx);
  241. return iocb;
  242. }
  243. uint16_t
  244. lpfc_sli_next_iotag(struct lpfc_hba * phba, struct lpfc_iocbq * iocbq)
  245. {
  246. struct lpfc_iocbq ** new_arr;
  247. struct lpfc_iocbq ** old_arr;
  248. size_t new_len;
  249. struct lpfc_sli *psli = &phba->sli;
  250. uint16_t iotag;
  251. spin_lock_irq(phba->host->host_lock);
  252. iotag = psli->last_iotag;
  253. if(++iotag < psli->iocbq_lookup_len) {
  254. psli->last_iotag = iotag;
  255. psli->iocbq_lookup[iotag] = iocbq;
  256. spin_unlock_irq(phba->host->host_lock);
  257. iocbq->iotag = iotag;
  258. return iotag;
  259. }
  260. else if (psli->iocbq_lookup_len < (0xffff
  261. - LPFC_IOCBQ_LOOKUP_INCREMENT)) {
  262. new_len = psli->iocbq_lookup_len + LPFC_IOCBQ_LOOKUP_INCREMENT;
  263. spin_unlock_irq(phba->host->host_lock);
  264. new_arr = kmalloc(new_len * sizeof (struct lpfc_iocbq *),
  265. GFP_KERNEL);
  266. if (new_arr) {
  267. memset((char *)new_arr, 0,
  268. new_len * sizeof (struct lpfc_iocbq *));
  269. spin_lock_irq(phba->host->host_lock);
  270. old_arr = psli->iocbq_lookup;
  271. if (new_len <= psli->iocbq_lookup_len) {
  272. /* highly unprobable case */
  273. kfree(new_arr);
  274. iotag = psli->last_iotag;
  275. if(++iotag < psli->iocbq_lookup_len) {
  276. psli->last_iotag = iotag;
  277. psli->iocbq_lookup[iotag] = iocbq;
  278. spin_unlock_irq(phba->host->host_lock);
  279. iocbq->iotag = iotag;
  280. return iotag;
  281. }
  282. spin_unlock_irq(phba->host->host_lock);
  283. return 0;
  284. }
  285. if (psli->iocbq_lookup)
  286. memcpy(new_arr, old_arr,
  287. ((psli->last_iotag + 1) *
  288. sizeof (struct lpfc_iocbq *)));
  289. psli->iocbq_lookup = new_arr;
  290. psli->iocbq_lookup_len = new_len;
  291. psli->last_iotag = iotag;
  292. psli->iocbq_lookup[iotag] = iocbq;
  293. spin_unlock_irq(phba->host->host_lock);
  294. iocbq->iotag = iotag;
  295. kfree(old_arr);
  296. return iotag;
  297. }
  298. } else
  299. spin_unlock_irq(phba->host->host_lock);
  300. lpfc_printf_log(phba, KERN_ERR,LOG_SLI,
  301. "%d:0318 Failed to allocate IOTAG.last IOTAG is %d\n",
  302. phba->brd_no, psli->last_iotag);
  303. return 0;
  304. }
  305. static void
  306. lpfc_sli_submit_iocb(struct lpfc_hba *phba, struct lpfc_sli_ring *pring,
  307. IOCB_t *iocb, struct lpfc_iocbq *nextiocb)
  308. {
  309. /*
  310. * Set up an iotag
  311. */
  312. nextiocb->iocb.ulpIoTag = (nextiocb->iocb_cmpl) ? nextiocb->iotag : 0;
  313. /*
  314. * Issue iocb command to adapter
  315. */
  316. lpfc_sli_pcimem_bcopy(&nextiocb->iocb, iocb, sizeof (IOCB_t));
  317. wmb();
  318. pring->stats.iocb_cmd++;
  319. /*
  320. * If there is no completion routine to call, we can release the
  321. * IOCB buffer back right now. For IOCBs, like QUE_RING_BUF,
  322. * that have no rsp ring completion, iocb_cmpl MUST be NULL.
  323. */
  324. if (nextiocb->iocb_cmpl)
  325. lpfc_sli_ringtxcmpl_put(phba, pring, nextiocb);
  326. else
  327. lpfc_sli_release_iocbq(phba, nextiocb);
  328. /*
  329. * Let the HBA know what IOCB slot will be the next one the
  330. * driver will put a command into.
  331. */
  332. pring->cmdidx = pring->next_cmdidx;
  333. writel(pring->cmdidx, phba->MBslimaddr
  334. + (SLIMOFF + (pring->ringno * 2)) * 4);
  335. }
  336. static void
  337. lpfc_sli_update_full_ring(struct lpfc_hba * phba,
  338. struct lpfc_sli_ring *pring)
  339. {
  340. int ringno = pring->ringno;
  341. pring->flag |= LPFC_CALL_RING_AVAILABLE;
  342. wmb();
  343. /*
  344. * Set ring 'ringno' to SET R0CE_REQ in Chip Att register.
  345. * The HBA will tell us when an IOCB entry is available.
  346. */
  347. writel((CA_R0ATT|CA_R0CE_REQ) << (ringno*4), phba->CAregaddr);
  348. readl(phba->CAregaddr); /* flush */
  349. pring->stats.iocb_cmd_full++;
  350. }
  351. static void
  352. lpfc_sli_update_ring(struct lpfc_hba * phba,
  353. struct lpfc_sli_ring *pring)
  354. {
  355. int ringno = pring->ringno;
  356. /*
  357. * Tell the HBA that there is work to do in this ring.
  358. */
  359. wmb();
  360. writel(CA_R0ATT << (ringno * 4), phba->CAregaddr);
  361. readl(phba->CAregaddr); /* flush */
  362. }
  363. static void
  364. lpfc_sli_resume_iocb(struct lpfc_hba * phba, struct lpfc_sli_ring * pring)
  365. {
  366. IOCB_t *iocb;
  367. struct lpfc_iocbq *nextiocb;
  368. /*
  369. * Check to see if:
  370. * (a) there is anything on the txq to send
  371. * (b) link is up
  372. * (c) link attention events can be processed (fcp ring only)
  373. * (d) IOCB processing is not blocked by the outstanding mbox command.
  374. */
  375. if (pring->txq_cnt &&
  376. (phba->hba_state > LPFC_LINK_DOWN) &&
  377. (pring->ringno != phba->sli.fcp_ring ||
  378. phba->sli.sli_flag & LPFC_PROCESS_LA) &&
  379. !(pring->flag & LPFC_STOP_IOCB_MBX)) {
  380. while ((iocb = lpfc_sli_next_iocb_slot(phba, pring)) &&
  381. (nextiocb = lpfc_sli_ringtx_get(phba, pring)))
  382. lpfc_sli_submit_iocb(phba, pring, iocb, nextiocb);
  383. if (iocb)
  384. lpfc_sli_update_ring(phba, pring);
  385. else
  386. lpfc_sli_update_full_ring(phba, pring);
  387. }
  388. return;
  389. }
  390. /* lpfc_sli_turn_on_ring is only called by lpfc_sli_handle_mb_event below */
  391. static void
  392. lpfc_sli_turn_on_ring(struct lpfc_hba * phba, int ringno)
  393. {
  394. struct lpfc_pgp *pgp = &phba->slim2p->mbx.us.s2.port[ringno];
  395. /* If the ring is active, flag it */
  396. if (phba->sli.ring[ringno].cmdringaddr) {
  397. if (phba->sli.ring[ringno].flag & LPFC_STOP_IOCB_MBX) {
  398. phba->sli.ring[ringno].flag &= ~LPFC_STOP_IOCB_MBX;
  399. /*
  400. * Force update of the local copy of cmdGetInx
  401. */
  402. phba->sli.ring[ringno].local_getidx
  403. = le32_to_cpu(pgp->cmdGetInx);
  404. spin_lock_irq(phba->host->host_lock);
  405. lpfc_sli_resume_iocb(phba, &phba->sli.ring[ringno]);
  406. spin_unlock_irq(phba->host->host_lock);
  407. }
  408. }
  409. }
  410. static int
  411. lpfc_sli_chk_mbx_command(uint8_t mbxCommand)
  412. {
  413. uint8_t ret;
  414. switch (mbxCommand) {
  415. case MBX_LOAD_SM:
  416. case MBX_READ_NV:
  417. case MBX_WRITE_NV:
  418. case MBX_RUN_BIU_DIAG:
  419. case MBX_INIT_LINK:
  420. case MBX_DOWN_LINK:
  421. case MBX_CONFIG_LINK:
  422. case MBX_CONFIG_RING:
  423. case MBX_RESET_RING:
  424. case MBX_READ_CONFIG:
  425. case MBX_READ_RCONFIG:
  426. case MBX_READ_SPARM:
  427. case MBX_READ_STATUS:
  428. case MBX_READ_RPI:
  429. case MBX_READ_XRI:
  430. case MBX_READ_REV:
  431. case MBX_READ_LNK_STAT:
  432. case MBX_REG_LOGIN:
  433. case MBX_UNREG_LOGIN:
  434. case MBX_READ_LA:
  435. case MBX_CLEAR_LA:
  436. case MBX_DUMP_MEMORY:
  437. case MBX_DUMP_CONTEXT:
  438. case MBX_RUN_DIAGS:
  439. case MBX_RESTART:
  440. case MBX_UPDATE_CFG:
  441. case MBX_DOWN_LOAD:
  442. case MBX_DEL_LD_ENTRY:
  443. case MBX_RUN_PROGRAM:
  444. case MBX_SET_MASK:
  445. case MBX_SET_SLIM:
  446. case MBX_UNREG_D_ID:
  447. case MBX_KILL_BOARD:
  448. case MBX_CONFIG_FARP:
  449. case MBX_BEACON:
  450. case MBX_LOAD_AREA:
  451. case MBX_RUN_BIU_DIAG64:
  452. case MBX_CONFIG_PORT:
  453. case MBX_READ_SPARM64:
  454. case MBX_READ_RPI64:
  455. case MBX_REG_LOGIN64:
  456. case MBX_READ_LA64:
  457. case MBX_FLASH_WR_ULA:
  458. case MBX_SET_DEBUG:
  459. case MBX_LOAD_EXP_ROM:
  460. ret = mbxCommand;
  461. break;
  462. default:
  463. ret = MBX_SHUTDOWN;
  464. break;
  465. }
  466. return (ret);
  467. }
  468. static void
  469. lpfc_sli_wake_mbox_wait(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmboxq)
  470. {
  471. wait_queue_head_t *pdone_q;
  472. /*
  473. * If pdone_q is empty, the driver thread gave up waiting and
  474. * continued running.
  475. */
  476. pdone_q = (wait_queue_head_t *) pmboxq->context1;
  477. if (pdone_q)
  478. wake_up_interruptible(pdone_q);
  479. return;
  480. }
  481. void
  482. lpfc_sli_def_mbox_cmpl(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb)
  483. {
  484. struct lpfc_dmabuf *mp;
  485. mp = (struct lpfc_dmabuf *) (pmb->context1);
  486. if (mp) {
  487. lpfc_mbuf_free(phba, mp->virt, mp->phys);
  488. kfree(mp);
  489. }
  490. mempool_free( pmb, phba->mbox_mem_pool);
  491. return;
  492. }
  493. int
  494. lpfc_sli_handle_mb_event(struct lpfc_hba * phba)
  495. {
  496. MAILBOX_t *mbox;
  497. MAILBOX_t *pmbox;
  498. LPFC_MBOXQ_t *pmb;
  499. struct lpfc_sli *psli;
  500. int i, rc;
  501. uint32_t process_next;
  502. psli = &phba->sli;
  503. /* We should only get here if we are in SLI2 mode */
  504. if (!(phba->sli.sli_flag & LPFC_SLI2_ACTIVE)) {
  505. return (1);
  506. }
  507. phba->sli.slistat.mbox_event++;
  508. /* Get a Mailbox buffer to setup mailbox commands for callback */
  509. if ((pmb = phba->sli.mbox_active)) {
  510. pmbox = &pmb->mb;
  511. mbox = &phba->slim2p->mbx;
  512. /* First check out the status word */
  513. lpfc_sli_pcimem_bcopy(mbox, pmbox, sizeof (uint32_t));
  514. /* Sanity check to ensure the host owns the mailbox */
  515. if (pmbox->mbxOwner != OWN_HOST) {
  516. /* Lets try for a while */
  517. for (i = 0; i < 10240; i++) {
  518. /* First copy command data */
  519. lpfc_sli_pcimem_bcopy(mbox, pmbox,
  520. sizeof (uint32_t));
  521. if (pmbox->mbxOwner == OWN_HOST)
  522. goto mbout;
  523. }
  524. /* Stray Mailbox Interrupt, mbxCommand <cmd> mbxStatus
  525. <status> */
  526. lpfc_printf_log(phba,
  527. KERN_WARNING,
  528. LOG_MBOX | LOG_SLI,
  529. "%d:0304 Stray Mailbox Interrupt "
  530. "mbxCommand x%x mbxStatus x%x\n",
  531. phba->brd_no,
  532. pmbox->mbxCommand,
  533. pmbox->mbxStatus);
  534. spin_lock_irq(phba->host->host_lock);
  535. phba->sli.sli_flag |= LPFC_SLI_MBOX_ACTIVE;
  536. spin_unlock_irq(phba->host->host_lock);
  537. return (1);
  538. }
  539. mbout:
  540. del_timer_sync(&phba->sli.mbox_tmo);
  541. phba->work_hba_events &= ~WORKER_MBOX_TMO;
  542. /*
  543. * It is a fatal error if unknown mbox command completion.
  544. */
  545. if (lpfc_sli_chk_mbx_command(pmbox->mbxCommand) ==
  546. MBX_SHUTDOWN) {
  547. /* Unknow mailbox command compl */
  548. lpfc_printf_log(phba,
  549. KERN_ERR,
  550. LOG_MBOX | LOG_SLI,
  551. "%d:0323 Unknown Mailbox command %x Cmpl\n",
  552. phba->brd_no,
  553. pmbox->mbxCommand);
  554. phba->hba_state = LPFC_HBA_ERROR;
  555. phba->work_hs = HS_FFER3;
  556. lpfc_handle_eratt(phba);
  557. return (0);
  558. }
  559. phba->sli.mbox_active = NULL;
  560. if (pmbox->mbxStatus) {
  561. phba->sli.slistat.mbox_stat_err++;
  562. if (pmbox->mbxStatus == MBXERR_NO_RESOURCES) {
  563. /* Mbox cmd cmpl error - RETRYing */
  564. lpfc_printf_log(phba,
  565. KERN_INFO,
  566. LOG_MBOX | LOG_SLI,
  567. "%d:0305 Mbox cmd cmpl error - "
  568. "RETRYing Data: x%x x%x x%x x%x\n",
  569. phba->brd_no,
  570. pmbox->mbxCommand,
  571. pmbox->mbxStatus,
  572. pmbox->un.varWords[0],
  573. phba->hba_state);
  574. pmbox->mbxStatus = 0;
  575. pmbox->mbxOwner = OWN_HOST;
  576. spin_lock_irq(phba->host->host_lock);
  577. phba->sli.sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
  578. spin_unlock_irq(phba->host->host_lock);
  579. rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
  580. if (rc == MBX_SUCCESS)
  581. return (0);
  582. }
  583. }
  584. /* Mailbox cmd <cmd> Cmpl <cmpl> */
  585. lpfc_printf_log(phba,
  586. KERN_INFO,
  587. LOG_MBOX | LOG_SLI,
  588. "%d:0307 Mailbox cmd x%x Cmpl x%p "
  589. "Data: x%x x%x x%x x%x x%x x%x x%x x%x x%x\n",
  590. phba->brd_no,
  591. pmbox->mbxCommand,
  592. pmb->mbox_cmpl,
  593. *((uint32_t *) pmbox),
  594. pmbox->un.varWords[0],
  595. pmbox->un.varWords[1],
  596. pmbox->un.varWords[2],
  597. pmbox->un.varWords[3],
  598. pmbox->un.varWords[4],
  599. pmbox->un.varWords[5],
  600. pmbox->un.varWords[6],
  601. pmbox->un.varWords[7]);
  602. if (pmb->mbox_cmpl) {
  603. lpfc_sli_pcimem_bcopy(mbox, pmbox, MAILBOX_CMD_SIZE);
  604. pmb->mbox_cmpl(phba,pmb);
  605. }
  606. }
  607. do {
  608. process_next = 0; /* by default don't loop */
  609. spin_lock_irq(phba->host->host_lock);
  610. phba->sli.sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
  611. /* Process next mailbox command if there is one */
  612. if ((pmb = lpfc_mbox_get(phba))) {
  613. spin_unlock_irq(phba->host->host_lock);
  614. rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
  615. if (rc == MBX_NOT_FINISHED) {
  616. pmb->mb.mbxStatus = MBX_NOT_FINISHED;
  617. pmb->mbox_cmpl(phba,pmb);
  618. process_next = 1;
  619. continue; /* loop back */
  620. }
  621. } else {
  622. spin_unlock_irq(phba->host->host_lock);
  623. /* Turn on IOCB processing */
  624. for (i = 0; i < phba->sli.num_rings; i++) {
  625. lpfc_sli_turn_on_ring(phba, i);
  626. }
  627. /* Free any lpfc_dmabuf's waiting for mbox cmd cmpls */
  628. while (!list_empty(&phba->freebufList)) {
  629. struct lpfc_dmabuf *mp;
  630. mp = NULL;
  631. list_remove_head((&phba->freebufList),
  632. mp,
  633. struct lpfc_dmabuf,
  634. list);
  635. if (mp) {
  636. lpfc_mbuf_free(phba, mp->virt,
  637. mp->phys);
  638. kfree(mp);
  639. }
  640. }
  641. }
  642. } while (process_next);
  643. return (0);
  644. }
  645. static int
  646. lpfc_sli_process_unsol_iocb(struct lpfc_hba *phba, struct lpfc_sli_ring *pring,
  647. struct lpfc_iocbq *saveq)
  648. {
  649. IOCB_t * irsp;
  650. WORD5 * w5p;
  651. uint32_t Rctl, Type;
  652. uint32_t match, i;
  653. match = 0;
  654. irsp = &(saveq->iocb);
  655. if ((irsp->ulpCommand == CMD_RCV_ELS_REQ64_CX)
  656. || (irsp->ulpCommand == CMD_RCV_ELS_REQ_CX)) {
  657. Rctl = FC_ELS_REQ;
  658. Type = FC_ELS_DATA;
  659. } else {
  660. w5p =
  661. (WORD5 *) & (saveq->iocb.un.
  662. ulpWord[5]);
  663. Rctl = w5p->hcsw.Rctl;
  664. Type = w5p->hcsw.Type;
  665. /* Firmware Workaround */
  666. if ((Rctl == 0) && (pring->ringno == LPFC_ELS_RING) &&
  667. (irsp->ulpCommand == CMD_RCV_SEQUENCE64_CX)) {
  668. Rctl = FC_ELS_REQ;
  669. Type = FC_ELS_DATA;
  670. w5p->hcsw.Rctl = Rctl;
  671. w5p->hcsw.Type = Type;
  672. }
  673. }
  674. /* unSolicited Responses */
  675. if (pring->prt[0].profile) {
  676. if (pring->prt[0].lpfc_sli_rcv_unsol_event)
  677. (pring->prt[0].lpfc_sli_rcv_unsol_event) (phba, pring,
  678. saveq);
  679. match = 1;
  680. } else {
  681. /* We must search, based on rctl / type
  682. for the right routine */
  683. for (i = 0; i < pring->num_mask;
  684. i++) {
  685. if ((pring->prt[i].rctl ==
  686. Rctl)
  687. && (pring->prt[i].
  688. type == Type)) {
  689. if (pring->prt[i].lpfc_sli_rcv_unsol_event)
  690. (pring->prt[i].lpfc_sli_rcv_unsol_event)
  691. (phba, pring, saveq);
  692. match = 1;
  693. break;
  694. }
  695. }
  696. }
  697. if (match == 0) {
  698. /* Unexpected Rctl / Type received */
  699. /* Ring <ringno> handler: unexpected
  700. Rctl <Rctl> Type <Type> received */
  701. lpfc_printf_log(phba,
  702. KERN_WARNING,
  703. LOG_SLI,
  704. "%d:0313 Ring %d handler: unexpected Rctl x%x "
  705. "Type x%x received \n",
  706. phba->brd_no,
  707. pring->ringno,
  708. Rctl,
  709. Type);
  710. }
  711. return(1);
  712. }
  713. static struct lpfc_iocbq *
  714. lpfc_sli_iocbq_lookup(struct lpfc_hba * phba,
  715. struct lpfc_sli_ring * pring,
  716. struct lpfc_iocbq * prspiocb)
  717. {
  718. struct lpfc_iocbq *cmd_iocb = NULL;
  719. uint16_t iotag;
  720. iotag = prspiocb->iocb.ulpIoTag;
  721. if (iotag != 0 && iotag <= phba->sli.last_iotag) {
  722. cmd_iocb = phba->sli.iocbq_lookup[iotag];
  723. list_del(&cmd_iocb->list);
  724. pring->txcmplq_cnt--;
  725. return cmd_iocb;
  726. }
  727. lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
  728. "%d:0317 iotag x%x is out off "
  729. "range: max iotag x%x wd0 x%x\n",
  730. phba->brd_no, iotag,
  731. phba->sli.last_iotag,
  732. *(((uint32_t *) &prspiocb->iocb) + 7));
  733. return NULL;
  734. }
  735. static int
  736. lpfc_sli_process_sol_iocb(struct lpfc_hba * phba, struct lpfc_sli_ring * pring,
  737. struct lpfc_iocbq *saveq)
  738. {
  739. struct lpfc_iocbq * cmdiocbp;
  740. int rc = 1;
  741. unsigned long iflag;
  742. /* Based on the iotag field, get the cmd IOCB from the txcmplq */
  743. spin_lock_irqsave(phba->host->host_lock, iflag);
  744. cmdiocbp = lpfc_sli_iocbq_lookup(phba, pring, saveq);
  745. if (cmdiocbp) {
  746. if (cmdiocbp->iocb_cmpl) {
  747. /*
  748. * Post all ELS completions to the worker thread.
  749. * All other are passed to the completion callback.
  750. */
  751. if (pring->ringno == LPFC_ELS_RING) {
  752. spin_unlock_irqrestore(phba->host->host_lock,
  753. iflag);
  754. (cmdiocbp->iocb_cmpl) (phba, cmdiocbp, saveq);
  755. spin_lock_irqsave(phba->host->host_lock, iflag);
  756. }
  757. else {
  758. spin_unlock_irqrestore(phba->host->host_lock,
  759. iflag);
  760. (cmdiocbp->iocb_cmpl) (phba, cmdiocbp, saveq);
  761. spin_lock_irqsave(phba->host->host_lock, iflag);
  762. }
  763. } else
  764. lpfc_sli_release_iocbq(phba, cmdiocbp);
  765. } else {
  766. /*
  767. * Unknown initiating command based on the response iotag.
  768. * This could be the case on the ELS ring because of
  769. * lpfc_els_abort().
  770. */
  771. if (pring->ringno != LPFC_ELS_RING) {
  772. /*
  773. * Ring <ringno> handler: unexpected completion IoTag
  774. * <IoTag>
  775. */
  776. lpfc_printf_log(phba,
  777. KERN_WARNING,
  778. LOG_SLI,
  779. "%d:0322 Ring %d handler: unexpected "
  780. "completion IoTag x%x Data: x%x x%x x%x x%x\n",
  781. phba->brd_no,
  782. pring->ringno,
  783. saveq->iocb.ulpIoTag,
  784. saveq->iocb.ulpStatus,
  785. saveq->iocb.un.ulpWord[4],
  786. saveq->iocb.ulpCommand,
  787. saveq->iocb.ulpContext);
  788. }
  789. }
  790. spin_unlock_irqrestore(phba->host->host_lock, iflag);
  791. return rc;
  792. }
  793. static void lpfc_sli_rsp_pointers_error(struct lpfc_hba * phba,
  794. struct lpfc_sli_ring * pring)
  795. {
  796. struct lpfc_pgp *pgp = &phba->slim2p->mbx.us.s2.port[pring->ringno];
  797. /*
  798. * Ring <ringno> handler: portRspPut <portRspPut> is bigger then
  799. * rsp ring <portRspMax>
  800. */
  801. lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
  802. "%d:0312 Ring %d handler: portRspPut %d "
  803. "is bigger then rsp ring %d\n",
  804. phba->brd_no, pring->ringno,
  805. le32_to_cpu(pgp->rspPutInx),
  806. pring->numRiocb);
  807. phba->hba_state = LPFC_HBA_ERROR;
  808. /*
  809. * All error attention handlers are posted to
  810. * worker thread
  811. */
  812. phba->work_ha |= HA_ERATT;
  813. phba->work_hs = HS_FFER3;
  814. if (phba->work_wait)
  815. wake_up(phba->work_wait);
  816. return;
  817. }
  818. void lpfc_sli_poll_fcp_ring(struct lpfc_hba * phba)
  819. {
  820. struct lpfc_sli * psli = &phba->sli;
  821. struct lpfc_sli_ring * pring = &psli->ring[LPFC_FCP_RING];
  822. IOCB_t *irsp = NULL;
  823. IOCB_t *entry = NULL;
  824. struct lpfc_iocbq *cmdiocbq = NULL;
  825. struct lpfc_iocbq rspiocbq;
  826. struct lpfc_pgp *pgp;
  827. uint32_t status;
  828. uint32_t portRspPut, portRspMax;
  829. int type;
  830. uint32_t rsp_cmpl = 0;
  831. void __iomem *to_slim;
  832. uint32_t ha_copy;
  833. pring->stats.iocb_event++;
  834. /* The driver assumes SLI-2 mode */
  835. pgp = &phba->slim2p->mbx.us.s2.port[pring->ringno];
  836. /*
  837. * The next available response entry should never exceed the maximum
  838. * entries. If it does, treat it as an adapter hardware error.
  839. */
  840. portRspMax = pring->numRiocb;
  841. portRspPut = le32_to_cpu(pgp->rspPutInx);
  842. if (unlikely(portRspPut >= portRspMax)) {
  843. lpfc_sli_rsp_pointers_error(phba, pring);
  844. return;
  845. }
  846. rmb();
  847. while (pring->rspidx != portRspPut) {
  848. entry = IOCB_ENTRY(pring->rspringaddr, pring->rspidx);
  849. if (++pring->rspidx >= portRspMax)
  850. pring->rspidx = 0;
  851. lpfc_sli_pcimem_bcopy((uint32_t *) entry,
  852. (uint32_t *) &rspiocbq.iocb,
  853. sizeof (IOCB_t));
  854. irsp = &rspiocbq.iocb;
  855. type = lpfc_sli_iocb_cmd_type(irsp->ulpCommand & CMD_IOCB_MASK);
  856. pring->stats.iocb_rsp++;
  857. rsp_cmpl++;
  858. if (unlikely(irsp->ulpStatus)) {
  859. /* Rsp ring <ringno> error: IOCB */
  860. lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
  861. "%d:0326 Rsp Ring %d error: IOCB Data: "
  862. "x%x x%x x%x x%x x%x x%x x%x x%x\n",
  863. phba->brd_no, pring->ringno,
  864. irsp->un.ulpWord[0],
  865. irsp->un.ulpWord[1],
  866. irsp->un.ulpWord[2],
  867. irsp->un.ulpWord[3],
  868. irsp->un.ulpWord[4],
  869. irsp->un.ulpWord[5],
  870. *(((uint32_t *) irsp) + 6),
  871. *(((uint32_t *) irsp) + 7));
  872. }
  873. switch (type) {
  874. case LPFC_ABORT_IOCB:
  875. case LPFC_SOL_IOCB:
  876. /*
  877. * Idle exchange closed via ABTS from port. No iocb
  878. * resources need to be recovered.
  879. */
  880. if (unlikely(irsp->ulpCommand == CMD_XRI_ABORTED_CX)) {
  881. lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
  882. "%d:0314 IOCB cmd 0x%x"
  883. " processed. Skipping"
  884. " completion", phba->brd_no,
  885. irsp->ulpCommand);
  886. break;
  887. }
  888. cmdiocbq = lpfc_sli_iocbq_lookup(phba, pring,
  889. &rspiocbq);
  890. if ((cmdiocbq) && (cmdiocbq->iocb_cmpl)) {
  891. (cmdiocbq->iocb_cmpl)(phba, cmdiocbq,
  892. &rspiocbq);
  893. }
  894. break;
  895. default:
  896. if (irsp->ulpCommand == CMD_ADAPTER_MSG) {
  897. char adaptermsg[LPFC_MAX_ADPTMSG];
  898. memset(adaptermsg, 0, LPFC_MAX_ADPTMSG);
  899. memcpy(&adaptermsg[0], (uint8_t *) irsp,
  900. MAX_MSG_DATA);
  901. dev_warn(&((phba->pcidev)->dev), "lpfc%d: %s",
  902. phba->brd_no, adaptermsg);
  903. } else {
  904. /* Unknown IOCB command */
  905. lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
  906. "%d:0321 Unknown IOCB command "
  907. "Data: x%x, x%x x%x x%x x%x\n",
  908. phba->brd_no, type,
  909. irsp->ulpCommand,
  910. irsp->ulpStatus,
  911. irsp->ulpIoTag,
  912. irsp->ulpContext);
  913. }
  914. break;
  915. }
  916. /*
  917. * The response IOCB has been processed. Update the ring
  918. * pointer in SLIM. If the port response put pointer has not
  919. * been updated, sync the pgp->rspPutInx and fetch the new port
  920. * response put pointer.
  921. */
  922. to_slim = phba->MBslimaddr +
  923. (SLIMOFF + (pring->ringno * 2) + 1) * 4;
  924. writeb(pring->rspidx, to_slim);
  925. if (pring->rspidx == portRspPut)
  926. portRspPut = le32_to_cpu(pgp->rspPutInx);
  927. }
  928. ha_copy = readl(phba->HAregaddr);
  929. ha_copy >>= (LPFC_FCP_RING * 4);
  930. if ((rsp_cmpl > 0) && (ha_copy & HA_R0RE_REQ)) {
  931. pring->stats.iocb_rsp_full++;
  932. status = ((CA_R0ATT | CA_R0RE_RSP) << (LPFC_FCP_RING * 4));
  933. writel(status, phba->CAregaddr);
  934. readl(phba->CAregaddr);
  935. }
  936. if ((ha_copy & HA_R0CE_RSP) &&
  937. (pring->flag & LPFC_CALL_RING_AVAILABLE)) {
  938. pring->flag &= ~LPFC_CALL_RING_AVAILABLE;
  939. pring->stats.iocb_cmd_empty++;
  940. /* Force update of the local copy of cmdGetInx */
  941. pring->local_getidx = le32_to_cpu(pgp->cmdGetInx);
  942. lpfc_sli_resume_iocb(phba, pring);
  943. if ((pring->lpfc_sli_cmd_available))
  944. (pring->lpfc_sli_cmd_available) (phba, pring);
  945. }
  946. return;
  947. }
  948. /*
  949. * This routine presumes LPFC_FCP_RING handling and doesn't bother
  950. * to check it explicitly.
  951. */
  952. static int
  953. lpfc_sli_handle_fast_ring_event(struct lpfc_hba * phba,
  954. struct lpfc_sli_ring * pring, uint32_t mask)
  955. {
  956. struct lpfc_pgp *pgp = &phba->slim2p->mbx.us.s2.port[pring->ringno];
  957. IOCB_t *irsp = NULL;
  958. IOCB_t *entry = NULL;
  959. struct lpfc_iocbq *cmdiocbq = NULL;
  960. struct lpfc_iocbq rspiocbq;
  961. uint32_t status;
  962. uint32_t portRspPut, portRspMax;
  963. int rc = 1;
  964. lpfc_iocb_type type;
  965. unsigned long iflag;
  966. uint32_t rsp_cmpl = 0;
  967. void __iomem *to_slim;
  968. spin_lock_irqsave(phba->host->host_lock, iflag);
  969. pring->stats.iocb_event++;
  970. /*
  971. * The next available response entry should never exceed the maximum
  972. * entries. If it does, treat it as an adapter hardware error.
  973. */
  974. portRspMax = pring->numRiocb;
  975. portRspPut = le32_to_cpu(pgp->rspPutInx);
  976. if (unlikely(portRspPut >= portRspMax)) {
  977. lpfc_sli_rsp_pointers_error(phba, pring);
  978. spin_unlock_irqrestore(phba->host->host_lock, iflag);
  979. return 1;
  980. }
  981. rmb();
  982. while (pring->rspidx != portRspPut) {
  983. /*
  984. * Fetch an entry off the ring and copy it into a local data
  985. * structure. The copy involves a byte-swap since the
  986. * network byte order and pci byte orders are different.
  987. */
  988. entry = IOCB_ENTRY(pring->rspringaddr, pring->rspidx);
  989. if (++pring->rspidx >= portRspMax)
  990. pring->rspidx = 0;
  991. lpfc_sli_pcimem_bcopy((uint32_t *) entry,
  992. (uint32_t *) &rspiocbq.iocb,
  993. sizeof (IOCB_t));
  994. INIT_LIST_HEAD(&(rspiocbq.list));
  995. irsp = &rspiocbq.iocb;
  996. type = lpfc_sli_iocb_cmd_type(irsp->ulpCommand & CMD_IOCB_MASK);
  997. pring->stats.iocb_rsp++;
  998. rsp_cmpl++;
  999. if (unlikely(irsp->ulpStatus)) {
  1000. /* Rsp ring <ringno> error: IOCB */
  1001. lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
  1002. "%d:0336 Rsp Ring %d error: IOCB Data: "
  1003. "x%x x%x x%x x%x x%x x%x x%x x%x\n",
  1004. phba->brd_no, pring->ringno,
  1005. irsp->un.ulpWord[0], irsp->un.ulpWord[1],
  1006. irsp->un.ulpWord[2], irsp->un.ulpWord[3],
  1007. irsp->un.ulpWord[4], irsp->un.ulpWord[5],
  1008. *(((uint32_t *) irsp) + 6),
  1009. *(((uint32_t *) irsp) + 7));
  1010. }
  1011. switch (type) {
  1012. case LPFC_ABORT_IOCB:
  1013. case LPFC_SOL_IOCB:
  1014. /*
  1015. * Idle exchange closed via ABTS from port. No iocb
  1016. * resources need to be recovered.
  1017. */
  1018. if (unlikely(irsp->ulpCommand == CMD_XRI_ABORTED_CX)) {
  1019. lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
  1020. "%d:0333 IOCB cmd 0x%x"
  1021. " processed. Skipping"
  1022. " completion\n", phba->brd_no,
  1023. irsp->ulpCommand);
  1024. break;
  1025. }
  1026. cmdiocbq = lpfc_sli_iocbq_lookup(phba, pring,
  1027. &rspiocbq);
  1028. if ((cmdiocbq) && (cmdiocbq->iocb_cmpl)) {
  1029. if (phba->cfg_poll & ENABLE_FCP_RING_POLLING) {
  1030. (cmdiocbq->iocb_cmpl)(phba, cmdiocbq,
  1031. &rspiocbq);
  1032. } else {
  1033. spin_unlock_irqrestore(
  1034. phba->host->host_lock, iflag);
  1035. (cmdiocbq->iocb_cmpl)(phba, cmdiocbq,
  1036. &rspiocbq);
  1037. spin_lock_irqsave(phba->host->host_lock,
  1038. iflag);
  1039. }
  1040. }
  1041. break;
  1042. case LPFC_UNSOL_IOCB:
  1043. spin_unlock_irqrestore(phba->host->host_lock, iflag);
  1044. lpfc_sli_process_unsol_iocb(phba, pring, &rspiocbq);
  1045. spin_lock_irqsave(phba->host->host_lock, iflag);
  1046. break;
  1047. default:
  1048. if (irsp->ulpCommand == CMD_ADAPTER_MSG) {
  1049. char adaptermsg[LPFC_MAX_ADPTMSG];
  1050. memset(adaptermsg, 0, LPFC_MAX_ADPTMSG);
  1051. memcpy(&adaptermsg[0], (uint8_t *) irsp,
  1052. MAX_MSG_DATA);
  1053. dev_warn(&((phba->pcidev)->dev), "lpfc%d: %s",
  1054. phba->brd_no, adaptermsg);
  1055. } else {
  1056. /* Unknown IOCB command */
  1057. lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
  1058. "%d:0334 Unknown IOCB command "
  1059. "Data: x%x, x%x x%x x%x x%x\n",
  1060. phba->brd_no, type, irsp->ulpCommand,
  1061. irsp->ulpStatus, irsp->ulpIoTag,
  1062. irsp->ulpContext);
  1063. }
  1064. break;
  1065. }
  1066. /*
  1067. * The response IOCB has been processed. Update the ring
  1068. * pointer in SLIM. If the port response put pointer has not
  1069. * been updated, sync the pgp->rspPutInx and fetch the new port
  1070. * response put pointer.
  1071. */
  1072. to_slim = phba->MBslimaddr +
  1073. (SLIMOFF + (pring->ringno * 2) + 1) * 4;
  1074. writel(pring->rspidx, to_slim);
  1075. if (pring->rspidx == portRspPut)
  1076. portRspPut = le32_to_cpu(pgp->rspPutInx);
  1077. }
  1078. if ((rsp_cmpl > 0) && (mask & HA_R0RE_REQ)) {
  1079. pring->stats.iocb_rsp_full++;
  1080. status = ((CA_R0ATT | CA_R0RE_RSP) << (pring->ringno * 4));
  1081. writel(status, phba->CAregaddr);
  1082. readl(phba->CAregaddr);
  1083. }
  1084. if ((mask & HA_R0CE_RSP) && (pring->flag & LPFC_CALL_RING_AVAILABLE)) {
  1085. pring->flag &= ~LPFC_CALL_RING_AVAILABLE;
  1086. pring->stats.iocb_cmd_empty++;
  1087. /* Force update of the local copy of cmdGetInx */
  1088. pring->local_getidx = le32_to_cpu(pgp->cmdGetInx);
  1089. lpfc_sli_resume_iocb(phba, pring);
  1090. if ((pring->lpfc_sli_cmd_available))
  1091. (pring->lpfc_sli_cmd_available) (phba, pring);
  1092. }
  1093. spin_unlock_irqrestore(phba->host->host_lock, iflag);
  1094. return rc;
  1095. }
  1096. int
  1097. lpfc_sli_handle_slow_ring_event(struct lpfc_hba * phba,
  1098. struct lpfc_sli_ring * pring, uint32_t mask)
  1099. {
  1100. IOCB_t *entry;
  1101. IOCB_t *irsp = NULL;
  1102. struct lpfc_iocbq *rspiocbp = NULL;
  1103. struct lpfc_iocbq *next_iocb;
  1104. struct lpfc_iocbq *cmdiocbp;
  1105. struct lpfc_iocbq *saveq;
  1106. struct lpfc_pgp *pgp = &phba->slim2p->mbx.us.s2.port[pring->ringno];
  1107. uint8_t iocb_cmd_type;
  1108. lpfc_iocb_type type;
  1109. uint32_t status, free_saveq;
  1110. uint32_t portRspPut, portRspMax;
  1111. int rc = 1;
  1112. unsigned long iflag;
  1113. void __iomem *to_slim;
  1114. spin_lock_irqsave(phba->host->host_lock, iflag);
  1115. pring->stats.iocb_event++;
  1116. /*
  1117. * The next available response entry should never exceed the maximum
  1118. * entries. If it does, treat it as an adapter hardware error.
  1119. */
  1120. portRspMax = pring->numRiocb;
  1121. portRspPut = le32_to_cpu(pgp->rspPutInx);
  1122. if (portRspPut >= portRspMax) {
  1123. /*
  1124. * Ring <ringno> handler: portRspPut <portRspPut> is bigger then
  1125. * rsp ring <portRspMax>
  1126. */
  1127. lpfc_printf_log(phba,
  1128. KERN_ERR,
  1129. LOG_SLI,
  1130. "%d:0303 Ring %d handler: portRspPut %d "
  1131. "is bigger then rsp ring %d\n",
  1132. phba->brd_no,
  1133. pring->ringno, portRspPut, portRspMax);
  1134. phba->hba_state = LPFC_HBA_ERROR;
  1135. spin_unlock_irqrestore(phba->host->host_lock, iflag);
  1136. phba->work_hs = HS_FFER3;
  1137. lpfc_handle_eratt(phba);
  1138. return 1;
  1139. }
  1140. rmb();
  1141. while (pring->rspidx != portRspPut) {
  1142. /*
  1143. * Build a completion list and call the appropriate handler.
  1144. * The process is to get the next available response iocb, get
  1145. * a free iocb from the list, copy the response data into the
  1146. * free iocb, insert to the continuation list, and update the
  1147. * next response index to slim. This process makes response
  1148. * iocb's in the ring available to DMA as fast as possible but
  1149. * pays a penalty for a copy operation. Since the iocb is
  1150. * only 32 bytes, this penalty is considered small relative to
  1151. * the PCI reads for register values and a slim write. When
  1152. * the ulpLe field is set, the entire Command has been
  1153. * received.
  1154. */
  1155. entry = IOCB_ENTRY(pring->rspringaddr, pring->rspidx);
  1156. rspiocbp = lpfc_sli_get_iocbq(phba);
  1157. if (rspiocbp == NULL) {
  1158. printk(KERN_ERR "%s: out of buffers! Failing "
  1159. "completion.\n", __FUNCTION__);
  1160. break;
  1161. }
  1162. lpfc_sli_pcimem_bcopy(entry, &rspiocbp->iocb, sizeof (IOCB_t));
  1163. irsp = &rspiocbp->iocb;
  1164. if (++pring->rspidx >= portRspMax)
  1165. pring->rspidx = 0;
  1166. to_slim = phba->MBslimaddr + (SLIMOFF + (pring->ringno * 2)
  1167. + 1) * 4;
  1168. writel(pring->rspidx, to_slim);
  1169. if (list_empty(&(pring->iocb_continueq))) {
  1170. list_add(&rspiocbp->list, &(pring->iocb_continueq));
  1171. } else {
  1172. list_add_tail(&rspiocbp->list,
  1173. &(pring->iocb_continueq));
  1174. }
  1175. pring->iocb_continueq_cnt++;
  1176. if (irsp->ulpLe) {
  1177. /*
  1178. * By default, the driver expects to free all resources
  1179. * associated with this iocb completion.
  1180. */
  1181. free_saveq = 1;
  1182. saveq = list_get_first(&pring->iocb_continueq,
  1183. struct lpfc_iocbq, list);
  1184. irsp = &(saveq->iocb);
  1185. list_del_init(&pring->iocb_continueq);
  1186. pring->iocb_continueq_cnt = 0;
  1187. pring->stats.iocb_rsp++;
  1188. if (irsp->ulpStatus) {
  1189. /* Rsp ring <ringno> error: IOCB */
  1190. lpfc_printf_log(phba,
  1191. KERN_WARNING,
  1192. LOG_SLI,
  1193. "%d:0328 Rsp Ring %d error: IOCB Data: "
  1194. "x%x x%x x%x x%x x%x x%x x%x x%x\n",
  1195. phba->brd_no,
  1196. pring->ringno,
  1197. irsp->un.ulpWord[0],
  1198. irsp->un.ulpWord[1],
  1199. irsp->un.ulpWord[2],
  1200. irsp->un.ulpWord[3],
  1201. irsp->un.ulpWord[4],
  1202. irsp->un.ulpWord[5],
  1203. *(((uint32_t *) irsp) + 6),
  1204. *(((uint32_t *) irsp) + 7));
  1205. }
  1206. /*
  1207. * Fetch the IOCB command type and call the correct
  1208. * completion routine. Solicited and Unsolicited
  1209. * IOCBs on the ELS ring get freed back to the
  1210. * lpfc_iocb_list by the discovery kernel thread.
  1211. */
  1212. iocb_cmd_type = irsp->ulpCommand & CMD_IOCB_MASK;
  1213. type = lpfc_sli_iocb_cmd_type(iocb_cmd_type);
  1214. if (type == LPFC_SOL_IOCB) {
  1215. spin_unlock_irqrestore(phba->host->host_lock,
  1216. iflag);
  1217. rc = lpfc_sli_process_sol_iocb(phba, pring,
  1218. saveq);
  1219. spin_lock_irqsave(phba->host->host_lock, iflag);
  1220. } else if (type == LPFC_UNSOL_IOCB) {
  1221. spin_unlock_irqrestore(phba->host->host_lock,
  1222. iflag);
  1223. rc = lpfc_sli_process_unsol_iocb(phba, pring,
  1224. saveq);
  1225. spin_lock_irqsave(phba->host->host_lock, iflag);
  1226. } else if (type == LPFC_ABORT_IOCB) {
  1227. if ((irsp->ulpCommand != CMD_XRI_ABORTED_CX) &&
  1228. ((cmdiocbp =
  1229. lpfc_sli_iocbq_lookup(phba, pring,
  1230. saveq)))) {
  1231. /* Call the specified completion
  1232. routine */
  1233. if (cmdiocbp->iocb_cmpl) {
  1234. spin_unlock_irqrestore(
  1235. phba->host->host_lock,
  1236. iflag);
  1237. (cmdiocbp->iocb_cmpl) (phba,
  1238. cmdiocbp, saveq);
  1239. spin_lock_irqsave(
  1240. phba->host->host_lock,
  1241. iflag);
  1242. } else
  1243. lpfc_sli_release_iocbq(phba,
  1244. cmdiocbp);
  1245. }
  1246. } else if (type == LPFC_UNKNOWN_IOCB) {
  1247. if (irsp->ulpCommand == CMD_ADAPTER_MSG) {
  1248. char adaptermsg[LPFC_MAX_ADPTMSG];
  1249. memset(adaptermsg, 0,
  1250. LPFC_MAX_ADPTMSG);
  1251. memcpy(&adaptermsg[0], (uint8_t *) irsp,
  1252. MAX_MSG_DATA);
  1253. dev_warn(&((phba->pcidev)->dev),
  1254. "lpfc%d: %s",
  1255. phba->brd_no, adaptermsg);
  1256. } else {
  1257. /* Unknown IOCB command */
  1258. lpfc_printf_log(phba,
  1259. KERN_ERR,
  1260. LOG_SLI,
  1261. "%d:0335 Unknown IOCB command "
  1262. "Data: x%x x%x x%x x%x\n",
  1263. phba->brd_no,
  1264. irsp->ulpCommand,
  1265. irsp->ulpStatus,
  1266. irsp->ulpIoTag,
  1267. irsp->ulpContext);
  1268. }
  1269. }
  1270. if (free_saveq) {
  1271. if (!list_empty(&saveq->list)) {
  1272. list_for_each_entry_safe(rspiocbp,
  1273. next_iocb,
  1274. &saveq->list,
  1275. list) {
  1276. list_del(&rspiocbp->list);
  1277. lpfc_sli_release_iocbq(phba,
  1278. rspiocbp);
  1279. }
  1280. }
  1281. lpfc_sli_release_iocbq(phba, saveq);
  1282. }
  1283. }
  1284. /*
  1285. * If the port response put pointer has not been updated, sync
  1286. * the pgp->rspPutInx in the MAILBOX_tand fetch the new port
  1287. * response put pointer.
  1288. */
  1289. if (pring->rspidx == portRspPut) {
  1290. portRspPut = le32_to_cpu(pgp->rspPutInx);
  1291. }
  1292. } /* while (pring->rspidx != portRspPut) */
  1293. if ((rspiocbp != 0) && (mask & HA_R0RE_REQ)) {
  1294. /* At least one response entry has been freed */
  1295. pring->stats.iocb_rsp_full++;
  1296. /* SET RxRE_RSP in Chip Att register */
  1297. status = ((CA_R0ATT | CA_R0RE_RSP) << (pring->ringno * 4));
  1298. writel(status, phba->CAregaddr);
  1299. readl(phba->CAregaddr); /* flush */
  1300. }
  1301. if ((mask & HA_R0CE_RSP) && (pring->flag & LPFC_CALL_RING_AVAILABLE)) {
  1302. pring->flag &= ~LPFC_CALL_RING_AVAILABLE;
  1303. pring->stats.iocb_cmd_empty++;
  1304. /* Force update of the local copy of cmdGetInx */
  1305. pring->local_getidx = le32_to_cpu(pgp->cmdGetInx);
  1306. lpfc_sli_resume_iocb(phba, pring);
  1307. if ((pring->lpfc_sli_cmd_available))
  1308. (pring->lpfc_sli_cmd_available) (phba, pring);
  1309. }
  1310. spin_unlock_irqrestore(phba->host->host_lock, iflag);
  1311. return rc;
  1312. }
  1313. int
  1314. lpfc_sli_abort_iocb_ring(struct lpfc_hba *phba, struct lpfc_sli_ring *pring)
  1315. {
  1316. struct lpfc_iocbq *iocb, *next_iocb;
  1317. IOCB_t *icmd = NULL, *cmd = NULL;
  1318. int errcnt;
  1319. errcnt = 0;
  1320. /* Error everything on txq and txcmplq
  1321. * First do the txq.
  1322. */
  1323. spin_lock_irq(phba->host->host_lock);
  1324. list_for_each_entry_safe(iocb, next_iocb, &pring->txq, list) {
  1325. list_del_init(&iocb->list);
  1326. if (iocb->iocb_cmpl) {
  1327. icmd = &iocb->iocb;
  1328. icmd->ulpStatus = IOSTAT_LOCAL_REJECT;
  1329. icmd->un.ulpWord[4] = IOERR_SLI_ABORTED;
  1330. spin_unlock_irq(phba->host->host_lock);
  1331. (iocb->iocb_cmpl) (phba, iocb, iocb);
  1332. spin_lock_irq(phba->host->host_lock);
  1333. } else
  1334. lpfc_sli_release_iocbq(phba, iocb);
  1335. }
  1336. pring->txq_cnt = 0;
  1337. INIT_LIST_HEAD(&(pring->txq));
  1338. /* Next issue ABTS for everything on the txcmplq */
  1339. list_for_each_entry_safe(iocb, next_iocb, &pring->txcmplq, list) {
  1340. cmd = &iocb->iocb;
  1341. /*
  1342. * Imediate abort of IOCB, deque and call compl
  1343. */
  1344. list_del_init(&iocb->list);
  1345. pring->txcmplq_cnt--;
  1346. if (iocb->iocb_cmpl) {
  1347. cmd->ulpStatus = IOSTAT_LOCAL_REJECT;
  1348. cmd->un.ulpWord[4] = IOERR_SLI_ABORTED;
  1349. spin_unlock_irq(phba->host->host_lock);
  1350. (iocb->iocb_cmpl) (phba, iocb, iocb);
  1351. spin_lock_irq(phba->host->host_lock);
  1352. } else
  1353. lpfc_sli_release_iocbq(phba, iocb);
  1354. }
  1355. INIT_LIST_HEAD(&pring->txcmplq);
  1356. pring->txcmplq_cnt = 0;
  1357. spin_unlock_irq(phba->host->host_lock);
  1358. return errcnt;
  1359. }
  1360. int
  1361. lpfc_sli_brdready(struct lpfc_hba * phba, uint32_t mask)
  1362. {
  1363. uint32_t status;
  1364. int i = 0;
  1365. int retval = 0;
  1366. /* Read the HBA Host Status Register */
  1367. status = readl(phba->HSregaddr);
  1368. /*
  1369. * Check status register every 100ms for 5 retries, then every
  1370. * 500ms for 5, then every 2.5 sec for 5, then reset board and
  1371. * every 2.5 sec for 4.
  1372. * Break our of the loop if errors occurred during init.
  1373. */
  1374. while (((status & mask) != mask) &&
  1375. !(status & HS_FFERM) &&
  1376. i++ < 20) {
  1377. if (i <= 5)
  1378. msleep(10);
  1379. else if (i <= 10)
  1380. msleep(500);
  1381. else
  1382. msleep(2500);
  1383. if (i == 15) {
  1384. phba->hba_state = LPFC_STATE_UNKNOWN; /* Do post */
  1385. lpfc_sli_brdrestart(phba);
  1386. }
  1387. /* Read the HBA Host Status Register */
  1388. status = readl(phba->HSregaddr);
  1389. }
  1390. /* Check to see if any errors occurred during init */
  1391. if ((status & HS_FFERM) || (i >= 20)) {
  1392. phba->hba_state = LPFC_HBA_ERROR;
  1393. retval = 1;
  1394. }
  1395. return retval;
  1396. }
  1397. #define BARRIER_TEST_PATTERN (0xdeadbeef)
  1398. void lpfc_reset_barrier(struct lpfc_hba * phba)
  1399. {
  1400. uint32_t __iomem *resp_buf;
  1401. uint32_t __iomem *mbox_buf;
  1402. volatile uint32_t mbox;
  1403. uint32_t hc_copy;
  1404. int i;
  1405. uint8_t hdrtype;
  1406. pci_read_config_byte(phba->pcidev, PCI_HEADER_TYPE, &hdrtype);
  1407. if (hdrtype != 0x80 ||
  1408. (FC_JEDEC_ID(phba->vpd.rev.biuRev) != HELIOS_JEDEC_ID &&
  1409. FC_JEDEC_ID(phba->vpd.rev.biuRev) != THOR_JEDEC_ID))
  1410. return;
  1411. /*
  1412. * Tell the other part of the chip to suspend temporarily all
  1413. * its DMA activity.
  1414. */
  1415. resp_buf = phba->MBslimaddr;
  1416. /* Disable the error attention */
  1417. hc_copy = readl(phba->HCregaddr);
  1418. writel((hc_copy & ~HC_ERINT_ENA), phba->HCregaddr);
  1419. readl(phba->HCregaddr); /* flush */
  1420. if (readl(phba->HAregaddr) & HA_ERATT) {
  1421. /* Clear Chip error bit */
  1422. writel(HA_ERATT, phba->HAregaddr);
  1423. phba->stopped = 1;
  1424. }
  1425. mbox = 0;
  1426. ((MAILBOX_t *)&mbox)->mbxCommand = MBX_KILL_BOARD;
  1427. ((MAILBOX_t *)&mbox)->mbxOwner = OWN_CHIP;
  1428. writel(BARRIER_TEST_PATTERN, (resp_buf + 1));
  1429. mbox_buf = phba->MBslimaddr;
  1430. writel(mbox, mbox_buf);
  1431. for (i = 0;
  1432. readl(resp_buf + 1) != ~(BARRIER_TEST_PATTERN) && i < 50; i++)
  1433. mdelay(1);
  1434. if (readl(resp_buf + 1) != ~(BARRIER_TEST_PATTERN)) {
  1435. if (phba->sli.sli_flag & LPFC_SLI2_ACTIVE ||
  1436. phba->stopped)
  1437. goto restore_hc;
  1438. else
  1439. goto clear_errat;
  1440. }
  1441. ((MAILBOX_t *)&mbox)->mbxOwner = OWN_HOST;
  1442. for (i = 0; readl(resp_buf) != mbox && i < 500; i++)
  1443. mdelay(1);
  1444. clear_errat:
  1445. while (!(readl(phba->HAregaddr) & HA_ERATT) && ++i < 500)
  1446. mdelay(1);
  1447. if (readl(phba->HAregaddr) & HA_ERATT) {
  1448. writel(HA_ERATT, phba->HAregaddr);
  1449. phba->stopped = 1;
  1450. }
  1451. restore_hc:
  1452. writel(hc_copy, phba->HCregaddr);
  1453. readl(phba->HCregaddr); /* flush */
  1454. }
  1455. int
  1456. lpfc_sli_brdkill(struct lpfc_hba * phba)
  1457. {
  1458. struct lpfc_sli *psli;
  1459. LPFC_MBOXQ_t *pmb;
  1460. uint32_t status;
  1461. uint32_t ha_copy;
  1462. int retval;
  1463. int i = 0;
  1464. psli = &phba->sli;
  1465. /* Kill HBA */
  1466. lpfc_printf_log(phba,
  1467. KERN_INFO,
  1468. LOG_SLI,
  1469. "%d:0329 Kill HBA Data: x%x x%x\n",
  1470. phba->brd_no,
  1471. phba->hba_state,
  1472. psli->sli_flag);
  1473. if ((pmb = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
  1474. GFP_KERNEL)) == 0)
  1475. return 1;
  1476. /* Disable the error attention */
  1477. spin_lock_irq(phba->host->host_lock);
  1478. status = readl(phba->HCregaddr);
  1479. status &= ~HC_ERINT_ENA;
  1480. writel(status, phba->HCregaddr);
  1481. readl(phba->HCregaddr); /* flush */
  1482. spin_unlock_irq(phba->host->host_lock);
  1483. lpfc_kill_board(phba, pmb);
  1484. pmb->mbox_cmpl = lpfc_sli_def_mbox_cmpl;
  1485. retval = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
  1486. if (retval != MBX_SUCCESS) {
  1487. if (retval != MBX_BUSY)
  1488. mempool_free(pmb, phba->mbox_mem_pool);
  1489. return 1;
  1490. }
  1491. psli->sli_flag &= ~LPFC_SLI2_ACTIVE;
  1492. mempool_free(pmb, phba->mbox_mem_pool);
  1493. /* There is no completion for a KILL_BOARD mbox cmd. Check for an error
  1494. * attention every 100ms for 3 seconds. If we don't get ERATT after
  1495. * 3 seconds we still set HBA_ERROR state because the status of the
  1496. * board is now undefined.
  1497. */
  1498. ha_copy = readl(phba->HAregaddr);
  1499. while ((i++ < 30) && !(ha_copy & HA_ERATT)) {
  1500. mdelay(100);
  1501. ha_copy = readl(phba->HAregaddr);
  1502. }
  1503. del_timer_sync(&psli->mbox_tmo);
  1504. if (ha_copy & HA_ERATT) {
  1505. writel(HA_ERATT, phba->HAregaddr);
  1506. phba->stopped = 1;
  1507. }
  1508. spin_lock_irq(phba->host->host_lock);
  1509. psli->sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
  1510. spin_unlock_irq(phba->host->host_lock);
  1511. psli->mbox_active = NULL;
  1512. lpfc_hba_down_post(phba);
  1513. phba->hba_state = LPFC_HBA_ERROR;
  1514. return (ha_copy & HA_ERATT ? 0 : 1);
  1515. }
  1516. int
  1517. lpfc_sli_brdreset(struct lpfc_hba * phba)
  1518. {
  1519. struct lpfc_sli *psli;
  1520. struct lpfc_sli_ring *pring;
  1521. uint16_t cfg_value;
  1522. int i;
  1523. psli = &phba->sli;
  1524. /* Reset HBA */
  1525. lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
  1526. "%d:0325 Reset HBA Data: x%x x%x\n", phba->brd_no,
  1527. phba->hba_state, psli->sli_flag);
  1528. /* perform board reset */
  1529. phba->fc_eventTag = 0;
  1530. phba->fc_myDID = 0;
  1531. phba->fc_prevDID = 0;
  1532. /* Turn off parity checking and serr during the physical reset */
  1533. pci_read_config_word(phba->pcidev, PCI_COMMAND, &cfg_value);
  1534. pci_write_config_word(phba->pcidev, PCI_COMMAND,
  1535. (cfg_value &
  1536. ~(PCI_COMMAND_PARITY | PCI_COMMAND_SERR)));
  1537. psli->sli_flag &= ~(LPFC_SLI2_ACTIVE | LPFC_PROCESS_LA);
  1538. /* Now toggle INITFF bit in the Host Control Register */
  1539. writel(HC_INITFF, phba->HCregaddr);
  1540. mdelay(1);
  1541. readl(phba->HCregaddr); /* flush */
  1542. writel(0, phba->HCregaddr);
  1543. readl(phba->HCregaddr); /* flush */
  1544. /* Restore PCI cmd register */
  1545. pci_write_config_word(phba->pcidev, PCI_COMMAND, cfg_value);
  1546. /* Initialize relevant SLI info */
  1547. for (i = 0; i < psli->num_rings; i++) {
  1548. pring = &psli->ring[i];
  1549. pring->flag = 0;
  1550. pring->rspidx = 0;
  1551. pring->next_cmdidx = 0;
  1552. pring->local_getidx = 0;
  1553. pring->cmdidx = 0;
  1554. pring->missbufcnt = 0;
  1555. }
  1556. phba->hba_state = LPFC_WARM_START;
  1557. return 0;
  1558. }
  1559. int
  1560. lpfc_sli_brdrestart(struct lpfc_hba * phba)
  1561. {
  1562. MAILBOX_t *mb;
  1563. struct lpfc_sli *psli;
  1564. uint16_t skip_post;
  1565. volatile uint32_t word0;
  1566. void __iomem *to_slim;
  1567. spin_lock_irq(phba->host->host_lock);
  1568. psli = &phba->sli;
  1569. /* Restart HBA */
  1570. lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
  1571. "%d:0337 Restart HBA Data: x%x x%x\n", phba->brd_no,
  1572. phba->hba_state, psli->sli_flag);
  1573. word0 = 0;
  1574. mb = (MAILBOX_t *) &word0;
  1575. mb->mbxCommand = MBX_RESTART;
  1576. mb->mbxHc = 1;
  1577. lpfc_reset_barrier(phba);
  1578. to_slim = phba->MBslimaddr;
  1579. writel(*(uint32_t *) mb, to_slim);
  1580. readl(to_slim); /* flush */
  1581. /* Only skip post after fc_ffinit is completed */
  1582. if (phba->hba_state) {
  1583. skip_post = 1;
  1584. word0 = 1; /* This is really setting up word1 */
  1585. } else {
  1586. skip_post = 0;
  1587. word0 = 0; /* This is really setting up word1 */
  1588. }
  1589. to_slim = phba->MBslimaddr + sizeof (uint32_t);
  1590. writel(*(uint32_t *) mb, to_slim);
  1591. readl(to_slim); /* flush */
  1592. lpfc_sli_brdreset(phba);
  1593. phba->stopped = 0;
  1594. phba->hba_state = LPFC_INIT_START;
  1595. spin_unlock_irq(phba->host->host_lock);
  1596. memset(&psli->lnk_stat_offsets, 0, sizeof(psli->lnk_stat_offsets));
  1597. psli->stats_start = get_seconds();
  1598. if (skip_post)
  1599. mdelay(100);
  1600. else
  1601. mdelay(2000);
  1602. lpfc_hba_down_post(phba);
  1603. return 0;
  1604. }
  1605. static int
  1606. lpfc_sli_chipset_init(struct lpfc_hba *phba)
  1607. {
  1608. uint32_t status, i = 0;
  1609. /* Read the HBA Host Status Register */
  1610. status = readl(phba->HSregaddr);
  1611. /* Check status register to see what current state is */
  1612. i = 0;
  1613. while ((status & (HS_FFRDY | HS_MBRDY)) != (HS_FFRDY | HS_MBRDY)) {
  1614. /* Check every 100ms for 5 retries, then every 500ms for 5, then
  1615. * every 2.5 sec for 5, then reset board and every 2.5 sec for
  1616. * 4.
  1617. */
  1618. if (i++ >= 20) {
  1619. /* Adapter failed to init, timeout, status reg
  1620. <status> */
  1621. lpfc_printf_log(phba,
  1622. KERN_ERR,
  1623. LOG_INIT,
  1624. "%d:0436 Adapter failed to init, "
  1625. "timeout, status reg x%x\n",
  1626. phba->brd_no,
  1627. status);
  1628. phba->hba_state = LPFC_HBA_ERROR;
  1629. return -ETIMEDOUT;
  1630. }
  1631. /* Check to see if any errors occurred during init */
  1632. if (status & HS_FFERM) {
  1633. /* ERROR: During chipset initialization */
  1634. /* Adapter failed to init, chipset, status reg
  1635. <status> */
  1636. lpfc_printf_log(phba,
  1637. KERN_ERR,
  1638. LOG_INIT,
  1639. "%d:0437 Adapter failed to init, "
  1640. "chipset, status reg x%x\n",
  1641. phba->brd_no,
  1642. status);
  1643. phba->hba_state = LPFC_HBA_ERROR;
  1644. return -EIO;
  1645. }
  1646. if (i <= 5) {
  1647. msleep(10);
  1648. } else if (i <= 10) {
  1649. msleep(500);
  1650. } else {
  1651. msleep(2500);
  1652. }
  1653. if (i == 15) {
  1654. phba->hba_state = LPFC_STATE_UNKNOWN; /* Do post */
  1655. lpfc_sli_brdrestart(phba);
  1656. }
  1657. /* Read the HBA Host Status Register */
  1658. status = readl(phba->HSregaddr);
  1659. }
  1660. /* Check to see if any errors occurred during init */
  1661. if (status & HS_FFERM) {
  1662. /* ERROR: During chipset initialization */
  1663. /* Adapter failed to init, chipset, status reg <status> */
  1664. lpfc_printf_log(phba,
  1665. KERN_ERR,
  1666. LOG_INIT,
  1667. "%d:0438 Adapter failed to init, chipset, "
  1668. "status reg x%x\n",
  1669. phba->brd_no,
  1670. status);
  1671. phba->hba_state = LPFC_HBA_ERROR;
  1672. return -EIO;
  1673. }
  1674. /* Clear all interrupt enable conditions */
  1675. writel(0, phba->HCregaddr);
  1676. readl(phba->HCregaddr); /* flush */
  1677. /* setup host attn register */
  1678. writel(0xffffffff, phba->HAregaddr);
  1679. readl(phba->HAregaddr); /* flush */
  1680. return 0;
  1681. }
  1682. int
  1683. lpfc_sli_hba_setup(struct lpfc_hba * phba)
  1684. {
  1685. LPFC_MBOXQ_t *pmb;
  1686. uint32_t resetcount = 0, rc = 0, done = 0;
  1687. pmb = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
  1688. if (!pmb) {
  1689. phba->hba_state = LPFC_HBA_ERROR;
  1690. return -ENOMEM;
  1691. }
  1692. while (resetcount < 2 && !done) {
  1693. spin_lock_irq(phba->host->host_lock);
  1694. phba->sli.sli_flag |= LPFC_SLI_MBOX_ACTIVE;
  1695. spin_unlock_irq(phba->host->host_lock);
  1696. phba->hba_state = LPFC_STATE_UNKNOWN;
  1697. lpfc_sli_brdrestart(phba);
  1698. msleep(2500);
  1699. rc = lpfc_sli_chipset_init(phba);
  1700. if (rc)
  1701. break;
  1702. spin_lock_irq(phba->host->host_lock);
  1703. phba->sli.sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
  1704. spin_unlock_irq(phba->host->host_lock);
  1705. resetcount++;
  1706. /* Call pre CONFIG_PORT mailbox command initialization. A value of 0
  1707. * means the call was successful. Any other nonzero value is a failure,
  1708. * but if ERESTART is returned, the driver may reset the HBA and try
  1709. * again.
  1710. */
  1711. rc = lpfc_config_port_prep(phba);
  1712. if (rc == -ERESTART) {
  1713. phba->hba_state = 0;
  1714. continue;
  1715. } else if (rc) {
  1716. break;
  1717. }
  1718. phba->hba_state = LPFC_INIT_MBX_CMDS;
  1719. lpfc_config_port(phba, pmb);
  1720. rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
  1721. if (rc == MBX_SUCCESS)
  1722. done = 1;
  1723. else {
  1724. lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
  1725. "%d:0442 Adapter failed to init, mbxCmd x%x "
  1726. "CONFIG_PORT, mbxStatus x%x Data: x%x\n",
  1727. phba->brd_no, pmb->mb.mbxCommand,
  1728. pmb->mb.mbxStatus, 0);
  1729. phba->sli.sli_flag &= ~LPFC_SLI2_ACTIVE;
  1730. }
  1731. }
  1732. if (!done)
  1733. goto lpfc_sli_hba_setup_error;
  1734. rc = lpfc_sli_ring_map(phba, pmb);
  1735. if (rc)
  1736. goto lpfc_sli_hba_setup_error;
  1737. phba->sli.sli_flag |= LPFC_PROCESS_LA;
  1738. rc = lpfc_config_port_post(phba);
  1739. if (rc)
  1740. goto lpfc_sli_hba_setup_error;
  1741. goto lpfc_sli_hba_setup_exit;
  1742. lpfc_sli_hba_setup_error:
  1743. phba->hba_state = LPFC_HBA_ERROR;
  1744. lpfc_sli_hba_setup_exit:
  1745. mempool_free(pmb, phba->mbox_mem_pool);
  1746. return rc;
  1747. }
  1748. static void
  1749. lpfc_mbox_abort(struct lpfc_hba * phba)
  1750. {
  1751. LPFC_MBOXQ_t *pmbox;
  1752. MAILBOX_t *mb;
  1753. if (phba->sli.mbox_active) {
  1754. del_timer_sync(&phba->sli.mbox_tmo);
  1755. phba->work_hba_events &= ~WORKER_MBOX_TMO;
  1756. pmbox = phba->sli.mbox_active;
  1757. mb = &pmbox->mb;
  1758. phba->sli.mbox_active = NULL;
  1759. if (pmbox->mbox_cmpl) {
  1760. mb->mbxStatus = MBX_NOT_FINISHED;
  1761. (pmbox->mbox_cmpl) (phba, pmbox);
  1762. }
  1763. phba->sli.sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
  1764. }
  1765. /* Abort all the non active mailbox commands. */
  1766. spin_lock_irq(phba->host->host_lock);
  1767. pmbox = lpfc_mbox_get(phba);
  1768. while (pmbox) {
  1769. mb = &pmbox->mb;
  1770. if (pmbox->mbox_cmpl) {
  1771. mb->mbxStatus = MBX_NOT_FINISHED;
  1772. spin_unlock_irq(phba->host->host_lock);
  1773. (pmbox->mbox_cmpl) (phba, pmbox);
  1774. spin_lock_irq(phba->host->host_lock);
  1775. }
  1776. pmbox = lpfc_mbox_get(phba);
  1777. }
  1778. spin_unlock_irq(phba->host->host_lock);
  1779. return;
  1780. }
  1781. /*! lpfc_mbox_timeout
  1782. *
  1783. * \pre
  1784. * \post
  1785. * \param hba Pointer to per struct lpfc_hba structure
  1786. * \param l1 Pointer to the driver's mailbox queue.
  1787. * \return
  1788. * void
  1789. *
  1790. * \b Description:
  1791. *
  1792. * This routine handles mailbox timeout events at timer interrupt context.
  1793. */
  1794. void
  1795. lpfc_mbox_timeout(unsigned long ptr)
  1796. {
  1797. struct lpfc_hba *phba;
  1798. unsigned long iflag;
  1799. phba = (struct lpfc_hba *)ptr;
  1800. spin_lock_irqsave(phba->host->host_lock, iflag);
  1801. if (!(phba->work_hba_events & WORKER_MBOX_TMO)) {
  1802. phba->work_hba_events |= WORKER_MBOX_TMO;
  1803. if (phba->work_wait)
  1804. wake_up(phba->work_wait);
  1805. }
  1806. spin_unlock_irqrestore(phba->host->host_lock, iflag);
  1807. }
  1808. void
  1809. lpfc_mbox_timeout_handler(struct lpfc_hba *phba)
  1810. {
  1811. LPFC_MBOXQ_t *pmbox;
  1812. MAILBOX_t *mb;
  1813. spin_lock_irq(phba->host->host_lock);
  1814. if (!(phba->work_hba_events & WORKER_MBOX_TMO)) {
  1815. spin_unlock_irq(phba->host->host_lock);
  1816. return;
  1817. }
  1818. phba->work_hba_events &= ~WORKER_MBOX_TMO;
  1819. pmbox = phba->sli.mbox_active;
  1820. mb = &pmbox->mb;
  1821. /* Mbox cmd <mbxCommand> timeout */
  1822. lpfc_printf_log(phba,
  1823. KERN_ERR,
  1824. LOG_MBOX | LOG_SLI,
  1825. "%d:0310 Mailbox command x%x timeout Data: x%x x%x x%p\n",
  1826. phba->brd_no,
  1827. mb->mbxCommand,
  1828. phba->hba_state,
  1829. phba->sli.sli_flag,
  1830. phba->sli.mbox_active);
  1831. phba->sli.mbox_active = NULL;
  1832. if (pmbox->mbox_cmpl) {
  1833. mb->mbxStatus = MBX_NOT_FINISHED;
  1834. spin_unlock_irq(phba->host->host_lock);
  1835. (pmbox->mbox_cmpl) (phba, pmbox);
  1836. spin_lock_irq(phba->host->host_lock);
  1837. }
  1838. phba->sli.sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
  1839. spin_unlock_irq(phba->host->host_lock);
  1840. lpfc_mbox_abort(phba);
  1841. return;
  1842. }
  1843. int
  1844. lpfc_sli_issue_mbox(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmbox, uint32_t flag)
  1845. {
  1846. MAILBOX_t *mb;
  1847. struct lpfc_sli *psli;
  1848. uint32_t status, evtctr;
  1849. uint32_t ha_copy;
  1850. int i;
  1851. unsigned long drvr_flag = 0;
  1852. volatile uint32_t word0, ldata;
  1853. void __iomem *to_slim;
  1854. /* If the PCI channel is in offline state, do not post mbox. */
  1855. if (unlikely(pci_channel_offline(phba->pcidev)))
  1856. return MBX_NOT_FINISHED;
  1857. psli = &phba->sli;
  1858. spin_lock_irqsave(phba->host->host_lock, drvr_flag);
  1859. mb = &pmbox->mb;
  1860. status = MBX_SUCCESS;
  1861. if (phba->hba_state == LPFC_HBA_ERROR) {
  1862. spin_unlock_irqrestore(phba->host->host_lock, drvr_flag);
  1863. /* Mbox command <mbxCommand> cannot issue */
  1864. LOG_MBOX_CANNOT_ISSUE_DATA( phba, mb, psli, flag)
  1865. return (MBX_NOT_FINISHED);
  1866. }
  1867. if (mb->mbxCommand != MBX_KILL_BOARD && flag & MBX_NOWAIT &&
  1868. !(readl(phba->HCregaddr) & HC_MBINT_ENA)) {
  1869. spin_unlock_irqrestore(phba->host->host_lock, drvr_flag);
  1870. LOG_MBOX_CANNOT_ISSUE_DATA( phba, mb, psli, flag)
  1871. return (MBX_NOT_FINISHED);
  1872. }
  1873. if (psli->sli_flag & LPFC_SLI_MBOX_ACTIVE) {
  1874. /* Polling for a mbox command when another one is already active
  1875. * is not allowed in SLI. Also, the driver must have established
  1876. * SLI2 mode to queue and process multiple mbox commands.
  1877. */
  1878. if (flag & MBX_POLL) {
  1879. spin_unlock_irqrestore(phba->host->host_lock,
  1880. drvr_flag);
  1881. /* Mbox command <mbxCommand> cannot issue */
  1882. LOG_MBOX_CANNOT_ISSUE_DATA( phba, mb, psli, flag)
  1883. return (MBX_NOT_FINISHED);
  1884. }
  1885. if (!(psli->sli_flag & LPFC_SLI2_ACTIVE)) {
  1886. spin_unlock_irqrestore(phba->host->host_lock,
  1887. drvr_flag);
  1888. /* Mbox command <mbxCommand> cannot issue */
  1889. LOG_MBOX_CANNOT_ISSUE_DATA( phba, mb, psli, flag)
  1890. return (MBX_NOT_FINISHED);
  1891. }
  1892. /* Handle STOP IOCB processing flag. This is only meaningful
  1893. * if we are not polling for mbox completion.
  1894. */
  1895. if (flag & MBX_STOP_IOCB) {
  1896. flag &= ~MBX_STOP_IOCB;
  1897. /* Now flag each ring */
  1898. for (i = 0; i < psli->num_rings; i++) {
  1899. /* If the ring is active, flag it */
  1900. if (psli->ring[i].cmdringaddr) {
  1901. psli->ring[i].flag |=
  1902. LPFC_STOP_IOCB_MBX;
  1903. }
  1904. }
  1905. }
  1906. /* Another mailbox command is still being processed, queue this
  1907. * command to be processed later.
  1908. */
  1909. lpfc_mbox_put(phba, pmbox);
  1910. /* Mbox cmd issue - BUSY */
  1911. lpfc_printf_log(phba,
  1912. KERN_INFO,
  1913. LOG_MBOX | LOG_SLI,
  1914. "%d:0308 Mbox cmd issue - BUSY Data: x%x x%x x%x x%x\n",
  1915. phba->brd_no,
  1916. mb->mbxCommand,
  1917. phba->hba_state,
  1918. psli->sli_flag,
  1919. flag);
  1920. psli->slistat.mbox_busy++;
  1921. spin_unlock_irqrestore(phba->host->host_lock,
  1922. drvr_flag);
  1923. return (MBX_BUSY);
  1924. }
  1925. /* Handle STOP IOCB processing flag. This is only meaningful
  1926. * if we are not polling for mbox completion.
  1927. */
  1928. if (flag & MBX_STOP_IOCB) {
  1929. flag &= ~MBX_STOP_IOCB;
  1930. if (flag == MBX_NOWAIT) {
  1931. /* Now flag each ring */
  1932. for (i = 0; i < psli->num_rings; i++) {
  1933. /* If the ring is active, flag it */
  1934. if (psli->ring[i].cmdringaddr) {
  1935. psli->ring[i].flag |=
  1936. LPFC_STOP_IOCB_MBX;
  1937. }
  1938. }
  1939. }
  1940. }
  1941. psli->sli_flag |= LPFC_SLI_MBOX_ACTIVE;
  1942. /* If we are not polling, we MUST be in SLI2 mode */
  1943. if (flag != MBX_POLL) {
  1944. if (!(psli->sli_flag & LPFC_SLI2_ACTIVE) &&
  1945. (mb->mbxCommand != MBX_KILL_BOARD)) {
  1946. psli->sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
  1947. spin_unlock_irqrestore(phba->host->host_lock,
  1948. drvr_flag);
  1949. /* Mbox command <mbxCommand> cannot issue */
  1950. LOG_MBOX_CANNOT_ISSUE_DATA( phba, mb, psli, flag);
  1951. return (MBX_NOT_FINISHED);
  1952. }
  1953. /* timeout active mbox command */
  1954. mod_timer(&psli->mbox_tmo, (jiffies +
  1955. (HZ * lpfc_mbox_tmo_val(phba, mb->mbxCommand))));
  1956. }
  1957. /* Mailbox cmd <cmd> issue */
  1958. lpfc_printf_log(phba,
  1959. KERN_INFO,
  1960. LOG_MBOX | LOG_SLI,
  1961. "%d:0309 Mailbox cmd x%x issue Data: x%x x%x x%x\n",
  1962. phba->brd_no,
  1963. mb->mbxCommand,
  1964. phba->hba_state,
  1965. psli->sli_flag,
  1966. flag);
  1967. psli->slistat.mbox_cmd++;
  1968. evtctr = psli->slistat.mbox_event;
  1969. /* next set own bit for the adapter and copy over command word */
  1970. mb->mbxOwner = OWN_CHIP;
  1971. if (psli->sli_flag & LPFC_SLI2_ACTIVE) {
  1972. /* First copy command data to host SLIM area */
  1973. lpfc_sli_pcimem_bcopy(mb, &phba->slim2p->mbx, MAILBOX_CMD_SIZE);
  1974. } else {
  1975. if (mb->mbxCommand == MBX_CONFIG_PORT) {
  1976. /* copy command data into host mbox for cmpl */
  1977. lpfc_sli_pcimem_bcopy(mb, &phba->slim2p->mbx,
  1978. MAILBOX_CMD_SIZE);
  1979. }
  1980. /* First copy mbox command data to HBA SLIM, skip past first
  1981. word */
  1982. to_slim = phba->MBslimaddr + sizeof (uint32_t);
  1983. lpfc_memcpy_to_slim(to_slim, &mb->un.varWords[0],
  1984. MAILBOX_CMD_SIZE - sizeof (uint32_t));
  1985. /* Next copy over first word, with mbxOwner set */
  1986. ldata = *((volatile uint32_t *)mb);
  1987. to_slim = phba->MBslimaddr;
  1988. writel(ldata, to_slim);
  1989. readl(to_slim); /* flush */
  1990. if (mb->mbxCommand == MBX_CONFIG_PORT) {
  1991. /* switch over to host mailbox */
  1992. psli->sli_flag |= LPFC_SLI2_ACTIVE;
  1993. }
  1994. }
  1995. wmb();
  1996. /* interrupt board to doit right away */
  1997. writel(CA_MBATT, phba->CAregaddr);
  1998. readl(phba->CAregaddr); /* flush */
  1999. switch (flag) {
  2000. case MBX_NOWAIT:
  2001. /* Don't wait for it to finish, just return */
  2002. psli->mbox_active = pmbox;
  2003. break;
  2004. case MBX_POLL:
  2005. psli->mbox_active = NULL;
  2006. if (psli->sli_flag & LPFC_SLI2_ACTIVE) {
  2007. /* First read mbox status word */
  2008. word0 = *((volatile uint32_t *)&phba->slim2p->mbx);
  2009. word0 = le32_to_cpu(word0);
  2010. } else {
  2011. /* First read mbox status word */
  2012. word0 = readl(phba->MBslimaddr);
  2013. }
  2014. /* Read the HBA Host Attention Register */
  2015. ha_copy = readl(phba->HAregaddr);
  2016. i = lpfc_mbox_tmo_val(phba, mb->mbxCommand);
  2017. i *= 1000; /* Convert to ms */
  2018. /* Wait for command to complete */
  2019. while (((word0 & OWN_CHIP) == OWN_CHIP) ||
  2020. (!(ha_copy & HA_MBATT) &&
  2021. (phba->hba_state > LPFC_WARM_START))) {
  2022. if (i-- <= 0) {
  2023. psli->sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
  2024. spin_unlock_irqrestore(phba->host->host_lock,
  2025. drvr_flag);
  2026. return (MBX_NOT_FINISHED);
  2027. }
  2028. /* Check if we took a mbox interrupt while we were
  2029. polling */
  2030. if (((word0 & OWN_CHIP) != OWN_CHIP)
  2031. && (evtctr != psli->slistat.mbox_event))
  2032. break;
  2033. spin_unlock_irqrestore(phba->host->host_lock,
  2034. drvr_flag);
  2035. /* Can be in interrupt context, do not sleep */
  2036. /* (or might be called with interrupts disabled) */
  2037. mdelay(1);
  2038. spin_lock_irqsave(phba->host->host_lock, drvr_flag);
  2039. if (psli->sli_flag & LPFC_SLI2_ACTIVE) {
  2040. /* First copy command data */
  2041. word0 = *((volatile uint32_t *)
  2042. &phba->slim2p->mbx);
  2043. word0 = le32_to_cpu(word0);
  2044. if (mb->mbxCommand == MBX_CONFIG_PORT) {
  2045. MAILBOX_t *slimmb;
  2046. volatile uint32_t slimword0;
  2047. /* Check real SLIM for any errors */
  2048. slimword0 = readl(phba->MBslimaddr);
  2049. slimmb = (MAILBOX_t *) & slimword0;
  2050. if (((slimword0 & OWN_CHIP) != OWN_CHIP)
  2051. && slimmb->mbxStatus) {
  2052. psli->sli_flag &=
  2053. ~LPFC_SLI2_ACTIVE;
  2054. word0 = slimword0;
  2055. }
  2056. }
  2057. } else {
  2058. /* First copy command data */
  2059. word0 = readl(phba->MBslimaddr);
  2060. }
  2061. /* Read the HBA Host Attention Register */
  2062. ha_copy = readl(phba->HAregaddr);
  2063. }
  2064. if (psli->sli_flag & LPFC_SLI2_ACTIVE) {
  2065. /* copy results back to user */
  2066. lpfc_sli_pcimem_bcopy(&phba->slim2p->mbx, mb,
  2067. MAILBOX_CMD_SIZE);
  2068. } else {
  2069. /* First copy command data */
  2070. lpfc_memcpy_from_slim(mb, phba->MBslimaddr,
  2071. MAILBOX_CMD_SIZE);
  2072. if ((mb->mbxCommand == MBX_DUMP_MEMORY) &&
  2073. pmbox->context2) {
  2074. lpfc_memcpy_from_slim((void *)pmbox->context2,
  2075. phba->MBslimaddr + DMP_RSP_OFFSET,
  2076. mb->un.varDmp.word_cnt);
  2077. }
  2078. }
  2079. writel(HA_MBATT, phba->HAregaddr);
  2080. readl(phba->HAregaddr); /* flush */
  2081. psli->sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
  2082. status = mb->mbxStatus;
  2083. }
  2084. spin_unlock_irqrestore(phba->host->host_lock, drvr_flag);
  2085. return (status);
  2086. }
  2087. static int
  2088. lpfc_sli_ringtx_put(struct lpfc_hba * phba, struct lpfc_sli_ring * pring,
  2089. struct lpfc_iocbq * piocb)
  2090. {
  2091. /* Insert the caller's iocb in the txq tail for later processing. */
  2092. list_add_tail(&piocb->list, &pring->txq);
  2093. pring->txq_cnt++;
  2094. return (0);
  2095. }
  2096. static struct lpfc_iocbq *
  2097. lpfc_sli_next_iocb(struct lpfc_hba *phba, struct lpfc_sli_ring *pring,
  2098. struct lpfc_iocbq ** piocb)
  2099. {
  2100. struct lpfc_iocbq * nextiocb;
  2101. nextiocb = lpfc_sli_ringtx_get(phba, pring);
  2102. if (!nextiocb) {
  2103. nextiocb = *piocb;
  2104. *piocb = NULL;
  2105. }
  2106. return nextiocb;
  2107. }
  2108. int
  2109. lpfc_sli_issue_iocb(struct lpfc_hba *phba, struct lpfc_sli_ring *pring,
  2110. struct lpfc_iocbq *piocb, uint32_t flag)
  2111. {
  2112. struct lpfc_iocbq *nextiocb;
  2113. IOCB_t *iocb;
  2114. /* If the PCI channel is in offline state, do not post iocbs. */
  2115. if (unlikely(pci_channel_offline(phba->pcidev)))
  2116. return IOCB_ERROR;
  2117. /*
  2118. * We should never get an IOCB if we are in a < LINK_DOWN state
  2119. */
  2120. if (unlikely(phba->hba_state < LPFC_LINK_DOWN))
  2121. return IOCB_ERROR;
  2122. /*
  2123. * Check to see if we are blocking IOCB processing because of a
  2124. * outstanding mbox command.
  2125. */
  2126. if (unlikely(pring->flag & LPFC_STOP_IOCB_MBX))
  2127. goto iocb_busy;
  2128. if (unlikely(phba->hba_state == LPFC_LINK_DOWN)) {
  2129. /*
  2130. * Only CREATE_XRI, CLOSE_XRI, ABORT_XRI, and QUE_RING_BUF
  2131. * can be issued if the link is not up.
  2132. */
  2133. switch (piocb->iocb.ulpCommand) {
  2134. case CMD_QUE_RING_BUF_CN:
  2135. case CMD_QUE_RING_BUF64_CN:
  2136. /*
  2137. * For IOCBs, like QUE_RING_BUF, that have no rsp ring
  2138. * completion, iocb_cmpl MUST be 0.
  2139. */
  2140. if (piocb->iocb_cmpl)
  2141. piocb->iocb_cmpl = NULL;
  2142. /*FALLTHROUGH*/
  2143. case CMD_CREATE_XRI_CR:
  2144. break;
  2145. default:
  2146. goto iocb_busy;
  2147. }
  2148. /*
  2149. * For FCP commands, we must be in a state where we can process link
  2150. * attention events.
  2151. */
  2152. } else if (unlikely(pring->ringno == phba->sli.fcp_ring &&
  2153. !(phba->sli.sli_flag & LPFC_PROCESS_LA)))
  2154. goto iocb_busy;
  2155. while ((iocb = lpfc_sli_next_iocb_slot(phba, pring)) &&
  2156. (nextiocb = lpfc_sli_next_iocb(phba, pring, &piocb)))
  2157. lpfc_sli_submit_iocb(phba, pring, iocb, nextiocb);
  2158. if (iocb)
  2159. lpfc_sli_update_ring(phba, pring);
  2160. else
  2161. lpfc_sli_update_full_ring(phba, pring);
  2162. if (!piocb)
  2163. return IOCB_SUCCESS;
  2164. goto out_busy;
  2165. iocb_busy:
  2166. pring->stats.iocb_cmd_delay++;
  2167. out_busy:
  2168. if (!(flag & SLI_IOCB_RET_IOCB)) {
  2169. lpfc_sli_ringtx_put(phba, pring, piocb);
  2170. return IOCB_SUCCESS;
  2171. }
  2172. return IOCB_BUSY;
  2173. }
  2174. static int
  2175. lpfc_extra_ring_setup( struct lpfc_hba *phba)
  2176. {
  2177. struct lpfc_sli *psli;
  2178. struct lpfc_sli_ring *pring;
  2179. psli = &phba->sli;
  2180. /* Adjust cmd/rsp ring iocb entries more evenly */
  2181. /* Take some away from the FCP ring */
  2182. pring = &psli->ring[psli->fcp_ring];
  2183. pring->numCiocb -= SLI2_IOCB_CMD_R1XTRA_ENTRIES;
  2184. pring->numRiocb -= SLI2_IOCB_RSP_R1XTRA_ENTRIES;
  2185. pring->numCiocb -= SLI2_IOCB_CMD_R3XTRA_ENTRIES;
  2186. pring->numRiocb -= SLI2_IOCB_RSP_R3XTRA_ENTRIES;
  2187. /* and give them to the extra ring */
  2188. pring = &psli->ring[psli->extra_ring];
  2189. pring->numCiocb += SLI2_IOCB_CMD_R1XTRA_ENTRIES;
  2190. pring->numRiocb += SLI2_IOCB_RSP_R1XTRA_ENTRIES;
  2191. pring->numCiocb += SLI2_IOCB_CMD_R3XTRA_ENTRIES;
  2192. pring->numRiocb += SLI2_IOCB_RSP_R3XTRA_ENTRIES;
  2193. /* Setup default profile for this ring */
  2194. pring->iotag_max = 4096;
  2195. pring->num_mask = 1;
  2196. pring->prt[0].profile = 0; /* Mask 0 */
  2197. pring->prt[0].rctl = phba->cfg_multi_ring_rctl;
  2198. pring->prt[0].type = phba->cfg_multi_ring_type;
  2199. pring->prt[0].lpfc_sli_rcv_unsol_event = NULL;
  2200. return 0;
  2201. }
  2202. int
  2203. lpfc_sli_setup(struct lpfc_hba *phba)
  2204. {
  2205. int i, totiocb = 0;
  2206. struct lpfc_sli *psli = &phba->sli;
  2207. struct lpfc_sli_ring *pring;
  2208. psli->num_rings = MAX_CONFIGURED_RINGS;
  2209. psli->sli_flag = 0;
  2210. psli->fcp_ring = LPFC_FCP_RING;
  2211. psli->next_ring = LPFC_FCP_NEXT_RING;
  2212. psli->extra_ring = LPFC_EXTRA_RING;
  2213. psli->iocbq_lookup = NULL;
  2214. psli->iocbq_lookup_len = 0;
  2215. psli->last_iotag = 0;
  2216. for (i = 0; i < psli->num_rings; i++) {
  2217. pring = &psli->ring[i];
  2218. switch (i) {
  2219. case LPFC_FCP_RING: /* ring 0 - FCP */
  2220. /* numCiocb and numRiocb are used in config_port */
  2221. pring->numCiocb = SLI2_IOCB_CMD_R0_ENTRIES;
  2222. pring->numRiocb = SLI2_IOCB_RSP_R0_ENTRIES;
  2223. pring->numCiocb += SLI2_IOCB_CMD_R1XTRA_ENTRIES;
  2224. pring->numRiocb += SLI2_IOCB_RSP_R1XTRA_ENTRIES;
  2225. pring->numCiocb += SLI2_IOCB_CMD_R3XTRA_ENTRIES;
  2226. pring->numRiocb += SLI2_IOCB_RSP_R3XTRA_ENTRIES;
  2227. pring->iotag_ctr = 0;
  2228. pring->iotag_max =
  2229. (phba->cfg_hba_queue_depth * 2);
  2230. pring->fast_iotag = pring->iotag_max;
  2231. pring->num_mask = 0;
  2232. break;
  2233. case LPFC_EXTRA_RING: /* ring 1 - EXTRA */
  2234. /* numCiocb and numRiocb are used in config_port */
  2235. pring->numCiocb = SLI2_IOCB_CMD_R1_ENTRIES;
  2236. pring->numRiocb = SLI2_IOCB_RSP_R1_ENTRIES;
  2237. pring->num_mask = 0;
  2238. break;
  2239. case LPFC_ELS_RING: /* ring 2 - ELS / CT */
  2240. /* numCiocb and numRiocb are used in config_port */
  2241. pring->numCiocb = SLI2_IOCB_CMD_R2_ENTRIES;
  2242. pring->numRiocb = SLI2_IOCB_RSP_R2_ENTRIES;
  2243. pring->fast_iotag = 0;
  2244. pring->iotag_ctr = 0;
  2245. pring->iotag_max = 4096;
  2246. pring->num_mask = 4;
  2247. pring->prt[0].profile = 0; /* Mask 0 */
  2248. pring->prt[0].rctl = FC_ELS_REQ;
  2249. pring->prt[0].type = FC_ELS_DATA;
  2250. pring->prt[0].lpfc_sli_rcv_unsol_event =
  2251. lpfc_els_unsol_event;
  2252. pring->prt[1].profile = 0; /* Mask 1 */
  2253. pring->prt[1].rctl = FC_ELS_RSP;
  2254. pring->prt[1].type = FC_ELS_DATA;
  2255. pring->prt[1].lpfc_sli_rcv_unsol_event =
  2256. lpfc_els_unsol_event;
  2257. pring->prt[2].profile = 0; /* Mask 2 */
  2258. /* NameServer Inquiry */
  2259. pring->prt[2].rctl = FC_UNSOL_CTL;
  2260. /* NameServer */
  2261. pring->prt[2].type = FC_COMMON_TRANSPORT_ULP;
  2262. pring->prt[2].lpfc_sli_rcv_unsol_event =
  2263. lpfc_ct_unsol_event;
  2264. pring->prt[3].profile = 0; /* Mask 3 */
  2265. /* NameServer response */
  2266. pring->prt[3].rctl = FC_SOL_CTL;
  2267. /* NameServer */
  2268. pring->prt[3].type = FC_COMMON_TRANSPORT_ULP;
  2269. pring->prt[3].lpfc_sli_rcv_unsol_event =
  2270. lpfc_ct_unsol_event;
  2271. break;
  2272. }
  2273. totiocb += (pring->numCiocb + pring->numRiocb);
  2274. }
  2275. if (totiocb > MAX_SLI2_IOCB) {
  2276. /* Too many cmd / rsp ring entries in SLI2 SLIM */
  2277. lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
  2278. "%d:0462 Too many cmd / rsp ring entries in "
  2279. "SLI2 SLIM Data: x%x x%x\n",
  2280. phba->brd_no, totiocb, MAX_SLI2_IOCB);
  2281. }
  2282. if (phba->cfg_multi_ring_support == 2)
  2283. lpfc_extra_ring_setup(phba);
  2284. return 0;
  2285. }
  2286. int
  2287. lpfc_sli_queue_setup(struct lpfc_hba * phba)
  2288. {
  2289. struct lpfc_sli *psli;
  2290. struct lpfc_sli_ring *pring;
  2291. int i;
  2292. psli = &phba->sli;
  2293. spin_lock_irq(phba->host->host_lock);
  2294. INIT_LIST_HEAD(&psli->mboxq);
  2295. /* Initialize list headers for txq and txcmplq as double linked lists */
  2296. for (i = 0; i < psli->num_rings; i++) {
  2297. pring = &psli->ring[i];
  2298. pring->ringno = i;
  2299. pring->next_cmdidx = 0;
  2300. pring->local_getidx = 0;
  2301. pring->cmdidx = 0;
  2302. INIT_LIST_HEAD(&pring->txq);
  2303. INIT_LIST_HEAD(&pring->txcmplq);
  2304. INIT_LIST_HEAD(&pring->iocb_continueq);
  2305. INIT_LIST_HEAD(&pring->postbufq);
  2306. }
  2307. spin_unlock_irq(phba->host->host_lock);
  2308. return (1);
  2309. }
  2310. int
  2311. lpfc_sli_hba_down(struct lpfc_hba * phba)
  2312. {
  2313. struct lpfc_sli *psli;
  2314. struct lpfc_sli_ring *pring;
  2315. LPFC_MBOXQ_t *pmb;
  2316. struct lpfc_iocbq *iocb, *next_iocb;
  2317. IOCB_t *icmd = NULL;
  2318. int i;
  2319. unsigned long flags = 0;
  2320. psli = &phba->sli;
  2321. lpfc_hba_down_prep(phba);
  2322. spin_lock_irqsave(phba->host->host_lock, flags);
  2323. for (i = 0; i < psli->num_rings; i++) {
  2324. pring = &psli->ring[i];
  2325. pring->flag |= LPFC_DEFERRED_RING_EVENT;
  2326. /*
  2327. * Error everything on the txq since these iocbs have not been
  2328. * given to the FW yet.
  2329. */
  2330. pring->txq_cnt = 0;
  2331. list_for_each_entry_safe(iocb, next_iocb, &pring->txq, list) {
  2332. list_del_init(&iocb->list);
  2333. if (iocb->iocb_cmpl) {
  2334. icmd = &iocb->iocb;
  2335. icmd->ulpStatus = IOSTAT_LOCAL_REJECT;
  2336. icmd->un.ulpWord[4] = IOERR_SLI_DOWN;
  2337. spin_unlock_irqrestore(phba->host->host_lock,
  2338. flags);
  2339. (iocb->iocb_cmpl) (phba, iocb, iocb);
  2340. spin_lock_irqsave(phba->host->host_lock, flags);
  2341. } else
  2342. lpfc_sli_release_iocbq(phba, iocb);
  2343. }
  2344. INIT_LIST_HEAD(&(pring->txq));
  2345. }
  2346. spin_unlock_irqrestore(phba->host->host_lock, flags);
  2347. /* Return any active mbox cmds */
  2348. del_timer_sync(&psli->mbox_tmo);
  2349. spin_lock_irqsave(phba->host->host_lock, flags);
  2350. phba->work_hba_events &= ~WORKER_MBOX_TMO;
  2351. if (psli->mbox_active) {
  2352. pmb = psli->mbox_active;
  2353. pmb->mb.mbxStatus = MBX_NOT_FINISHED;
  2354. if (pmb->mbox_cmpl) {
  2355. spin_unlock_irqrestore(phba->host->host_lock, flags);
  2356. pmb->mbox_cmpl(phba,pmb);
  2357. spin_lock_irqsave(phba->host->host_lock, flags);
  2358. }
  2359. }
  2360. psli->sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
  2361. psli->mbox_active = NULL;
  2362. /* Return any pending mbox cmds */
  2363. while ((pmb = lpfc_mbox_get(phba)) != NULL) {
  2364. pmb->mb.mbxStatus = MBX_NOT_FINISHED;
  2365. if (pmb->mbox_cmpl) {
  2366. spin_unlock_irqrestore(phba->host->host_lock, flags);
  2367. pmb->mbox_cmpl(phba,pmb);
  2368. spin_lock_irqsave(phba->host->host_lock, flags);
  2369. }
  2370. }
  2371. INIT_LIST_HEAD(&psli->mboxq);
  2372. spin_unlock_irqrestore(phba->host->host_lock, flags);
  2373. return 1;
  2374. }
  2375. void
  2376. lpfc_sli_pcimem_bcopy(void *srcp, void *destp, uint32_t cnt)
  2377. {
  2378. uint32_t *src = srcp;
  2379. uint32_t *dest = destp;
  2380. uint32_t ldata;
  2381. int i;
  2382. for (i = 0; i < (int)cnt; i += sizeof (uint32_t)) {
  2383. ldata = *src;
  2384. ldata = le32_to_cpu(ldata);
  2385. *dest = ldata;
  2386. src++;
  2387. dest++;
  2388. }
  2389. }
  2390. int
  2391. lpfc_sli_ringpostbuf_put(struct lpfc_hba * phba, struct lpfc_sli_ring * pring,
  2392. struct lpfc_dmabuf * mp)
  2393. {
  2394. /* Stick struct lpfc_dmabuf at end of postbufq so driver can look it up
  2395. later */
  2396. list_add_tail(&mp->list, &pring->postbufq);
  2397. pring->postbufq_cnt++;
  2398. return 0;
  2399. }
  2400. struct lpfc_dmabuf *
  2401. lpfc_sli_ringpostbuf_get(struct lpfc_hba *phba, struct lpfc_sli_ring *pring,
  2402. dma_addr_t phys)
  2403. {
  2404. struct lpfc_dmabuf *mp, *next_mp;
  2405. struct list_head *slp = &pring->postbufq;
  2406. /* Search postbufq, from the begining, looking for a match on phys */
  2407. list_for_each_entry_safe(mp, next_mp, &pring->postbufq, list) {
  2408. if (mp->phys == phys) {
  2409. list_del_init(&mp->list);
  2410. pring->postbufq_cnt--;
  2411. return mp;
  2412. }
  2413. }
  2414. lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
  2415. "%d:0410 Cannot find virtual addr for mapped buf on "
  2416. "ring %d Data x%llx x%p x%p x%x\n",
  2417. phba->brd_no, pring->ringno, (unsigned long long)phys,
  2418. slp->next, slp->prev, pring->postbufq_cnt);
  2419. return NULL;
  2420. }
  2421. static void
  2422. lpfc_sli_abort_elsreq_cmpl(struct lpfc_hba * phba, struct lpfc_iocbq * cmdiocb,
  2423. struct lpfc_iocbq * rspiocb)
  2424. {
  2425. struct lpfc_dmabuf *buf_ptr, *buf_ptr1;
  2426. /* Free the resources associated with the ELS_REQUEST64 IOCB the driver
  2427. * just aborted.
  2428. * In this case, context2 = cmd, context2->next = rsp, context3 = bpl
  2429. */
  2430. if (cmdiocb->context2) {
  2431. buf_ptr1 = (struct lpfc_dmabuf *) cmdiocb->context2;
  2432. /* Free the response IOCB before completing the abort
  2433. command. */
  2434. buf_ptr = NULL;
  2435. list_remove_head((&buf_ptr1->list), buf_ptr,
  2436. struct lpfc_dmabuf, list);
  2437. if (buf_ptr) {
  2438. lpfc_mbuf_free(phba, buf_ptr->virt, buf_ptr->phys);
  2439. kfree(buf_ptr);
  2440. }
  2441. lpfc_mbuf_free(phba, buf_ptr1->virt, buf_ptr1->phys);
  2442. kfree(buf_ptr1);
  2443. }
  2444. if (cmdiocb->context3) {
  2445. buf_ptr = (struct lpfc_dmabuf *) cmdiocb->context3;
  2446. lpfc_mbuf_free(phba, buf_ptr->virt, buf_ptr->phys);
  2447. kfree(buf_ptr);
  2448. }
  2449. lpfc_sli_release_iocbq(phba, cmdiocb);
  2450. return;
  2451. }
  2452. int
  2453. lpfc_sli_issue_abort_iotag32(struct lpfc_hba * phba,
  2454. struct lpfc_sli_ring * pring,
  2455. struct lpfc_iocbq * cmdiocb)
  2456. {
  2457. struct lpfc_iocbq *abtsiocbp;
  2458. IOCB_t *icmd = NULL;
  2459. IOCB_t *iabt = NULL;
  2460. /* issue ABTS for this IOCB based on iotag */
  2461. abtsiocbp = lpfc_sli_get_iocbq(phba);
  2462. if (abtsiocbp == NULL)
  2463. return 0;
  2464. iabt = &abtsiocbp->iocb;
  2465. icmd = &cmdiocb->iocb;
  2466. switch (icmd->ulpCommand) {
  2467. case CMD_ELS_REQUEST64_CR:
  2468. /* Even though we abort the ELS command, the firmware may access
  2469. * the BPL or other resources before it processes our
  2470. * ABORT_MXRI64. Thus we must delay reusing the cmdiocb
  2471. * resources till the actual abort request completes.
  2472. */
  2473. abtsiocbp->context1 = (void *)((unsigned long)icmd->ulpCommand);
  2474. abtsiocbp->context2 = cmdiocb->context2;
  2475. abtsiocbp->context3 = cmdiocb->context3;
  2476. cmdiocb->context2 = NULL;
  2477. cmdiocb->context3 = NULL;
  2478. abtsiocbp->iocb_cmpl = lpfc_sli_abort_elsreq_cmpl;
  2479. break;
  2480. default:
  2481. lpfc_sli_release_iocbq(phba, abtsiocbp);
  2482. return 0;
  2483. }
  2484. iabt->un.amxri.abortType = ABORT_TYPE_ABTS;
  2485. iabt->un.amxri.iotag32 = icmd->un.elsreq64.bdl.ulpIoTag32;
  2486. iabt->ulpLe = 1;
  2487. iabt->ulpClass = CLASS3;
  2488. iabt->ulpCommand = CMD_ABORT_MXRI64_CN;
  2489. if (lpfc_sli_issue_iocb(phba, pring, abtsiocbp, 0) == IOCB_ERROR) {
  2490. lpfc_sli_release_iocbq(phba, abtsiocbp);
  2491. return 0;
  2492. }
  2493. return 1;
  2494. }
  2495. static int
  2496. lpfc_sli_validate_fcp_iocb(struct lpfc_iocbq *iocbq, uint16_t tgt_id,
  2497. uint64_t lun_id, uint32_t ctx,
  2498. lpfc_ctx_cmd ctx_cmd)
  2499. {
  2500. struct lpfc_scsi_buf *lpfc_cmd;
  2501. struct scsi_cmnd *cmnd;
  2502. int rc = 1;
  2503. if (!(iocbq->iocb_flag & LPFC_IO_FCP))
  2504. return rc;
  2505. lpfc_cmd = container_of(iocbq, struct lpfc_scsi_buf, cur_iocbq);
  2506. cmnd = lpfc_cmd->pCmd;
  2507. if (cmnd == NULL)
  2508. return rc;
  2509. switch (ctx_cmd) {
  2510. case LPFC_CTX_LUN:
  2511. if ((cmnd->device->id == tgt_id) &&
  2512. (cmnd->device->lun == lun_id))
  2513. rc = 0;
  2514. break;
  2515. case LPFC_CTX_TGT:
  2516. if (cmnd->device->id == tgt_id)
  2517. rc = 0;
  2518. break;
  2519. case LPFC_CTX_CTX:
  2520. if (iocbq->iocb.ulpContext == ctx)
  2521. rc = 0;
  2522. break;
  2523. case LPFC_CTX_HOST:
  2524. rc = 0;
  2525. break;
  2526. default:
  2527. printk(KERN_ERR "%s: Unknown context cmd type, value %d\n",
  2528. __FUNCTION__, ctx_cmd);
  2529. break;
  2530. }
  2531. return rc;
  2532. }
  2533. int
  2534. lpfc_sli_sum_iocb(struct lpfc_hba *phba, struct lpfc_sli_ring *pring,
  2535. uint16_t tgt_id, uint64_t lun_id, lpfc_ctx_cmd ctx_cmd)
  2536. {
  2537. struct lpfc_iocbq *iocbq;
  2538. int sum, i;
  2539. for (i = 1, sum = 0; i <= phba->sli.last_iotag; i++) {
  2540. iocbq = phba->sli.iocbq_lookup[i];
  2541. if (lpfc_sli_validate_fcp_iocb (iocbq, tgt_id, lun_id,
  2542. 0, ctx_cmd) == 0)
  2543. sum++;
  2544. }
  2545. return sum;
  2546. }
  2547. void
  2548. lpfc_sli_abort_fcp_cmpl(struct lpfc_hba * phba, struct lpfc_iocbq * cmdiocb,
  2549. struct lpfc_iocbq * rspiocb)
  2550. {
  2551. spin_lock_irq(phba->host->host_lock);
  2552. lpfc_sli_release_iocbq(phba, cmdiocb);
  2553. spin_unlock_irq(phba->host->host_lock);
  2554. return;
  2555. }
  2556. int
  2557. lpfc_sli_abort_iocb(struct lpfc_hba *phba, struct lpfc_sli_ring *pring,
  2558. uint16_t tgt_id, uint64_t lun_id, uint32_t ctx,
  2559. lpfc_ctx_cmd abort_cmd)
  2560. {
  2561. struct lpfc_iocbq *iocbq;
  2562. struct lpfc_iocbq *abtsiocb;
  2563. IOCB_t *cmd = NULL;
  2564. int errcnt = 0, ret_val = 0;
  2565. int i;
  2566. for (i = 1; i <= phba->sli.last_iotag; i++) {
  2567. iocbq = phba->sli.iocbq_lookup[i];
  2568. if (lpfc_sli_validate_fcp_iocb (iocbq, tgt_id, lun_id,
  2569. 0, abort_cmd) != 0)
  2570. continue;
  2571. /* issue ABTS for this IOCB based on iotag */
  2572. abtsiocb = lpfc_sli_get_iocbq(phba);
  2573. if (abtsiocb == NULL) {
  2574. errcnt++;
  2575. continue;
  2576. }
  2577. cmd = &iocbq->iocb;
  2578. abtsiocb->iocb.un.acxri.abortType = ABORT_TYPE_ABTS;
  2579. abtsiocb->iocb.un.acxri.abortContextTag = cmd->ulpContext;
  2580. abtsiocb->iocb.un.acxri.abortIoTag = cmd->ulpIoTag;
  2581. abtsiocb->iocb.ulpLe = 1;
  2582. abtsiocb->iocb.ulpClass = cmd->ulpClass;
  2583. if (phba->hba_state >= LPFC_LINK_UP)
  2584. abtsiocb->iocb.ulpCommand = CMD_ABORT_XRI_CN;
  2585. else
  2586. abtsiocb->iocb.ulpCommand = CMD_CLOSE_XRI_CN;
  2587. /* Setup callback routine and issue the command. */
  2588. abtsiocb->iocb_cmpl = lpfc_sli_abort_fcp_cmpl;
  2589. ret_val = lpfc_sli_issue_iocb(phba, pring, abtsiocb, 0);
  2590. if (ret_val == IOCB_ERROR) {
  2591. lpfc_sli_release_iocbq(phba, abtsiocb);
  2592. errcnt++;
  2593. continue;
  2594. }
  2595. }
  2596. return errcnt;
  2597. }
  2598. static void
  2599. lpfc_sli_wake_iocb_wait(struct lpfc_hba *phba,
  2600. struct lpfc_iocbq *cmdiocbq,
  2601. struct lpfc_iocbq *rspiocbq)
  2602. {
  2603. wait_queue_head_t *pdone_q;
  2604. unsigned long iflags;
  2605. spin_lock_irqsave(phba->host->host_lock, iflags);
  2606. cmdiocbq->iocb_flag |= LPFC_IO_WAKE;
  2607. if (cmdiocbq->context2 && rspiocbq)
  2608. memcpy(&((struct lpfc_iocbq *)cmdiocbq->context2)->iocb,
  2609. &rspiocbq->iocb, sizeof(IOCB_t));
  2610. pdone_q = cmdiocbq->context_un.wait_queue;
  2611. spin_unlock_irqrestore(phba->host->host_lock, iflags);
  2612. if (pdone_q)
  2613. wake_up(pdone_q);
  2614. return;
  2615. }
  2616. /*
  2617. * Issue the caller's iocb and wait for its completion, but no longer than the
  2618. * caller's timeout. Note that iocb_flags is cleared before the
  2619. * lpfc_sli_issue_call since the wake routine sets a unique value and by
  2620. * definition this is a wait function.
  2621. */
  2622. int
  2623. lpfc_sli_issue_iocb_wait(struct lpfc_hba * phba,
  2624. struct lpfc_sli_ring * pring,
  2625. struct lpfc_iocbq * piocb,
  2626. struct lpfc_iocbq * prspiocbq,
  2627. uint32_t timeout)
  2628. {
  2629. DECLARE_WAIT_QUEUE_HEAD_ONSTACK(done_q);
  2630. long timeleft, timeout_req = 0;
  2631. int retval = IOCB_SUCCESS;
  2632. uint32_t creg_val;
  2633. /*
  2634. * If the caller has provided a response iocbq buffer, then context2
  2635. * is NULL or its an error.
  2636. */
  2637. if (prspiocbq) {
  2638. if (piocb->context2)
  2639. return IOCB_ERROR;
  2640. piocb->context2 = prspiocbq;
  2641. }
  2642. piocb->iocb_cmpl = lpfc_sli_wake_iocb_wait;
  2643. piocb->context_un.wait_queue = &done_q;
  2644. piocb->iocb_flag &= ~LPFC_IO_WAKE;
  2645. if (phba->cfg_poll & DISABLE_FCP_RING_INT) {
  2646. creg_val = readl(phba->HCregaddr);
  2647. creg_val |= (HC_R0INT_ENA << LPFC_FCP_RING);
  2648. writel(creg_val, phba->HCregaddr);
  2649. readl(phba->HCregaddr); /* flush */
  2650. }
  2651. retval = lpfc_sli_issue_iocb(phba, pring, piocb, 0);
  2652. if (retval == IOCB_SUCCESS) {
  2653. timeout_req = timeout * HZ;
  2654. spin_unlock_irq(phba->host->host_lock);
  2655. timeleft = wait_event_timeout(done_q,
  2656. piocb->iocb_flag & LPFC_IO_WAKE,
  2657. timeout_req);
  2658. spin_lock_irq(phba->host->host_lock);
  2659. if (timeleft == 0) {
  2660. lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
  2661. "%d:0338 IOCB wait timeout error - no "
  2662. "wake response Data x%x\n",
  2663. phba->brd_no, timeout);
  2664. retval = IOCB_TIMEDOUT;
  2665. } else if (!(piocb->iocb_flag & LPFC_IO_WAKE)) {
  2666. lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
  2667. "%d:0330 IOCB wake NOT set, "
  2668. "Data x%x x%lx\n", phba->brd_no,
  2669. timeout, (timeleft / jiffies));
  2670. retval = IOCB_TIMEDOUT;
  2671. } else {
  2672. lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
  2673. "%d:0331 IOCB wake signaled\n",
  2674. phba->brd_no);
  2675. }
  2676. } else {
  2677. lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
  2678. "%d:0332 IOCB wait issue failed, Data x%x\n",
  2679. phba->brd_no, retval);
  2680. retval = IOCB_ERROR;
  2681. }
  2682. if (phba->cfg_poll & DISABLE_FCP_RING_INT) {
  2683. creg_val = readl(phba->HCregaddr);
  2684. creg_val &= ~(HC_R0INT_ENA << LPFC_FCP_RING);
  2685. writel(creg_val, phba->HCregaddr);
  2686. readl(phba->HCregaddr); /* flush */
  2687. }
  2688. if (prspiocbq)
  2689. piocb->context2 = NULL;
  2690. piocb->context_un.wait_queue = NULL;
  2691. piocb->iocb_cmpl = NULL;
  2692. return retval;
  2693. }
  2694. int
  2695. lpfc_sli_issue_mbox_wait(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmboxq,
  2696. uint32_t timeout)
  2697. {
  2698. DECLARE_WAIT_QUEUE_HEAD_ONSTACK(done_q);
  2699. DECLARE_WAITQUEUE(wq_entry, current);
  2700. uint32_t timeleft = 0;
  2701. int retval;
  2702. /* The caller must leave context1 empty. */
  2703. if (pmboxq->context1 != 0) {
  2704. return (MBX_NOT_FINISHED);
  2705. }
  2706. /* setup wake call as IOCB callback */
  2707. pmboxq->mbox_cmpl = lpfc_sli_wake_mbox_wait;
  2708. /* setup context field to pass wait_queue pointer to wake function */
  2709. pmboxq->context1 = &done_q;
  2710. /* start to sleep before we wait, to avoid races */
  2711. set_current_state(TASK_INTERRUPTIBLE);
  2712. add_wait_queue(&done_q, &wq_entry);
  2713. /* now issue the command */
  2714. retval = lpfc_sli_issue_mbox(phba, pmboxq, MBX_NOWAIT);
  2715. if (retval == MBX_BUSY || retval == MBX_SUCCESS) {
  2716. timeleft = schedule_timeout(timeout * HZ);
  2717. pmboxq->context1 = NULL;
  2718. /* if schedule_timeout returns 0, we timed out and were not
  2719. woken up */
  2720. if ((timeleft == 0) || signal_pending(current))
  2721. retval = MBX_TIMEOUT;
  2722. else
  2723. retval = MBX_SUCCESS;
  2724. }
  2725. set_current_state(TASK_RUNNING);
  2726. remove_wait_queue(&done_q, &wq_entry);
  2727. return retval;
  2728. }
  2729. int
  2730. lpfc_sli_flush_mbox_queue(struct lpfc_hba * phba)
  2731. {
  2732. int i = 0;
  2733. while (phba->sli.sli_flag & LPFC_SLI_MBOX_ACTIVE && !phba->stopped) {
  2734. if (i++ > LPFC_MBOX_TMO * 1000)
  2735. return 1;
  2736. if (lpfc_sli_handle_mb_event(phba) == 0)
  2737. i = 0;
  2738. msleep(1);
  2739. }
  2740. return (phba->sli.sli_flag & LPFC_SLI_MBOX_ACTIVE) ? 1 : 0;
  2741. }
  2742. irqreturn_t
  2743. lpfc_intr_handler(int irq, void *dev_id)
  2744. {
  2745. struct lpfc_hba *phba;
  2746. uint32_t ha_copy;
  2747. uint32_t work_ha_copy;
  2748. unsigned long status;
  2749. int i;
  2750. uint32_t control;
  2751. /*
  2752. * Get the driver's phba structure from the dev_id and
  2753. * assume the HBA is not interrupting.
  2754. */
  2755. phba = (struct lpfc_hba *) dev_id;
  2756. if (unlikely(!phba))
  2757. return IRQ_NONE;
  2758. /* If the pci channel is offline, ignore all the interrupts. */
  2759. if (unlikely(pci_channel_offline(phba->pcidev)))
  2760. return IRQ_NONE;
  2761. phba->sli.slistat.sli_intr++;
  2762. /*
  2763. * Call the HBA to see if it is interrupting. If not, don't claim
  2764. * the interrupt
  2765. */
  2766. /* Ignore all interrupts during initialization. */
  2767. if (unlikely(phba->hba_state < LPFC_LINK_DOWN))
  2768. return IRQ_NONE;
  2769. /*
  2770. * Read host attention register to determine interrupt source
  2771. * Clear Attention Sources, except Error Attention (to
  2772. * preserve status) and Link Attention
  2773. */
  2774. spin_lock(phba->host->host_lock);
  2775. ha_copy = readl(phba->HAregaddr);
  2776. writel((ha_copy & ~(HA_LATT | HA_ERATT)), phba->HAregaddr);
  2777. readl(phba->HAregaddr); /* flush */
  2778. spin_unlock(phba->host->host_lock);
  2779. if (unlikely(!ha_copy))
  2780. return IRQ_NONE;
  2781. work_ha_copy = ha_copy & phba->work_ha_mask;
  2782. if (unlikely(work_ha_copy)) {
  2783. if (work_ha_copy & HA_LATT) {
  2784. if (phba->sli.sli_flag & LPFC_PROCESS_LA) {
  2785. /*
  2786. * Turn off Link Attention interrupts
  2787. * until CLEAR_LA done
  2788. */
  2789. spin_lock(phba->host->host_lock);
  2790. phba->sli.sli_flag &= ~LPFC_PROCESS_LA;
  2791. control = readl(phba->HCregaddr);
  2792. control &= ~HC_LAINT_ENA;
  2793. writel(control, phba->HCregaddr);
  2794. readl(phba->HCregaddr); /* flush */
  2795. spin_unlock(phba->host->host_lock);
  2796. }
  2797. else
  2798. work_ha_copy &= ~HA_LATT;
  2799. }
  2800. if (work_ha_copy & ~(HA_ERATT|HA_MBATT|HA_LATT)) {
  2801. for (i = 0; i < phba->sli.num_rings; i++) {
  2802. if (work_ha_copy & (HA_RXATT << (4*i))) {
  2803. /*
  2804. * Turn off Slow Rings interrupts
  2805. */
  2806. spin_lock(phba->host->host_lock);
  2807. control = readl(phba->HCregaddr);
  2808. control &= ~(HC_R0INT_ENA << i);
  2809. writel(control, phba->HCregaddr);
  2810. readl(phba->HCregaddr); /* flush */
  2811. spin_unlock(phba->host->host_lock);
  2812. }
  2813. }
  2814. }
  2815. if (work_ha_copy & HA_ERATT) {
  2816. phba->hba_state = LPFC_HBA_ERROR;
  2817. /*
  2818. * There was a link/board error. Read the
  2819. * status register to retrieve the error event
  2820. * and process it.
  2821. */
  2822. phba->sli.slistat.err_attn_event++;
  2823. /* Save status info */
  2824. phba->work_hs = readl(phba->HSregaddr);
  2825. phba->work_status[0] = readl(phba->MBslimaddr + 0xa8);
  2826. phba->work_status[1] = readl(phba->MBslimaddr + 0xac);
  2827. /* Clear Chip error bit */
  2828. writel(HA_ERATT, phba->HAregaddr);
  2829. readl(phba->HAregaddr); /* flush */
  2830. phba->stopped = 1;
  2831. }
  2832. spin_lock(phba->host->host_lock);
  2833. phba->work_ha |= work_ha_copy;
  2834. if (phba->work_wait)
  2835. wake_up(phba->work_wait);
  2836. spin_unlock(phba->host->host_lock);
  2837. }
  2838. ha_copy &= ~(phba->work_ha_mask);
  2839. /*
  2840. * Process all events on FCP ring. Take the optimized path for
  2841. * FCP IO. Any other IO is slow path and is handled by
  2842. * the worker thread.
  2843. */
  2844. status = (ha_copy & (HA_RXMASK << (4*LPFC_FCP_RING)));
  2845. status >>= (4*LPFC_FCP_RING);
  2846. if (status & HA_RXATT)
  2847. lpfc_sli_handle_fast_ring_event(phba,
  2848. &phba->sli.ring[LPFC_FCP_RING],
  2849. status);
  2850. if (phba->cfg_multi_ring_support == 2) {
  2851. /*
  2852. * Process all events on extra ring. Take the optimized path
  2853. * for extra ring IO. Any other IO is slow path and is handled
  2854. * by the worker thread.
  2855. */
  2856. status = (ha_copy & (HA_RXMASK << (4*LPFC_EXTRA_RING)));
  2857. status >>= (4*LPFC_EXTRA_RING);
  2858. if (status & HA_RXATT) {
  2859. lpfc_sli_handle_fast_ring_event(phba,
  2860. &phba->sli.ring[LPFC_EXTRA_RING],
  2861. status);
  2862. }
  2863. }
  2864. return IRQ_HANDLED;
  2865. } /* lpfc_intr_handler */