s3c-pcm.c 12 KB

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  1. /* sound/soc/s3c24xx/s3c-pcm.c
  2. *
  3. * ALSA SoC Audio Layer - S3C PCM-Controller driver
  4. *
  5. * Copyright (c) 2009 Samsung Electronics Co. Ltd
  6. * Author: Jaswinder Singh <jassi.brar@samsung.com>
  7. * based upon I2S drivers by Ben Dooks.
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/init.h>
  14. #include <linux/module.h>
  15. #include <linux/device.h>
  16. #include <linux/delay.h>
  17. #include <linux/clk.h>
  18. #include <linux/kernel.h>
  19. #include <linux/gpio.h>
  20. #include <linux/io.h>
  21. #include <sound/core.h>
  22. #include <sound/pcm.h>
  23. #include <sound/pcm_params.h>
  24. #include <sound/initval.h>
  25. #include <sound/soc.h>
  26. #include <plat/audio.h>
  27. #include <plat/dma.h>
  28. #include "s3c-dma.h"
  29. #include "s3c-pcm.h"
  30. static struct s3c2410_dma_client s3c_pcm_dma_client_out = {
  31. .name = "PCM Stereo out"
  32. };
  33. static struct s3c2410_dma_client s3c_pcm_dma_client_in = {
  34. .name = "PCM Stereo in"
  35. };
  36. static struct s3c_dma_params s3c_pcm_stereo_out[] = {
  37. [0] = {
  38. .client = &s3c_pcm_dma_client_out,
  39. .dma_size = 4,
  40. },
  41. [1] = {
  42. .client = &s3c_pcm_dma_client_out,
  43. .dma_size = 4,
  44. },
  45. };
  46. static struct s3c_dma_params s3c_pcm_stereo_in[] = {
  47. [0] = {
  48. .client = &s3c_pcm_dma_client_in,
  49. .dma_size = 4,
  50. },
  51. [1] = {
  52. .client = &s3c_pcm_dma_client_in,
  53. .dma_size = 4,
  54. },
  55. };
  56. static struct s3c_pcm_info s3c_pcm[2];
  57. static void s3c_pcm_snd_txctrl(struct s3c_pcm_info *pcm, int on)
  58. {
  59. void __iomem *regs = pcm->regs;
  60. u32 ctl, clkctl;
  61. clkctl = readl(regs + S3C_PCM_CLKCTL);
  62. ctl = readl(regs + S3C_PCM_CTL);
  63. ctl &= ~(S3C_PCM_CTL_TXDIPSTICK_MASK
  64. << S3C_PCM_CTL_TXDIPSTICK_SHIFT);
  65. if (on) {
  66. ctl |= S3C_PCM_CTL_TXDMA_EN;
  67. ctl |= S3C_PCM_CTL_TXFIFO_EN;
  68. ctl |= S3C_PCM_CTL_ENABLE;
  69. ctl |= (0x20<<S3C_PCM_CTL_TXDIPSTICK_SHIFT);
  70. clkctl |= S3C_PCM_CLKCTL_SERCLK_EN;
  71. } else {
  72. ctl &= ~S3C_PCM_CTL_TXDMA_EN;
  73. ctl &= ~S3C_PCM_CTL_TXFIFO_EN;
  74. if (!(ctl & S3C_PCM_CTL_RXFIFO_EN)) {
  75. ctl &= ~S3C_PCM_CTL_ENABLE;
  76. if (!pcm->idleclk)
  77. clkctl |= S3C_PCM_CLKCTL_SERCLK_EN;
  78. }
  79. }
  80. writel(clkctl, regs + S3C_PCM_CLKCTL);
  81. writel(ctl, regs + S3C_PCM_CTL);
  82. }
  83. static void s3c_pcm_snd_rxctrl(struct s3c_pcm_info *pcm, int on)
  84. {
  85. void __iomem *regs = pcm->regs;
  86. u32 ctl, clkctl;
  87. ctl = readl(regs + S3C_PCM_CTL);
  88. clkctl = readl(regs + S3C_PCM_CLKCTL);
  89. if (on) {
  90. ctl |= S3C_PCM_CTL_RXDMA_EN;
  91. ctl |= S3C_PCM_CTL_RXFIFO_EN;
  92. ctl |= S3C_PCM_CTL_ENABLE;
  93. clkctl |= S3C_PCM_CLKCTL_SERCLK_EN;
  94. } else {
  95. ctl &= ~S3C_PCM_CTL_RXDMA_EN;
  96. ctl &= ~S3C_PCM_CTL_RXFIFO_EN;
  97. if (!(ctl & S3C_PCM_CTL_TXFIFO_EN)) {
  98. ctl &= ~S3C_PCM_CTL_ENABLE;
  99. if (!pcm->idleclk)
  100. clkctl |= S3C_PCM_CLKCTL_SERCLK_EN;
  101. }
  102. }
  103. writel(clkctl, regs + S3C_PCM_CLKCTL);
  104. writel(ctl, regs + S3C_PCM_CTL);
  105. }
  106. static int s3c_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
  107. struct snd_soc_dai *dai)
  108. {
  109. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  110. struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(rtd->cpu_dai);
  111. unsigned long flags;
  112. dev_dbg(pcm->dev, "Entered %s\n", __func__);
  113. switch (cmd) {
  114. case SNDRV_PCM_TRIGGER_START:
  115. case SNDRV_PCM_TRIGGER_RESUME:
  116. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  117. spin_lock_irqsave(&pcm->lock, flags);
  118. if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
  119. s3c_pcm_snd_rxctrl(pcm, 1);
  120. else
  121. s3c_pcm_snd_txctrl(pcm, 1);
  122. spin_unlock_irqrestore(&pcm->lock, flags);
  123. break;
  124. case SNDRV_PCM_TRIGGER_STOP:
  125. case SNDRV_PCM_TRIGGER_SUSPEND:
  126. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  127. spin_lock_irqsave(&pcm->lock, flags);
  128. if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
  129. s3c_pcm_snd_rxctrl(pcm, 0);
  130. else
  131. s3c_pcm_snd_txctrl(pcm, 0);
  132. spin_unlock_irqrestore(&pcm->lock, flags);
  133. break;
  134. default:
  135. return -EINVAL;
  136. }
  137. return 0;
  138. }
  139. static int s3c_pcm_hw_params(struct snd_pcm_substream *substream,
  140. struct snd_pcm_hw_params *params,
  141. struct snd_soc_dai *socdai)
  142. {
  143. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  144. struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(rtd->cpu_dai);
  145. struct s3c_dma_params *dma_data;
  146. void __iomem *regs = pcm->regs;
  147. struct clk *clk;
  148. int sclk_div, sync_div;
  149. unsigned long flags;
  150. u32 clkctl;
  151. dev_dbg(pcm->dev, "Entered %s\n", __func__);
  152. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  153. dma_data = pcm->dma_playback;
  154. else
  155. dma_data = pcm->dma_capture;
  156. snd_soc_dai_set_dma_data(rtd->cpu_dai, substream, dma_data);
  157. /* Strictly check for sample size */
  158. switch (params_format(params)) {
  159. case SNDRV_PCM_FORMAT_S16_LE:
  160. break;
  161. default:
  162. return -EINVAL;
  163. }
  164. spin_lock_irqsave(&pcm->lock, flags);
  165. /* Get hold of the PCMSOURCE_CLK */
  166. clkctl = readl(regs + S3C_PCM_CLKCTL);
  167. if (clkctl & S3C_PCM_CLKCTL_SERCLKSEL_PCLK)
  168. clk = pcm->pclk;
  169. else
  170. clk = pcm->cclk;
  171. /* Set the SCLK divider */
  172. sclk_div = clk_get_rate(clk) / pcm->sclk_per_fs /
  173. params_rate(params) / 2 - 1;
  174. clkctl &= ~(S3C_PCM_CLKCTL_SCLKDIV_MASK
  175. << S3C_PCM_CLKCTL_SCLKDIV_SHIFT);
  176. clkctl |= ((sclk_div & S3C_PCM_CLKCTL_SCLKDIV_MASK)
  177. << S3C_PCM_CLKCTL_SCLKDIV_SHIFT);
  178. /* Set the SYNC divider */
  179. sync_div = pcm->sclk_per_fs - 1;
  180. clkctl &= ~(S3C_PCM_CLKCTL_SYNCDIV_MASK
  181. << S3C_PCM_CLKCTL_SYNCDIV_SHIFT);
  182. clkctl |= ((sync_div & S3C_PCM_CLKCTL_SYNCDIV_MASK)
  183. << S3C_PCM_CLKCTL_SYNCDIV_SHIFT);
  184. writel(clkctl, regs + S3C_PCM_CLKCTL);
  185. spin_unlock_irqrestore(&pcm->lock, flags);
  186. dev_dbg(pcm->dev, "PCMSOURCE_CLK-%lu SCLK=%ufs SCLK_DIV=%d SYNC_DIV=%d\n",
  187. clk_get_rate(clk), pcm->sclk_per_fs,
  188. sclk_div, sync_div);
  189. return 0;
  190. }
  191. static int s3c_pcm_set_fmt(struct snd_soc_dai *cpu_dai,
  192. unsigned int fmt)
  193. {
  194. struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(cpu_dai);
  195. void __iomem *regs = pcm->regs;
  196. unsigned long flags;
  197. int ret = 0;
  198. u32 ctl;
  199. dev_dbg(pcm->dev, "Entered %s\n", __func__);
  200. spin_lock_irqsave(&pcm->lock, flags);
  201. ctl = readl(regs + S3C_PCM_CTL);
  202. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  203. case SND_SOC_DAIFMT_NB_NF:
  204. /* Nothing to do, NB_NF by default */
  205. break;
  206. default:
  207. dev_err(pcm->dev, "Unsupported clock inversion!\n");
  208. ret = -EINVAL;
  209. goto exit;
  210. }
  211. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  212. case SND_SOC_DAIFMT_CBS_CFS:
  213. /* Nothing to do, Master by default */
  214. break;
  215. default:
  216. dev_err(pcm->dev, "Unsupported master/slave format!\n");
  217. ret = -EINVAL;
  218. goto exit;
  219. }
  220. switch (fmt & SND_SOC_DAIFMT_CLOCK_MASK) {
  221. case SND_SOC_DAIFMT_CONT:
  222. pcm->idleclk = 1;
  223. break;
  224. case SND_SOC_DAIFMT_GATED:
  225. pcm->idleclk = 0;
  226. break;
  227. default:
  228. dev_err(pcm->dev, "Invalid Clock gating request!\n");
  229. ret = -EINVAL;
  230. goto exit;
  231. }
  232. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  233. case SND_SOC_DAIFMT_DSP_A:
  234. ctl |= S3C_PCM_CTL_TXMSB_AFTER_FSYNC;
  235. ctl |= S3C_PCM_CTL_RXMSB_AFTER_FSYNC;
  236. break;
  237. case SND_SOC_DAIFMT_DSP_B:
  238. ctl &= ~S3C_PCM_CTL_TXMSB_AFTER_FSYNC;
  239. ctl &= ~S3C_PCM_CTL_RXMSB_AFTER_FSYNC;
  240. break;
  241. default:
  242. dev_err(pcm->dev, "Unsupported data format!\n");
  243. ret = -EINVAL;
  244. goto exit;
  245. }
  246. writel(ctl, regs + S3C_PCM_CTL);
  247. exit:
  248. spin_unlock_irqrestore(&pcm->lock, flags);
  249. return ret;
  250. }
  251. static int s3c_pcm_set_clkdiv(struct snd_soc_dai *cpu_dai,
  252. int div_id, int div)
  253. {
  254. struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(cpu_dai);
  255. switch (div_id) {
  256. case S3C_PCM_SCLK_PER_FS:
  257. pcm->sclk_per_fs = div;
  258. break;
  259. default:
  260. return -EINVAL;
  261. }
  262. return 0;
  263. }
  264. static int s3c_pcm_set_sysclk(struct snd_soc_dai *cpu_dai,
  265. int clk_id, unsigned int freq, int dir)
  266. {
  267. struct s3c_pcm_info *pcm = snd_soc_dai_get_drvdata(cpu_dai);
  268. void __iomem *regs = pcm->regs;
  269. u32 clkctl = readl(regs + S3C_PCM_CLKCTL);
  270. switch (clk_id) {
  271. case S3C_PCM_CLKSRC_PCLK:
  272. clkctl |= S3C_PCM_CLKCTL_SERCLKSEL_PCLK;
  273. break;
  274. case S3C_PCM_CLKSRC_MUX:
  275. clkctl &= ~S3C_PCM_CLKCTL_SERCLKSEL_PCLK;
  276. if (clk_get_rate(pcm->cclk) != freq)
  277. clk_set_rate(pcm->cclk, freq);
  278. break;
  279. default:
  280. return -EINVAL;
  281. }
  282. writel(clkctl, regs + S3C_PCM_CLKCTL);
  283. return 0;
  284. }
  285. static struct snd_soc_dai_ops s3c_pcm_dai_ops = {
  286. .set_sysclk = s3c_pcm_set_sysclk,
  287. .set_clkdiv = s3c_pcm_set_clkdiv,
  288. .trigger = s3c_pcm_trigger,
  289. .hw_params = s3c_pcm_hw_params,
  290. .set_fmt = s3c_pcm_set_fmt,
  291. };
  292. #define S3C_PCM_RATES SNDRV_PCM_RATE_8000_96000
  293. #define S3C_PCM_DAI_DECLARE \
  294. { \
  295. .name = "samsung-dai", \
  296. .symmetric_rates = 1, \
  297. .ops = &s3c_pcm_dai_ops, \
  298. .playback = { \
  299. .channels_min = 2, \
  300. .channels_max = 2, \
  301. .rates = S3C_PCM_RATES, \
  302. .formats = SNDRV_PCM_FMTBIT_S16_LE, \
  303. }, \
  304. .capture = { \
  305. .channels_min = 2, \
  306. .channels_max = 2, \
  307. .rates = S3C_PCM_RATES, \
  308. .formats = SNDRV_PCM_FMTBIT_S16_LE, \
  309. }, \
  310. }
  311. struct snd_soc_dai_driver s3c_pcm_dai[] = {
  312. S3C_PCM_DAI_DECLARE,
  313. S3C_PCM_DAI_DECLARE,
  314. };
  315. EXPORT_SYMBOL_GPL(s3c_pcm_dai);
  316. static __devinit int s3c_pcm_dev_probe(struct platform_device *pdev)
  317. {
  318. struct s3c_pcm_info *pcm;
  319. struct resource *mem_res, *dmatx_res, *dmarx_res;
  320. struct s3c_audio_pdata *pcm_pdata;
  321. int ret;
  322. /* Check for valid device index */
  323. if ((pdev->id < 0) || pdev->id >= ARRAY_SIZE(s3c_pcm)) {
  324. dev_err(&pdev->dev, "id %d out of range\n", pdev->id);
  325. return -EINVAL;
  326. }
  327. pcm_pdata = pdev->dev.platform_data;
  328. /* Check for availability of necessary resource */
  329. dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
  330. if (!dmatx_res) {
  331. dev_err(&pdev->dev, "Unable to get PCM-TX dma resource\n");
  332. return -ENXIO;
  333. }
  334. dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
  335. if (!dmarx_res) {
  336. dev_err(&pdev->dev, "Unable to get PCM-RX dma resource\n");
  337. return -ENXIO;
  338. }
  339. mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  340. if (!mem_res) {
  341. dev_err(&pdev->dev, "Unable to get register resource\n");
  342. return -ENXIO;
  343. }
  344. if (pcm_pdata && pcm_pdata->cfg_gpio && pcm_pdata->cfg_gpio(pdev)) {
  345. dev_err(&pdev->dev, "Unable to configure gpio\n");
  346. return -EINVAL;
  347. }
  348. pcm = &s3c_pcm[pdev->id];
  349. pcm->dev = &pdev->dev;
  350. spin_lock_init(&pcm->lock);
  351. /* Default is 128fs */
  352. pcm->sclk_per_fs = 128;
  353. pcm->cclk = clk_get(&pdev->dev, "audio-bus");
  354. if (IS_ERR(pcm->cclk)) {
  355. dev_err(&pdev->dev, "failed to get audio-bus\n");
  356. ret = PTR_ERR(pcm->cclk);
  357. goto err1;
  358. }
  359. clk_enable(pcm->cclk);
  360. /* record our pcm structure for later use in the callbacks */
  361. dev_set_drvdata(&pdev->dev, pcm);
  362. if (!request_mem_region(mem_res->start,
  363. resource_size(mem_res), "samsung-pcm")) {
  364. dev_err(&pdev->dev, "Unable to request register region\n");
  365. ret = -EBUSY;
  366. goto err2;
  367. }
  368. pcm->regs = ioremap(mem_res->start, 0x100);
  369. if (pcm->regs == NULL) {
  370. dev_err(&pdev->dev, "cannot ioremap registers\n");
  371. ret = -ENXIO;
  372. goto err3;
  373. }
  374. pcm->pclk = clk_get(&pdev->dev, "pcm");
  375. if (IS_ERR(pcm->pclk)) {
  376. dev_err(&pdev->dev, "failed to get pcm_clock\n");
  377. ret = -ENOENT;
  378. goto err4;
  379. }
  380. clk_enable(pcm->pclk);
  381. ret = snd_soc_register_dai(&pdev->dev, s3c_pcm_dai);
  382. if (ret != 0) {
  383. dev_err(&pdev->dev, "failed to get pcm_clock\n");
  384. goto err5;
  385. }
  386. s3c_pcm_stereo_in[pdev->id].dma_addr = mem_res->start
  387. + S3C_PCM_RXFIFO;
  388. s3c_pcm_stereo_out[pdev->id].dma_addr = mem_res->start
  389. + S3C_PCM_TXFIFO;
  390. s3c_pcm_stereo_in[pdev->id].channel = dmarx_res->start;
  391. s3c_pcm_stereo_out[pdev->id].channel = dmatx_res->start;
  392. pcm->dma_capture = &s3c_pcm_stereo_in[pdev->id];
  393. pcm->dma_playback = &s3c_pcm_stereo_out[pdev->id];
  394. return 0;
  395. err5:
  396. clk_disable(pcm->pclk);
  397. clk_put(pcm->pclk);
  398. err4:
  399. iounmap(pcm->regs);
  400. err3:
  401. release_mem_region(mem_res->start, resource_size(mem_res));
  402. err2:
  403. clk_disable(pcm->cclk);
  404. clk_put(pcm->cclk);
  405. err1:
  406. return ret;
  407. }
  408. static __devexit int s3c_pcm_dev_remove(struct platform_device *pdev)
  409. {
  410. struct s3c_pcm_info *pcm = &s3c_pcm[pdev->id];
  411. struct resource *mem_res;
  412. snd_soc_unregister_dai(&pdev->dev);
  413. iounmap(pcm->regs);
  414. mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  415. release_mem_region(mem_res->start, resource_size(mem_res));
  416. clk_disable(pcm->cclk);
  417. clk_disable(pcm->pclk);
  418. clk_put(pcm->pclk);
  419. clk_put(pcm->cclk);
  420. return 0;
  421. }
  422. static struct platform_driver s3c_pcm_driver = {
  423. .probe = s3c_pcm_dev_probe,
  424. .remove = s3c_pcm_dev_remove,
  425. .driver = {
  426. .name = "samsung-pcm",
  427. .owner = THIS_MODULE,
  428. },
  429. };
  430. static int __init s3c_pcm_init(void)
  431. {
  432. return platform_driver_register(&s3c_pcm_driver);
  433. }
  434. module_init(s3c_pcm_init);
  435. static void __exit s3c_pcm_exit(void)
  436. {
  437. platform_driver_unregister(&s3c_pcm_driver);
  438. }
  439. module_exit(s3c_pcm_exit);
  440. /* Module information */
  441. MODULE_AUTHOR("Jaswinder Singh, <jassi.brar@samsung.com>");
  442. MODULE_DESCRIPTION("S3C PCM Controller Driver");
  443. MODULE_LICENSE("GPL");
  444. MODULE_ALIAS("platform:samsung-pcm");