em28xx-core.c 23 KB

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  1. /*
  2. em28xx-core.c - driver for Empia EM2800/EM2820/2840 USB video capture devices
  3. Copyright (C) 2005 Ludovico Cavedon <cavedon@sssup.it>
  4. Markus Rechberger <mrechberger@gmail.com>
  5. Mauro Carvalho Chehab <mchehab@infradead.org>
  6. Sascha Sommer <saschasommer@freenet.de>
  7. This program is free software; you can redistribute it and/or modify
  8. it under the terms of the GNU General Public License as published by
  9. the Free Software Foundation; either version 2 of the License, or
  10. (at your option) any later version.
  11. This program is distributed in the hope that it will be useful,
  12. but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. GNU General Public License for more details.
  15. You should have received a copy of the GNU General Public License
  16. along with this program; if not, write to the Free Software
  17. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18. */
  19. #include <linux/init.h>
  20. #include <linux/list.h>
  21. #include <linux/module.h>
  22. #include <linux/usb.h>
  23. #include <linux/vmalloc.h>
  24. #include "em28xx.h"
  25. /* #define ENABLE_DEBUG_ISOC_FRAMES */
  26. static unsigned int core_debug;
  27. module_param(core_debug,int,0644);
  28. MODULE_PARM_DESC(core_debug,"enable debug messages [core]");
  29. #define em28xx_coredbg(fmt, arg...) do {\
  30. if (core_debug) \
  31. printk(KERN_INFO "%s %s :"fmt, \
  32. dev->name, __func__ , ##arg); } while (0)
  33. static unsigned int reg_debug;
  34. module_param(reg_debug,int,0644);
  35. MODULE_PARM_DESC(reg_debug,"enable debug messages [URB reg]");
  36. #define em28xx_regdbg(fmt, arg...) do {\
  37. if (reg_debug) \
  38. printk(KERN_INFO "%s %s :"fmt, \
  39. dev->name, __func__ , ##arg); } while (0)
  40. static int alt = EM28XX_PINOUT;
  41. module_param(alt, int, 0644);
  42. MODULE_PARM_DESC(alt, "alternate setting to use for video endpoint");
  43. /* FIXME */
  44. #define em28xx_isocdbg(fmt, arg...) do {\
  45. if (core_debug) \
  46. printk(KERN_INFO "%s %s :"fmt, \
  47. dev->name, __func__ , ##arg); } while (0)
  48. /*
  49. * em28xx_read_reg_req()
  50. * reads data from the usb device specifying bRequest
  51. */
  52. int em28xx_read_reg_req_len(struct em28xx *dev, u8 req, u16 reg,
  53. char *buf, int len)
  54. {
  55. int ret, byte;
  56. if (dev->state & DEV_DISCONNECTED)
  57. return -ENODEV;
  58. if (len > URB_MAX_CTRL_SIZE)
  59. return -EINVAL;
  60. em28xx_regdbg("req=%02x, reg=%02x ", req, reg);
  61. mutex_lock(&dev->ctrl_urb_lock);
  62. ret = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0), req,
  63. USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  64. 0x0000, reg, dev->urb_buf, len, HZ);
  65. if (ret < 0) {
  66. if (reg_debug)
  67. printk(" failed!\n");
  68. mutex_unlock(&dev->ctrl_urb_lock);
  69. return ret;
  70. }
  71. if (len)
  72. memcpy(buf, dev->urb_buf, len);
  73. mutex_unlock(&dev->ctrl_urb_lock);
  74. if (reg_debug) {
  75. printk("%02x values: ", ret);
  76. for (byte = 0; byte < len; byte++)
  77. printk(" %02x", (unsigned char)buf[byte]);
  78. printk("\n");
  79. }
  80. return ret;
  81. }
  82. /*
  83. * em28xx_read_reg_req()
  84. * reads data from the usb device specifying bRequest
  85. */
  86. int em28xx_read_reg_req(struct em28xx *dev, u8 req, u16 reg)
  87. {
  88. u8 val;
  89. int ret;
  90. if (dev->state & DEV_DISCONNECTED)
  91. return(-ENODEV);
  92. em28xx_regdbg("req=%02x, reg=%02x:", req, reg);
  93. mutex_lock(&dev->ctrl_urb_lock);
  94. ret = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0), req,
  95. USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  96. 0x0000, reg, dev->urb_buf, 1, HZ);
  97. val = dev->urb_buf[0];
  98. mutex_unlock(&dev->ctrl_urb_lock);
  99. if (ret < 0) {
  100. printk(" failed!\n");
  101. return ret;
  102. }
  103. if (reg_debug)
  104. printk("%02x\n", (unsigned char) val);
  105. return val;
  106. }
  107. int em28xx_read_reg(struct em28xx *dev, u16 reg)
  108. {
  109. return em28xx_read_reg_req(dev, USB_REQ_GET_STATUS, reg);
  110. }
  111. /*
  112. * em28xx_write_regs_req()
  113. * sends data to the usb device, specifying bRequest
  114. */
  115. int em28xx_write_regs_req(struct em28xx *dev, u8 req, u16 reg, char *buf,
  116. int len)
  117. {
  118. int ret;
  119. if (dev->state & DEV_DISCONNECTED)
  120. return -ENODEV;
  121. if ((len < 1) || (len > URB_MAX_CTRL_SIZE))
  122. return -EINVAL;
  123. em28xx_regdbg("req=%02x reg=%02x:", req, reg);
  124. if (reg_debug) {
  125. int i;
  126. for (i = 0; i < len; ++i)
  127. printk(" %02x", (unsigned char)buf[i]);
  128. printk("\n");
  129. }
  130. mutex_lock(&dev->ctrl_urb_lock);
  131. memcpy(dev->urb_buf, buf, len);
  132. ret = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0), req,
  133. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  134. 0x0000, reg, dev->urb_buf, len, HZ);
  135. mutex_unlock(&dev->ctrl_urb_lock);
  136. if (dev->wait_after_write)
  137. msleep(dev->wait_after_write);
  138. return ret;
  139. }
  140. int em28xx_write_regs(struct em28xx *dev, u16 reg, char *buf, int len)
  141. {
  142. int rc;
  143. rc = em28xx_write_regs_req(dev, USB_REQ_GET_STATUS, reg, buf, len);
  144. /* Stores GPO/GPIO values at the cache, if changed
  145. Only write values should be stored, since input on a GPIO
  146. register will return the input bits.
  147. Not sure what happens on reading GPO register.
  148. */
  149. if (rc >= 0) {
  150. if (reg == dev->reg_gpo_num)
  151. dev->reg_gpo = buf[0];
  152. else if (reg == dev->reg_gpio_num)
  153. dev->reg_gpio = buf[0];
  154. }
  155. return rc;
  156. }
  157. /*
  158. * em28xx_write_reg_bits()
  159. * sets only some bits (specified by bitmask) of a register, by first reading
  160. * the actual value
  161. */
  162. static int em28xx_write_reg_bits(struct em28xx *dev, u16 reg, u8 val,
  163. u8 bitmask)
  164. {
  165. int oldval;
  166. u8 newval;
  167. /* Uses cache for gpo/gpio registers */
  168. if (reg == dev->reg_gpo_num)
  169. oldval = dev->reg_gpo;
  170. else if (reg == dev->reg_gpio_num)
  171. oldval = dev->reg_gpio;
  172. else
  173. oldval = em28xx_read_reg(dev, reg);
  174. if (oldval < 0)
  175. return oldval;
  176. newval = (((u8) oldval) & ~bitmask) | (val & bitmask);
  177. return em28xx_write_regs(dev, reg, &newval, 1);
  178. }
  179. /*
  180. * em28xx_is_ac97_ready()
  181. * Checks if ac97 is ready
  182. */
  183. static int em28xx_is_ac97_ready(struct em28xx *dev)
  184. {
  185. int ret, i;
  186. /* Wait up to 50 ms for AC97 command to complete */
  187. for (i = 0; i < 10; i++, msleep(5)) {
  188. ret = em28xx_read_reg(dev, EM28XX_R43_AC97BUSY);
  189. if (ret < 0)
  190. return ret;
  191. if (!(ret & 0x01))
  192. return 0;
  193. }
  194. em28xx_warn("AC97 command still being executed: not handled properly!\n");
  195. return -EBUSY;
  196. }
  197. /*
  198. * em28xx_read_ac97()
  199. * write a 16 bit value to the specified AC97 address (LSB first!)
  200. */
  201. static int em28xx_read_ac97(struct em28xx *dev, u8 reg)
  202. {
  203. int ret;
  204. u8 addr = (reg & 0x7f) | 0x80;
  205. u16 val;
  206. ret = em28xx_is_ac97_ready(dev);
  207. if (ret < 0)
  208. return ret;
  209. ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
  210. if (ret < 0)
  211. return ret;
  212. ret = dev->em28xx_read_reg_req_len(dev, 0, EM28XX_R40_AC97LSB,
  213. (u8 *)&val, sizeof(val));
  214. if (ret < 0)
  215. return ret;
  216. return le16_to_cpu(val);
  217. }
  218. /*
  219. * em28xx_write_ac97()
  220. * write a 16 bit value to the specified AC97 address (LSB first!)
  221. */
  222. static int em28xx_write_ac97(struct em28xx *dev, u8 reg, u16 val)
  223. {
  224. int ret;
  225. u8 addr = reg & 0x7f;
  226. __le16 value;
  227. value = cpu_to_le16(val);
  228. ret = em28xx_is_ac97_ready(dev);
  229. if (ret < 0)
  230. return ret;
  231. ret = em28xx_write_regs(dev, EM28XX_R40_AC97LSB, (u8 *) &value, 2);
  232. if (ret < 0)
  233. return ret;
  234. ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
  235. if (ret < 0)
  236. return ret;
  237. return 0;
  238. }
  239. struct em28xx_input_table {
  240. enum em28xx_amux amux;
  241. u8 reg;
  242. };
  243. static struct em28xx_input_table inputs[] = {
  244. { EM28XX_AMUX_VIDEO, AC97_VIDEO_VOL },
  245. { EM28XX_AMUX_LINE_IN, AC97_LINEIN_VOL },
  246. { EM28XX_AMUX_PHONE, AC97_PHONE_VOL },
  247. { EM28XX_AMUX_MIC, AC97_MIC_VOL },
  248. { EM28XX_AMUX_CD, AC97_CD_VOL },
  249. { EM28XX_AMUX_AUX, AC97_AUX_VOL },
  250. { EM28XX_AMUX_PCM_OUT, AC97_PCM_OUT_VOL },
  251. };
  252. static int set_ac97_input(struct em28xx *dev)
  253. {
  254. int ret, i;
  255. enum em28xx_amux amux = dev->ctl_ainput;
  256. /* EM28XX_AMUX_VIDEO2 is a special case used to indicate that
  257. em28xx should point to LINE IN, while AC97 should use VIDEO
  258. */
  259. if (amux == EM28XX_AMUX_VIDEO2)
  260. amux = dev->ctl_ainput;
  261. /* Mute all entres but the one that were selected */
  262. for (i = 0; i < ARRAY_SIZE(inputs); i++) {
  263. if (amux == inputs[i].amux)
  264. ret = em28xx_write_ac97(dev, inputs[i].reg, 0x0808);
  265. else
  266. ret = em28xx_write_ac97(dev, inputs[i].reg, 0x8000);
  267. if (ret < 0)
  268. em28xx_warn("couldn't setup AC97 register %d\n",
  269. inputs[i].reg);
  270. }
  271. return 0;
  272. }
  273. static int em28xx_set_audio_source(struct em28xx *dev)
  274. {
  275. int ret;
  276. u8 input;
  277. if (dev->is_em2800) {
  278. if (dev->ctl_ainput == EM28XX_AMUX_VIDEO)
  279. input = EM2800_AUDIO_SRC_TUNER;
  280. else
  281. input = EM2800_AUDIO_SRC_LINE;
  282. ret = em28xx_write_regs(dev, EM2800_R08_AUDIOSRC, &input, 1);
  283. if (ret < 0)
  284. return ret;
  285. }
  286. if (dev->has_msp34xx)
  287. input = EM28XX_AUDIO_SRC_TUNER;
  288. else {
  289. switch (dev->ctl_ainput) {
  290. case EM28XX_AMUX_VIDEO:
  291. input = EM28XX_AUDIO_SRC_TUNER;
  292. break;
  293. default:
  294. input = EM28XX_AUDIO_SRC_LINE;
  295. break;
  296. }
  297. }
  298. ret = em28xx_write_reg_bits(dev, EM28XX_R0E_AUDIOSRC, input, 0xc0);
  299. if (ret < 0)
  300. return ret;
  301. msleep(5);
  302. switch (dev->audio_mode.ac97) {
  303. case EM28XX_NO_AC97:
  304. break;
  305. default:
  306. ret = set_ac97_input(dev);
  307. }
  308. return ret;
  309. }
  310. int em28xx_audio_analog_set(struct em28xx *dev)
  311. {
  312. int ret;
  313. u8 xclk = 0x07;
  314. if (!dev->audio_mode.has_audio)
  315. return 0;
  316. /* It is assumed that all devices use master volume for output.
  317. It would be possible to use also line output.
  318. */
  319. if (dev->audio_mode.ac97 != EM28XX_NO_AC97) {
  320. /* Mute */
  321. ret = em28xx_write_ac97(dev, AC97_MASTER_VOL, 0x8000);
  322. if (ret < 0)
  323. return ret;
  324. }
  325. if (dev->has_12mhz_i2s)
  326. xclk |= 0x20;
  327. if (!dev->mute)
  328. xclk |= 0x80;
  329. ret = em28xx_write_reg_bits(dev, EM28XX_R0F_XCLK, xclk, 0xa7);
  330. if (ret < 0)
  331. return ret;
  332. msleep(10);
  333. /* Selects the proper audio input */
  334. ret = em28xx_set_audio_source(dev);
  335. /* Sets volume */
  336. if (dev->audio_mode.ac97 != EM28XX_NO_AC97) {
  337. int vol;
  338. /* LSB: left channel - both channels with the same level */
  339. vol = (0x1f - dev->volume) | ((0x1f - dev->volume) << 8);
  340. /* Mute device, if needed */
  341. if (dev->mute)
  342. vol |= 0x8000;
  343. /* Sets volume */
  344. ret = em28xx_write_ac97(dev, AC97_MASTER_VOL, vol);
  345. }
  346. return ret;
  347. }
  348. EXPORT_SYMBOL_GPL(em28xx_audio_analog_set);
  349. int em28xx_audio_setup(struct em28xx *dev)
  350. {
  351. int vid1, vid2, feat, cfg;
  352. u32 vid;
  353. if (dev->chip_id == CHIP_ID_EM2874) {
  354. /* Digital only device - don't load any alsa module */
  355. dev->audio_mode.has_audio = 0;
  356. dev->has_audio_class = 0;
  357. dev->has_alsa_audio = 0;
  358. return 0;
  359. }
  360. /* If device doesn't support Usb Audio Class, use vendor class */
  361. if (!dev->has_audio_class)
  362. dev->has_alsa_audio = 1;
  363. dev->audio_mode.has_audio = 1;
  364. /* See how this device is configured */
  365. cfg = em28xx_read_reg(dev, EM28XX_R00_CHIPCFG);
  366. if (cfg < 0)
  367. cfg = EM28XX_CHIPCFG_AC97; /* Be conservative */
  368. else
  369. em28xx_info("Config register raw data: 0x%02x\n", cfg);
  370. if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
  371. EM28XX_CHIPCFG_I2S_3_SAMPRATES) {
  372. em28xx_info("I2S Audio (3 sample rates)\n");
  373. dev->audio_mode.i2s_3rates = 1;
  374. }
  375. if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
  376. EM28XX_CHIPCFG_I2S_5_SAMPRATES) {
  377. em28xx_info("I2S Audio (5 sample rates)\n");
  378. dev->audio_mode.i2s_5rates = 1;
  379. }
  380. if (!(cfg & EM28XX_CHIPCFG_AC97)) {
  381. dev->audio_mode.ac97 = EM28XX_NO_AC97;
  382. goto init_audio;
  383. }
  384. dev->audio_mode.ac97 = EM28XX_AC97_OTHER;
  385. vid1 = em28xx_read_ac97(dev, AC97_VENDOR_ID1);
  386. if (vid1 < 0) {
  387. /* Device likely doesn't support AC97 */
  388. em28xx_warn("AC97 chip type couldn't be determined\n");
  389. goto init_audio;
  390. }
  391. vid2 = em28xx_read_ac97(dev, AC97_VENDOR_ID2);
  392. if (vid2 < 0)
  393. goto init_audio;
  394. vid = vid1 << 16 | vid2;
  395. dev->audio_mode.ac97_vendor_id = vid;
  396. em28xx_warn("AC97 vendor ID = 0x%08x\n", vid);
  397. feat = em28xx_read_ac97(dev, AC97_RESET);
  398. if (feat < 0)
  399. goto init_audio;
  400. dev->audio_mode.ac97_feat = feat;
  401. em28xx_warn("AC97 features = 0x%04x\n", feat);
  402. /* Try to identify what audio processor we have */
  403. if ((vid == 0xffffffff) && (feat == 0x6a90))
  404. dev->audio_mode.ac97 = EM28XX_AC97_EM202;
  405. init_audio:
  406. /* Reports detected AC97 processor */
  407. switch (dev->audio_mode.ac97) {
  408. case EM28XX_NO_AC97:
  409. em28xx_info("No AC97 audio processor\n");
  410. break;
  411. case EM28XX_AC97_EM202:
  412. em28xx_info("Empia 202 AC97 audio processor detected\n");
  413. break;
  414. case EM28XX_AC97_OTHER:
  415. em28xx_warn("Unknown AC97 audio processor detected!\n");
  416. break;
  417. default:
  418. break;
  419. }
  420. return em28xx_audio_analog_set(dev);
  421. }
  422. EXPORT_SYMBOL_GPL(em28xx_audio_setup);
  423. int em28xx_colorlevels_set_default(struct em28xx *dev)
  424. {
  425. em28xx_write_regs(dev, EM28XX_R20_YGAIN, "\x10", 1); /* contrast */
  426. em28xx_write_regs(dev, EM28XX_R21_YOFFSET, "\x00", 1); /* brightness */
  427. em28xx_write_regs(dev, EM28XX_R22_UVGAIN, "\x10", 1); /* saturation */
  428. em28xx_write_regs(dev, EM28XX_R23_UOFFSET, "\x00", 1);
  429. em28xx_write_regs(dev, EM28XX_R24_VOFFSET, "\x00", 1);
  430. em28xx_write_regs(dev, EM28XX_R25_SHARPNESS, "\x00", 1);
  431. em28xx_write_regs(dev, EM28XX_R14_GAMMA, "\x20", 1);
  432. em28xx_write_regs(dev, EM28XX_R15_RGAIN, "\x20", 1);
  433. em28xx_write_regs(dev, EM28XX_R16_GGAIN, "\x20", 1);
  434. em28xx_write_regs(dev, EM28XX_R17_BGAIN, "\x20", 1);
  435. em28xx_write_regs(dev, EM28XX_R18_ROFFSET, "\x00", 1);
  436. em28xx_write_regs(dev, EM28XX_R19_GOFFSET, "\x00", 1);
  437. return em28xx_write_regs(dev, EM28XX_R1A_BOFFSET, "\x00", 1);
  438. }
  439. int em28xx_capture_start(struct em28xx *dev, int start)
  440. {
  441. int rc;
  442. if (dev->chip_id == CHIP_ID_EM2874) {
  443. /* The Transport Stream Enable Register moved in em2874 */
  444. if (!start) {
  445. rc = em28xx_write_reg_bits(dev, EM2874_R5F_TS_ENABLE,
  446. 0x00,
  447. EM2874_TS1_CAPTURE_ENABLE);
  448. return rc;
  449. }
  450. /* Enable Transport Stream */
  451. rc = em28xx_write_reg_bits(dev, EM2874_R5F_TS_ENABLE,
  452. EM2874_TS1_CAPTURE_ENABLE,
  453. EM2874_TS1_CAPTURE_ENABLE);
  454. return rc;
  455. }
  456. /* FIXME: which is the best order? */
  457. /* video registers are sampled by VREF */
  458. rc = em28xx_write_reg_bits(dev, EM28XX_R0C_USBSUSP,
  459. start ? 0x10 : 0x00, 0x10);
  460. if (rc < 0)
  461. return rc;
  462. if (!start) {
  463. /* disable video capture */
  464. rc = em28xx_write_regs(dev, EM28XX_R12_VINENABLE, "\x27", 1);
  465. return rc;
  466. }
  467. /* enable video capture */
  468. rc = em28xx_write_regs_req(dev, 0x00, 0x48, "\x00", 1);
  469. if (dev->mode == EM28XX_ANALOG_MODE)
  470. rc = em28xx_write_regs(dev, EM28XX_R12_VINENABLE, "\x67", 1);
  471. else
  472. rc = em28xx_write_regs(dev, EM28XX_R12_VINENABLE, "\x37", 1);
  473. msleep(6);
  474. return rc;
  475. }
  476. int em28xx_outfmt_set_yuv422(struct em28xx *dev)
  477. {
  478. em28xx_write_regs(dev, EM28XX_R27_OUTFMT, "\x34", 1);
  479. em28xx_write_regs(dev, EM28XX_R10_VINMODE, "\x10", 1);
  480. return em28xx_write_regs(dev, EM28XX_R11_VINCTRL, "\x11", 1);
  481. }
  482. static int em28xx_accumulator_set(struct em28xx *dev, u8 xmin, u8 xmax,
  483. u8 ymin, u8 ymax)
  484. {
  485. em28xx_coredbg("em28xx Scale: (%d,%d)-(%d,%d)\n",
  486. xmin, ymin, xmax, ymax);
  487. em28xx_write_regs(dev, EM28XX_R28_XMIN, &xmin, 1);
  488. em28xx_write_regs(dev, EM28XX_R29_XMAX, &xmax, 1);
  489. em28xx_write_regs(dev, EM28XX_R2A_YMIN, &ymin, 1);
  490. return em28xx_write_regs(dev, EM28XX_R2B_YMAX, &ymax, 1);
  491. }
  492. static int em28xx_capture_area_set(struct em28xx *dev, u8 hstart, u8 vstart,
  493. u16 width, u16 height)
  494. {
  495. u8 cwidth = width;
  496. u8 cheight = height;
  497. u8 overflow = (height >> 7 & 0x02) | (width >> 8 & 0x01);
  498. em28xx_coredbg("em28xx Area Set: (%d,%d)\n",
  499. (width | (overflow & 2) << 7),
  500. (height | (overflow & 1) << 8));
  501. em28xx_write_regs(dev, EM28XX_R1C_HSTART, &hstart, 1);
  502. em28xx_write_regs(dev, EM28XX_R1D_VSTART, &vstart, 1);
  503. em28xx_write_regs(dev, EM28XX_R1E_CWIDTH, &cwidth, 1);
  504. em28xx_write_regs(dev, EM28XX_R1F_CHEIGHT, &cheight, 1);
  505. return em28xx_write_regs(dev, EM28XX_R1B_OFLOW, &overflow, 1);
  506. }
  507. static int em28xx_scaler_set(struct em28xx *dev, u16 h, u16 v)
  508. {
  509. u8 mode;
  510. /* the em2800 scaler only supports scaling down to 50% */
  511. if (dev->is_em2800)
  512. mode = (v ? 0x20 : 0x00) | (h ? 0x10 : 0x00);
  513. else {
  514. u8 buf[2];
  515. buf[0] = h;
  516. buf[1] = h >> 8;
  517. em28xx_write_regs(dev, EM28XX_R30_HSCALELOW, (char *)buf, 2);
  518. buf[0] = v;
  519. buf[1] = v >> 8;
  520. em28xx_write_regs(dev, EM28XX_R32_VSCALELOW, (char *)buf, 2);
  521. /* it seems that both H and V scalers must be active
  522. to work correctly */
  523. mode = (h || v)? 0x30: 0x00;
  524. }
  525. return em28xx_write_reg_bits(dev, EM28XX_R26_COMPR, mode, 0x30);
  526. }
  527. /* FIXME: this only function read values from dev */
  528. int em28xx_resolution_set(struct em28xx *dev)
  529. {
  530. int width, height;
  531. width = norm_maxw(dev);
  532. height = norm_maxh(dev) >> 1;
  533. em28xx_outfmt_set_yuv422(dev);
  534. em28xx_accumulator_set(dev, 1, (width - 4) >> 2, 1, (height - 4) >> 2);
  535. em28xx_capture_area_set(dev, 0, 0, width >> 2, height >> 2);
  536. return em28xx_scaler_set(dev, dev->hscale, dev->vscale);
  537. }
  538. int em28xx_set_alternate(struct em28xx *dev)
  539. {
  540. int errCode, prev_alt = dev->alt;
  541. int i;
  542. unsigned int min_pkt_size = dev->width * 2 + 4;
  543. /* When image size is bigger than a certain value,
  544. the frame size should be increased, otherwise, only
  545. green screen will be received.
  546. */
  547. if (dev->width * 2 * dev->height > 720 * 240 * 2)
  548. min_pkt_size *= 2;
  549. for (i = 0; i < dev->num_alt; i++) {
  550. /* stop when the selected alt setting offers enough bandwidth */
  551. if (dev->alt_max_pkt_size[i] >= min_pkt_size) {
  552. dev->alt = i;
  553. break;
  554. /* otherwise make sure that we end up with the maximum bandwidth
  555. because the min_pkt_size equation might be wrong...
  556. */
  557. } else if (dev->alt_max_pkt_size[i] >
  558. dev->alt_max_pkt_size[dev->alt])
  559. dev->alt = i;
  560. }
  561. if (dev->alt != prev_alt) {
  562. em28xx_coredbg("minimum isoc packet size: %u (alt=%d)\n",
  563. min_pkt_size, dev->alt);
  564. dev->max_pkt_size = dev->alt_max_pkt_size[dev->alt];
  565. em28xx_coredbg("setting alternate %d with wMaxPacketSize=%u\n",
  566. dev->alt, dev->max_pkt_size);
  567. errCode = usb_set_interface(dev->udev, 0, dev->alt);
  568. if (errCode < 0) {
  569. em28xx_errdev("cannot change alternate number to %d (error=%i)\n",
  570. dev->alt, errCode);
  571. return errCode;
  572. }
  573. }
  574. return 0;
  575. }
  576. int em28xx_gpio_set(struct em28xx *dev, struct em28xx_reg_seq *gpio)
  577. {
  578. int rc = 0;
  579. if (!gpio)
  580. return rc;
  581. dev->em28xx_write_regs_req(dev, 0x00, 0x48, "\x00", 1);
  582. if (dev->mode == EM28XX_ANALOG_MODE)
  583. dev->em28xx_write_regs_req(dev, 0x00, 0x12, "\x67", 1);
  584. else
  585. dev->em28xx_write_regs_req(dev, 0x00, 0x12, "\x37", 1);
  586. msleep(6);
  587. /* Send GPIO reset sequences specified at board entry */
  588. while (gpio->sleep >= 0) {
  589. if (gpio->reg >= 0) {
  590. rc = em28xx_write_reg_bits(dev,
  591. gpio->reg,
  592. gpio->val,
  593. gpio->mask);
  594. if (rc < 0)
  595. return rc;
  596. }
  597. if (gpio->sleep > 0)
  598. msleep(gpio->sleep);
  599. gpio++;
  600. }
  601. return rc;
  602. }
  603. int em28xx_set_mode(struct em28xx *dev, enum em28xx_mode set_mode)
  604. {
  605. if (dev->mode == set_mode)
  606. return 0;
  607. if (set_mode == EM28XX_MODE_UNDEFINED) {
  608. dev->mode = set_mode;
  609. return 0;
  610. }
  611. dev->mode = set_mode;
  612. if (dev->mode == EM28XX_DIGITAL_MODE)
  613. return em28xx_gpio_set(dev, dev->digital_gpio);
  614. else
  615. return em28xx_gpio_set(dev, dev->analog_gpio);
  616. }
  617. EXPORT_SYMBOL_GPL(em28xx_set_mode);
  618. /* ------------------------------------------------------------------
  619. URB control
  620. ------------------------------------------------------------------*/
  621. /*
  622. * IRQ callback, called by URB callback
  623. */
  624. static void em28xx_irq_callback(struct urb *urb)
  625. {
  626. struct em28xx_dmaqueue *dma_q = urb->context;
  627. struct em28xx *dev = container_of(dma_q, struct em28xx, vidq);
  628. int rc, i;
  629. /* Copy data from URB */
  630. spin_lock(&dev->slock);
  631. rc = dev->isoc_ctl.isoc_copy(dev, urb);
  632. spin_unlock(&dev->slock);
  633. /* Reset urb buffers */
  634. for (i = 0; i < urb->number_of_packets; i++) {
  635. urb->iso_frame_desc[i].status = 0;
  636. urb->iso_frame_desc[i].actual_length = 0;
  637. }
  638. urb->status = 0;
  639. urb->status = usb_submit_urb(urb, GFP_ATOMIC);
  640. if (urb->status) {
  641. em28xx_isocdbg("urb resubmit failed (error=%i)\n",
  642. urb->status);
  643. }
  644. }
  645. /*
  646. * Stop and Deallocate URBs
  647. */
  648. void em28xx_uninit_isoc(struct em28xx *dev)
  649. {
  650. struct urb *urb;
  651. int i;
  652. em28xx_isocdbg("em28xx: called em28xx_uninit_isoc\n");
  653. dev->isoc_ctl.nfields = -1;
  654. for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
  655. urb = dev->isoc_ctl.urb[i];
  656. if (urb) {
  657. usb_kill_urb(urb);
  658. usb_unlink_urb(urb);
  659. if (dev->isoc_ctl.transfer_buffer[i]) {
  660. usb_buffer_free(dev->udev,
  661. urb->transfer_buffer_length,
  662. dev->isoc_ctl.transfer_buffer[i],
  663. urb->transfer_dma);
  664. }
  665. usb_free_urb(urb);
  666. dev->isoc_ctl.urb[i] = NULL;
  667. }
  668. dev->isoc_ctl.transfer_buffer[i] = NULL;
  669. }
  670. kfree(dev->isoc_ctl.urb);
  671. kfree(dev->isoc_ctl.transfer_buffer);
  672. dev->isoc_ctl.urb = NULL;
  673. dev->isoc_ctl.transfer_buffer = NULL;
  674. dev->isoc_ctl.num_bufs = 0;
  675. em28xx_capture_start(dev, 0);
  676. }
  677. EXPORT_SYMBOL_GPL(em28xx_uninit_isoc);
  678. /*
  679. * Allocate URBs and start IRQ
  680. */
  681. int em28xx_init_isoc(struct em28xx *dev, int max_packets,
  682. int num_bufs, int max_pkt_size,
  683. int (*isoc_copy) (struct em28xx *dev, struct urb *urb))
  684. {
  685. struct em28xx_dmaqueue *dma_q = &dev->vidq;
  686. int i;
  687. int sb_size, pipe;
  688. struct urb *urb;
  689. int j, k;
  690. int rc;
  691. em28xx_isocdbg("em28xx: called em28xx_prepare_isoc\n");
  692. /* De-allocates all pending stuff */
  693. em28xx_uninit_isoc(dev);
  694. dev->isoc_ctl.isoc_copy = isoc_copy;
  695. dev->isoc_ctl.num_bufs = num_bufs;
  696. dev->isoc_ctl.urb = kzalloc(sizeof(void *)*num_bufs, GFP_KERNEL);
  697. if (!dev->isoc_ctl.urb) {
  698. em28xx_errdev("cannot alloc memory for usb buffers\n");
  699. return -ENOMEM;
  700. }
  701. dev->isoc_ctl.transfer_buffer = kzalloc(sizeof(void *)*num_bufs,
  702. GFP_KERNEL);
  703. if (!dev->isoc_ctl.transfer_buffer) {
  704. em28xx_errdev("cannot allocate memory for usbtransfer\n");
  705. kfree(dev->isoc_ctl.urb);
  706. return -ENOMEM;
  707. }
  708. dev->isoc_ctl.max_pkt_size = max_pkt_size;
  709. dev->isoc_ctl.buf = NULL;
  710. sb_size = max_packets * dev->isoc_ctl.max_pkt_size;
  711. /* allocate urbs and transfer buffers */
  712. for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
  713. urb = usb_alloc_urb(max_packets, GFP_KERNEL);
  714. if (!urb) {
  715. em28xx_err("cannot alloc isoc_ctl.urb %i\n", i);
  716. em28xx_uninit_isoc(dev);
  717. return -ENOMEM;
  718. }
  719. dev->isoc_ctl.urb[i] = urb;
  720. dev->isoc_ctl.transfer_buffer[i] = usb_buffer_alloc(dev->udev,
  721. sb_size, GFP_KERNEL, &urb->transfer_dma);
  722. if (!dev->isoc_ctl.transfer_buffer[i]) {
  723. em28xx_err("unable to allocate %i bytes for transfer"
  724. " buffer %i%s\n",
  725. sb_size, i,
  726. in_interrupt()?" while in int":"");
  727. em28xx_uninit_isoc(dev);
  728. return -ENOMEM;
  729. }
  730. memset(dev->isoc_ctl.transfer_buffer[i], 0, sb_size);
  731. /* FIXME: this is a hack - should be
  732. 'desc.bEndpointAddress & USB_ENDPOINT_NUMBER_MASK'
  733. should also be using 'desc.bInterval'
  734. */
  735. pipe = usb_rcvisocpipe(dev->udev,
  736. dev->mode == EM28XX_ANALOG_MODE ? 0x82 : 0x84);
  737. usb_fill_int_urb(urb, dev->udev, pipe,
  738. dev->isoc_ctl.transfer_buffer[i], sb_size,
  739. em28xx_irq_callback, dma_q, 1);
  740. urb->number_of_packets = max_packets;
  741. urb->transfer_flags = URB_ISO_ASAP;
  742. k = 0;
  743. for (j = 0; j < max_packets; j++) {
  744. urb->iso_frame_desc[j].offset = k;
  745. urb->iso_frame_desc[j].length =
  746. dev->isoc_ctl.max_pkt_size;
  747. k += dev->isoc_ctl.max_pkt_size;
  748. }
  749. }
  750. init_waitqueue_head(&dma_q->wq);
  751. em28xx_capture_start(dev, 1);
  752. /* submit urbs and enables IRQ */
  753. for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
  754. rc = usb_submit_urb(dev->isoc_ctl.urb[i], GFP_ATOMIC);
  755. if (rc) {
  756. em28xx_err("submit of urb %i failed (error=%i)\n", i,
  757. rc);
  758. em28xx_uninit_isoc(dev);
  759. return rc;
  760. }
  761. }
  762. return 0;
  763. }
  764. EXPORT_SYMBOL_GPL(em28xx_init_isoc);