be_main.c 142 KB

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  1. /**
  2. * Copyright (C) 2005 - 2012 Emulex
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License version 2
  7. * as published by the Free Software Foundation. The full GNU General
  8. * Public License is included in this distribution in the file called COPYING.
  9. *
  10. * Written by: Jayamohan Kallickal (jayamohan.kallickal@emulex.com)
  11. *
  12. * Contact Information:
  13. * linux-drivers@emulex.com
  14. *
  15. * Emulex
  16. * 3333 Susan Street
  17. * Costa Mesa, CA 92626
  18. */
  19. #include <linux/reboot.h>
  20. #include <linux/delay.h>
  21. #include <linux/slab.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/blkdev.h>
  24. #include <linux/pci.h>
  25. #include <linux/string.h>
  26. #include <linux/kernel.h>
  27. #include <linux/semaphore.h>
  28. #include <linux/iscsi_boot_sysfs.h>
  29. #include <linux/module.h>
  30. #include <linux/bsg-lib.h>
  31. #include <scsi/libiscsi.h>
  32. #include <scsi/scsi_bsg_iscsi.h>
  33. #include <scsi/scsi_netlink.h>
  34. #include <scsi/scsi_transport_iscsi.h>
  35. #include <scsi/scsi_transport.h>
  36. #include <scsi/scsi_cmnd.h>
  37. #include <scsi/scsi_device.h>
  38. #include <scsi/scsi_host.h>
  39. #include <scsi/scsi.h>
  40. #include "be_main.h"
  41. #include "be_iscsi.h"
  42. #include "be_mgmt.h"
  43. #include "be_cmds.h"
  44. static unsigned int be_iopoll_budget = 10;
  45. static unsigned int be_max_phys_size = 64;
  46. static unsigned int enable_msix = 1;
  47. MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table);
  48. MODULE_DESCRIPTION(DRV_DESC " " BUILD_STR);
  49. MODULE_VERSION(BUILD_STR);
  50. MODULE_AUTHOR("Emulex Corporation");
  51. MODULE_LICENSE("GPL");
  52. module_param(be_iopoll_budget, int, 0);
  53. module_param(enable_msix, int, 0);
  54. module_param(be_max_phys_size, uint, S_IRUGO);
  55. MODULE_PARM_DESC(be_max_phys_size,
  56. "Maximum Size (In Kilobytes) of physically contiguous "
  57. "memory that can be allocated. Range is 16 - 128");
  58. #define beiscsi_disp_param(_name)\
  59. ssize_t \
  60. beiscsi_##_name##_disp(struct device *dev,\
  61. struct device_attribute *attrib, char *buf) \
  62. { \
  63. struct Scsi_Host *shost = class_to_shost(dev);\
  64. struct beiscsi_hba *phba = iscsi_host_priv(shost); \
  65. uint32_t param_val = 0; \
  66. param_val = phba->attr_##_name;\
  67. return snprintf(buf, PAGE_SIZE, "%d\n",\
  68. phba->attr_##_name);\
  69. }
  70. #define beiscsi_change_param(_name, _minval, _maxval, _defaval)\
  71. int \
  72. beiscsi_##_name##_change(struct beiscsi_hba *phba, uint32_t val)\
  73. {\
  74. if (val >= _minval && val <= _maxval) {\
  75. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\
  76. "BA_%d : beiscsi_"#_name" updated "\
  77. "from 0x%x ==> 0x%x\n",\
  78. phba->attr_##_name, val); \
  79. phba->attr_##_name = val;\
  80. return 0;\
  81. } \
  82. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, \
  83. "BA_%d beiscsi_"#_name" attribute "\
  84. "cannot be updated to 0x%x, "\
  85. "range allowed is ["#_minval" - "#_maxval"]\n", val);\
  86. return -EINVAL;\
  87. }
  88. #define beiscsi_store_param(_name) \
  89. ssize_t \
  90. beiscsi_##_name##_store(struct device *dev,\
  91. struct device_attribute *attr, const char *buf,\
  92. size_t count) \
  93. { \
  94. struct Scsi_Host *shost = class_to_shost(dev);\
  95. struct beiscsi_hba *phba = iscsi_host_priv(shost);\
  96. uint32_t param_val = 0;\
  97. if (!isdigit(buf[0]))\
  98. return -EINVAL;\
  99. if (sscanf(buf, "%i", &param_val) != 1)\
  100. return -EINVAL;\
  101. if (beiscsi_##_name##_change(phba, param_val) == 0) \
  102. return strlen(buf);\
  103. else \
  104. return -EINVAL;\
  105. }
  106. #define beiscsi_init_param(_name, _minval, _maxval, _defval) \
  107. int \
  108. beiscsi_##_name##_init(struct beiscsi_hba *phba, uint32_t val) \
  109. { \
  110. if (val >= _minval && val <= _maxval) {\
  111. phba->attr_##_name = val;\
  112. return 0;\
  113. } \
  114. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\
  115. "BA_%d beiscsi_"#_name" attribute " \
  116. "cannot be updated to 0x%x, "\
  117. "range allowed is ["#_minval" - "#_maxval"]\n", val);\
  118. phba->attr_##_name = _defval;\
  119. return -EINVAL;\
  120. }
  121. #define BEISCSI_RW_ATTR(_name, _minval, _maxval, _defval, _descp) \
  122. static uint beiscsi_##_name = _defval;\
  123. module_param(beiscsi_##_name, uint, S_IRUGO);\
  124. MODULE_PARM_DESC(beiscsi_##_name, _descp);\
  125. beiscsi_disp_param(_name)\
  126. beiscsi_change_param(_name, _minval, _maxval, _defval)\
  127. beiscsi_store_param(_name)\
  128. beiscsi_init_param(_name, _minval, _maxval, _defval)\
  129. DEVICE_ATTR(beiscsi_##_name, S_IRUGO | S_IWUSR,\
  130. beiscsi_##_name##_disp, beiscsi_##_name##_store)
  131. /*
  132. * When new log level added update the
  133. * the MAX allowed value for log_enable
  134. */
  135. BEISCSI_RW_ATTR(log_enable, 0x00,
  136. 0xFF, 0x00, "Enable logging Bit Mask\n"
  137. "\t\t\t\tInitialization Events : 0x01\n"
  138. "\t\t\t\tMailbox Events : 0x02\n"
  139. "\t\t\t\tMiscellaneous Events : 0x04\n"
  140. "\t\t\t\tError Handling : 0x08\n"
  141. "\t\t\t\tIO Path Events : 0x10\n"
  142. "\t\t\t\tConfiguration Path : 0x20\n");
  143. DEVICE_ATTR(beiscsi_drvr_ver, S_IRUGO, beiscsi_drvr_ver_disp, NULL);
  144. DEVICE_ATTR(beiscsi_adapter_family, S_IRUGO, beiscsi_adap_family_disp, NULL);
  145. struct device_attribute *beiscsi_attrs[] = {
  146. &dev_attr_beiscsi_log_enable,
  147. &dev_attr_beiscsi_drvr_ver,
  148. &dev_attr_beiscsi_adapter_family,
  149. NULL,
  150. };
  151. static char const *cqe_desc[] = {
  152. "RESERVED_DESC",
  153. "SOL_CMD_COMPLETE",
  154. "SOL_CMD_KILLED_DATA_DIGEST_ERR",
  155. "CXN_KILLED_PDU_SIZE_EXCEEDS_DSL",
  156. "CXN_KILLED_BURST_LEN_MISMATCH",
  157. "CXN_KILLED_AHS_RCVD",
  158. "CXN_KILLED_HDR_DIGEST_ERR",
  159. "CXN_KILLED_UNKNOWN_HDR",
  160. "CXN_KILLED_STALE_ITT_TTT_RCVD",
  161. "CXN_KILLED_INVALID_ITT_TTT_RCVD",
  162. "CXN_KILLED_RST_RCVD",
  163. "CXN_KILLED_TIMED_OUT",
  164. "CXN_KILLED_RST_SENT",
  165. "CXN_KILLED_FIN_RCVD",
  166. "CXN_KILLED_BAD_UNSOL_PDU_RCVD",
  167. "CXN_KILLED_BAD_WRB_INDEX_ERROR",
  168. "CXN_KILLED_OVER_RUN_RESIDUAL",
  169. "CXN_KILLED_UNDER_RUN_RESIDUAL",
  170. "CMD_KILLED_INVALID_STATSN_RCVD",
  171. "CMD_KILLED_INVALID_R2T_RCVD",
  172. "CMD_CXN_KILLED_LUN_INVALID",
  173. "CMD_CXN_KILLED_ICD_INVALID",
  174. "CMD_CXN_KILLED_ITT_INVALID",
  175. "CMD_CXN_KILLED_SEQ_OUTOFORDER",
  176. "CMD_CXN_KILLED_INVALID_DATASN_RCVD",
  177. "CXN_INVALIDATE_NOTIFY",
  178. "CXN_INVALIDATE_INDEX_NOTIFY",
  179. "CMD_INVALIDATED_NOTIFY",
  180. "UNSOL_HDR_NOTIFY",
  181. "UNSOL_DATA_NOTIFY",
  182. "UNSOL_DATA_DIGEST_ERROR_NOTIFY",
  183. "DRIVERMSG_NOTIFY",
  184. "CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN",
  185. "SOL_CMD_KILLED_DIF_ERR",
  186. "CXN_KILLED_SYN_RCVD",
  187. "CXN_KILLED_IMM_DATA_RCVD"
  188. };
  189. static int beiscsi_slave_configure(struct scsi_device *sdev)
  190. {
  191. blk_queue_max_segment_size(sdev->request_queue, 65536);
  192. return 0;
  193. }
  194. static int beiscsi_eh_abort(struct scsi_cmnd *sc)
  195. {
  196. struct iscsi_cls_session *cls_session;
  197. struct iscsi_task *aborted_task = (struct iscsi_task *)sc->SCp.ptr;
  198. struct beiscsi_io_task *aborted_io_task;
  199. struct iscsi_conn *conn;
  200. struct beiscsi_conn *beiscsi_conn;
  201. struct beiscsi_hba *phba;
  202. struct iscsi_session *session;
  203. struct invalidate_command_table *inv_tbl;
  204. struct be_dma_mem nonemb_cmd;
  205. unsigned int cid, tag, num_invalidate;
  206. cls_session = starget_to_session(scsi_target(sc->device));
  207. session = cls_session->dd_data;
  208. spin_lock_bh(&session->lock);
  209. if (!aborted_task || !aborted_task->sc) {
  210. /* we raced */
  211. spin_unlock_bh(&session->lock);
  212. return SUCCESS;
  213. }
  214. aborted_io_task = aborted_task->dd_data;
  215. if (!aborted_io_task->scsi_cmnd) {
  216. /* raced or invalid command */
  217. spin_unlock_bh(&session->lock);
  218. return SUCCESS;
  219. }
  220. spin_unlock_bh(&session->lock);
  221. conn = aborted_task->conn;
  222. beiscsi_conn = conn->dd_data;
  223. phba = beiscsi_conn->phba;
  224. /* invalidate iocb */
  225. cid = beiscsi_conn->beiscsi_conn_cid;
  226. inv_tbl = phba->inv_tbl;
  227. memset(inv_tbl, 0x0, sizeof(*inv_tbl));
  228. inv_tbl->cid = cid;
  229. inv_tbl->icd = aborted_io_task->psgl_handle->sgl_index;
  230. num_invalidate = 1;
  231. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  232. sizeof(struct invalidate_commands_params_in),
  233. &nonemb_cmd.dma);
  234. if (nonemb_cmd.va == NULL) {
  235. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH,
  236. "BM_%d : Failed to allocate memory for"
  237. "mgmt_invalidate_icds\n");
  238. return FAILED;
  239. }
  240. nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
  241. tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
  242. cid, &nonemb_cmd);
  243. if (!tag) {
  244. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH,
  245. "BM_%d : mgmt_invalidate_icds could not be"
  246. "submitted\n");
  247. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  248. nonemb_cmd.va, nonemb_cmd.dma);
  249. return FAILED;
  250. } else {
  251. wait_event_interruptible(phba->ctrl.mcc_wait[tag],
  252. phba->ctrl.mcc_numtag[tag]);
  253. free_mcc_tag(&phba->ctrl, tag);
  254. }
  255. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  256. nonemb_cmd.va, nonemb_cmd.dma);
  257. return iscsi_eh_abort(sc);
  258. }
  259. static int beiscsi_eh_device_reset(struct scsi_cmnd *sc)
  260. {
  261. struct iscsi_task *abrt_task;
  262. struct beiscsi_io_task *abrt_io_task;
  263. struct iscsi_conn *conn;
  264. struct beiscsi_conn *beiscsi_conn;
  265. struct beiscsi_hba *phba;
  266. struct iscsi_session *session;
  267. struct iscsi_cls_session *cls_session;
  268. struct invalidate_command_table *inv_tbl;
  269. struct be_dma_mem nonemb_cmd;
  270. unsigned int cid, tag, i, num_invalidate;
  271. /* invalidate iocbs */
  272. cls_session = starget_to_session(scsi_target(sc->device));
  273. session = cls_session->dd_data;
  274. spin_lock_bh(&session->lock);
  275. if (!session->leadconn || session->state != ISCSI_STATE_LOGGED_IN) {
  276. spin_unlock_bh(&session->lock);
  277. return FAILED;
  278. }
  279. conn = session->leadconn;
  280. beiscsi_conn = conn->dd_data;
  281. phba = beiscsi_conn->phba;
  282. cid = beiscsi_conn->beiscsi_conn_cid;
  283. inv_tbl = phba->inv_tbl;
  284. memset(inv_tbl, 0x0, sizeof(*inv_tbl) * BE2_CMDS_PER_CXN);
  285. num_invalidate = 0;
  286. for (i = 0; i < conn->session->cmds_max; i++) {
  287. abrt_task = conn->session->cmds[i];
  288. abrt_io_task = abrt_task->dd_data;
  289. if (!abrt_task->sc || abrt_task->state == ISCSI_TASK_FREE)
  290. continue;
  291. if (abrt_task->sc->device->lun != abrt_task->sc->device->lun)
  292. continue;
  293. inv_tbl->cid = cid;
  294. inv_tbl->icd = abrt_io_task->psgl_handle->sgl_index;
  295. num_invalidate++;
  296. inv_tbl++;
  297. }
  298. spin_unlock_bh(&session->lock);
  299. inv_tbl = phba->inv_tbl;
  300. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  301. sizeof(struct invalidate_commands_params_in),
  302. &nonemb_cmd.dma);
  303. if (nonemb_cmd.va == NULL) {
  304. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH,
  305. "BM_%d : Failed to allocate memory for"
  306. "mgmt_invalidate_icds\n");
  307. return FAILED;
  308. }
  309. nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
  310. memset(nonemb_cmd.va, 0, nonemb_cmd.size);
  311. tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
  312. cid, &nonemb_cmd);
  313. if (!tag) {
  314. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH,
  315. "BM_%d : mgmt_invalidate_icds could not be"
  316. " submitted\n");
  317. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  318. nonemb_cmd.va, nonemb_cmd.dma);
  319. return FAILED;
  320. } else {
  321. wait_event_interruptible(phba->ctrl.mcc_wait[tag],
  322. phba->ctrl.mcc_numtag[tag]);
  323. free_mcc_tag(&phba->ctrl, tag);
  324. }
  325. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  326. nonemb_cmd.va, nonemb_cmd.dma);
  327. return iscsi_eh_device_reset(sc);
  328. }
  329. static ssize_t beiscsi_show_boot_tgt_info(void *data, int type, char *buf)
  330. {
  331. struct beiscsi_hba *phba = data;
  332. struct mgmt_session_info *boot_sess = &phba->boot_sess;
  333. struct mgmt_conn_info *boot_conn = &boot_sess->conn_list[0];
  334. char *str = buf;
  335. int rc;
  336. switch (type) {
  337. case ISCSI_BOOT_TGT_NAME:
  338. rc = sprintf(buf, "%.*s\n",
  339. (int)strlen(boot_sess->target_name),
  340. (char *)&boot_sess->target_name);
  341. break;
  342. case ISCSI_BOOT_TGT_IP_ADDR:
  343. if (boot_conn->dest_ipaddr.ip_type == 0x1)
  344. rc = sprintf(buf, "%pI4\n",
  345. (char *)&boot_conn->dest_ipaddr.addr);
  346. else
  347. rc = sprintf(str, "%pI6\n",
  348. (char *)&boot_conn->dest_ipaddr.addr);
  349. break;
  350. case ISCSI_BOOT_TGT_PORT:
  351. rc = sprintf(str, "%d\n", boot_conn->dest_port);
  352. break;
  353. case ISCSI_BOOT_TGT_CHAP_NAME:
  354. rc = sprintf(str, "%.*s\n",
  355. boot_conn->negotiated_login_options.auth_data.chap.
  356. target_chap_name_length,
  357. (char *)&boot_conn->negotiated_login_options.
  358. auth_data.chap.target_chap_name);
  359. break;
  360. case ISCSI_BOOT_TGT_CHAP_SECRET:
  361. rc = sprintf(str, "%.*s\n",
  362. boot_conn->negotiated_login_options.auth_data.chap.
  363. target_secret_length,
  364. (char *)&boot_conn->negotiated_login_options.
  365. auth_data.chap.target_secret);
  366. break;
  367. case ISCSI_BOOT_TGT_REV_CHAP_NAME:
  368. rc = sprintf(str, "%.*s\n",
  369. boot_conn->negotiated_login_options.auth_data.chap.
  370. intr_chap_name_length,
  371. (char *)&boot_conn->negotiated_login_options.
  372. auth_data.chap.intr_chap_name);
  373. break;
  374. case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
  375. rc = sprintf(str, "%.*s\n",
  376. boot_conn->negotiated_login_options.auth_data.chap.
  377. intr_secret_length,
  378. (char *)&boot_conn->negotiated_login_options.
  379. auth_data.chap.intr_secret);
  380. break;
  381. case ISCSI_BOOT_TGT_FLAGS:
  382. rc = sprintf(str, "2\n");
  383. break;
  384. case ISCSI_BOOT_TGT_NIC_ASSOC:
  385. rc = sprintf(str, "0\n");
  386. break;
  387. default:
  388. rc = -ENOSYS;
  389. break;
  390. }
  391. return rc;
  392. }
  393. static ssize_t beiscsi_show_boot_ini_info(void *data, int type, char *buf)
  394. {
  395. struct beiscsi_hba *phba = data;
  396. char *str = buf;
  397. int rc;
  398. switch (type) {
  399. case ISCSI_BOOT_INI_INITIATOR_NAME:
  400. rc = sprintf(str, "%s\n", phba->boot_sess.initiator_iscsiname);
  401. break;
  402. default:
  403. rc = -ENOSYS;
  404. break;
  405. }
  406. return rc;
  407. }
  408. static ssize_t beiscsi_show_boot_eth_info(void *data, int type, char *buf)
  409. {
  410. struct beiscsi_hba *phba = data;
  411. char *str = buf;
  412. int rc;
  413. switch (type) {
  414. case ISCSI_BOOT_ETH_FLAGS:
  415. rc = sprintf(str, "2\n");
  416. break;
  417. case ISCSI_BOOT_ETH_INDEX:
  418. rc = sprintf(str, "0\n");
  419. break;
  420. case ISCSI_BOOT_ETH_MAC:
  421. rc = beiscsi_get_macaddr(str, phba);
  422. break;
  423. default:
  424. rc = -ENOSYS;
  425. break;
  426. }
  427. return rc;
  428. }
  429. static umode_t beiscsi_tgt_get_attr_visibility(void *data, int type)
  430. {
  431. umode_t rc;
  432. switch (type) {
  433. case ISCSI_BOOT_TGT_NAME:
  434. case ISCSI_BOOT_TGT_IP_ADDR:
  435. case ISCSI_BOOT_TGT_PORT:
  436. case ISCSI_BOOT_TGT_CHAP_NAME:
  437. case ISCSI_BOOT_TGT_CHAP_SECRET:
  438. case ISCSI_BOOT_TGT_REV_CHAP_NAME:
  439. case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
  440. case ISCSI_BOOT_TGT_NIC_ASSOC:
  441. case ISCSI_BOOT_TGT_FLAGS:
  442. rc = S_IRUGO;
  443. break;
  444. default:
  445. rc = 0;
  446. break;
  447. }
  448. return rc;
  449. }
  450. static umode_t beiscsi_ini_get_attr_visibility(void *data, int type)
  451. {
  452. umode_t rc;
  453. switch (type) {
  454. case ISCSI_BOOT_INI_INITIATOR_NAME:
  455. rc = S_IRUGO;
  456. break;
  457. default:
  458. rc = 0;
  459. break;
  460. }
  461. return rc;
  462. }
  463. static umode_t beiscsi_eth_get_attr_visibility(void *data, int type)
  464. {
  465. umode_t rc;
  466. switch (type) {
  467. case ISCSI_BOOT_ETH_FLAGS:
  468. case ISCSI_BOOT_ETH_MAC:
  469. case ISCSI_BOOT_ETH_INDEX:
  470. rc = S_IRUGO;
  471. break;
  472. default:
  473. rc = 0;
  474. break;
  475. }
  476. return rc;
  477. }
  478. /*------------------- PCI Driver operations and data ----------------- */
  479. static DEFINE_PCI_DEVICE_TABLE(beiscsi_pci_id_table) = {
  480. { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
  481. { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
  482. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
  483. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
  484. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID3) },
  485. { PCI_DEVICE(ELX_VENDOR_ID, OC_SKH_ID1) },
  486. { 0 }
  487. };
  488. MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table);
  489. static struct scsi_host_template beiscsi_sht = {
  490. .module = THIS_MODULE,
  491. .name = "Emulex 10Gbe open-iscsi Initiator Driver",
  492. .proc_name = DRV_NAME,
  493. .queuecommand = iscsi_queuecommand,
  494. .change_queue_depth = iscsi_change_queue_depth,
  495. .slave_configure = beiscsi_slave_configure,
  496. .target_alloc = iscsi_target_alloc,
  497. .eh_abort_handler = beiscsi_eh_abort,
  498. .eh_device_reset_handler = beiscsi_eh_device_reset,
  499. .eh_target_reset_handler = iscsi_eh_session_reset,
  500. .shost_attrs = beiscsi_attrs,
  501. .sg_tablesize = BEISCSI_SGLIST_ELEMENTS,
  502. .can_queue = BE2_IO_DEPTH,
  503. .this_id = -1,
  504. .max_sectors = BEISCSI_MAX_SECTORS,
  505. .cmd_per_lun = BEISCSI_CMD_PER_LUN,
  506. .use_clustering = ENABLE_CLUSTERING,
  507. .vendor_id = SCSI_NL_VID_TYPE_PCI | BE_VENDOR_ID,
  508. };
  509. static struct scsi_transport_template *beiscsi_scsi_transport;
  510. static struct beiscsi_hba *beiscsi_hba_alloc(struct pci_dev *pcidev)
  511. {
  512. struct beiscsi_hba *phba;
  513. struct Scsi_Host *shost;
  514. shost = iscsi_host_alloc(&beiscsi_sht, sizeof(*phba), 0);
  515. if (!shost) {
  516. dev_err(&pcidev->dev,
  517. "beiscsi_hba_alloc - iscsi_host_alloc failed\n");
  518. return NULL;
  519. }
  520. shost->dma_boundary = pcidev->dma_mask;
  521. shost->max_id = BE2_MAX_SESSIONS;
  522. shost->max_channel = 0;
  523. shost->max_cmd_len = BEISCSI_MAX_CMD_LEN;
  524. shost->max_lun = BEISCSI_NUM_MAX_LUN;
  525. shost->transportt = beiscsi_scsi_transport;
  526. phba = iscsi_host_priv(shost);
  527. memset(phba, 0, sizeof(*phba));
  528. phba->shost = shost;
  529. phba->pcidev = pci_dev_get(pcidev);
  530. pci_set_drvdata(pcidev, phba);
  531. phba->interface_handle = 0xFFFFFFFF;
  532. if (iscsi_host_add(shost, &phba->pcidev->dev))
  533. goto free_devices;
  534. return phba;
  535. free_devices:
  536. pci_dev_put(phba->pcidev);
  537. iscsi_host_free(phba->shost);
  538. return NULL;
  539. }
  540. static void beiscsi_unmap_pci_function(struct beiscsi_hba *phba)
  541. {
  542. if (phba->csr_va) {
  543. iounmap(phba->csr_va);
  544. phba->csr_va = NULL;
  545. }
  546. if (phba->db_va) {
  547. iounmap(phba->db_va);
  548. phba->db_va = NULL;
  549. }
  550. if (phba->pci_va) {
  551. iounmap(phba->pci_va);
  552. phba->pci_va = NULL;
  553. }
  554. }
  555. static int beiscsi_map_pci_bars(struct beiscsi_hba *phba,
  556. struct pci_dev *pcidev)
  557. {
  558. u8 __iomem *addr;
  559. int pcicfg_reg;
  560. addr = ioremap_nocache(pci_resource_start(pcidev, 2),
  561. pci_resource_len(pcidev, 2));
  562. if (addr == NULL)
  563. return -ENOMEM;
  564. phba->ctrl.csr = addr;
  565. phba->csr_va = addr;
  566. phba->csr_pa.u.a64.address = pci_resource_start(pcidev, 2);
  567. addr = ioremap_nocache(pci_resource_start(pcidev, 4), 128 * 1024);
  568. if (addr == NULL)
  569. goto pci_map_err;
  570. phba->ctrl.db = addr;
  571. phba->db_va = addr;
  572. phba->db_pa.u.a64.address = pci_resource_start(pcidev, 4);
  573. if (phba->generation == BE_GEN2)
  574. pcicfg_reg = 1;
  575. else
  576. pcicfg_reg = 0;
  577. addr = ioremap_nocache(pci_resource_start(pcidev, pcicfg_reg),
  578. pci_resource_len(pcidev, pcicfg_reg));
  579. if (addr == NULL)
  580. goto pci_map_err;
  581. phba->ctrl.pcicfg = addr;
  582. phba->pci_va = addr;
  583. phba->pci_pa.u.a64.address = pci_resource_start(pcidev, pcicfg_reg);
  584. return 0;
  585. pci_map_err:
  586. beiscsi_unmap_pci_function(phba);
  587. return -ENOMEM;
  588. }
  589. static int beiscsi_enable_pci(struct pci_dev *pcidev)
  590. {
  591. int ret;
  592. ret = pci_enable_device(pcidev);
  593. if (ret) {
  594. dev_err(&pcidev->dev,
  595. "beiscsi_enable_pci - enable device failed\n");
  596. return ret;
  597. }
  598. pci_set_master(pcidev);
  599. if (pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(64))) {
  600. ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(32));
  601. if (ret) {
  602. dev_err(&pcidev->dev, "Could not set PCI DMA Mask\n");
  603. pci_disable_device(pcidev);
  604. return ret;
  605. }
  606. }
  607. return 0;
  608. }
  609. static int be_ctrl_init(struct beiscsi_hba *phba, struct pci_dev *pdev)
  610. {
  611. struct be_ctrl_info *ctrl = &phba->ctrl;
  612. struct be_dma_mem *mbox_mem_alloc = &ctrl->mbox_mem_alloced;
  613. struct be_dma_mem *mbox_mem_align = &ctrl->mbox_mem;
  614. int status = 0;
  615. ctrl->pdev = pdev;
  616. status = beiscsi_map_pci_bars(phba, pdev);
  617. if (status)
  618. return status;
  619. mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
  620. mbox_mem_alloc->va = pci_alloc_consistent(pdev,
  621. mbox_mem_alloc->size,
  622. &mbox_mem_alloc->dma);
  623. if (!mbox_mem_alloc->va) {
  624. beiscsi_unmap_pci_function(phba);
  625. return -ENOMEM;
  626. }
  627. mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
  628. mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
  629. mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
  630. memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
  631. spin_lock_init(&ctrl->mbox_lock);
  632. spin_lock_init(&phba->ctrl.mcc_lock);
  633. spin_lock_init(&phba->ctrl.mcc_cq_lock);
  634. return status;
  635. }
  636. static void beiscsi_get_params(struct beiscsi_hba *phba)
  637. {
  638. phba->params.ios_per_ctrl = (phba->fw_config.iscsi_icd_count
  639. - (phba->fw_config.iscsi_cid_count
  640. + BE2_TMFS
  641. + BE2_NOPOUT_REQ));
  642. phba->params.cxns_per_ctrl = phba->fw_config.iscsi_cid_count;
  643. phba->params.asyncpdus_per_ctrl = phba->fw_config.iscsi_cid_count * 2;
  644. phba->params.icds_per_ctrl = phba->fw_config.iscsi_icd_count;
  645. phba->params.num_sge_per_io = BE2_SGE;
  646. phba->params.defpdu_hdr_sz = BE2_DEFPDU_HDR_SZ;
  647. phba->params.defpdu_data_sz = BE2_DEFPDU_DATA_SZ;
  648. phba->params.eq_timer = 64;
  649. phba->params.num_eq_entries =
  650. (((BE2_CMDS_PER_CXN * 2 + phba->fw_config.iscsi_cid_count * 2
  651. + BE2_TMFS) / 512) + 1) * 512;
  652. phba->params.num_eq_entries = (phba->params.num_eq_entries < 1024)
  653. ? 1024 : phba->params.num_eq_entries;
  654. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  655. "BM_%d : phba->params.num_eq_entries=%d\n",
  656. phba->params.num_eq_entries);
  657. phba->params.num_cq_entries =
  658. (((BE2_CMDS_PER_CXN * 2 + phba->fw_config.iscsi_cid_count * 2
  659. + BE2_TMFS) / 512) + 1) * 512;
  660. phba->params.wrbs_per_cxn = 256;
  661. }
  662. static void hwi_ring_eq_db(struct beiscsi_hba *phba,
  663. unsigned int id, unsigned int clr_interrupt,
  664. unsigned int num_processed,
  665. unsigned char rearm, unsigned char event)
  666. {
  667. u32 val = 0;
  668. val |= id & DB_EQ_RING_ID_MASK;
  669. if (rearm)
  670. val |= 1 << DB_EQ_REARM_SHIFT;
  671. if (clr_interrupt)
  672. val |= 1 << DB_EQ_CLR_SHIFT;
  673. if (event)
  674. val |= 1 << DB_EQ_EVNT_SHIFT;
  675. val |= num_processed << DB_EQ_NUM_POPPED_SHIFT;
  676. iowrite32(val, phba->db_va + DB_EQ_OFFSET);
  677. }
  678. /**
  679. * be_isr_mcc - The isr routine of the driver.
  680. * @irq: Not used
  681. * @dev_id: Pointer to host adapter structure
  682. */
  683. static irqreturn_t be_isr_mcc(int irq, void *dev_id)
  684. {
  685. struct beiscsi_hba *phba;
  686. struct be_eq_entry *eqe = NULL;
  687. struct be_queue_info *eq;
  688. struct be_queue_info *mcc;
  689. unsigned int num_eq_processed;
  690. struct be_eq_obj *pbe_eq;
  691. unsigned long flags;
  692. pbe_eq = dev_id;
  693. eq = &pbe_eq->q;
  694. phba = pbe_eq->phba;
  695. mcc = &phba->ctrl.mcc_obj.cq;
  696. eqe = queue_tail_node(eq);
  697. num_eq_processed = 0;
  698. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  699. & EQE_VALID_MASK) {
  700. if (((eqe->dw[offsetof(struct amap_eq_entry,
  701. resource_id) / 32] &
  702. EQE_RESID_MASK) >> 16) == mcc->id) {
  703. spin_lock_irqsave(&phba->isr_lock, flags);
  704. pbe_eq->todo_mcc_cq = true;
  705. spin_unlock_irqrestore(&phba->isr_lock, flags);
  706. }
  707. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  708. queue_tail_inc(eq);
  709. eqe = queue_tail_node(eq);
  710. num_eq_processed++;
  711. }
  712. if (pbe_eq->todo_mcc_cq)
  713. queue_work(phba->wq, &pbe_eq->work_cqs);
  714. if (num_eq_processed)
  715. hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 1, 1);
  716. return IRQ_HANDLED;
  717. }
  718. /**
  719. * be_isr_msix - The isr routine of the driver.
  720. * @irq: Not used
  721. * @dev_id: Pointer to host adapter structure
  722. */
  723. static irqreturn_t be_isr_msix(int irq, void *dev_id)
  724. {
  725. struct beiscsi_hba *phba;
  726. struct be_eq_entry *eqe = NULL;
  727. struct be_queue_info *eq;
  728. struct be_queue_info *cq;
  729. unsigned int num_eq_processed;
  730. struct be_eq_obj *pbe_eq;
  731. unsigned long flags;
  732. pbe_eq = dev_id;
  733. eq = &pbe_eq->q;
  734. cq = pbe_eq->cq;
  735. eqe = queue_tail_node(eq);
  736. phba = pbe_eq->phba;
  737. num_eq_processed = 0;
  738. if (blk_iopoll_enabled) {
  739. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  740. & EQE_VALID_MASK) {
  741. if (!blk_iopoll_sched_prep(&pbe_eq->iopoll))
  742. blk_iopoll_sched(&pbe_eq->iopoll);
  743. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  744. queue_tail_inc(eq);
  745. eqe = queue_tail_node(eq);
  746. num_eq_processed++;
  747. }
  748. } else {
  749. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  750. & EQE_VALID_MASK) {
  751. spin_lock_irqsave(&phba->isr_lock, flags);
  752. pbe_eq->todo_cq = true;
  753. spin_unlock_irqrestore(&phba->isr_lock, flags);
  754. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  755. queue_tail_inc(eq);
  756. eqe = queue_tail_node(eq);
  757. num_eq_processed++;
  758. }
  759. if (pbe_eq->todo_cq)
  760. queue_work(phba->wq, &pbe_eq->work_cqs);
  761. }
  762. if (num_eq_processed)
  763. hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 0, 1);
  764. return IRQ_HANDLED;
  765. }
  766. /**
  767. * be_isr - The isr routine of the driver.
  768. * @irq: Not used
  769. * @dev_id: Pointer to host adapter structure
  770. */
  771. static irqreturn_t be_isr(int irq, void *dev_id)
  772. {
  773. struct beiscsi_hba *phba;
  774. struct hwi_controller *phwi_ctrlr;
  775. struct hwi_context_memory *phwi_context;
  776. struct be_eq_entry *eqe = NULL;
  777. struct be_queue_info *eq;
  778. struct be_queue_info *cq;
  779. struct be_queue_info *mcc;
  780. unsigned long flags, index;
  781. unsigned int num_mcceq_processed, num_ioeq_processed;
  782. struct be_ctrl_info *ctrl;
  783. struct be_eq_obj *pbe_eq;
  784. int isr;
  785. phba = dev_id;
  786. ctrl = &phba->ctrl;
  787. isr = ioread32(ctrl->csr + CEV_ISR0_OFFSET +
  788. (PCI_FUNC(ctrl->pdev->devfn) * CEV_ISR_SIZE));
  789. if (!isr)
  790. return IRQ_NONE;
  791. phwi_ctrlr = phba->phwi_ctrlr;
  792. phwi_context = phwi_ctrlr->phwi_ctxt;
  793. pbe_eq = &phwi_context->be_eq[0];
  794. eq = &phwi_context->be_eq[0].q;
  795. mcc = &phba->ctrl.mcc_obj.cq;
  796. index = 0;
  797. eqe = queue_tail_node(eq);
  798. num_ioeq_processed = 0;
  799. num_mcceq_processed = 0;
  800. if (blk_iopoll_enabled) {
  801. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  802. & EQE_VALID_MASK) {
  803. if (((eqe->dw[offsetof(struct amap_eq_entry,
  804. resource_id) / 32] &
  805. EQE_RESID_MASK) >> 16) == mcc->id) {
  806. spin_lock_irqsave(&phba->isr_lock, flags);
  807. pbe_eq->todo_mcc_cq = true;
  808. spin_unlock_irqrestore(&phba->isr_lock, flags);
  809. num_mcceq_processed++;
  810. } else {
  811. if (!blk_iopoll_sched_prep(&pbe_eq->iopoll))
  812. blk_iopoll_sched(&pbe_eq->iopoll);
  813. num_ioeq_processed++;
  814. }
  815. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  816. queue_tail_inc(eq);
  817. eqe = queue_tail_node(eq);
  818. }
  819. if (num_ioeq_processed || num_mcceq_processed) {
  820. if (pbe_eq->todo_mcc_cq)
  821. queue_work(phba->wq, &pbe_eq->work_cqs);
  822. if ((num_mcceq_processed) && (!num_ioeq_processed))
  823. hwi_ring_eq_db(phba, eq->id, 0,
  824. (num_ioeq_processed +
  825. num_mcceq_processed) , 1, 1);
  826. else
  827. hwi_ring_eq_db(phba, eq->id, 0,
  828. (num_ioeq_processed +
  829. num_mcceq_processed), 0, 1);
  830. return IRQ_HANDLED;
  831. } else
  832. return IRQ_NONE;
  833. } else {
  834. cq = &phwi_context->be_cq[0];
  835. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  836. & EQE_VALID_MASK) {
  837. if (((eqe->dw[offsetof(struct amap_eq_entry,
  838. resource_id) / 32] &
  839. EQE_RESID_MASK) >> 16) != cq->id) {
  840. spin_lock_irqsave(&phba->isr_lock, flags);
  841. pbe_eq->todo_mcc_cq = true;
  842. spin_unlock_irqrestore(&phba->isr_lock, flags);
  843. } else {
  844. spin_lock_irqsave(&phba->isr_lock, flags);
  845. pbe_eq->todo_cq = true;
  846. spin_unlock_irqrestore(&phba->isr_lock, flags);
  847. }
  848. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  849. queue_tail_inc(eq);
  850. eqe = queue_tail_node(eq);
  851. num_ioeq_processed++;
  852. }
  853. if (pbe_eq->todo_cq || pbe_eq->todo_mcc_cq)
  854. queue_work(phba->wq, &pbe_eq->work_cqs);
  855. if (num_ioeq_processed) {
  856. hwi_ring_eq_db(phba, eq->id, 0,
  857. num_ioeq_processed, 1, 1);
  858. return IRQ_HANDLED;
  859. } else
  860. return IRQ_NONE;
  861. }
  862. }
  863. static int beiscsi_init_irqs(struct beiscsi_hba *phba)
  864. {
  865. struct pci_dev *pcidev = phba->pcidev;
  866. struct hwi_controller *phwi_ctrlr;
  867. struct hwi_context_memory *phwi_context;
  868. int ret, msix_vec, i, j;
  869. phwi_ctrlr = phba->phwi_ctrlr;
  870. phwi_context = phwi_ctrlr->phwi_ctxt;
  871. if (phba->msix_enabled) {
  872. for (i = 0; i < phba->num_cpus; i++) {
  873. phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME,
  874. GFP_KERNEL);
  875. if (!phba->msi_name[i]) {
  876. ret = -ENOMEM;
  877. goto free_msix_irqs;
  878. }
  879. sprintf(phba->msi_name[i], "beiscsi_%02x_%02x",
  880. phba->shost->host_no, i);
  881. msix_vec = phba->msix_entries[i].vector;
  882. ret = request_irq(msix_vec, be_isr_msix, 0,
  883. phba->msi_name[i],
  884. &phwi_context->be_eq[i]);
  885. if (ret) {
  886. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  887. "BM_%d : beiscsi_init_irqs-Failed to"
  888. "register msix for i = %d\n",
  889. i);
  890. kfree(phba->msi_name[i]);
  891. goto free_msix_irqs;
  892. }
  893. }
  894. phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME, GFP_KERNEL);
  895. if (!phba->msi_name[i]) {
  896. ret = -ENOMEM;
  897. goto free_msix_irqs;
  898. }
  899. sprintf(phba->msi_name[i], "beiscsi_mcc_%02x",
  900. phba->shost->host_no);
  901. msix_vec = phba->msix_entries[i].vector;
  902. ret = request_irq(msix_vec, be_isr_mcc, 0, phba->msi_name[i],
  903. &phwi_context->be_eq[i]);
  904. if (ret) {
  905. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT ,
  906. "BM_%d : beiscsi_init_irqs-"
  907. "Failed to register beiscsi_msix_mcc\n");
  908. kfree(phba->msi_name[i]);
  909. goto free_msix_irqs;
  910. }
  911. } else {
  912. ret = request_irq(pcidev->irq, be_isr, IRQF_SHARED,
  913. "beiscsi", phba);
  914. if (ret) {
  915. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  916. "BM_%d : beiscsi_init_irqs-"
  917. "Failed to register irq\\n");
  918. return ret;
  919. }
  920. }
  921. return 0;
  922. free_msix_irqs:
  923. for (j = i - 1; j >= 0; j--) {
  924. kfree(phba->msi_name[j]);
  925. msix_vec = phba->msix_entries[j].vector;
  926. free_irq(msix_vec, &phwi_context->be_eq[j]);
  927. }
  928. return ret;
  929. }
  930. static void hwi_ring_cq_db(struct beiscsi_hba *phba,
  931. unsigned int id, unsigned int num_processed,
  932. unsigned char rearm, unsigned char event)
  933. {
  934. u32 val = 0;
  935. val |= id & DB_CQ_RING_ID_MASK;
  936. if (rearm)
  937. val |= 1 << DB_CQ_REARM_SHIFT;
  938. val |= num_processed << DB_CQ_NUM_POPPED_SHIFT;
  939. iowrite32(val, phba->db_va + DB_CQ_OFFSET);
  940. }
  941. static unsigned int
  942. beiscsi_process_async_pdu(struct beiscsi_conn *beiscsi_conn,
  943. struct beiscsi_hba *phba,
  944. unsigned short cid,
  945. struct pdu_base *ppdu,
  946. unsigned long pdu_len,
  947. void *pbuffer, unsigned long buf_len)
  948. {
  949. struct iscsi_conn *conn = beiscsi_conn->conn;
  950. struct iscsi_session *session = conn->session;
  951. struct iscsi_task *task;
  952. struct beiscsi_io_task *io_task;
  953. struct iscsi_hdr *login_hdr;
  954. switch (ppdu->dw[offsetof(struct amap_pdu_base, opcode) / 32] &
  955. PDUBASE_OPCODE_MASK) {
  956. case ISCSI_OP_NOOP_IN:
  957. pbuffer = NULL;
  958. buf_len = 0;
  959. break;
  960. case ISCSI_OP_ASYNC_EVENT:
  961. break;
  962. case ISCSI_OP_REJECT:
  963. WARN_ON(!pbuffer);
  964. WARN_ON(!(buf_len == 48));
  965. beiscsi_log(phba, KERN_ERR,
  966. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  967. "BM_%d : In ISCSI_OP_REJECT\n");
  968. break;
  969. case ISCSI_OP_LOGIN_RSP:
  970. case ISCSI_OP_TEXT_RSP:
  971. task = conn->login_task;
  972. io_task = task->dd_data;
  973. login_hdr = (struct iscsi_hdr *)ppdu;
  974. login_hdr->itt = io_task->libiscsi_itt;
  975. break;
  976. default:
  977. beiscsi_log(phba, KERN_WARNING,
  978. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  979. "BM_%d : Unrecognized opcode 0x%x in async msg\n",
  980. (ppdu->
  981. dw[offsetof(struct amap_pdu_base, opcode) / 32]
  982. & PDUBASE_OPCODE_MASK));
  983. return 1;
  984. }
  985. spin_lock_bh(&session->lock);
  986. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)ppdu, pbuffer, buf_len);
  987. spin_unlock_bh(&session->lock);
  988. return 0;
  989. }
  990. static struct sgl_handle *alloc_io_sgl_handle(struct beiscsi_hba *phba)
  991. {
  992. struct sgl_handle *psgl_handle;
  993. if (phba->io_sgl_hndl_avbl) {
  994. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
  995. "BM_%d : In alloc_io_sgl_handle,"
  996. " io_sgl_alloc_index=%d\n",
  997. phba->io_sgl_alloc_index);
  998. psgl_handle = phba->io_sgl_hndl_base[phba->
  999. io_sgl_alloc_index];
  1000. phba->io_sgl_hndl_base[phba->io_sgl_alloc_index] = NULL;
  1001. phba->io_sgl_hndl_avbl--;
  1002. if (phba->io_sgl_alloc_index == (phba->params.
  1003. ios_per_ctrl - 1))
  1004. phba->io_sgl_alloc_index = 0;
  1005. else
  1006. phba->io_sgl_alloc_index++;
  1007. } else
  1008. psgl_handle = NULL;
  1009. return psgl_handle;
  1010. }
  1011. static void
  1012. free_io_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
  1013. {
  1014. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
  1015. "BM_%d : In free_,io_sgl_free_index=%d\n",
  1016. phba->io_sgl_free_index);
  1017. if (phba->io_sgl_hndl_base[phba->io_sgl_free_index]) {
  1018. /*
  1019. * this can happen if clean_task is called on a task that
  1020. * failed in xmit_task or alloc_pdu.
  1021. */
  1022. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
  1023. "BM_%d : Double Free in IO SGL io_sgl_free_index=%d,"
  1024. "value there=%p\n", phba->io_sgl_free_index,
  1025. phba->io_sgl_hndl_base
  1026. [phba->io_sgl_free_index]);
  1027. return;
  1028. }
  1029. phba->io_sgl_hndl_base[phba->io_sgl_free_index] = psgl_handle;
  1030. phba->io_sgl_hndl_avbl++;
  1031. if (phba->io_sgl_free_index == (phba->params.ios_per_ctrl - 1))
  1032. phba->io_sgl_free_index = 0;
  1033. else
  1034. phba->io_sgl_free_index++;
  1035. }
  1036. /**
  1037. * alloc_wrb_handle - To allocate a wrb handle
  1038. * @phba: The hba pointer
  1039. * @cid: The cid to use for allocation
  1040. *
  1041. * This happens under session_lock until submission to chip
  1042. */
  1043. struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid)
  1044. {
  1045. struct hwi_wrb_context *pwrb_context;
  1046. struct hwi_controller *phwi_ctrlr;
  1047. struct wrb_handle *pwrb_handle, *pwrb_handle_tmp;
  1048. phwi_ctrlr = phba->phwi_ctrlr;
  1049. pwrb_context = &phwi_ctrlr->wrb_context[cid];
  1050. if (pwrb_context->wrb_handles_available >= 2) {
  1051. pwrb_handle = pwrb_context->pwrb_handle_base[
  1052. pwrb_context->alloc_index];
  1053. pwrb_context->wrb_handles_available--;
  1054. if (pwrb_context->alloc_index ==
  1055. (phba->params.wrbs_per_cxn - 1))
  1056. pwrb_context->alloc_index = 0;
  1057. else
  1058. pwrb_context->alloc_index++;
  1059. pwrb_handle_tmp = pwrb_context->pwrb_handle_base[
  1060. pwrb_context->alloc_index];
  1061. pwrb_handle->nxt_wrb_index = pwrb_handle_tmp->wrb_index;
  1062. } else
  1063. pwrb_handle = NULL;
  1064. return pwrb_handle;
  1065. }
  1066. /**
  1067. * free_wrb_handle - To free the wrb handle back to pool
  1068. * @phba: The hba pointer
  1069. * @pwrb_context: The context to free from
  1070. * @pwrb_handle: The wrb_handle to free
  1071. *
  1072. * This happens under session_lock until submission to chip
  1073. */
  1074. static void
  1075. free_wrb_handle(struct beiscsi_hba *phba, struct hwi_wrb_context *pwrb_context,
  1076. struct wrb_handle *pwrb_handle)
  1077. {
  1078. pwrb_context->pwrb_handle_base[pwrb_context->free_index] = pwrb_handle;
  1079. pwrb_context->wrb_handles_available++;
  1080. if (pwrb_context->free_index == (phba->params.wrbs_per_cxn - 1))
  1081. pwrb_context->free_index = 0;
  1082. else
  1083. pwrb_context->free_index++;
  1084. beiscsi_log(phba, KERN_INFO,
  1085. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1086. "BM_%d : FREE WRB: pwrb_handle=%p free_index=0x%x"
  1087. "wrb_handles_available=%d\n",
  1088. pwrb_handle, pwrb_context->free_index,
  1089. pwrb_context->wrb_handles_available);
  1090. }
  1091. static struct sgl_handle *alloc_mgmt_sgl_handle(struct beiscsi_hba *phba)
  1092. {
  1093. struct sgl_handle *psgl_handle;
  1094. if (phba->eh_sgl_hndl_avbl) {
  1095. psgl_handle = phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index];
  1096. phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index] = NULL;
  1097. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG,
  1098. "BM_%d : mgmt_sgl_alloc_index=%d=0x%x\n",
  1099. phba->eh_sgl_alloc_index,
  1100. phba->eh_sgl_alloc_index);
  1101. phba->eh_sgl_hndl_avbl--;
  1102. if (phba->eh_sgl_alloc_index ==
  1103. (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl -
  1104. 1))
  1105. phba->eh_sgl_alloc_index = 0;
  1106. else
  1107. phba->eh_sgl_alloc_index++;
  1108. } else
  1109. psgl_handle = NULL;
  1110. return psgl_handle;
  1111. }
  1112. void
  1113. free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
  1114. {
  1115. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG,
  1116. "BM_%d : In free_mgmt_sgl_handle,"
  1117. "eh_sgl_free_index=%d\n",
  1118. phba->eh_sgl_free_index);
  1119. if (phba->eh_sgl_hndl_base[phba->eh_sgl_free_index]) {
  1120. /*
  1121. * this can happen if clean_task is called on a task that
  1122. * failed in xmit_task or alloc_pdu.
  1123. */
  1124. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_CONFIG,
  1125. "BM_%d : Double Free in eh SGL ,"
  1126. "eh_sgl_free_index=%d\n",
  1127. phba->eh_sgl_free_index);
  1128. return;
  1129. }
  1130. phba->eh_sgl_hndl_base[phba->eh_sgl_free_index] = psgl_handle;
  1131. phba->eh_sgl_hndl_avbl++;
  1132. if (phba->eh_sgl_free_index ==
  1133. (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl - 1))
  1134. phba->eh_sgl_free_index = 0;
  1135. else
  1136. phba->eh_sgl_free_index++;
  1137. }
  1138. static void
  1139. be_complete_io(struct beiscsi_conn *beiscsi_conn,
  1140. struct iscsi_task *task,
  1141. struct common_sol_cqe *csol_cqe)
  1142. {
  1143. struct beiscsi_io_task *io_task = task->dd_data;
  1144. struct be_status_bhs *sts_bhs =
  1145. (struct be_status_bhs *)io_task->cmd_bhs;
  1146. struct iscsi_conn *conn = beiscsi_conn->conn;
  1147. unsigned char *sense;
  1148. u32 resid = 0, exp_cmdsn, max_cmdsn;
  1149. u8 rsp, status, flags;
  1150. exp_cmdsn = csol_cqe->exp_cmdsn;
  1151. max_cmdsn = (csol_cqe->exp_cmdsn +
  1152. csol_cqe->cmd_wnd - 1);
  1153. rsp = csol_cqe->i_resp;
  1154. status = csol_cqe->i_sts;
  1155. flags = csol_cqe->i_flags;
  1156. resid = csol_cqe->res_cnt;
  1157. if (!task->sc) {
  1158. if (io_task->scsi_cmnd)
  1159. scsi_dma_unmap(io_task->scsi_cmnd);
  1160. return;
  1161. }
  1162. task->sc->result = (DID_OK << 16) | status;
  1163. if (rsp != ISCSI_STATUS_CMD_COMPLETED) {
  1164. task->sc->result = DID_ERROR << 16;
  1165. goto unmap;
  1166. }
  1167. /* bidi not initially supported */
  1168. if (flags & (ISCSI_FLAG_CMD_UNDERFLOW | ISCSI_FLAG_CMD_OVERFLOW)) {
  1169. if (!status && (flags & ISCSI_FLAG_CMD_OVERFLOW))
  1170. task->sc->result = DID_ERROR << 16;
  1171. if (flags & ISCSI_FLAG_CMD_UNDERFLOW) {
  1172. scsi_set_resid(task->sc, resid);
  1173. if (!status && (scsi_bufflen(task->sc) - resid <
  1174. task->sc->underflow))
  1175. task->sc->result = DID_ERROR << 16;
  1176. }
  1177. }
  1178. if (status == SAM_STAT_CHECK_CONDITION) {
  1179. u16 sense_len;
  1180. unsigned short *slen = (unsigned short *)sts_bhs->sense_info;
  1181. sense = sts_bhs->sense_info + sizeof(unsigned short);
  1182. sense_len = be16_to_cpu(*slen);
  1183. memcpy(task->sc->sense_buffer, sense,
  1184. min_t(u16, sense_len, SCSI_SENSE_BUFFERSIZE));
  1185. }
  1186. if (io_task->cmd_bhs->iscsi_hdr.flags & ISCSI_FLAG_CMD_READ)
  1187. conn->rxdata_octets += resid;
  1188. unmap:
  1189. scsi_dma_unmap(io_task->scsi_cmnd);
  1190. iscsi_complete_scsi_task(task, exp_cmdsn, max_cmdsn);
  1191. }
  1192. static void
  1193. be_complete_logout(struct beiscsi_conn *beiscsi_conn,
  1194. struct iscsi_task *task,
  1195. struct common_sol_cqe *csol_cqe)
  1196. {
  1197. struct iscsi_logout_rsp *hdr;
  1198. struct beiscsi_io_task *io_task = task->dd_data;
  1199. struct iscsi_conn *conn = beiscsi_conn->conn;
  1200. hdr = (struct iscsi_logout_rsp *)task->hdr;
  1201. hdr->opcode = ISCSI_OP_LOGOUT_RSP;
  1202. hdr->t2wait = 5;
  1203. hdr->t2retain = 0;
  1204. hdr->flags = csol_cqe->i_flags;
  1205. hdr->response = csol_cqe->i_resp;
  1206. hdr->exp_cmdsn = csol_cqe->exp_cmdsn;
  1207. hdr->max_cmdsn = (csol_cqe->exp_cmdsn + csol_cqe->cmd_wnd - 1);
  1208. hdr->dlength[0] = 0;
  1209. hdr->dlength[1] = 0;
  1210. hdr->dlength[2] = 0;
  1211. hdr->hlength = 0;
  1212. hdr->itt = io_task->libiscsi_itt;
  1213. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1214. }
  1215. static void
  1216. be_complete_tmf(struct beiscsi_conn *beiscsi_conn,
  1217. struct iscsi_task *task,
  1218. struct common_sol_cqe *csol_cqe)
  1219. {
  1220. struct iscsi_tm_rsp *hdr;
  1221. struct iscsi_conn *conn = beiscsi_conn->conn;
  1222. struct beiscsi_io_task *io_task = task->dd_data;
  1223. hdr = (struct iscsi_tm_rsp *)task->hdr;
  1224. hdr->opcode = ISCSI_OP_SCSI_TMFUNC_RSP;
  1225. hdr->flags = csol_cqe->i_flags;
  1226. hdr->response = csol_cqe->i_resp;
  1227. hdr->exp_cmdsn = csol_cqe->exp_cmdsn;
  1228. hdr->max_cmdsn = (csol_cqe->exp_cmdsn +
  1229. csol_cqe->cmd_wnd - 1);
  1230. hdr->itt = io_task->libiscsi_itt;
  1231. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1232. }
  1233. static void
  1234. hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
  1235. struct beiscsi_hba *phba, struct sol_cqe *psol)
  1236. {
  1237. struct hwi_wrb_context *pwrb_context;
  1238. struct wrb_handle *pwrb_handle = NULL;
  1239. struct hwi_controller *phwi_ctrlr;
  1240. struct iscsi_task *task;
  1241. struct beiscsi_io_task *io_task;
  1242. struct iscsi_conn *conn = beiscsi_conn->conn;
  1243. struct iscsi_session *session = conn->session;
  1244. uint16_t wrb_index, cid;
  1245. phwi_ctrlr = phba->phwi_ctrlr;
  1246. if (chip_skh_r(phba->pcidev)) {
  1247. wrb_index = AMAP_GET_BITS(struct amap_it_dmsg_cqe_v2,
  1248. wrb_idx, psol);
  1249. cid = AMAP_GET_BITS(struct amap_it_dmsg_cqe_v2,
  1250. cid, psol);
  1251. } else {
  1252. wrb_index = AMAP_GET_BITS(struct amap_it_dmsg_cqe,
  1253. wrb_idx, psol);
  1254. cid = AMAP_GET_BITS(struct amap_it_dmsg_cqe,
  1255. cid, psol);
  1256. }
  1257. pwrb_context = &phwi_ctrlr->wrb_context[
  1258. cid - phba->fw_config.iscsi_cid_start];
  1259. pwrb_handle = pwrb_context->pwrb_handle_basestd[wrb_index];
  1260. task = pwrb_handle->pio_handle;
  1261. io_task = task->dd_data;
  1262. spin_lock_bh(&phba->mgmt_sgl_lock);
  1263. free_mgmt_sgl_handle(phba, io_task->psgl_handle);
  1264. spin_unlock_bh(&phba->mgmt_sgl_lock);
  1265. spin_lock_bh(&session->lock);
  1266. free_wrb_handle(phba, pwrb_context, pwrb_handle);
  1267. spin_unlock_bh(&session->lock);
  1268. }
  1269. static void
  1270. be_complete_nopin_resp(struct beiscsi_conn *beiscsi_conn,
  1271. struct iscsi_task *task,
  1272. struct common_sol_cqe *csol_cqe)
  1273. {
  1274. struct iscsi_nopin *hdr;
  1275. struct iscsi_conn *conn = beiscsi_conn->conn;
  1276. struct beiscsi_io_task *io_task = task->dd_data;
  1277. hdr = (struct iscsi_nopin *)task->hdr;
  1278. hdr->flags = csol_cqe->i_flags;
  1279. hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn);
  1280. hdr->max_cmdsn = be32_to_cpu(hdr->exp_cmdsn +
  1281. csol_cqe->cmd_wnd - 1);
  1282. hdr->opcode = ISCSI_OP_NOOP_IN;
  1283. hdr->itt = io_task->libiscsi_itt;
  1284. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1285. }
  1286. static void adapter_get_sol_cqe(struct beiscsi_hba *phba,
  1287. struct sol_cqe *psol,
  1288. struct common_sol_cqe *csol_cqe)
  1289. {
  1290. if (chip_skh_r(phba->pcidev)) {
  1291. csol_cqe->exp_cmdsn = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1292. i_exp_cmd_sn, psol);
  1293. csol_cqe->res_cnt = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1294. i_res_cnt, psol);
  1295. csol_cqe->wrb_index = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1296. wrb_index, psol);
  1297. csol_cqe->cid = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1298. cid, psol);
  1299. csol_cqe->hw_sts = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1300. hw_sts, psol);
  1301. csol_cqe->cmd_wnd = AMAP_GET_BITS(struct amap_sol_cqe,
  1302. i_cmd_wnd, psol);
  1303. if (AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1304. cmd_cmpl, psol))
  1305. csol_cqe->i_sts = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1306. i_sts, psol);
  1307. else
  1308. csol_cqe->i_resp = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1309. i_sts, psol);
  1310. if (AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1311. u, psol))
  1312. csol_cqe->i_flags = ISCSI_FLAG_CMD_UNDERFLOW;
  1313. if (AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1314. o, psol))
  1315. csol_cqe->i_flags |= ISCSI_FLAG_CMD_OVERFLOW;
  1316. } else {
  1317. csol_cqe->exp_cmdsn = AMAP_GET_BITS(struct amap_sol_cqe,
  1318. i_exp_cmd_sn, psol);
  1319. csol_cqe->res_cnt = AMAP_GET_BITS(struct amap_sol_cqe,
  1320. i_res_cnt, psol);
  1321. csol_cqe->cmd_wnd = AMAP_GET_BITS(struct amap_sol_cqe,
  1322. i_cmd_wnd, psol);
  1323. csol_cqe->wrb_index = AMAP_GET_BITS(struct amap_sol_cqe,
  1324. wrb_index, psol);
  1325. csol_cqe->cid = AMAP_GET_BITS(struct amap_sol_cqe,
  1326. cid, psol);
  1327. csol_cqe->hw_sts = AMAP_GET_BITS(struct amap_sol_cqe,
  1328. hw_sts, psol);
  1329. csol_cqe->i_resp = AMAP_GET_BITS(struct amap_sol_cqe,
  1330. i_resp, psol);
  1331. csol_cqe->i_sts = AMAP_GET_BITS(struct amap_sol_cqe,
  1332. i_sts, psol);
  1333. csol_cqe->i_flags = AMAP_GET_BITS(struct amap_sol_cqe,
  1334. i_flags, psol);
  1335. }
  1336. }
  1337. static void hwi_complete_cmd(struct beiscsi_conn *beiscsi_conn,
  1338. struct beiscsi_hba *phba, struct sol_cqe *psol)
  1339. {
  1340. struct hwi_wrb_context *pwrb_context;
  1341. struct wrb_handle *pwrb_handle;
  1342. struct iscsi_wrb *pwrb = NULL;
  1343. struct hwi_controller *phwi_ctrlr;
  1344. struct iscsi_task *task;
  1345. unsigned int type;
  1346. struct iscsi_conn *conn = beiscsi_conn->conn;
  1347. struct iscsi_session *session = conn->session;
  1348. struct common_sol_cqe csol_cqe = {0};
  1349. phwi_ctrlr = phba->phwi_ctrlr;
  1350. /* Copy the elements to a common structure */
  1351. adapter_get_sol_cqe(phba, psol, &csol_cqe);
  1352. pwrb_context = &phwi_ctrlr->wrb_context[
  1353. csol_cqe.cid - phba->fw_config.iscsi_cid_start];
  1354. pwrb_handle = pwrb_context->pwrb_handle_basestd[
  1355. csol_cqe.wrb_index];
  1356. task = pwrb_handle->pio_handle;
  1357. pwrb = pwrb_handle->pwrb;
  1358. type = ((struct beiscsi_io_task *)task->dd_data)->wrb_type;
  1359. spin_lock_bh(&session->lock);
  1360. switch (type) {
  1361. case HWH_TYPE_IO:
  1362. case HWH_TYPE_IO_RD:
  1363. if ((task->hdr->opcode & ISCSI_OPCODE_MASK) ==
  1364. ISCSI_OP_NOOP_OUT)
  1365. be_complete_nopin_resp(beiscsi_conn, task, &csol_cqe);
  1366. else
  1367. be_complete_io(beiscsi_conn, task, &csol_cqe);
  1368. break;
  1369. case HWH_TYPE_LOGOUT:
  1370. if ((task->hdr->opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGOUT)
  1371. be_complete_logout(beiscsi_conn, task, &csol_cqe);
  1372. else
  1373. be_complete_tmf(beiscsi_conn, task, &csol_cqe);
  1374. break;
  1375. case HWH_TYPE_LOGIN:
  1376. beiscsi_log(phba, KERN_ERR,
  1377. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1378. "BM_%d :\t\t No HWH_TYPE_LOGIN Expected in"
  1379. " hwi_complete_cmd- Solicited path\n");
  1380. break;
  1381. case HWH_TYPE_NOP:
  1382. be_complete_nopin_resp(beiscsi_conn, task, &csol_cqe);
  1383. break;
  1384. default:
  1385. beiscsi_log(phba, KERN_WARNING,
  1386. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1387. "BM_%d : In hwi_complete_cmd, unknown type = %d"
  1388. "wrb_index 0x%x CID 0x%x\n", type,
  1389. csol_cqe.wrb_index,
  1390. csol_cqe.cid);
  1391. break;
  1392. }
  1393. spin_unlock_bh(&session->lock);
  1394. }
  1395. static struct list_head *hwi_get_async_busy_list(struct hwi_async_pdu_context
  1396. *pasync_ctx, unsigned int is_header,
  1397. unsigned int host_write_ptr)
  1398. {
  1399. if (is_header)
  1400. return &pasync_ctx->async_entry[host_write_ptr].
  1401. header_busy_list;
  1402. else
  1403. return &pasync_ctx->async_entry[host_write_ptr].data_busy_list;
  1404. }
  1405. static struct async_pdu_handle *
  1406. hwi_get_async_handle(struct beiscsi_hba *phba,
  1407. struct beiscsi_conn *beiscsi_conn,
  1408. struct hwi_async_pdu_context *pasync_ctx,
  1409. struct i_t_dpdu_cqe *pdpdu_cqe, unsigned int *pcq_index)
  1410. {
  1411. struct be_bus_address phys_addr;
  1412. struct list_head *pbusy_list;
  1413. struct async_pdu_handle *pasync_handle = NULL;
  1414. unsigned char is_header = 0;
  1415. unsigned int index, dpl;
  1416. if (chip_skh_r(phba->pcidev)) {
  1417. dpl = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe_v2,
  1418. dpl, pdpdu_cqe);
  1419. index = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe_v2,
  1420. index, pdpdu_cqe);
  1421. } else {
  1422. dpl = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe,
  1423. dpl, pdpdu_cqe);
  1424. index = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe,
  1425. index, pdpdu_cqe);
  1426. }
  1427. phys_addr.u.a32.address_lo =
  1428. (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1429. db_addr_lo) / 32] - dpl);
  1430. phys_addr.u.a32.address_hi =
  1431. pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1432. db_addr_hi) / 32];
  1433. phys_addr.u.a64.address =
  1434. *((unsigned long long *)(&phys_addr.u.a64.address));
  1435. switch (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, code) / 32]
  1436. & PDUCQE_CODE_MASK) {
  1437. case UNSOL_HDR_NOTIFY:
  1438. is_header = 1;
  1439. pbusy_list = hwi_get_async_busy_list(pasync_ctx,
  1440. is_header, index);
  1441. break;
  1442. case UNSOL_DATA_NOTIFY:
  1443. pbusy_list = hwi_get_async_busy_list(pasync_ctx,
  1444. is_header, index);
  1445. break;
  1446. default:
  1447. pbusy_list = NULL;
  1448. beiscsi_log(phba, KERN_WARNING,
  1449. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1450. "BM_%d : Unexpected code=%d\n",
  1451. pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1452. code) / 32] & PDUCQE_CODE_MASK);
  1453. return NULL;
  1454. }
  1455. WARN_ON(list_empty(pbusy_list));
  1456. list_for_each_entry(pasync_handle, pbusy_list, link) {
  1457. if (pasync_handle->pa.u.a64.address == phys_addr.u.a64.address)
  1458. break;
  1459. }
  1460. WARN_ON(!pasync_handle);
  1461. pasync_handle->cri = (unsigned short)beiscsi_conn->beiscsi_conn_cid -
  1462. phba->fw_config.iscsi_cid_start;
  1463. pasync_handle->is_header = is_header;
  1464. pasync_handle->buffer_len = dpl;
  1465. *pcq_index = index;
  1466. return pasync_handle;
  1467. }
  1468. static unsigned int
  1469. hwi_update_async_writables(struct beiscsi_hba *phba,
  1470. struct hwi_async_pdu_context *pasync_ctx,
  1471. unsigned int is_header, unsigned int cq_index)
  1472. {
  1473. struct list_head *pbusy_list;
  1474. struct async_pdu_handle *pasync_handle;
  1475. unsigned int num_entries, writables = 0;
  1476. unsigned int *pep_read_ptr, *pwritables;
  1477. num_entries = pasync_ctx->num_entries;
  1478. if (is_header) {
  1479. pep_read_ptr = &pasync_ctx->async_header.ep_read_ptr;
  1480. pwritables = &pasync_ctx->async_header.writables;
  1481. } else {
  1482. pep_read_ptr = &pasync_ctx->async_data.ep_read_ptr;
  1483. pwritables = &pasync_ctx->async_data.writables;
  1484. }
  1485. while ((*pep_read_ptr) != cq_index) {
  1486. (*pep_read_ptr)++;
  1487. *pep_read_ptr = (*pep_read_ptr) % num_entries;
  1488. pbusy_list = hwi_get_async_busy_list(pasync_ctx, is_header,
  1489. *pep_read_ptr);
  1490. if (writables == 0)
  1491. WARN_ON(list_empty(pbusy_list));
  1492. if (!list_empty(pbusy_list)) {
  1493. pasync_handle = list_entry(pbusy_list->next,
  1494. struct async_pdu_handle,
  1495. link);
  1496. WARN_ON(!pasync_handle);
  1497. pasync_handle->consumed = 1;
  1498. }
  1499. writables++;
  1500. }
  1501. if (!writables) {
  1502. beiscsi_log(phba, KERN_ERR,
  1503. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1504. "BM_%d : Duplicate notification received - index 0x%x!!\n",
  1505. cq_index);
  1506. WARN_ON(1);
  1507. }
  1508. *pwritables = *pwritables + writables;
  1509. return 0;
  1510. }
  1511. static void hwi_free_async_msg(struct beiscsi_hba *phba,
  1512. unsigned int cri)
  1513. {
  1514. struct hwi_controller *phwi_ctrlr;
  1515. struct hwi_async_pdu_context *pasync_ctx;
  1516. struct async_pdu_handle *pasync_handle, *tmp_handle;
  1517. struct list_head *plist;
  1518. phwi_ctrlr = phba->phwi_ctrlr;
  1519. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1520. plist = &pasync_ctx->async_entry[cri].wait_queue.list;
  1521. list_for_each_entry_safe(pasync_handle, tmp_handle, plist, link) {
  1522. list_del(&pasync_handle->link);
  1523. if (pasync_handle->is_header) {
  1524. list_add_tail(&pasync_handle->link,
  1525. &pasync_ctx->async_header.free_list);
  1526. pasync_ctx->async_header.free_entries++;
  1527. } else {
  1528. list_add_tail(&pasync_handle->link,
  1529. &pasync_ctx->async_data.free_list);
  1530. pasync_ctx->async_data.free_entries++;
  1531. }
  1532. }
  1533. INIT_LIST_HEAD(&pasync_ctx->async_entry[cri].wait_queue.list);
  1534. pasync_ctx->async_entry[cri].wait_queue.hdr_received = 0;
  1535. pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0;
  1536. }
  1537. static struct phys_addr *
  1538. hwi_get_ring_address(struct hwi_async_pdu_context *pasync_ctx,
  1539. unsigned int is_header, unsigned int host_write_ptr)
  1540. {
  1541. struct phys_addr *pasync_sge = NULL;
  1542. if (is_header)
  1543. pasync_sge = pasync_ctx->async_header.ring_base;
  1544. else
  1545. pasync_sge = pasync_ctx->async_data.ring_base;
  1546. return pasync_sge + host_write_ptr;
  1547. }
  1548. static void hwi_post_async_buffers(struct beiscsi_hba *phba,
  1549. unsigned int is_header)
  1550. {
  1551. struct hwi_controller *phwi_ctrlr;
  1552. struct hwi_async_pdu_context *pasync_ctx;
  1553. struct async_pdu_handle *pasync_handle;
  1554. struct list_head *pfree_link, *pbusy_list;
  1555. struct phys_addr *pasync_sge;
  1556. unsigned int ring_id, num_entries;
  1557. unsigned int host_write_num;
  1558. unsigned int writables;
  1559. unsigned int i = 0;
  1560. u32 doorbell = 0;
  1561. phwi_ctrlr = phba->phwi_ctrlr;
  1562. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1563. num_entries = pasync_ctx->num_entries;
  1564. if (is_header) {
  1565. writables = min(pasync_ctx->async_header.writables,
  1566. pasync_ctx->async_header.free_entries);
  1567. pfree_link = pasync_ctx->async_header.free_list.next;
  1568. host_write_num = pasync_ctx->async_header.host_write_ptr;
  1569. ring_id = phwi_ctrlr->default_pdu_hdr.id;
  1570. } else {
  1571. writables = min(pasync_ctx->async_data.writables,
  1572. pasync_ctx->async_data.free_entries);
  1573. pfree_link = pasync_ctx->async_data.free_list.next;
  1574. host_write_num = pasync_ctx->async_data.host_write_ptr;
  1575. ring_id = phwi_ctrlr->default_pdu_data.id;
  1576. }
  1577. writables = (writables / 8) * 8;
  1578. if (writables) {
  1579. for (i = 0; i < writables; i++) {
  1580. pbusy_list =
  1581. hwi_get_async_busy_list(pasync_ctx, is_header,
  1582. host_write_num);
  1583. pasync_handle =
  1584. list_entry(pfree_link, struct async_pdu_handle,
  1585. link);
  1586. WARN_ON(!pasync_handle);
  1587. pasync_handle->consumed = 0;
  1588. pfree_link = pfree_link->next;
  1589. pasync_sge = hwi_get_ring_address(pasync_ctx,
  1590. is_header, host_write_num);
  1591. pasync_sge->hi = pasync_handle->pa.u.a32.address_lo;
  1592. pasync_sge->lo = pasync_handle->pa.u.a32.address_hi;
  1593. list_move(&pasync_handle->link, pbusy_list);
  1594. host_write_num++;
  1595. host_write_num = host_write_num % num_entries;
  1596. }
  1597. if (is_header) {
  1598. pasync_ctx->async_header.host_write_ptr =
  1599. host_write_num;
  1600. pasync_ctx->async_header.free_entries -= writables;
  1601. pasync_ctx->async_header.writables -= writables;
  1602. pasync_ctx->async_header.busy_entries += writables;
  1603. } else {
  1604. pasync_ctx->async_data.host_write_ptr = host_write_num;
  1605. pasync_ctx->async_data.free_entries -= writables;
  1606. pasync_ctx->async_data.writables -= writables;
  1607. pasync_ctx->async_data.busy_entries += writables;
  1608. }
  1609. doorbell |= ring_id & DB_DEF_PDU_RING_ID_MASK;
  1610. doorbell |= 1 << DB_DEF_PDU_REARM_SHIFT;
  1611. doorbell |= 0 << DB_DEF_PDU_EVENT_SHIFT;
  1612. doorbell |= (writables & DB_DEF_PDU_CQPROC_MASK)
  1613. << DB_DEF_PDU_CQPROC_SHIFT;
  1614. iowrite32(doorbell, phba->db_va + DB_RXULP0_OFFSET);
  1615. }
  1616. }
  1617. static void hwi_flush_default_pdu_buffer(struct beiscsi_hba *phba,
  1618. struct beiscsi_conn *beiscsi_conn,
  1619. struct i_t_dpdu_cqe *pdpdu_cqe)
  1620. {
  1621. struct hwi_controller *phwi_ctrlr;
  1622. struct hwi_async_pdu_context *pasync_ctx;
  1623. struct async_pdu_handle *pasync_handle = NULL;
  1624. unsigned int cq_index = -1;
  1625. phwi_ctrlr = phba->phwi_ctrlr;
  1626. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1627. pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx,
  1628. pdpdu_cqe, &cq_index);
  1629. BUG_ON(pasync_handle->is_header != 0);
  1630. if (pasync_handle->consumed == 0)
  1631. hwi_update_async_writables(phba, pasync_ctx,
  1632. pasync_handle->is_header, cq_index);
  1633. hwi_free_async_msg(phba, pasync_handle->cri);
  1634. hwi_post_async_buffers(phba, pasync_handle->is_header);
  1635. }
  1636. static unsigned int
  1637. hwi_fwd_async_msg(struct beiscsi_conn *beiscsi_conn,
  1638. struct beiscsi_hba *phba,
  1639. struct hwi_async_pdu_context *pasync_ctx, unsigned short cri)
  1640. {
  1641. struct list_head *plist;
  1642. struct async_pdu_handle *pasync_handle;
  1643. void *phdr = NULL;
  1644. unsigned int hdr_len = 0, buf_len = 0;
  1645. unsigned int status, index = 0, offset = 0;
  1646. void *pfirst_buffer = NULL;
  1647. unsigned int num_buf = 0;
  1648. plist = &pasync_ctx->async_entry[cri].wait_queue.list;
  1649. list_for_each_entry(pasync_handle, plist, link) {
  1650. if (index == 0) {
  1651. phdr = pasync_handle->pbuffer;
  1652. hdr_len = pasync_handle->buffer_len;
  1653. } else {
  1654. buf_len = pasync_handle->buffer_len;
  1655. if (!num_buf) {
  1656. pfirst_buffer = pasync_handle->pbuffer;
  1657. num_buf++;
  1658. }
  1659. memcpy(pfirst_buffer + offset,
  1660. pasync_handle->pbuffer, buf_len);
  1661. offset += buf_len;
  1662. }
  1663. index++;
  1664. }
  1665. status = beiscsi_process_async_pdu(beiscsi_conn, phba,
  1666. (beiscsi_conn->beiscsi_conn_cid -
  1667. phba->fw_config.iscsi_cid_start),
  1668. phdr, hdr_len, pfirst_buffer,
  1669. offset);
  1670. hwi_free_async_msg(phba, cri);
  1671. return 0;
  1672. }
  1673. static unsigned int
  1674. hwi_gather_async_pdu(struct beiscsi_conn *beiscsi_conn,
  1675. struct beiscsi_hba *phba,
  1676. struct async_pdu_handle *pasync_handle)
  1677. {
  1678. struct hwi_async_pdu_context *pasync_ctx;
  1679. struct hwi_controller *phwi_ctrlr;
  1680. unsigned int bytes_needed = 0, status = 0;
  1681. unsigned short cri = pasync_handle->cri;
  1682. struct pdu_base *ppdu;
  1683. phwi_ctrlr = phba->phwi_ctrlr;
  1684. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1685. list_del(&pasync_handle->link);
  1686. if (pasync_handle->is_header) {
  1687. pasync_ctx->async_header.busy_entries--;
  1688. if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) {
  1689. hwi_free_async_msg(phba, cri);
  1690. BUG();
  1691. }
  1692. pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0;
  1693. pasync_ctx->async_entry[cri].wait_queue.hdr_received = 1;
  1694. pasync_ctx->async_entry[cri].wait_queue.hdr_len =
  1695. (unsigned short)pasync_handle->buffer_len;
  1696. list_add_tail(&pasync_handle->link,
  1697. &pasync_ctx->async_entry[cri].wait_queue.list);
  1698. ppdu = pasync_handle->pbuffer;
  1699. bytes_needed = ((((ppdu->dw[offsetof(struct amap_pdu_base,
  1700. data_len_hi) / 32] & PDUBASE_DATALENHI_MASK) << 8) &
  1701. 0xFFFF0000) | ((be16_to_cpu((ppdu->
  1702. dw[offsetof(struct amap_pdu_base, data_len_lo) / 32]
  1703. & PDUBASE_DATALENLO_MASK) >> 16)) & 0x0000FFFF));
  1704. if (status == 0) {
  1705. pasync_ctx->async_entry[cri].wait_queue.bytes_needed =
  1706. bytes_needed;
  1707. if (bytes_needed == 0)
  1708. status = hwi_fwd_async_msg(beiscsi_conn, phba,
  1709. pasync_ctx, cri);
  1710. }
  1711. } else {
  1712. pasync_ctx->async_data.busy_entries--;
  1713. if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) {
  1714. list_add_tail(&pasync_handle->link,
  1715. &pasync_ctx->async_entry[cri].wait_queue.
  1716. list);
  1717. pasync_ctx->async_entry[cri].wait_queue.
  1718. bytes_received +=
  1719. (unsigned short)pasync_handle->buffer_len;
  1720. if (pasync_ctx->async_entry[cri].wait_queue.
  1721. bytes_received >=
  1722. pasync_ctx->async_entry[cri].wait_queue.
  1723. bytes_needed)
  1724. status = hwi_fwd_async_msg(beiscsi_conn, phba,
  1725. pasync_ctx, cri);
  1726. }
  1727. }
  1728. return status;
  1729. }
  1730. static void hwi_process_default_pdu_ring(struct beiscsi_conn *beiscsi_conn,
  1731. struct beiscsi_hba *phba,
  1732. struct i_t_dpdu_cqe *pdpdu_cqe)
  1733. {
  1734. struct hwi_controller *phwi_ctrlr;
  1735. struct hwi_async_pdu_context *pasync_ctx;
  1736. struct async_pdu_handle *pasync_handle = NULL;
  1737. unsigned int cq_index = -1;
  1738. phwi_ctrlr = phba->phwi_ctrlr;
  1739. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1740. pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx,
  1741. pdpdu_cqe, &cq_index);
  1742. if (pasync_handle->consumed == 0)
  1743. hwi_update_async_writables(phba, pasync_ctx,
  1744. pasync_handle->is_header, cq_index);
  1745. hwi_gather_async_pdu(beiscsi_conn, phba, pasync_handle);
  1746. hwi_post_async_buffers(phba, pasync_handle->is_header);
  1747. }
  1748. static void beiscsi_process_mcc_isr(struct beiscsi_hba *phba)
  1749. {
  1750. struct be_queue_info *mcc_cq;
  1751. struct be_mcc_compl *mcc_compl;
  1752. unsigned int num_processed = 0;
  1753. mcc_cq = &phba->ctrl.mcc_obj.cq;
  1754. mcc_compl = queue_tail_node(mcc_cq);
  1755. mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
  1756. while (mcc_compl->flags & CQE_FLAGS_VALID_MASK) {
  1757. if (num_processed >= 32) {
  1758. hwi_ring_cq_db(phba, mcc_cq->id,
  1759. num_processed, 0, 0);
  1760. num_processed = 0;
  1761. }
  1762. if (mcc_compl->flags & CQE_FLAGS_ASYNC_MASK) {
  1763. /* Interpret flags as an async trailer */
  1764. if (is_link_state_evt(mcc_compl->flags))
  1765. /* Interpret compl as a async link evt */
  1766. beiscsi_async_link_state_process(phba,
  1767. (struct be_async_event_link_state *) mcc_compl);
  1768. else
  1769. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_MBOX,
  1770. "BM_%d : Unsupported Async Event, flags"
  1771. " = 0x%08x\n",
  1772. mcc_compl->flags);
  1773. } else if (mcc_compl->flags & CQE_FLAGS_COMPLETED_MASK) {
  1774. be_mcc_compl_process_isr(&phba->ctrl, mcc_compl);
  1775. atomic_dec(&phba->ctrl.mcc_obj.q.used);
  1776. }
  1777. mcc_compl->flags = 0;
  1778. queue_tail_inc(mcc_cq);
  1779. mcc_compl = queue_tail_node(mcc_cq);
  1780. mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
  1781. num_processed++;
  1782. }
  1783. if (num_processed > 0)
  1784. hwi_ring_cq_db(phba, mcc_cq->id, num_processed, 1, 0);
  1785. }
  1786. /**
  1787. * beiscsi_process_cq()- Process the Completion Queue
  1788. * @pbe_eq: Event Q on which the Completion has come
  1789. *
  1790. * return
  1791. * Number of Completion Entries processed.
  1792. **/
  1793. static unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq)
  1794. {
  1795. struct be_queue_info *cq;
  1796. struct sol_cqe *sol;
  1797. struct dmsg_cqe *dmsg;
  1798. unsigned int num_processed = 0;
  1799. unsigned int tot_nump = 0;
  1800. unsigned short code = 0, cid = 0;
  1801. struct beiscsi_conn *beiscsi_conn;
  1802. struct beiscsi_endpoint *beiscsi_ep;
  1803. struct iscsi_endpoint *ep;
  1804. struct beiscsi_hba *phba;
  1805. cq = pbe_eq->cq;
  1806. sol = queue_tail_node(cq);
  1807. phba = pbe_eq->phba;
  1808. while (sol->dw[offsetof(struct amap_sol_cqe, valid) / 32] &
  1809. CQE_VALID_MASK) {
  1810. be_dws_le_to_cpu(sol, sizeof(struct sol_cqe));
  1811. code = (sol->dw[offsetof(struct amap_sol_cqe, code) /
  1812. 32] & CQE_CODE_MASK);
  1813. /* Get the CID */
  1814. if (chip_skh_r(phba->pcidev)) {
  1815. if ((code == DRIVERMSG_NOTIFY) ||
  1816. (code == UNSOL_HDR_NOTIFY) ||
  1817. (code == UNSOL_DATA_NOTIFY))
  1818. cid = AMAP_GET_BITS(
  1819. struct amap_i_t_dpdu_cqe_v2,
  1820. cid, sol);
  1821. else
  1822. cid = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1823. cid, sol);
  1824. } else
  1825. cid = AMAP_GET_BITS(struct amap_sol_cqe, cid, sol);
  1826. ep = phba->ep_array[cid - phba->fw_config.iscsi_cid_start];
  1827. beiscsi_ep = ep->dd_data;
  1828. beiscsi_conn = beiscsi_ep->conn;
  1829. if (num_processed >= 32) {
  1830. hwi_ring_cq_db(phba, cq->id,
  1831. num_processed, 0, 0);
  1832. tot_nump += num_processed;
  1833. num_processed = 0;
  1834. }
  1835. switch (code) {
  1836. case SOL_CMD_COMPLETE:
  1837. hwi_complete_cmd(beiscsi_conn, phba, sol);
  1838. break;
  1839. case DRIVERMSG_NOTIFY:
  1840. beiscsi_log(phba, KERN_INFO,
  1841. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1842. "BM_%d : Received %s[%d] on CID : %d\n",
  1843. cqe_desc[code], code, cid);
  1844. dmsg = (struct dmsg_cqe *)sol;
  1845. hwi_complete_drvr_msgs(beiscsi_conn, phba, sol);
  1846. break;
  1847. case UNSOL_HDR_NOTIFY:
  1848. beiscsi_log(phba, KERN_INFO,
  1849. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1850. "BM_%d : Received %s[%d] on CID : %d\n",
  1851. cqe_desc[code], code, cid);
  1852. hwi_process_default_pdu_ring(beiscsi_conn, phba,
  1853. (struct i_t_dpdu_cqe *)sol);
  1854. break;
  1855. case UNSOL_DATA_NOTIFY:
  1856. beiscsi_log(phba, KERN_INFO,
  1857. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1858. "BM_%d : Received %s[%d] on CID : %d\n",
  1859. cqe_desc[code], code, cid);
  1860. hwi_process_default_pdu_ring(beiscsi_conn, phba,
  1861. (struct i_t_dpdu_cqe *)sol);
  1862. break;
  1863. case CXN_INVALIDATE_INDEX_NOTIFY:
  1864. case CMD_INVALIDATED_NOTIFY:
  1865. case CXN_INVALIDATE_NOTIFY:
  1866. beiscsi_log(phba, KERN_ERR,
  1867. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1868. "BM_%d : Ignoring %s[%d] on CID : %d\n",
  1869. cqe_desc[code], code, cid);
  1870. break;
  1871. case SOL_CMD_KILLED_DATA_DIGEST_ERR:
  1872. case CMD_KILLED_INVALID_STATSN_RCVD:
  1873. case CMD_KILLED_INVALID_R2T_RCVD:
  1874. case CMD_CXN_KILLED_LUN_INVALID:
  1875. case CMD_CXN_KILLED_ICD_INVALID:
  1876. case CMD_CXN_KILLED_ITT_INVALID:
  1877. case CMD_CXN_KILLED_SEQ_OUTOFORDER:
  1878. case CMD_CXN_KILLED_INVALID_DATASN_RCVD:
  1879. beiscsi_log(phba, KERN_ERR,
  1880. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1881. "BM_%d : Cmd Notification %s[%d] on CID : %d\n",
  1882. cqe_desc[code], code, cid);
  1883. break;
  1884. case UNSOL_DATA_DIGEST_ERROR_NOTIFY:
  1885. beiscsi_log(phba, KERN_ERR,
  1886. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1887. "BM_%d : Dropping %s[%d] on DPDU ring on CID : %d\n",
  1888. cqe_desc[code], code, cid);
  1889. hwi_flush_default_pdu_buffer(phba, beiscsi_conn,
  1890. (struct i_t_dpdu_cqe *) sol);
  1891. break;
  1892. case CXN_KILLED_PDU_SIZE_EXCEEDS_DSL:
  1893. case CXN_KILLED_BURST_LEN_MISMATCH:
  1894. case CXN_KILLED_AHS_RCVD:
  1895. case CXN_KILLED_HDR_DIGEST_ERR:
  1896. case CXN_KILLED_UNKNOWN_HDR:
  1897. case CXN_KILLED_STALE_ITT_TTT_RCVD:
  1898. case CXN_KILLED_INVALID_ITT_TTT_RCVD:
  1899. case CXN_KILLED_TIMED_OUT:
  1900. case CXN_KILLED_FIN_RCVD:
  1901. case CXN_KILLED_RST_SENT:
  1902. case CXN_KILLED_RST_RCVD:
  1903. case CXN_KILLED_BAD_UNSOL_PDU_RCVD:
  1904. case CXN_KILLED_BAD_WRB_INDEX_ERROR:
  1905. case CXN_KILLED_OVER_RUN_RESIDUAL:
  1906. case CXN_KILLED_UNDER_RUN_RESIDUAL:
  1907. case CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN:
  1908. beiscsi_log(phba, KERN_ERR,
  1909. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1910. "BM_%d : Event %s[%d] received on CID : %d\n",
  1911. cqe_desc[code], code, cid);
  1912. if (beiscsi_conn)
  1913. iscsi_conn_failure(beiscsi_conn->conn,
  1914. ISCSI_ERR_CONN_FAILED);
  1915. break;
  1916. default:
  1917. beiscsi_log(phba, KERN_ERR,
  1918. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1919. "BM_%d : Invalid CQE Event Received Code : %d"
  1920. "CID 0x%x...\n",
  1921. code, cid);
  1922. break;
  1923. }
  1924. AMAP_SET_BITS(struct amap_sol_cqe, valid, sol, 0);
  1925. queue_tail_inc(cq);
  1926. sol = queue_tail_node(cq);
  1927. num_processed++;
  1928. }
  1929. if (num_processed > 0) {
  1930. tot_nump += num_processed;
  1931. hwi_ring_cq_db(phba, cq->id, num_processed, 1, 0);
  1932. }
  1933. return tot_nump;
  1934. }
  1935. void beiscsi_process_all_cqs(struct work_struct *work)
  1936. {
  1937. unsigned long flags;
  1938. struct hwi_controller *phwi_ctrlr;
  1939. struct hwi_context_memory *phwi_context;
  1940. struct beiscsi_hba *phba;
  1941. struct be_eq_obj *pbe_eq =
  1942. container_of(work, struct be_eq_obj, work_cqs);
  1943. phba = pbe_eq->phba;
  1944. phwi_ctrlr = phba->phwi_ctrlr;
  1945. phwi_context = phwi_ctrlr->phwi_ctxt;
  1946. if (pbe_eq->todo_mcc_cq) {
  1947. spin_lock_irqsave(&phba->isr_lock, flags);
  1948. pbe_eq->todo_mcc_cq = false;
  1949. spin_unlock_irqrestore(&phba->isr_lock, flags);
  1950. beiscsi_process_mcc_isr(phba);
  1951. }
  1952. if (pbe_eq->todo_cq) {
  1953. spin_lock_irqsave(&phba->isr_lock, flags);
  1954. pbe_eq->todo_cq = false;
  1955. spin_unlock_irqrestore(&phba->isr_lock, flags);
  1956. beiscsi_process_cq(pbe_eq);
  1957. }
  1958. /* rearm EQ for further interrupts */
  1959. hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1);
  1960. }
  1961. static int be_iopoll(struct blk_iopoll *iop, int budget)
  1962. {
  1963. static unsigned int ret;
  1964. struct beiscsi_hba *phba;
  1965. struct be_eq_obj *pbe_eq;
  1966. pbe_eq = container_of(iop, struct be_eq_obj, iopoll);
  1967. ret = beiscsi_process_cq(pbe_eq);
  1968. if (ret < budget) {
  1969. phba = pbe_eq->phba;
  1970. blk_iopoll_complete(iop);
  1971. beiscsi_log(phba, KERN_INFO,
  1972. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1973. "BM_%d : rearm pbe_eq->q.id =%d\n",
  1974. pbe_eq->q.id);
  1975. hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1);
  1976. }
  1977. return ret;
  1978. }
  1979. static void
  1980. hwi_write_sgl_v2(struct iscsi_wrb *pwrb, struct scatterlist *sg,
  1981. unsigned int num_sg, struct beiscsi_io_task *io_task)
  1982. {
  1983. struct iscsi_sge *psgl;
  1984. unsigned int sg_len, index;
  1985. unsigned int sge_len = 0;
  1986. unsigned long long addr;
  1987. struct scatterlist *l_sg;
  1988. unsigned int offset;
  1989. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, iscsi_bhs_addr_lo, pwrb,
  1990. io_task->bhs_pa.u.a32.address_lo);
  1991. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, iscsi_bhs_addr_hi, pwrb,
  1992. io_task->bhs_pa.u.a32.address_hi);
  1993. l_sg = sg;
  1994. for (index = 0; (index < num_sg) && (index < 2); index++,
  1995. sg = sg_next(sg)) {
  1996. if (index == 0) {
  1997. sg_len = sg_dma_len(sg);
  1998. addr = (u64) sg_dma_address(sg);
  1999. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  2000. sge0_addr_lo, pwrb,
  2001. lower_32_bits(addr));
  2002. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  2003. sge0_addr_hi, pwrb,
  2004. upper_32_bits(addr));
  2005. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  2006. sge0_len, pwrb,
  2007. sg_len);
  2008. sge_len = sg_len;
  2009. } else {
  2010. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_r2t_offset,
  2011. pwrb, sge_len);
  2012. sg_len = sg_dma_len(sg);
  2013. addr = (u64) sg_dma_address(sg);
  2014. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  2015. sge1_addr_lo, pwrb,
  2016. lower_32_bits(addr));
  2017. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  2018. sge1_addr_hi, pwrb,
  2019. upper_32_bits(addr));
  2020. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  2021. sge1_len, pwrb,
  2022. sg_len);
  2023. }
  2024. }
  2025. psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
  2026. memset(psgl, 0, sizeof(*psgl) * BE2_SGE);
  2027. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2);
  2028. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2029. io_task->bhs_pa.u.a32.address_hi);
  2030. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2031. io_task->bhs_pa.u.a32.address_lo);
  2032. if (num_sg == 1) {
  2033. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb,
  2034. 1);
  2035. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb,
  2036. 0);
  2037. } else if (num_sg == 2) {
  2038. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb,
  2039. 0);
  2040. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb,
  2041. 1);
  2042. } else {
  2043. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb,
  2044. 0);
  2045. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb,
  2046. 0);
  2047. }
  2048. sg = l_sg;
  2049. psgl++;
  2050. psgl++;
  2051. offset = 0;
  2052. for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) {
  2053. sg_len = sg_dma_len(sg);
  2054. addr = (u64) sg_dma_address(sg);
  2055. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2056. lower_32_bits(addr));
  2057. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2058. upper_32_bits(addr));
  2059. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len);
  2060. AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset);
  2061. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
  2062. offset += sg_len;
  2063. }
  2064. psgl--;
  2065. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
  2066. }
  2067. static void
  2068. hwi_write_sgl(struct iscsi_wrb *pwrb, struct scatterlist *sg,
  2069. unsigned int num_sg, struct beiscsi_io_task *io_task)
  2070. {
  2071. struct iscsi_sge *psgl;
  2072. unsigned int sg_len, index;
  2073. unsigned int sge_len = 0;
  2074. unsigned long long addr;
  2075. struct scatterlist *l_sg;
  2076. unsigned int offset;
  2077. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
  2078. io_task->bhs_pa.u.a32.address_lo);
  2079. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
  2080. io_task->bhs_pa.u.a32.address_hi);
  2081. l_sg = sg;
  2082. for (index = 0; (index < num_sg) && (index < 2); index++,
  2083. sg = sg_next(sg)) {
  2084. if (index == 0) {
  2085. sg_len = sg_dma_len(sg);
  2086. addr = (u64) sg_dma_address(sg);
  2087. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
  2088. ((u32)(addr & 0xFFFFFFFF)));
  2089. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
  2090. ((u32)(addr >> 32)));
  2091. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
  2092. sg_len);
  2093. sge_len = sg_len;
  2094. } else {
  2095. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_r2t_offset,
  2096. pwrb, sge_len);
  2097. sg_len = sg_dma_len(sg);
  2098. addr = (u64) sg_dma_address(sg);
  2099. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_lo, pwrb,
  2100. ((u32)(addr & 0xFFFFFFFF)));
  2101. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_hi, pwrb,
  2102. ((u32)(addr >> 32)));
  2103. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_len, pwrb,
  2104. sg_len);
  2105. }
  2106. }
  2107. psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
  2108. memset(psgl, 0, sizeof(*psgl) * BE2_SGE);
  2109. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2);
  2110. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2111. io_task->bhs_pa.u.a32.address_hi);
  2112. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2113. io_task->bhs_pa.u.a32.address_lo);
  2114. if (num_sg == 1) {
  2115. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  2116. 1);
  2117. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  2118. 0);
  2119. } else if (num_sg == 2) {
  2120. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  2121. 0);
  2122. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  2123. 1);
  2124. } else {
  2125. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  2126. 0);
  2127. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  2128. 0);
  2129. }
  2130. sg = l_sg;
  2131. psgl++;
  2132. psgl++;
  2133. offset = 0;
  2134. for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) {
  2135. sg_len = sg_dma_len(sg);
  2136. addr = (u64) sg_dma_address(sg);
  2137. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2138. (addr & 0xFFFFFFFF));
  2139. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2140. (addr >> 32));
  2141. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len);
  2142. AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset);
  2143. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
  2144. offset += sg_len;
  2145. }
  2146. psgl--;
  2147. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
  2148. }
  2149. /**
  2150. * hwi_write_buffer()- Populate the WRB with task info
  2151. * @pwrb: ptr to the WRB entry
  2152. * @task: iscsi task which is to be executed
  2153. **/
  2154. static void hwi_write_buffer(struct iscsi_wrb *pwrb, struct iscsi_task *task)
  2155. {
  2156. struct iscsi_sge *psgl;
  2157. struct beiscsi_io_task *io_task = task->dd_data;
  2158. struct beiscsi_conn *beiscsi_conn = io_task->conn;
  2159. struct beiscsi_hba *phba = beiscsi_conn->phba;
  2160. uint8_t dsp_value = 0;
  2161. io_task->bhs_len = sizeof(struct be_nonio_bhs) - 2;
  2162. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
  2163. io_task->bhs_pa.u.a32.address_lo);
  2164. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
  2165. io_task->bhs_pa.u.a32.address_hi);
  2166. if (task->data) {
  2167. /* Check for the data_count */
  2168. dsp_value = (task->data_count) ? 1 : 0;
  2169. if (chip_skh_r(phba->pcidev))
  2170. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp,
  2171. pwrb, dsp_value);
  2172. else
  2173. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp,
  2174. pwrb, dsp_value);
  2175. /* Map addr only if there is data_count */
  2176. if (dsp_value) {
  2177. io_task->mtask_addr = pci_map_single(phba->pcidev,
  2178. task->data,
  2179. task->data_count,
  2180. PCI_DMA_TODEVICE);
  2181. io_task->mtask_data_count = task->data_count;
  2182. } else
  2183. io_task->mtask_addr = 0;
  2184. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
  2185. lower_32_bits(io_task->mtask_addr));
  2186. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
  2187. upper_32_bits(io_task->mtask_addr));
  2188. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
  2189. task->data_count);
  2190. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, 1);
  2191. } else {
  2192. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
  2193. io_task->mtask_addr = 0;
  2194. }
  2195. psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
  2196. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len);
  2197. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2198. io_task->bhs_pa.u.a32.address_hi);
  2199. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2200. io_task->bhs_pa.u.a32.address_lo);
  2201. if (task->data) {
  2202. psgl++;
  2203. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 0);
  2204. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 0);
  2205. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0);
  2206. AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, 0);
  2207. AMAP_SET_BITS(struct amap_iscsi_sge, rsvd0, psgl, 0);
  2208. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
  2209. psgl++;
  2210. if (task->data) {
  2211. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2212. lower_32_bits(io_task->mtask_addr));
  2213. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2214. upper_32_bits(io_task->mtask_addr));
  2215. }
  2216. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0x106);
  2217. }
  2218. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
  2219. }
  2220. static void beiscsi_find_mem_req(struct beiscsi_hba *phba)
  2221. {
  2222. unsigned int num_cq_pages, num_async_pdu_buf_pages;
  2223. unsigned int num_async_pdu_data_pages, wrb_sz_per_cxn;
  2224. unsigned int num_async_pdu_buf_sgl_pages, num_async_pdu_data_sgl_pages;
  2225. num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
  2226. sizeof(struct sol_cqe));
  2227. num_async_pdu_buf_pages =
  2228. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  2229. phba->params.defpdu_hdr_sz);
  2230. num_async_pdu_buf_sgl_pages =
  2231. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  2232. sizeof(struct phys_addr));
  2233. num_async_pdu_data_pages =
  2234. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  2235. phba->params.defpdu_data_sz);
  2236. num_async_pdu_data_sgl_pages =
  2237. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  2238. sizeof(struct phys_addr));
  2239. phba->params.hwi_ws_sz = sizeof(struct hwi_controller);
  2240. phba->mem_req[ISCSI_MEM_GLOBAL_HEADER] = 2 *
  2241. BE_ISCSI_PDU_HEADER_SIZE;
  2242. phba->mem_req[HWI_MEM_ADDN_CONTEXT] =
  2243. sizeof(struct hwi_context_memory);
  2244. phba->mem_req[HWI_MEM_WRB] = sizeof(struct iscsi_wrb)
  2245. * (phba->params.wrbs_per_cxn)
  2246. * phba->params.cxns_per_ctrl;
  2247. wrb_sz_per_cxn = sizeof(struct wrb_handle) *
  2248. (phba->params.wrbs_per_cxn);
  2249. phba->mem_req[HWI_MEM_WRBH] = roundup_pow_of_two((wrb_sz_per_cxn) *
  2250. phba->params.cxns_per_ctrl);
  2251. phba->mem_req[HWI_MEM_SGLH] = sizeof(struct sgl_handle) *
  2252. phba->params.icds_per_ctrl;
  2253. phba->mem_req[HWI_MEM_SGE] = sizeof(struct iscsi_sge) *
  2254. phba->params.num_sge_per_io * phba->params.icds_per_ctrl;
  2255. phba->mem_req[HWI_MEM_ASYNC_HEADER_BUF] =
  2256. num_async_pdu_buf_pages * PAGE_SIZE;
  2257. phba->mem_req[HWI_MEM_ASYNC_DATA_BUF] =
  2258. num_async_pdu_data_pages * PAGE_SIZE;
  2259. phba->mem_req[HWI_MEM_ASYNC_HEADER_RING] =
  2260. num_async_pdu_buf_sgl_pages * PAGE_SIZE;
  2261. phba->mem_req[HWI_MEM_ASYNC_DATA_RING] =
  2262. num_async_pdu_data_sgl_pages * PAGE_SIZE;
  2263. phba->mem_req[HWI_MEM_ASYNC_HEADER_HANDLE] =
  2264. phba->params.asyncpdus_per_ctrl *
  2265. sizeof(struct async_pdu_handle);
  2266. phba->mem_req[HWI_MEM_ASYNC_DATA_HANDLE] =
  2267. phba->params.asyncpdus_per_ctrl *
  2268. sizeof(struct async_pdu_handle);
  2269. phba->mem_req[HWI_MEM_ASYNC_PDU_CONTEXT] =
  2270. sizeof(struct hwi_async_pdu_context) +
  2271. (phba->params.cxns_per_ctrl * sizeof(struct hwi_async_entry));
  2272. }
  2273. static int beiscsi_alloc_mem(struct beiscsi_hba *phba)
  2274. {
  2275. struct be_mem_descriptor *mem_descr;
  2276. dma_addr_t bus_add;
  2277. struct mem_array *mem_arr, *mem_arr_orig;
  2278. unsigned int i, j, alloc_size, curr_alloc_size;
  2279. phba->phwi_ctrlr = kzalloc(phba->params.hwi_ws_sz, GFP_KERNEL);
  2280. if (!phba->phwi_ctrlr)
  2281. return -ENOMEM;
  2282. phba->init_mem = kcalloc(SE_MEM_MAX, sizeof(*mem_descr),
  2283. GFP_KERNEL);
  2284. if (!phba->init_mem) {
  2285. kfree(phba->phwi_ctrlr);
  2286. return -ENOMEM;
  2287. }
  2288. mem_arr_orig = kmalloc(sizeof(*mem_arr_orig) * BEISCSI_MAX_FRAGS_INIT,
  2289. GFP_KERNEL);
  2290. if (!mem_arr_orig) {
  2291. kfree(phba->init_mem);
  2292. kfree(phba->phwi_ctrlr);
  2293. return -ENOMEM;
  2294. }
  2295. mem_descr = phba->init_mem;
  2296. for (i = 0; i < SE_MEM_MAX; i++) {
  2297. j = 0;
  2298. mem_arr = mem_arr_orig;
  2299. alloc_size = phba->mem_req[i];
  2300. memset(mem_arr, 0, sizeof(struct mem_array) *
  2301. BEISCSI_MAX_FRAGS_INIT);
  2302. curr_alloc_size = min(be_max_phys_size * 1024, alloc_size);
  2303. do {
  2304. mem_arr->virtual_address = pci_alloc_consistent(
  2305. phba->pcidev,
  2306. curr_alloc_size,
  2307. &bus_add);
  2308. if (!mem_arr->virtual_address) {
  2309. if (curr_alloc_size <= BE_MIN_MEM_SIZE)
  2310. goto free_mem;
  2311. if (curr_alloc_size -
  2312. rounddown_pow_of_two(curr_alloc_size))
  2313. curr_alloc_size = rounddown_pow_of_two
  2314. (curr_alloc_size);
  2315. else
  2316. curr_alloc_size = curr_alloc_size / 2;
  2317. } else {
  2318. mem_arr->bus_address.u.
  2319. a64.address = (__u64) bus_add;
  2320. mem_arr->size = curr_alloc_size;
  2321. alloc_size -= curr_alloc_size;
  2322. curr_alloc_size = min(be_max_phys_size *
  2323. 1024, alloc_size);
  2324. j++;
  2325. mem_arr++;
  2326. }
  2327. } while (alloc_size);
  2328. mem_descr->num_elements = j;
  2329. mem_descr->size_in_bytes = phba->mem_req[i];
  2330. mem_descr->mem_array = kmalloc(sizeof(*mem_arr) * j,
  2331. GFP_KERNEL);
  2332. if (!mem_descr->mem_array)
  2333. goto free_mem;
  2334. memcpy(mem_descr->mem_array, mem_arr_orig,
  2335. sizeof(struct mem_array) * j);
  2336. mem_descr++;
  2337. }
  2338. kfree(mem_arr_orig);
  2339. return 0;
  2340. free_mem:
  2341. mem_descr->num_elements = j;
  2342. while ((i) || (j)) {
  2343. for (j = mem_descr->num_elements; j > 0; j--) {
  2344. pci_free_consistent(phba->pcidev,
  2345. mem_descr->mem_array[j - 1].size,
  2346. mem_descr->mem_array[j - 1].
  2347. virtual_address,
  2348. (unsigned long)mem_descr->
  2349. mem_array[j - 1].
  2350. bus_address.u.a64.address);
  2351. }
  2352. if (i) {
  2353. i--;
  2354. kfree(mem_descr->mem_array);
  2355. mem_descr--;
  2356. }
  2357. }
  2358. kfree(mem_arr_orig);
  2359. kfree(phba->init_mem);
  2360. kfree(phba->phwi_ctrlr);
  2361. return -ENOMEM;
  2362. }
  2363. static int beiscsi_get_memory(struct beiscsi_hba *phba)
  2364. {
  2365. beiscsi_find_mem_req(phba);
  2366. return beiscsi_alloc_mem(phba);
  2367. }
  2368. static void iscsi_init_global_templates(struct beiscsi_hba *phba)
  2369. {
  2370. struct pdu_data_out *pdata_out;
  2371. struct pdu_nop_out *pnop_out;
  2372. struct be_mem_descriptor *mem_descr;
  2373. mem_descr = phba->init_mem;
  2374. mem_descr += ISCSI_MEM_GLOBAL_HEADER;
  2375. pdata_out =
  2376. (struct pdu_data_out *)mem_descr->mem_array[0].virtual_address;
  2377. memset(pdata_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
  2378. AMAP_SET_BITS(struct amap_pdu_data_out, opcode, pdata_out,
  2379. IIOC_SCSI_DATA);
  2380. pnop_out =
  2381. (struct pdu_nop_out *)((unsigned char *)mem_descr->mem_array[0].
  2382. virtual_address + BE_ISCSI_PDU_HEADER_SIZE);
  2383. memset(pnop_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
  2384. AMAP_SET_BITS(struct amap_pdu_nop_out, ttt, pnop_out, 0xFFFFFFFF);
  2385. AMAP_SET_BITS(struct amap_pdu_nop_out, f_bit, pnop_out, 1);
  2386. AMAP_SET_BITS(struct amap_pdu_nop_out, i_bit, pnop_out, 0);
  2387. }
  2388. static int beiscsi_init_wrb_handle(struct beiscsi_hba *phba)
  2389. {
  2390. struct be_mem_descriptor *mem_descr_wrbh, *mem_descr_wrb;
  2391. struct wrb_handle *pwrb_handle = NULL;
  2392. struct hwi_controller *phwi_ctrlr;
  2393. struct hwi_wrb_context *pwrb_context;
  2394. struct iscsi_wrb *pwrb = NULL;
  2395. unsigned int num_cxn_wrbh = 0;
  2396. unsigned int num_cxn_wrb = 0, j, idx = 0, index;
  2397. mem_descr_wrbh = phba->init_mem;
  2398. mem_descr_wrbh += HWI_MEM_WRBH;
  2399. mem_descr_wrb = phba->init_mem;
  2400. mem_descr_wrb += HWI_MEM_WRB;
  2401. phwi_ctrlr = phba->phwi_ctrlr;
  2402. for (index = 0; index < phba->params.cxns_per_ctrl * 2; index += 2) {
  2403. pwrb_context = &phwi_ctrlr->wrb_context[index];
  2404. pwrb_context->pwrb_handle_base =
  2405. kzalloc(sizeof(struct wrb_handle *) *
  2406. phba->params.wrbs_per_cxn, GFP_KERNEL);
  2407. if (!pwrb_context->pwrb_handle_base) {
  2408. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2409. "BM_%d : Mem Alloc Failed. Failing to load\n");
  2410. goto init_wrb_hndl_failed;
  2411. }
  2412. pwrb_context->pwrb_handle_basestd =
  2413. kzalloc(sizeof(struct wrb_handle *) *
  2414. phba->params.wrbs_per_cxn, GFP_KERNEL);
  2415. if (!pwrb_context->pwrb_handle_basestd) {
  2416. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2417. "BM_%d : Mem Alloc Failed. Failing to load\n");
  2418. goto init_wrb_hndl_failed;
  2419. }
  2420. if (!num_cxn_wrbh) {
  2421. pwrb_handle =
  2422. mem_descr_wrbh->mem_array[idx].virtual_address;
  2423. num_cxn_wrbh = ((mem_descr_wrbh->mem_array[idx].size) /
  2424. ((sizeof(struct wrb_handle)) *
  2425. phba->params.wrbs_per_cxn));
  2426. idx++;
  2427. }
  2428. pwrb_context->alloc_index = 0;
  2429. pwrb_context->wrb_handles_available = 0;
  2430. pwrb_context->free_index = 0;
  2431. if (num_cxn_wrbh) {
  2432. for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
  2433. pwrb_context->pwrb_handle_base[j] = pwrb_handle;
  2434. pwrb_context->pwrb_handle_basestd[j] =
  2435. pwrb_handle;
  2436. pwrb_context->wrb_handles_available++;
  2437. pwrb_handle->wrb_index = j;
  2438. pwrb_handle++;
  2439. }
  2440. num_cxn_wrbh--;
  2441. }
  2442. }
  2443. idx = 0;
  2444. for (index = 0; index < phba->params.cxns_per_ctrl * 2; index += 2) {
  2445. pwrb_context = &phwi_ctrlr->wrb_context[index];
  2446. if (!num_cxn_wrb) {
  2447. pwrb = mem_descr_wrb->mem_array[idx].virtual_address;
  2448. num_cxn_wrb = (mem_descr_wrb->mem_array[idx].size) /
  2449. ((sizeof(struct iscsi_wrb) *
  2450. phba->params.wrbs_per_cxn));
  2451. idx++;
  2452. }
  2453. if (num_cxn_wrb) {
  2454. for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
  2455. pwrb_handle = pwrb_context->pwrb_handle_base[j];
  2456. pwrb_handle->pwrb = pwrb;
  2457. pwrb++;
  2458. }
  2459. num_cxn_wrb--;
  2460. }
  2461. }
  2462. return 0;
  2463. init_wrb_hndl_failed:
  2464. for (j = index; j > 0; j--) {
  2465. pwrb_context = &phwi_ctrlr->wrb_context[j];
  2466. kfree(pwrb_context->pwrb_handle_base);
  2467. kfree(pwrb_context->pwrb_handle_basestd);
  2468. }
  2469. return -ENOMEM;
  2470. }
  2471. static void hwi_init_async_pdu_ctx(struct beiscsi_hba *phba)
  2472. {
  2473. struct hwi_controller *phwi_ctrlr;
  2474. struct hba_parameters *p = &phba->params;
  2475. struct hwi_async_pdu_context *pasync_ctx;
  2476. struct async_pdu_handle *pasync_header_h, *pasync_data_h;
  2477. unsigned int index, idx, num_per_mem, num_async_data;
  2478. struct be_mem_descriptor *mem_descr;
  2479. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2480. mem_descr += HWI_MEM_ASYNC_PDU_CONTEXT;
  2481. phwi_ctrlr = phba->phwi_ctrlr;
  2482. phwi_ctrlr->phwi_ctxt->pasync_ctx = (struct hwi_async_pdu_context *)
  2483. mem_descr->mem_array[0].virtual_address;
  2484. pasync_ctx = phwi_ctrlr->phwi_ctxt->pasync_ctx;
  2485. memset(pasync_ctx, 0, sizeof(*pasync_ctx));
  2486. pasync_ctx->num_entries = p->asyncpdus_per_ctrl;
  2487. pasync_ctx->buffer_size = p->defpdu_hdr_sz;
  2488. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2489. mem_descr += HWI_MEM_ASYNC_HEADER_BUF;
  2490. if (mem_descr->mem_array[0].virtual_address) {
  2491. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2492. "BM_%d : hwi_init_async_pdu_ctx"
  2493. " HWI_MEM_ASYNC_HEADER_BUF va=%p\n",
  2494. mem_descr->mem_array[0].virtual_address);
  2495. } else
  2496. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2497. "BM_%d : No Virtual address\n");
  2498. pasync_ctx->async_header.va_base =
  2499. mem_descr->mem_array[0].virtual_address;
  2500. pasync_ctx->async_header.pa_base.u.a64.address =
  2501. mem_descr->mem_array[0].bus_address.u.a64.address;
  2502. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2503. mem_descr += HWI_MEM_ASYNC_HEADER_RING;
  2504. if (mem_descr->mem_array[0].virtual_address) {
  2505. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2506. "BM_%d : hwi_init_async_pdu_ctx"
  2507. " HWI_MEM_ASYNC_HEADER_RING va=%p\n",
  2508. mem_descr->mem_array[0].virtual_address);
  2509. } else
  2510. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2511. "BM_%d : No Virtual address\n");
  2512. pasync_ctx->async_header.ring_base =
  2513. mem_descr->mem_array[0].virtual_address;
  2514. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2515. mem_descr += HWI_MEM_ASYNC_HEADER_HANDLE;
  2516. if (mem_descr->mem_array[0].virtual_address) {
  2517. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2518. "BM_%d : hwi_init_async_pdu_ctx"
  2519. " HWI_MEM_ASYNC_HEADER_HANDLE va=%p\n",
  2520. mem_descr->mem_array[0].virtual_address);
  2521. } else
  2522. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2523. "BM_%d : No Virtual address\n");
  2524. pasync_ctx->async_header.handle_base =
  2525. mem_descr->mem_array[0].virtual_address;
  2526. pasync_ctx->async_header.writables = 0;
  2527. INIT_LIST_HEAD(&pasync_ctx->async_header.free_list);
  2528. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2529. mem_descr += HWI_MEM_ASYNC_DATA_RING;
  2530. if (mem_descr->mem_array[0].virtual_address) {
  2531. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2532. "BM_%d : hwi_init_async_pdu_ctx"
  2533. " HWI_MEM_ASYNC_DATA_RING va=%p\n",
  2534. mem_descr->mem_array[0].virtual_address);
  2535. } else
  2536. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2537. "BM_%d : No Virtual address\n");
  2538. pasync_ctx->async_data.ring_base =
  2539. mem_descr->mem_array[0].virtual_address;
  2540. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2541. mem_descr += HWI_MEM_ASYNC_DATA_HANDLE;
  2542. if (!mem_descr->mem_array[0].virtual_address)
  2543. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2544. "BM_%d : No Virtual address\n");
  2545. pasync_ctx->async_data.handle_base =
  2546. mem_descr->mem_array[0].virtual_address;
  2547. pasync_ctx->async_data.writables = 0;
  2548. INIT_LIST_HEAD(&pasync_ctx->async_data.free_list);
  2549. pasync_header_h =
  2550. (struct async_pdu_handle *)pasync_ctx->async_header.handle_base;
  2551. pasync_data_h =
  2552. (struct async_pdu_handle *)pasync_ctx->async_data.handle_base;
  2553. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2554. mem_descr += HWI_MEM_ASYNC_DATA_BUF;
  2555. if (mem_descr->mem_array[0].virtual_address) {
  2556. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2557. "BM_%d : hwi_init_async_pdu_ctx"
  2558. " HWI_MEM_ASYNC_DATA_BUF va=%p\n",
  2559. mem_descr->mem_array[0].virtual_address);
  2560. } else
  2561. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2562. "BM_%d : No Virtual address\n");
  2563. idx = 0;
  2564. pasync_ctx->async_data.va_base =
  2565. mem_descr->mem_array[idx].virtual_address;
  2566. pasync_ctx->async_data.pa_base.u.a64.address =
  2567. mem_descr->mem_array[idx].bus_address.u.a64.address;
  2568. num_async_data = ((mem_descr->mem_array[idx].size) /
  2569. phba->params.defpdu_data_sz);
  2570. num_per_mem = 0;
  2571. for (index = 0; index < p->asyncpdus_per_ctrl; index++) {
  2572. pasync_header_h->cri = -1;
  2573. pasync_header_h->index = (char)index;
  2574. INIT_LIST_HEAD(&pasync_header_h->link);
  2575. pasync_header_h->pbuffer =
  2576. (void *)((unsigned long)
  2577. (pasync_ctx->async_header.va_base) +
  2578. (p->defpdu_hdr_sz * index));
  2579. pasync_header_h->pa.u.a64.address =
  2580. pasync_ctx->async_header.pa_base.u.a64.address +
  2581. (p->defpdu_hdr_sz * index);
  2582. list_add_tail(&pasync_header_h->link,
  2583. &pasync_ctx->async_header.free_list);
  2584. pasync_header_h++;
  2585. pasync_ctx->async_header.free_entries++;
  2586. pasync_ctx->async_header.writables++;
  2587. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].wait_queue.list);
  2588. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].
  2589. header_busy_list);
  2590. pasync_data_h->cri = -1;
  2591. pasync_data_h->index = (char)index;
  2592. INIT_LIST_HEAD(&pasync_data_h->link);
  2593. if (!num_async_data) {
  2594. num_per_mem = 0;
  2595. idx++;
  2596. pasync_ctx->async_data.va_base =
  2597. mem_descr->mem_array[idx].virtual_address;
  2598. pasync_ctx->async_data.pa_base.u.a64.address =
  2599. mem_descr->mem_array[idx].
  2600. bus_address.u.a64.address;
  2601. num_async_data = ((mem_descr->mem_array[idx].size) /
  2602. phba->params.defpdu_data_sz);
  2603. }
  2604. pasync_data_h->pbuffer =
  2605. (void *)((unsigned long)
  2606. (pasync_ctx->async_data.va_base) +
  2607. (p->defpdu_data_sz * num_per_mem));
  2608. pasync_data_h->pa.u.a64.address =
  2609. pasync_ctx->async_data.pa_base.u.a64.address +
  2610. (p->defpdu_data_sz * num_per_mem);
  2611. num_per_mem++;
  2612. num_async_data--;
  2613. list_add_tail(&pasync_data_h->link,
  2614. &pasync_ctx->async_data.free_list);
  2615. pasync_data_h++;
  2616. pasync_ctx->async_data.free_entries++;
  2617. pasync_ctx->async_data.writables++;
  2618. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].data_busy_list);
  2619. }
  2620. pasync_ctx->async_header.host_write_ptr = 0;
  2621. pasync_ctx->async_header.ep_read_ptr = -1;
  2622. pasync_ctx->async_data.host_write_ptr = 0;
  2623. pasync_ctx->async_data.ep_read_ptr = -1;
  2624. }
  2625. static int
  2626. be_sgl_create_contiguous(void *virtual_address,
  2627. u64 physical_address, u32 length,
  2628. struct be_dma_mem *sgl)
  2629. {
  2630. WARN_ON(!virtual_address);
  2631. WARN_ON(!physical_address);
  2632. WARN_ON(!length > 0);
  2633. WARN_ON(!sgl);
  2634. sgl->va = virtual_address;
  2635. sgl->dma = (unsigned long)physical_address;
  2636. sgl->size = length;
  2637. return 0;
  2638. }
  2639. static void be_sgl_destroy_contiguous(struct be_dma_mem *sgl)
  2640. {
  2641. memset(sgl, 0, sizeof(*sgl));
  2642. }
  2643. static void
  2644. hwi_build_be_sgl_arr(struct beiscsi_hba *phba,
  2645. struct mem_array *pmem, struct be_dma_mem *sgl)
  2646. {
  2647. if (sgl->va)
  2648. be_sgl_destroy_contiguous(sgl);
  2649. be_sgl_create_contiguous(pmem->virtual_address,
  2650. pmem->bus_address.u.a64.address,
  2651. pmem->size, sgl);
  2652. }
  2653. static void
  2654. hwi_build_be_sgl_by_offset(struct beiscsi_hba *phba,
  2655. struct mem_array *pmem, struct be_dma_mem *sgl)
  2656. {
  2657. if (sgl->va)
  2658. be_sgl_destroy_contiguous(sgl);
  2659. be_sgl_create_contiguous((unsigned char *)pmem->virtual_address,
  2660. pmem->bus_address.u.a64.address,
  2661. pmem->size, sgl);
  2662. }
  2663. static int be_fill_queue(struct be_queue_info *q,
  2664. u16 len, u16 entry_size, void *vaddress)
  2665. {
  2666. struct be_dma_mem *mem = &q->dma_mem;
  2667. memset(q, 0, sizeof(*q));
  2668. q->len = len;
  2669. q->entry_size = entry_size;
  2670. mem->size = len * entry_size;
  2671. mem->va = vaddress;
  2672. if (!mem->va)
  2673. return -ENOMEM;
  2674. memset(mem->va, 0, mem->size);
  2675. return 0;
  2676. }
  2677. static int beiscsi_create_eqs(struct beiscsi_hba *phba,
  2678. struct hwi_context_memory *phwi_context)
  2679. {
  2680. unsigned int i, num_eq_pages;
  2681. int ret = 0, eq_for_mcc;
  2682. struct be_queue_info *eq;
  2683. struct be_dma_mem *mem;
  2684. void *eq_vaddress;
  2685. dma_addr_t paddr;
  2686. num_eq_pages = PAGES_REQUIRED(phba->params.num_eq_entries * \
  2687. sizeof(struct be_eq_entry));
  2688. if (phba->msix_enabled)
  2689. eq_for_mcc = 1;
  2690. else
  2691. eq_for_mcc = 0;
  2692. for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) {
  2693. eq = &phwi_context->be_eq[i].q;
  2694. mem = &eq->dma_mem;
  2695. phwi_context->be_eq[i].phba = phba;
  2696. eq_vaddress = pci_alloc_consistent(phba->pcidev,
  2697. num_eq_pages * PAGE_SIZE,
  2698. &paddr);
  2699. if (!eq_vaddress)
  2700. goto create_eq_error;
  2701. mem->va = eq_vaddress;
  2702. ret = be_fill_queue(eq, phba->params.num_eq_entries,
  2703. sizeof(struct be_eq_entry), eq_vaddress);
  2704. if (ret) {
  2705. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2706. "BM_%d : be_fill_queue Failed for EQ\n");
  2707. goto create_eq_error;
  2708. }
  2709. mem->dma = paddr;
  2710. ret = beiscsi_cmd_eq_create(&phba->ctrl, eq,
  2711. phwi_context->cur_eqd);
  2712. if (ret) {
  2713. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2714. "BM_%d : beiscsi_cmd_eq_create"
  2715. "Failed for EQ\n");
  2716. goto create_eq_error;
  2717. }
  2718. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2719. "BM_%d : eqid = %d\n",
  2720. phwi_context->be_eq[i].q.id);
  2721. }
  2722. return 0;
  2723. create_eq_error:
  2724. for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) {
  2725. eq = &phwi_context->be_eq[i].q;
  2726. mem = &eq->dma_mem;
  2727. if (mem->va)
  2728. pci_free_consistent(phba->pcidev, num_eq_pages
  2729. * PAGE_SIZE,
  2730. mem->va, mem->dma);
  2731. }
  2732. return ret;
  2733. }
  2734. static int beiscsi_create_cqs(struct beiscsi_hba *phba,
  2735. struct hwi_context_memory *phwi_context)
  2736. {
  2737. unsigned int i, num_cq_pages;
  2738. int ret = 0;
  2739. struct be_queue_info *cq, *eq;
  2740. struct be_dma_mem *mem;
  2741. struct be_eq_obj *pbe_eq;
  2742. void *cq_vaddress;
  2743. dma_addr_t paddr;
  2744. num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
  2745. sizeof(struct sol_cqe));
  2746. for (i = 0; i < phba->num_cpus; i++) {
  2747. cq = &phwi_context->be_cq[i];
  2748. eq = &phwi_context->be_eq[i].q;
  2749. pbe_eq = &phwi_context->be_eq[i];
  2750. pbe_eq->cq = cq;
  2751. pbe_eq->phba = phba;
  2752. mem = &cq->dma_mem;
  2753. cq_vaddress = pci_alloc_consistent(phba->pcidev,
  2754. num_cq_pages * PAGE_SIZE,
  2755. &paddr);
  2756. if (!cq_vaddress)
  2757. goto create_cq_error;
  2758. ret = be_fill_queue(cq, phba->params.num_cq_entries,
  2759. sizeof(struct sol_cqe), cq_vaddress);
  2760. if (ret) {
  2761. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2762. "BM_%d : be_fill_queue Failed "
  2763. "for ISCSI CQ\n");
  2764. goto create_cq_error;
  2765. }
  2766. mem->dma = paddr;
  2767. ret = beiscsi_cmd_cq_create(&phba->ctrl, cq, eq, false,
  2768. false, 0);
  2769. if (ret) {
  2770. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2771. "BM_%d : beiscsi_cmd_eq_create"
  2772. "Failed for ISCSI CQ\n");
  2773. goto create_cq_error;
  2774. }
  2775. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2776. "BM_%d : iscsi cq_id is %d for eq_id %d\n"
  2777. "iSCSI CQ CREATED\n", cq->id, eq->id);
  2778. }
  2779. return 0;
  2780. create_cq_error:
  2781. for (i = 0; i < phba->num_cpus; i++) {
  2782. cq = &phwi_context->be_cq[i];
  2783. mem = &cq->dma_mem;
  2784. if (mem->va)
  2785. pci_free_consistent(phba->pcidev, num_cq_pages
  2786. * PAGE_SIZE,
  2787. mem->va, mem->dma);
  2788. }
  2789. return ret;
  2790. }
  2791. static int
  2792. beiscsi_create_def_hdr(struct beiscsi_hba *phba,
  2793. struct hwi_context_memory *phwi_context,
  2794. struct hwi_controller *phwi_ctrlr,
  2795. unsigned int def_pdu_ring_sz)
  2796. {
  2797. unsigned int idx;
  2798. int ret;
  2799. struct be_queue_info *dq, *cq;
  2800. struct be_dma_mem *mem;
  2801. struct be_mem_descriptor *mem_descr;
  2802. void *dq_vaddress;
  2803. idx = 0;
  2804. dq = &phwi_context->be_def_hdrq;
  2805. cq = &phwi_context->be_cq[0];
  2806. mem = &dq->dma_mem;
  2807. mem_descr = phba->init_mem;
  2808. mem_descr += HWI_MEM_ASYNC_HEADER_RING;
  2809. dq_vaddress = mem_descr->mem_array[idx].virtual_address;
  2810. ret = be_fill_queue(dq, mem_descr->mem_array[0].size /
  2811. sizeof(struct phys_addr),
  2812. sizeof(struct phys_addr), dq_vaddress);
  2813. if (ret) {
  2814. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2815. "BM_%d : be_fill_queue Failed for DEF PDU HDR\n");
  2816. return ret;
  2817. }
  2818. mem->dma = (unsigned long)mem_descr->mem_array[idx].
  2819. bus_address.u.a64.address;
  2820. ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dq,
  2821. def_pdu_ring_sz,
  2822. phba->params.defpdu_hdr_sz);
  2823. if (ret) {
  2824. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2825. "BM_%d : be_cmd_create_default_pdu_queue Failed DEFHDR\n");
  2826. return ret;
  2827. }
  2828. phwi_ctrlr->default_pdu_hdr.id = phwi_context->be_def_hdrq.id;
  2829. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2830. "BM_%d : iscsi def pdu id is %d\n",
  2831. phwi_context->be_def_hdrq.id);
  2832. hwi_post_async_buffers(phba, 1);
  2833. return 0;
  2834. }
  2835. static int
  2836. beiscsi_create_def_data(struct beiscsi_hba *phba,
  2837. struct hwi_context_memory *phwi_context,
  2838. struct hwi_controller *phwi_ctrlr,
  2839. unsigned int def_pdu_ring_sz)
  2840. {
  2841. unsigned int idx;
  2842. int ret;
  2843. struct be_queue_info *dataq, *cq;
  2844. struct be_dma_mem *mem;
  2845. struct be_mem_descriptor *mem_descr;
  2846. void *dq_vaddress;
  2847. idx = 0;
  2848. dataq = &phwi_context->be_def_dataq;
  2849. cq = &phwi_context->be_cq[0];
  2850. mem = &dataq->dma_mem;
  2851. mem_descr = phba->init_mem;
  2852. mem_descr += HWI_MEM_ASYNC_DATA_RING;
  2853. dq_vaddress = mem_descr->mem_array[idx].virtual_address;
  2854. ret = be_fill_queue(dataq, mem_descr->mem_array[0].size /
  2855. sizeof(struct phys_addr),
  2856. sizeof(struct phys_addr), dq_vaddress);
  2857. if (ret) {
  2858. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2859. "BM_%d : be_fill_queue Failed for DEF PDU DATA\n");
  2860. return ret;
  2861. }
  2862. mem->dma = (unsigned long)mem_descr->mem_array[idx].
  2863. bus_address.u.a64.address;
  2864. ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dataq,
  2865. def_pdu_ring_sz,
  2866. phba->params.defpdu_data_sz);
  2867. if (ret) {
  2868. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2869. "BM_%d be_cmd_create_default_pdu_queue"
  2870. " Failed for DEF PDU DATA\n");
  2871. return ret;
  2872. }
  2873. phwi_ctrlr->default_pdu_data.id = phwi_context->be_def_dataq.id;
  2874. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2875. "BM_%d : iscsi def data id is %d\n",
  2876. phwi_context->be_def_dataq.id);
  2877. hwi_post_async_buffers(phba, 0);
  2878. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2879. "BM_%d : DEFAULT PDU DATA RING CREATED\n");
  2880. return 0;
  2881. }
  2882. static int
  2883. beiscsi_post_pages(struct beiscsi_hba *phba)
  2884. {
  2885. struct be_mem_descriptor *mem_descr;
  2886. struct mem_array *pm_arr;
  2887. unsigned int page_offset, i;
  2888. struct be_dma_mem sgl;
  2889. int status;
  2890. mem_descr = phba->init_mem;
  2891. mem_descr += HWI_MEM_SGE;
  2892. pm_arr = mem_descr->mem_array;
  2893. page_offset = (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io *
  2894. phba->fw_config.iscsi_icd_start) / PAGE_SIZE;
  2895. for (i = 0; i < mem_descr->num_elements; i++) {
  2896. hwi_build_be_sgl_arr(phba, pm_arr, &sgl);
  2897. status = be_cmd_iscsi_post_sgl_pages(&phba->ctrl, &sgl,
  2898. page_offset,
  2899. (pm_arr->size / PAGE_SIZE));
  2900. page_offset += pm_arr->size / PAGE_SIZE;
  2901. if (status != 0) {
  2902. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2903. "BM_%d : post sgl failed.\n");
  2904. return status;
  2905. }
  2906. pm_arr++;
  2907. }
  2908. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2909. "BM_%d : POSTED PAGES\n");
  2910. return 0;
  2911. }
  2912. static void be_queue_free(struct beiscsi_hba *phba, struct be_queue_info *q)
  2913. {
  2914. struct be_dma_mem *mem = &q->dma_mem;
  2915. if (mem->va) {
  2916. pci_free_consistent(phba->pcidev, mem->size,
  2917. mem->va, mem->dma);
  2918. mem->va = NULL;
  2919. }
  2920. }
  2921. static int be_queue_alloc(struct beiscsi_hba *phba, struct be_queue_info *q,
  2922. u16 len, u16 entry_size)
  2923. {
  2924. struct be_dma_mem *mem = &q->dma_mem;
  2925. memset(q, 0, sizeof(*q));
  2926. q->len = len;
  2927. q->entry_size = entry_size;
  2928. mem->size = len * entry_size;
  2929. mem->va = pci_alloc_consistent(phba->pcidev, mem->size, &mem->dma);
  2930. if (!mem->va)
  2931. return -ENOMEM;
  2932. memset(mem->va, 0, mem->size);
  2933. return 0;
  2934. }
  2935. static int
  2936. beiscsi_create_wrb_rings(struct beiscsi_hba *phba,
  2937. struct hwi_context_memory *phwi_context,
  2938. struct hwi_controller *phwi_ctrlr)
  2939. {
  2940. unsigned int wrb_mem_index, offset, size, num_wrb_rings;
  2941. u64 pa_addr_lo;
  2942. unsigned int idx, num, i;
  2943. struct mem_array *pwrb_arr;
  2944. void *wrb_vaddr;
  2945. struct be_dma_mem sgl;
  2946. struct be_mem_descriptor *mem_descr;
  2947. int status;
  2948. idx = 0;
  2949. mem_descr = phba->init_mem;
  2950. mem_descr += HWI_MEM_WRB;
  2951. pwrb_arr = kmalloc(sizeof(*pwrb_arr) * phba->params.cxns_per_ctrl,
  2952. GFP_KERNEL);
  2953. if (!pwrb_arr) {
  2954. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2955. "BM_%d : Memory alloc failed in create wrb ring.\n");
  2956. return -ENOMEM;
  2957. }
  2958. wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
  2959. pa_addr_lo = mem_descr->mem_array[idx].bus_address.u.a64.address;
  2960. num_wrb_rings = mem_descr->mem_array[idx].size /
  2961. (phba->params.wrbs_per_cxn * sizeof(struct iscsi_wrb));
  2962. for (num = 0; num < phba->params.cxns_per_ctrl; num++) {
  2963. if (num_wrb_rings) {
  2964. pwrb_arr[num].virtual_address = wrb_vaddr;
  2965. pwrb_arr[num].bus_address.u.a64.address = pa_addr_lo;
  2966. pwrb_arr[num].size = phba->params.wrbs_per_cxn *
  2967. sizeof(struct iscsi_wrb);
  2968. wrb_vaddr += pwrb_arr[num].size;
  2969. pa_addr_lo += pwrb_arr[num].size;
  2970. num_wrb_rings--;
  2971. } else {
  2972. idx++;
  2973. wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
  2974. pa_addr_lo = mem_descr->mem_array[idx].\
  2975. bus_address.u.a64.address;
  2976. num_wrb_rings = mem_descr->mem_array[idx].size /
  2977. (phba->params.wrbs_per_cxn *
  2978. sizeof(struct iscsi_wrb));
  2979. pwrb_arr[num].virtual_address = wrb_vaddr;
  2980. pwrb_arr[num].bus_address.u.a64.address\
  2981. = pa_addr_lo;
  2982. pwrb_arr[num].size = phba->params.wrbs_per_cxn *
  2983. sizeof(struct iscsi_wrb);
  2984. wrb_vaddr += pwrb_arr[num].size;
  2985. pa_addr_lo += pwrb_arr[num].size;
  2986. num_wrb_rings--;
  2987. }
  2988. }
  2989. for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
  2990. wrb_mem_index = 0;
  2991. offset = 0;
  2992. size = 0;
  2993. hwi_build_be_sgl_by_offset(phba, &pwrb_arr[i], &sgl);
  2994. status = be_cmd_wrbq_create(&phba->ctrl, &sgl,
  2995. &phwi_context->be_wrbq[i]);
  2996. if (status != 0) {
  2997. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2998. "BM_%d : wrbq create failed.");
  2999. kfree(pwrb_arr);
  3000. return status;
  3001. }
  3002. phwi_ctrlr->wrb_context[i * 2].cid = phwi_context->be_wrbq[i].
  3003. id;
  3004. }
  3005. kfree(pwrb_arr);
  3006. return 0;
  3007. }
  3008. static void free_wrb_handles(struct beiscsi_hba *phba)
  3009. {
  3010. unsigned int index;
  3011. struct hwi_controller *phwi_ctrlr;
  3012. struct hwi_wrb_context *pwrb_context;
  3013. phwi_ctrlr = phba->phwi_ctrlr;
  3014. for (index = 0; index < phba->params.cxns_per_ctrl * 2; index += 2) {
  3015. pwrb_context = &phwi_ctrlr->wrb_context[index];
  3016. kfree(pwrb_context->pwrb_handle_base);
  3017. kfree(pwrb_context->pwrb_handle_basestd);
  3018. }
  3019. }
  3020. static void be_mcc_queues_destroy(struct beiscsi_hba *phba)
  3021. {
  3022. struct be_queue_info *q;
  3023. struct be_ctrl_info *ctrl = &phba->ctrl;
  3024. q = &phba->ctrl.mcc_obj.q;
  3025. if (q->created)
  3026. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_MCCQ);
  3027. be_queue_free(phba, q);
  3028. q = &phba->ctrl.mcc_obj.cq;
  3029. if (q->created)
  3030. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
  3031. be_queue_free(phba, q);
  3032. }
  3033. static void hwi_cleanup(struct beiscsi_hba *phba)
  3034. {
  3035. struct be_queue_info *q;
  3036. struct be_ctrl_info *ctrl = &phba->ctrl;
  3037. struct hwi_controller *phwi_ctrlr;
  3038. struct hwi_context_memory *phwi_context;
  3039. int i, eq_num;
  3040. phwi_ctrlr = phba->phwi_ctrlr;
  3041. phwi_context = phwi_ctrlr->phwi_ctxt;
  3042. for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
  3043. q = &phwi_context->be_wrbq[i];
  3044. if (q->created)
  3045. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_WRBQ);
  3046. }
  3047. free_wrb_handles(phba);
  3048. q = &phwi_context->be_def_hdrq;
  3049. if (q->created)
  3050. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
  3051. q = &phwi_context->be_def_dataq;
  3052. if (q->created)
  3053. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
  3054. beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL);
  3055. for (i = 0; i < (phba->num_cpus); i++) {
  3056. q = &phwi_context->be_cq[i];
  3057. if (q->created)
  3058. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
  3059. }
  3060. if (phba->msix_enabled)
  3061. eq_num = 1;
  3062. else
  3063. eq_num = 0;
  3064. for (i = 0; i < (phba->num_cpus + eq_num); i++) {
  3065. q = &phwi_context->be_eq[i].q;
  3066. if (q->created)
  3067. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_EQ);
  3068. }
  3069. be_mcc_queues_destroy(phba);
  3070. }
  3071. static int be_mcc_queues_create(struct beiscsi_hba *phba,
  3072. struct hwi_context_memory *phwi_context)
  3073. {
  3074. struct be_queue_info *q, *cq;
  3075. struct be_ctrl_info *ctrl = &phba->ctrl;
  3076. /* Alloc MCC compl queue */
  3077. cq = &phba->ctrl.mcc_obj.cq;
  3078. if (be_queue_alloc(phba, cq, MCC_CQ_LEN,
  3079. sizeof(struct be_mcc_compl)))
  3080. goto err;
  3081. /* Ask BE to create MCC compl queue; */
  3082. if (phba->msix_enabled) {
  3083. if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq
  3084. [phba->num_cpus].q, false, true, 0))
  3085. goto mcc_cq_free;
  3086. } else {
  3087. if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq[0].q,
  3088. false, true, 0))
  3089. goto mcc_cq_free;
  3090. }
  3091. /* Alloc MCC queue */
  3092. q = &phba->ctrl.mcc_obj.q;
  3093. if (be_queue_alloc(phba, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
  3094. goto mcc_cq_destroy;
  3095. /* Ask BE to create MCC queue */
  3096. if (beiscsi_cmd_mccq_create(phba, q, cq))
  3097. goto mcc_q_free;
  3098. return 0;
  3099. mcc_q_free:
  3100. be_queue_free(phba, q);
  3101. mcc_cq_destroy:
  3102. beiscsi_cmd_q_destroy(ctrl, cq, QTYPE_CQ);
  3103. mcc_cq_free:
  3104. be_queue_free(phba, cq);
  3105. err:
  3106. return -ENOMEM;
  3107. }
  3108. /**
  3109. * find_num_cpus()- Get the CPU online count
  3110. * @phba: ptr to priv structure
  3111. *
  3112. * CPU count is used for creating EQ.
  3113. **/
  3114. static void find_num_cpus(struct beiscsi_hba *phba)
  3115. {
  3116. int num_cpus = 0;
  3117. num_cpus = num_online_cpus();
  3118. switch (phba->generation) {
  3119. case BE_GEN2:
  3120. case BE_GEN3:
  3121. phba->num_cpus = (num_cpus > BEISCSI_MAX_NUM_CPUS) ?
  3122. BEISCSI_MAX_NUM_CPUS : num_cpus;
  3123. break;
  3124. case BE_GEN4:
  3125. phba->num_cpus = (num_cpus > OC_SKH_MAX_NUM_CPUS) ?
  3126. OC_SKH_MAX_NUM_CPUS : num_cpus;
  3127. break;
  3128. default:
  3129. phba->num_cpus = 1;
  3130. }
  3131. }
  3132. static int hwi_init_port(struct beiscsi_hba *phba)
  3133. {
  3134. struct hwi_controller *phwi_ctrlr;
  3135. struct hwi_context_memory *phwi_context;
  3136. unsigned int def_pdu_ring_sz;
  3137. struct be_ctrl_info *ctrl = &phba->ctrl;
  3138. int status;
  3139. def_pdu_ring_sz =
  3140. phba->params.asyncpdus_per_ctrl * sizeof(struct phys_addr);
  3141. phwi_ctrlr = phba->phwi_ctrlr;
  3142. phwi_context = phwi_ctrlr->phwi_ctxt;
  3143. phwi_context->max_eqd = 0;
  3144. phwi_context->min_eqd = 0;
  3145. phwi_context->cur_eqd = 64;
  3146. be_cmd_fw_initialize(&phba->ctrl);
  3147. status = beiscsi_create_eqs(phba, phwi_context);
  3148. if (status != 0) {
  3149. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3150. "BM_%d : EQ not created\n");
  3151. goto error;
  3152. }
  3153. status = be_mcc_queues_create(phba, phwi_context);
  3154. if (status != 0)
  3155. goto error;
  3156. status = mgmt_check_supported_fw(ctrl, phba);
  3157. if (status != 0) {
  3158. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3159. "BM_%d : Unsupported fw version\n");
  3160. goto error;
  3161. }
  3162. status = beiscsi_create_cqs(phba, phwi_context);
  3163. if (status != 0) {
  3164. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3165. "BM_%d : CQ not created\n");
  3166. goto error;
  3167. }
  3168. status = beiscsi_create_def_hdr(phba, phwi_context, phwi_ctrlr,
  3169. def_pdu_ring_sz);
  3170. if (status != 0) {
  3171. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3172. "BM_%d : Default Header not created\n");
  3173. goto error;
  3174. }
  3175. status = beiscsi_create_def_data(phba, phwi_context,
  3176. phwi_ctrlr, def_pdu_ring_sz);
  3177. if (status != 0) {
  3178. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3179. "BM_%d : Default Data not created\n");
  3180. goto error;
  3181. }
  3182. status = beiscsi_post_pages(phba);
  3183. if (status != 0) {
  3184. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3185. "BM_%d : Post SGL Pages Failed\n");
  3186. goto error;
  3187. }
  3188. status = beiscsi_create_wrb_rings(phba, phwi_context, phwi_ctrlr);
  3189. if (status != 0) {
  3190. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3191. "BM_%d : WRB Rings not created\n");
  3192. goto error;
  3193. }
  3194. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3195. "BM_%d : hwi_init_port success\n");
  3196. return 0;
  3197. error:
  3198. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3199. "BM_%d : hwi_init_port failed");
  3200. hwi_cleanup(phba);
  3201. return status;
  3202. }
  3203. static int hwi_init_controller(struct beiscsi_hba *phba)
  3204. {
  3205. struct hwi_controller *phwi_ctrlr;
  3206. phwi_ctrlr = phba->phwi_ctrlr;
  3207. if (1 == phba->init_mem[HWI_MEM_ADDN_CONTEXT].num_elements) {
  3208. phwi_ctrlr->phwi_ctxt = (struct hwi_context_memory *)phba->
  3209. init_mem[HWI_MEM_ADDN_CONTEXT].mem_array[0].virtual_address;
  3210. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3211. "BM_%d : phwi_ctrlr->phwi_ctxt=%p\n",
  3212. phwi_ctrlr->phwi_ctxt);
  3213. } else {
  3214. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3215. "BM_%d : HWI_MEM_ADDN_CONTEXT is more "
  3216. "than one element.Failing to load\n");
  3217. return -ENOMEM;
  3218. }
  3219. iscsi_init_global_templates(phba);
  3220. if (beiscsi_init_wrb_handle(phba))
  3221. return -ENOMEM;
  3222. hwi_init_async_pdu_ctx(phba);
  3223. if (hwi_init_port(phba) != 0) {
  3224. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3225. "BM_%d : hwi_init_controller failed\n");
  3226. return -ENOMEM;
  3227. }
  3228. return 0;
  3229. }
  3230. static void beiscsi_free_mem(struct beiscsi_hba *phba)
  3231. {
  3232. struct be_mem_descriptor *mem_descr;
  3233. int i, j;
  3234. mem_descr = phba->init_mem;
  3235. i = 0;
  3236. j = 0;
  3237. for (i = 0; i < SE_MEM_MAX; i++) {
  3238. for (j = mem_descr->num_elements; j > 0; j--) {
  3239. pci_free_consistent(phba->pcidev,
  3240. mem_descr->mem_array[j - 1].size,
  3241. mem_descr->mem_array[j - 1].virtual_address,
  3242. (unsigned long)mem_descr->mem_array[j - 1].
  3243. bus_address.u.a64.address);
  3244. }
  3245. kfree(mem_descr->mem_array);
  3246. mem_descr++;
  3247. }
  3248. kfree(phba->init_mem);
  3249. kfree(phba->phwi_ctrlr);
  3250. }
  3251. static int beiscsi_init_controller(struct beiscsi_hba *phba)
  3252. {
  3253. int ret = -ENOMEM;
  3254. ret = beiscsi_get_memory(phba);
  3255. if (ret < 0) {
  3256. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3257. "BM_%d : beiscsi_dev_probe -"
  3258. "Failed in beiscsi_alloc_memory\n");
  3259. return ret;
  3260. }
  3261. ret = hwi_init_controller(phba);
  3262. if (ret)
  3263. goto free_init;
  3264. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3265. "BM_%d : Return success from beiscsi_init_controller");
  3266. return 0;
  3267. free_init:
  3268. beiscsi_free_mem(phba);
  3269. return ret;
  3270. }
  3271. static int beiscsi_init_sgl_handle(struct beiscsi_hba *phba)
  3272. {
  3273. struct be_mem_descriptor *mem_descr_sglh, *mem_descr_sg;
  3274. struct sgl_handle *psgl_handle;
  3275. struct iscsi_sge *pfrag;
  3276. unsigned int arr_index, i, idx;
  3277. phba->io_sgl_hndl_avbl = 0;
  3278. phba->eh_sgl_hndl_avbl = 0;
  3279. mem_descr_sglh = phba->init_mem;
  3280. mem_descr_sglh += HWI_MEM_SGLH;
  3281. if (1 == mem_descr_sglh->num_elements) {
  3282. phba->io_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
  3283. phba->params.ios_per_ctrl,
  3284. GFP_KERNEL);
  3285. if (!phba->io_sgl_hndl_base) {
  3286. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3287. "BM_%d : Mem Alloc Failed. Failing to load\n");
  3288. return -ENOMEM;
  3289. }
  3290. phba->eh_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
  3291. (phba->params.icds_per_ctrl -
  3292. phba->params.ios_per_ctrl),
  3293. GFP_KERNEL);
  3294. if (!phba->eh_sgl_hndl_base) {
  3295. kfree(phba->io_sgl_hndl_base);
  3296. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3297. "BM_%d : Mem Alloc Failed. Failing to load\n");
  3298. return -ENOMEM;
  3299. }
  3300. } else {
  3301. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3302. "BM_%d : HWI_MEM_SGLH is more than one element."
  3303. "Failing to load\n");
  3304. return -ENOMEM;
  3305. }
  3306. arr_index = 0;
  3307. idx = 0;
  3308. while (idx < mem_descr_sglh->num_elements) {
  3309. psgl_handle = mem_descr_sglh->mem_array[idx].virtual_address;
  3310. for (i = 0; i < (mem_descr_sglh->mem_array[idx].size /
  3311. sizeof(struct sgl_handle)); i++) {
  3312. if (arr_index < phba->params.ios_per_ctrl) {
  3313. phba->io_sgl_hndl_base[arr_index] = psgl_handle;
  3314. phba->io_sgl_hndl_avbl++;
  3315. arr_index++;
  3316. } else {
  3317. phba->eh_sgl_hndl_base[arr_index -
  3318. phba->params.ios_per_ctrl] =
  3319. psgl_handle;
  3320. arr_index++;
  3321. phba->eh_sgl_hndl_avbl++;
  3322. }
  3323. psgl_handle++;
  3324. }
  3325. idx++;
  3326. }
  3327. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3328. "BM_%d : phba->io_sgl_hndl_avbl=%d"
  3329. "phba->eh_sgl_hndl_avbl=%d\n",
  3330. phba->io_sgl_hndl_avbl,
  3331. phba->eh_sgl_hndl_avbl);
  3332. mem_descr_sg = phba->init_mem;
  3333. mem_descr_sg += HWI_MEM_SGE;
  3334. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3335. "\n BM_%d : mem_descr_sg->num_elements=%d\n",
  3336. mem_descr_sg->num_elements);
  3337. arr_index = 0;
  3338. idx = 0;
  3339. while (idx < mem_descr_sg->num_elements) {
  3340. pfrag = mem_descr_sg->mem_array[idx].virtual_address;
  3341. for (i = 0;
  3342. i < (mem_descr_sg->mem_array[idx].size) /
  3343. (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io);
  3344. i++) {
  3345. if (arr_index < phba->params.ios_per_ctrl)
  3346. psgl_handle = phba->io_sgl_hndl_base[arr_index];
  3347. else
  3348. psgl_handle = phba->eh_sgl_hndl_base[arr_index -
  3349. phba->params.ios_per_ctrl];
  3350. psgl_handle->pfrag = pfrag;
  3351. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, pfrag, 0);
  3352. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, pfrag, 0);
  3353. pfrag += phba->params.num_sge_per_io;
  3354. psgl_handle->sgl_index =
  3355. phba->fw_config.iscsi_icd_start + arr_index++;
  3356. }
  3357. idx++;
  3358. }
  3359. phba->io_sgl_free_index = 0;
  3360. phba->io_sgl_alloc_index = 0;
  3361. phba->eh_sgl_free_index = 0;
  3362. phba->eh_sgl_alloc_index = 0;
  3363. return 0;
  3364. }
  3365. static int hba_setup_cid_tbls(struct beiscsi_hba *phba)
  3366. {
  3367. int i, new_cid;
  3368. phba->cid_array = kzalloc(sizeof(void *) * phba->params.cxns_per_ctrl,
  3369. GFP_KERNEL);
  3370. if (!phba->cid_array) {
  3371. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3372. "BM_%d : Failed to allocate memory in "
  3373. "hba_setup_cid_tbls\n");
  3374. return -ENOMEM;
  3375. }
  3376. phba->ep_array = kzalloc(sizeof(struct iscsi_endpoint *) *
  3377. phba->params.cxns_per_ctrl * 2, GFP_KERNEL);
  3378. if (!phba->ep_array) {
  3379. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3380. "BM_%d : Failed to allocate memory in "
  3381. "hba_setup_cid_tbls\n");
  3382. kfree(phba->cid_array);
  3383. return -ENOMEM;
  3384. }
  3385. new_cid = phba->fw_config.iscsi_cid_start;
  3386. for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
  3387. phba->cid_array[i] = new_cid;
  3388. new_cid += 2;
  3389. }
  3390. phba->avlbl_cids = phba->params.cxns_per_ctrl;
  3391. return 0;
  3392. }
  3393. static void hwi_enable_intr(struct beiscsi_hba *phba)
  3394. {
  3395. struct be_ctrl_info *ctrl = &phba->ctrl;
  3396. struct hwi_controller *phwi_ctrlr;
  3397. struct hwi_context_memory *phwi_context;
  3398. struct be_queue_info *eq;
  3399. u8 __iomem *addr;
  3400. u32 reg, i;
  3401. u32 enabled;
  3402. phwi_ctrlr = phba->phwi_ctrlr;
  3403. phwi_context = phwi_ctrlr->phwi_ctxt;
  3404. addr = (u8 __iomem *) ((u8 __iomem *) ctrl->pcicfg +
  3405. PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET);
  3406. reg = ioread32(addr);
  3407. enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3408. if (!enabled) {
  3409. reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3410. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3411. "BM_%d : reg =x%08x addr=%p\n", reg, addr);
  3412. iowrite32(reg, addr);
  3413. }
  3414. if (!phba->msix_enabled) {
  3415. eq = &phwi_context->be_eq[0].q;
  3416. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3417. "BM_%d : eq->id=%d\n", eq->id);
  3418. hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
  3419. } else {
  3420. for (i = 0; i <= phba->num_cpus; i++) {
  3421. eq = &phwi_context->be_eq[i].q;
  3422. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3423. "BM_%d : eq->id=%d\n", eq->id);
  3424. hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
  3425. }
  3426. }
  3427. }
  3428. static void hwi_disable_intr(struct beiscsi_hba *phba)
  3429. {
  3430. struct be_ctrl_info *ctrl = &phba->ctrl;
  3431. u8 __iomem *addr = ctrl->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
  3432. u32 reg = ioread32(addr);
  3433. u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3434. if (enabled) {
  3435. reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3436. iowrite32(reg, addr);
  3437. } else
  3438. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  3439. "BM_%d : In hwi_disable_intr, Already Disabled\n");
  3440. }
  3441. /**
  3442. * beiscsi_get_boot_info()- Get the boot session info
  3443. * @phba: The device priv structure instance
  3444. *
  3445. * Get the boot target info and store in driver priv structure
  3446. *
  3447. * return values
  3448. * Success: 0
  3449. * Failure: Non-Zero Value
  3450. **/
  3451. static int beiscsi_get_boot_info(struct beiscsi_hba *phba)
  3452. {
  3453. struct be_cmd_get_session_resp *session_resp;
  3454. struct be_mcc_wrb *wrb;
  3455. struct be_dma_mem nonemb_cmd;
  3456. unsigned int tag, wrb_num;
  3457. unsigned short status, extd_status;
  3458. unsigned int s_handle;
  3459. struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
  3460. int ret = -ENOMEM;
  3461. /* Get the session handle of the boot target */
  3462. ret = be_mgmt_get_boot_shandle(phba, &s_handle);
  3463. if (ret) {
  3464. beiscsi_log(phba, KERN_ERR,
  3465. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3466. "BM_%d : No boot session\n");
  3467. return ret;
  3468. }
  3469. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  3470. sizeof(*session_resp),
  3471. &nonemb_cmd.dma);
  3472. if (nonemb_cmd.va == NULL) {
  3473. beiscsi_log(phba, KERN_ERR,
  3474. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3475. "BM_%d : Failed to allocate memory for"
  3476. "beiscsi_get_session_info\n");
  3477. return -ENOMEM;
  3478. }
  3479. memset(nonemb_cmd.va, 0, sizeof(*session_resp));
  3480. tag = mgmt_get_session_info(phba, s_handle,
  3481. &nonemb_cmd);
  3482. if (!tag) {
  3483. beiscsi_log(phba, KERN_ERR,
  3484. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3485. "BM_%d : beiscsi_get_session_info"
  3486. " Failed\n");
  3487. goto boot_freemem;
  3488. } else
  3489. wait_event_interruptible(phba->ctrl.mcc_wait[tag],
  3490. phba->ctrl.mcc_numtag[tag]);
  3491. wrb_num = (phba->ctrl.mcc_numtag[tag] & 0x00FF0000) >> 16;
  3492. extd_status = (phba->ctrl.mcc_numtag[tag] & 0x0000FF00) >> 8;
  3493. status = phba->ctrl.mcc_numtag[tag] & 0x000000FF;
  3494. if (status || extd_status) {
  3495. beiscsi_log(phba, KERN_ERR,
  3496. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3497. "BM_%d : beiscsi_get_session_info Failed"
  3498. " status = %d extd_status = %d\n",
  3499. status, extd_status);
  3500. free_mcc_tag(&phba->ctrl, tag);
  3501. goto boot_freemem;
  3502. }
  3503. wrb = queue_get_wrb(mccq, wrb_num);
  3504. free_mcc_tag(&phba->ctrl, tag);
  3505. session_resp = nonemb_cmd.va ;
  3506. memcpy(&phba->boot_sess, &session_resp->session_info,
  3507. sizeof(struct mgmt_session_info));
  3508. ret = 0;
  3509. boot_freemem:
  3510. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  3511. nonemb_cmd.va, nonemb_cmd.dma);
  3512. return ret;
  3513. }
  3514. static void beiscsi_boot_release(void *data)
  3515. {
  3516. struct beiscsi_hba *phba = data;
  3517. scsi_host_put(phba->shost);
  3518. }
  3519. static int beiscsi_setup_boot_info(struct beiscsi_hba *phba)
  3520. {
  3521. struct iscsi_boot_kobj *boot_kobj;
  3522. /* get boot info using mgmt cmd */
  3523. if (beiscsi_get_boot_info(phba))
  3524. /* Try to see if we can carry on without this */
  3525. return 0;
  3526. phba->boot_kset = iscsi_boot_create_host_kset(phba->shost->host_no);
  3527. if (!phba->boot_kset)
  3528. return -ENOMEM;
  3529. /* get a ref because the show function will ref the phba */
  3530. if (!scsi_host_get(phba->shost))
  3531. goto free_kset;
  3532. boot_kobj = iscsi_boot_create_target(phba->boot_kset, 0, phba,
  3533. beiscsi_show_boot_tgt_info,
  3534. beiscsi_tgt_get_attr_visibility,
  3535. beiscsi_boot_release);
  3536. if (!boot_kobj)
  3537. goto put_shost;
  3538. if (!scsi_host_get(phba->shost))
  3539. goto free_kset;
  3540. boot_kobj = iscsi_boot_create_initiator(phba->boot_kset, 0, phba,
  3541. beiscsi_show_boot_ini_info,
  3542. beiscsi_ini_get_attr_visibility,
  3543. beiscsi_boot_release);
  3544. if (!boot_kobj)
  3545. goto put_shost;
  3546. if (!scsi_host_get(phba->shost))
  3547. goto free_kset;
  3548. boot_kobj = iscsi_boot_create_ethernet(phba->boot_kset, 0, phba,
  3549. beiscsi_show_boot_eth_info,
  3550. beiscsi_eth_get_attr_visibility,
  3551. beiscsi_boot_release);
  3552. if (!boot_kobj)
  3553. goto put_shost;
  3554. return 0;
  3555. put_shost:
  3556. scsi_host_put(phba->shost);
  3557. free_kset:
  3558. iscsi_boot_destroy_kset(phba->boot_kset);
  3559. return -ENOMEM;
  3560. }
  3561. static int beiscsi_init_port(struct beiscsi_hba *phba)
  3562. {
  3563. int ret;
  3564. ret = beiscsi_init_controller(phba);
  3565. if (ret < 0) {
  3566. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3567. "BM_%d : beiscsi_dev_probe - Failed in"
  3568. "beiscsi_init_controller\n");
  3569. return ret;
  3570. }
  3571. ret = beiscsi_init_sgl_handle(phba);
  3572. if (ret < 0) {
  3573. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3574. "BM_%d : beiscsi_dev_probe - Failed in"
  3575. "beiscsi_init_sgl_handle\n");
  3576. goto do_cleanup_ctrlr;
  3577. }
  3578. if (hba_setup_cid_tbls(phba)) {
  3579. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3580. "BM_%d : Failed in hba_setup_cid_tbls\n");
  3581. kfree(phba->io_sgl_hndl_base);
  3582. kfree(phba->eh_sgl_hndl_base);
  3583. goto do_cleanup_ctrlr;
  3584. }
  3585. return ret;
  3586. do_cleanup_ctrlr:
  3587. hwi_cleanup(phba);
  3588. return ret;
  3589. }
  3590. static void hwi_purge_eq(struct beiscsi_hba *phba)
  3591. {
  3592. struct hwi_controller *phwi_ctrlr;
  3593. struct hwi_context_memory *phwi_context;
  3594. struct be_queue_info *eq;
  3595. struct be_eq_entry *eqe = NULL;
  3596. int i, eq_msix;
  3597. unsigned int num_processed;
  3598. phwi_ctrlr = phba->phwi_ctrlr;
  3599. phwi_context = phwi_ctrlr->phwi_ctxt;
  3600. if (phba->msix_enabled)
  3601. eq_msix = 1;
  3602. else
  3603. eq_msix = 0;
  3604. for (i = 0; i < (phba->num_cpus + eq_msix); i++) {
  3605. eq = &phwi_context->be_eq[i].q;
  3606. eqe = queue_tail_node(eq);
  3607. num_processed = 0;
  3608. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  3609. & EQE_VALID_MASK) {
  3610. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  3611. queue_tail_inc(eq);
  3612. eqe = queue_tail_node(eq);
  3613. num_processed++;
  3614. }
  3615. if (num_processed)
  3616. hwi_ring_eq_db(phba, eq->id, 1, num_processed, 1, 1);
  3617. }
  3618. }
  3619. static void beiscsi_clean_port(struct beiscsi_hba *phba)
  3620. {
  3621. int mgmt_status;
  3622. mgmt_status = mgmt_epfw_cleanup(phba, CMD_CONNECTION_CHUTE_0);
  3623. if (mgmt_status)
  3624. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  3625. "BM_%d : mgmt_epfw_cleanup FAILED\n");
  3626. hwi_purge_eq(phba);
  3627. hwi_cleanup(phba);
  3628. kfree(phba->io_sgl_hndl_base);
  3629. kfree(phba->eh_sgl_hndl_base);
  3630. kfree(phba->cid_array);
  3631. kfree(phba->ep_array);
  3632. }
  3633. /**
  3634. * beiscsi_cleanup_task()- Free driver resources of the task
  3635. * @task: ptr to the iscsi task
  3636. *
  3637. **/
  3638. static void beiscsi_cleanup_task(struct iscsi_task *task)
  3639. {
  3640. struct beiscsi_io_task *io_task = task->dd_data;
  3641. struct iscsi_conn *conn = task->conn;
  3642. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3643. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3644. struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
  3645. struct hwi_wrb_context *pwrb_context;
  3646. struct hwi_controller *phwi_ctrlr;
  3647. phwi_ctrlr = phba->phwi_ctrlr;
  3648. pwrb_context = &phwi_ctrlr->wrb_context[beiscsi_conn->beiscsi_conn_cid
  3649. - phba->fw_config.iscsi_cid_start];
  3650. if (io_task->cmd_bhs) {
  3651. pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
  3652. io_task->bhs_pa.u.a64.address);
  3653. io_task->cmd_bhs = NULL;
  3654. }
  3655. if (task->sc) {
  3656. if (io_task->pwrb_handle) {
  3657. free_wrb_handle(phba, pwrb_context,
  3658. io_task->pwrb_handle);
  3659. io_task->pwrb_handle = NULL;
  3660. }
  3661. if (io_task->psgl_handle) {
  3662. spin_lock(&phba->io_sgl_lock);
  3663. free_io_sgl_handle(phba, io_task->psgl_handle);
  3664. spin_unlock(&phba->io_sgl_lock);
  3665. io_task->psgl_handle = NULL;
  3666. }
  3667. } else {
  3668. if (!beiscsi_conn->login_in_progress) {
  3669. if (io_task->pwrb_handle) {
  3670. free_wrb_handle(phba, pwrb_context,
  3671. io_task->pwrb_handle);
  3672. io_task->pwrb_handle = NULL;
  3673. }
  3674. if (io_task->psgl_handle) {
  3675. spin_lock(&phba->mgmt_sgl_lock);
  3676. free_mgmt_sgl_handle(phba,
  3677. io_task->psgl_handle);
  3678. spin_unlock(&phba->mgmt_sgl_lock);
  3679. io_task->psgl_handle = NULL;
  3680. }
  3681. if (io_task->mtask_addr) {
  3682. pci_unmap_single(phba->pcidev,
  3683. io_task->mtask_addr,
  3684. io_task->mtask_data_count,
  3685. PCI_DMA_TODEVICE);
  3686. io_task->mtask_addr = 0;
  3687. }
  3688. }
  3689. }
  3690. }
  3691. void
  3692. beiscsi_offload_connection(struct beiscsi_conn *beiscsi_conn,
  3693. struct beiscsi_offload_params *params)
  3694. {
  3695. struct wrb_handle *pwrb_handle;
  3696. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3697. struct iscsi_task *task = beiscsi_conn->task;
  3698. struct iscsi_session *session = task->conn->session;
  3699. u32 doorbell = 0;
  3700. /*
  3701. * We can always use 0 here because it is reserved by libiscsi for
  3702. * login/startup related tasks.
  3703. */
  3704. beiscsi_conn->login_in_progress = 0;
  3705. spin_lock_bh(&session->lock);
  3706. beiscsi_cleanup_task(task);
  3707. spin_unlock_bh(&session->lock);
  3708. pwrb_handle = alloc_wrb_handle(phba, (beiscsi_conn->beiscsi_conn_cid -
  3709. phba->fw_config.iscsi_cid_start));
  3710. /* Check for the adapter family */
  3711. if (chip_skh_r(phba->pcidev))
  3712. beiscsi_offload_cxn_v2(params, pwrb_handle);
  3713. else
  3714. beiscsi_offload_cxn_v0(params, pwrb_handle,
  3715. phba->init_mem);
  3716. be_dws_le_to_cpu(pwrb_handle->pwrb,
  3717. sizeof(struct iscsi_target_context_update_wrb));
  3718. doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
  3719. doorbell |= (pwrb_handle->wrb_index & DB_DEF_PDU_WRB_INDEX_MASK)
  3720. << DB_DEF_PDU_WRB_INDEX_SHIFT;
  3721. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  3722. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  3723. }
  3724. static void beiscsi_parse_pdu(struct iscsi_conn *conn, itt_t itt,
  3725. int *index, int *age)
  3726. {
  3727. *index = (int)itt;
  3728. if (age)
  3729. *age = conn->session->age;
  3730. }
  3731. /**
  3732. * beiscsi_alloc_pdu - allocates pdu and related resources
  3733. * @task: libiscsi task
  3734. * @opcode: opcode of pdu for task
  3735. *
  3736. * This is called with the session lock held. It will allocate
  3737. * the wrb and sgl if needed for the command. And it will prep
  3738. * the pdu's itt. beiscsi_parse_pdu will later translate
  3739. * the pdu itt to the libiscsi task itt.
  3740. */
  3741. static int beiscsi_alloc_pdu(struct iscsi_task *task, uint8_t opcode)
  3742. {
  3743. struct beiscsi_io_task *io_task = task->dd_data;
  3744. struct iscsi_conn *conn = task->conn;
  3745. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3746. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3747. struct hwi_wrb_context *pwrb_context;
  3748. struct hwi_controller *phwi_ctrlr;
  3749. itt_t itt;
  3750. struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
  3751. dma_addr_t paddr;
  3752. io_task->cmd_bhs = pci_pool_alloc(beiscsi_sess->bhs_pool,
  3753. GFP_ATOMIC, &paddr);
  3754. if (!io_task->cmd_bhs)
  3755. return -ENOMEM;
  3756. io_task->bhs_pa.u.a64.address = paddr;
  3757. io_task->libiscsi_itt = (itt_t)task->itt;
  3758. io_task->conn = beiscsi_conn;
  3759. task->hdr = (struct iscsi_hdr *)&io_task->cmd_bhs->iscsi_hdr;
  3760. task->hdr_max = sizeof(struct be_cmd_bhs);
  3761. io_task->psgl_handle = NULL;
  3762. io_task->pwrb_handle = NULL;
  3763. if (task->sc) {
  3764. spin_lock(&phba->io_sgl_lock);
  3765. io_task->psgl_handle = alloc_io_sgl_handle(phba);
  3766. spin_unlock(&phba->io_sgl_lock);
  3767. if (!io_task->psgl_handle) {
  3768. beiscsi_log(phba, KERN_ERR,
  3769. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  3770. "BM_%d : Alloc of IO_SGL_ICD Failed"
  3771. "for the CID : %d\n",
  3772. beiscsi_conn->beiscsi_conn_cid);
  3773. goto free_hndls;
  3774. }
  3775. io_task->pwrb_handle = alloc_wrb_handle(phba,
  3776. beiscsi_conn->beiscsi_conn_cid -
  3777. phba->fw_config.iscsi_cid_start);
  3778. if (!io_task->pwrb_handle) {
  3779. beiscsi_log(phba, KERN_ERR,
  3780. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  3781. "BM_%d : Alloc of WRB_HANDLE Failed"
  3782. "for the CID : %d\n",
  3783. beiscsi_conn->beiscsi_conn_cid);
  3784. goto free_io_hndls;
  3785. }
  3786. } else {
  3787. io_task->scsi_cmnd = NULL;
  3788. if ((opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGIN) {
  3789. if (!beiscsi_conn->login_in_progress) {
  3790. spin_lock(&phba->mgmt_sgl_lock);
  3791. io_task->psgl_handle = (struct sgl_handle *)
  3792. alloc_mgmt_sgl_handle(phba);
  3793. spin_unlock(&phba->mgmt_sgl_lock);
  3794. if (!io_task->psgl_handle) {
  3795. beiscsi_log(phba, KERN_ERR,
  3796. BEISCSI_LOG_IO |
  3797. BEISCSI_LOG_CONFIG,
  3798. "BM_%d : Alloc of MGMT_SGL_ICD Failed"
  3799. "for the CID : %d\n",
  3800. beiscsi_conn->
  3801. beiscsi_conn_cid);
  3802. goto free_hndls;
  3803. }
  3804. beiscsi_conn->login_in_progress = 1;
  3805. beiscsi_conn->plogin_sgl_handle =
  3806. io_task->psgl_handle;
  3807. io_task->pwrb_handle =
  3808. alloc_wrb_handle(phba,
  3809. beiscsi_conn->beiscsi_conn_cid -
  3810. phba->fw_config.iscsi_cid_start);
  3811. if (!io_task->pwrb_handle) {
  3812. beiscsi_log(phba, KERN_ERR,
  3813. BEISCSI_LOG_IO |
  3814. BEISCSI_LOG_CONFIG,
  3815. "BM_%d : Alloc of WRB_HANDLE Failed"
  3816. "for the CID : %d\n",
  3817. beiscsi_conn->
  3818. beiscsi_conn_cid);
  3819. goto free_mgmt_hndls;
  3820. }
  3821. beiscsi_conn->plogin_wrb_handle =
  3822. io_task->pwrb_handle;
  3823. } else {
  3824. io_task->psgl_handle =
  3825. beiscsi_conn->plogin_sgl_handle;
  3826. io_task->pwrb_handle =
  3827. beiscsi_conn->plogin_wrb_handle;
  3828. }
  3829. beiscsi_conn->task = task;
  3830. } else {
  3831. spin_lock(&phba->mgmt_sgl_lock);
  3832. io_task->psgl_handle = alloc_mgmt_sgl_handle(phba);
  3833. spin_unlock(&phba->mgmt_sgl_lock);
  3834. if (!io_task->psgl_handle) {
  3835. beiscsi_log(phba, KERN_ERR,
  3836. BEISCSI_LOG_IO |
  3837. BEISCSI_LOG_CONFIG,
  3838. "BM_%d : Alloc of MGMT_SGL_ICD Failed"
  3839. "for the CID : %d\n",
  3840. beiscsi_conn->
  3841. beiscsi_conn_cid);
  3842. goto free_hndls;
  3843. }
  3844. io_task->pwrb_handle =
  3845. alloc_wrb_handle(phba,
  3846. beiscsi_conn->beiscsi_conn_cid -
  3847. phba->fw_config.iscsi_cid_start);
  3848. if (!io_task->pwrb_handle) {
  3849. beiscsi_log(phba, KERN_ERR,
  3850. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  3851. "BM_%d : Alloc of WRB_HANDLE Failed"
  3852. "for the CID : %d\n",
  3853. beiscsi_conn->beiscsi_conn_cid);
  3854. goto free_mgmt_hndls;
  3855. }
  3856. }
  3857. }
  3858. itt = (itt_t) cpu_to_be32(((unsigned int)io_task->pwrb_handle->
  3859. wrb_index << 16) | (unsigned int)
  3860. (io_task->psgl_handle->sgl_index));
  3861. io_task->pwrb_handle->pio_handle = task;
  3862. io_task->cmd_bhs->iscsi_hdr.itt = itt;
  3863. return 0;
  3864. free_io_hndls:
  3865. spin_lock(&phba->io_sgl_lock);
  3866. free_io_sgl_handle(phba, io_task->psgl_handle);
  3867. spin_unlock(&phba->io_sgl_lock);
  3868. goto free_hndls;
  3869. free_mgmt_hndls:
  3870. spin_lock(&phba->mgmt_sgl_lock);
  3871. free_mgmt_sgl_handle(phba, io_task->psgl_handle);
  3872. spin_unlock(&phba->mgmt_sgl_lock);
  3873. free_hndls:
  3874. phwi_ctrlr = phba->phwi_ctrlr;
  3875. pwrb_context = &phwi_ctrlr->wrb_context[
  3876. beiscsi_conn->beiscsi_conn_cid -
  3877. phba->fw_config.iscsi_cid_start];
  3878. if (io_task->pwrb_handle)
  3879. free_wrb_handle(phba, pwrb_context, io_task->pwrb_handle);
  3880. io_task->pwrb_handle = NULL;
  3881. pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
  3882. io_task->bhs_pa.u.a64.address);
  3883. io_task->cmd_bhs = NULL;
  3884. return -ENOMEM;
  3885. }
  3886. int beiscsi_iotask_v2(struct iscsi_task *task, struct scatterlist *sg,
  3887. unsigned int num_sg, unsigned int xferlen,
  3888. unsigned int writedir)
  3889. {
  3890. struct beiscsi_io_task *io_task = task->dd_data;
  3891. struct iscsi_conn *conn = task->conn;
  3892. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3893. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3894. struct iscsi_wrb *pwrb = NULL;
  3895. unsigned int doorbell = 0;
  3896. pwrb = io_task->pwrb_handle->pwrb;
  3897. memset(pwrb, 0, sizeof(*pwrb));
  3898. io_task->cmd_bhs->iscsi_hdr.exp_statsn = 0;
  3899. io_task->bhs_len = sizeof(struct be_cmd_bhs);
  3900. if (writedir) {
  3901. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, type, pwrb,
  3902. INI_WR_CMD);
  3903. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp, pwrb, 1);
  3904. } else {
  3905. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, type, pwrb,
  3906. INI_RD_CMD);
  3907. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp, pwrb, 0);
  3908. }
  3909. io_task->wrb_type = AMAP_GET_BITS(struct amap_iscsi_wrb_v2,
  3910. type, pwrb);
  3911. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, lun, pwrb,
  3912. cpu_to_be16(*(unsigned short *)
  3913. &io_task->cmd_bhs->iscsi_hdr.lun));
  3914. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, r2t_exp_dtl, pwrb, xferlen);
  3915. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, wrb_idx, pwrb,
  3916. io_task->pwrb_handle->wrb_index);
  3917. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, cmdsn_itt, pwrb,
  3918. be32_to_cpu(task->cmdsn));
  3919. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sgl_idx, pwrb,
  3920. io_task->psgl_handle->sgl_index);
  3921. hwi_write_sgl_v2(pwrb, sg, num_sg, io_task);
  3922. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb, pwrb,
  3923. io_task->pwrb_handle->nxt_wrb_index);
  3924. be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
  3925. doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
  3926. doorbell |= (io_task->pwrb_handle->wrb_index &
  3927. DB_DEF_PDU_WRB_INDEX_MASK) <<
  3928. DB_DEF_PDU_WRB_INDEX_SHIFT;
  3929. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  3930. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  3931. return 0;
  3932. }
  3933. static int beiscsi_iotask(struct iscsi_task *task, struct scatterlist *sg,
  3934. unsigned int num_sg, unsigned int xferlen,
  3935. unsigned int writedir)
  3936. {
  3937. struct beiscsi_io_task *io_task = task->dd_data;
  3938. struct iscsi_conn *conn = task->conn;
  3939. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3940. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3941. struct iscsi_wrb *pwrb = NULL;
  3942. unsigned int doorbell = 0;
  3943. pwrb = io_task->pwrb_handle->pwrb;
  3944. io_task->cmd_bhs->iscsi_hdr.exp_statsn = 0;
  3945. io_task->bhs_len = sizeof(struct be_cmd_bhs);
  3946. if (writedir) {
  3947. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3948. INI_WR_CMD);
  3949. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 1);
  3950. } else {
  3951. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3952. INI_RD_CMD);
  3953. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
  3954. }
  3955. io_task->wrb_type = AMAP_GET_BITS(struct amap_iscsi_wrb,
  3956. type, pwrb);
  3957. AMAP_SET_BITS(struct amap_iscsi_wrb, lun, pwrb,
  3958. cpu_to_be16(*(unsigned short *)
  3959. &io_task->cmd_bhs->iscsi_hdr.lun));
  3960. AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb, xferlen);
  3961. AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
  3962. io_task->pwrb_handle->wrb_index);
  3963. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
  3964. be32_to_cpu(task->cmdsn));
  3965. AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
  3966. io_task->psgl_handle->sgl_index);
  3967. hwi_write_sgl(pwrb, sg, num_sg, io_task);
  3968. AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
  3969. io_task->pwrb_handle->nxt_wrb_index);
  3970. be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
  3971. doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
  3972. doorbell |= (io_task->pwrb_handle->wrb_index &
  3973. DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
  3974. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  3975. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  3976. return 0;
  3977. }
  3978. static int beiscsi_mtask(struct iscsi_task *task)
  3979. {
  3980. struct beiscsi_io_task *io_task = task->dd_data;
  3981. struct iscsi_conn *conn = task->conn;
  3982. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3983. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3984. struct iscsi_wrb *pwrb = NULL;
  3985. unsigned int doorbell = 0;
  3986. unsigned int cid;
  3987. unsigned int pwrb_typeoffset = 0;
  3988. cid = beiscsi_conn->beiscsi_conn_cid;
  3989. pwrb = io_task->pwrb_handle->pwrb;
  3990. memset(pwrb, 0, sizeof(*pwrb));
  3991. if (chip_skh_r(phba->pcidev)) {
  3992. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, cmdsn_itt, pwrb,
  3993. be32_to_cpu(task->cmdsn));
  3994. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, wrb_idx, pwrb,
  3995. io_task->pwrb_handle->wrb_index);
  3996. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sgl_idx, pwrb,
  3997. io_task->psgl_handle->sgl_index);
  3998. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, r2t_exp_dtl, pwrb,
  3999. task->data_count);
  4000. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb, pwrb,
  4001. io_task->pwrb_handle->nxt_wrb_index);
  4002. pwrb_typeoffset = SKH_WRB_TYPE_OFFSET;
  4003. } else {
  4004. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
  4005. be32_to_cpu(task->cmdsn));
  4006. AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
  4007. io_task->pwrb_handle->wrb_index);
  4008. AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
  4009. io_task->psgl_handle->sgl_index);
  4010. AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb,
  4011. task->data_count);
  4012. AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
  4013. io_task->pwrb_handle->nxt_wrb_index);
  4014. pwrb_typeoffset = BE_WRB_TYPE_OFFSET;
  4015. }
  4016. switch (task->hdr->opcode & ISCSI_OPCODE_MASK) {
  4017. case ISCSI_OP_LOGIN:
  4018. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb, 1);
  4019. ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset);
  4020. hwi_write_buffer(pwrb, task);
  4021. break;
  4022. case ISCSI_OP_NOOP_OUT:
  4023. if (task->hdr->ttt != ISCSI_RESERVED_TAG) {
  4024. ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset);
  4025. if (chip_skh_r(phba->pcidev))
  4026. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  4027. dmsg, pwrb, 1);
  4028. else
  4029. AMAP_SET_BITS(struct amap_iscsi_wrb,
  4030. dmsg, pwrb, 1);
  4031. } else {
  4032. ADAPTER_SET_WRB_TYPE(pwrb, INI_RD_CMD, pwrb_typeoffset);
  4033. if (chip_skh_r(phba->pcidev))
  4034. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  4035. dmsg, pwrb, 0);
  4036. else
  4037. AMAP_SET_BITS(struct amap_iscsi_wrb,
  4038. dmsg, pwrb, 0);
  4039. }
  4040. hwi_write_buffer(pwrb, task);
  4041. break;
  4042. case ISCSI_OP_TEXT:
  4043. ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset);
  4044. hwi_write_buffer(pwrb, task);
  4045. break;
  4046. case ISCSI_OP_SCSI_TMFUNC:
  4047. ADAPTER_SET_WRB_TYPE(pwrb, INI_TMF_CMD, pwrb_typeoffset);
  4048. hwi_write_buffer(pwrb, task);
  4049. break;
  4050. case ISCSI_OP_LOGOUT:
  4051. ADAPTER_SET_WRB_TYPE(pwrb, HWH_TYPE_LOGOUT, pwrb_typeoffset);
  4052. hwi_write_buffer(pwrb, task);
  4053. break;
  4054. default:
  4055. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  4056. "BM_%d : opcode =%d Not supported\n",
  4057. task->hdr->opcode & ISCSI_OPCODE_MASK);
  4058. return -EINVAL;
  4059. }
  4060. /* Set the task type */
  4061. io_task->wrb_type = (chip_skh_r(phba->pcidev)) ?
  4062. AMAP_GET_BITS(struct amap_iscsi_wrb_v2, type, pwrb) :
  4063. AMAP_GET_BITS(struct amap_iscsi_wrb, type, pwrb);
  4064. doorbell |= cid & DB_WRB_POST_CID_MASK;
  4065. doorbell |= (io_task->pwrb_handle->wrb_index &
  4066. DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
  4067. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  4068. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  4069. return 0;
  4070. }
  4071. static int beiscsi_task_xmit(struct iscsi_task *task)
  4072. {
  4073. struct beiscsi_io_task *io_task = task->dd_data;
  4074. struct scsi_cmnd *sc = task->sc;
  4075. struct beiscsi_hba *phba = NULL;
  4076. struct scatterlist *sg;
  4077. int num_sg;
  4078. unsigned int writedir = 0, xferlen = 0;
  4079. phba = ((struct beiscsi_conn *)task->conn->dd_data)->phba;
  4080. if (!sc)
  4081. return beiscsi_mtask(task);
  4082. io_task->scsi_cmnd = sc;
  4083. num_sg = scsi_dma_map(sc);
  4084. if (num_sg < 0) {
  4085. struct iscsi_conn *conn = task->conn;
  4086. struct beiscsi_hba *phba = NULL;
  4087. phba = ((struct beiscsi_conn *)conn->dd_data)->phba;
  4088. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_IO,
  4089. "BM_%d : scsi_dma_map Failed\n");
  4090. return num_sg;
  4091. }
  4092. xferlen = scsi_bufflen(sc);
  4093. sg = scsi_sglist(sc);
  4094. if (sc->sc_data_direction == DMA_TO_DEVICE)
  4095. writedir = 1;
  4096. else
  4097. writedir = 0;
  4098. return phba->iotask_fn(task, sg, num_sg, xferlen, writedir);
  4099. }
  4100. /**
  4101. * beiscsi_bsg_request - handle bsg request from ISCSI transport
  4102. * @job: job to handle
  4103. */
  4104. static int beiscsi_bsg_request(struct bsg_job *job)
  4105. {
  4106. struct Scsi_Host *shost;
  4107. struct beiscsi_hba *phba;
  4108. struct iscsi_bsg_request *bsg_req = job->request;
  4109. int rc = -EINVAL;
  4110. unsigned int tag;
  4111. struct be_dma_mem nonemb_cmd;
  4112. struct be_cmd_resp_hdr *resp;
  4113. struct iscsi_bsg_reply *bsg_reply = job->reply;
  4114. unsigned short status, extd_status;
  4115. shost = iscsi_job_to_shost(job);
  4116. phba = iscsi_host_priv(shost);
  4117. switch (bsg_req->msgcode) {
  4118. case ISCSI_BSG_HST_VENDOR:
  4119. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  4120. job->request_payload.payload_len,
  4121. &nonemb_cmd.dma);
  4122. if (nonemb_cmd.va == NULL) {
  4123. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  4124. "BM_%d : Failed to allocate memory for "
  4125. "beiscsi_bsg_request\n");
  4126. return -ENOMEM;
  4127. }
  4128. tag = mgmt_vendor_specific_fw_cmd(&phba->ctrl, phba, job,
  4129. &nonemb_cmd);
  4130. if (!tag) {
  4131. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  4132. "BM_%d : MBX Tag Allocation Failed\n");
  4133. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  4134. nonemb_cmd.va, nonemb_cmd.dma);
  4135. return -EAGAIN;
  4136. } else
  4137. wait_event_interruptible(phba->ctrl.mcc_wait[tag],
  4138. phba->ctrl.mcc_numtag[tag]);
  4139. extd_status = (phba->ctrl.mcc_numtag[tag] & 0x0000FF00) >> 8;
  4140. status = phba->ctrl.mcc_numtag[tag] & 0x000000FF;
  4141. free_mcc_tag(&phba->ctrl, tag);
  4142. resp = (struct be_cmd_resp_hdr *)nonemb_cmd.va;
  4143. sg_copy_from_buffer(job->reply_payload.sg_list,
  4144. job->reply_payload.sg_cnt,
  4145. nonemb_cmd.va, (resp->response_length
  4146. + sizeof(*resp)));
  4147. bsg_reply->reply_payload_rcv_len = resp->response_length;
  4148. bsg_reply->result = status;
  4149. bsg_job_done(job, bsg_reply->result,
  4150. bsg_reply->reply_payload_rcv_len);
  4151. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  4152. nonemb_cmd.va, nonemb_cmd.dma);
  4153. if (status || extd_status) {
  4154. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  4155. "BM_%d : MBX Cmd Failed"
  4156. " status = %d extd_status = %d\n",
  4157. status, extd_status);
  4158. return -EIO;
  4159. } else {
  4160. rc = 0;
  4161. }
  4162. break;
  4163. default:
  4164. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  4165. "BM_%d : Unsupported bsg command: 0x%x\n",
  4166. bsg_req->msgcode);
  4167. break;
  4168. }
  4169. return rc;
  4170. }
  4171. void beiscsi_hba_attrs_init(struct beiscsi_hba *phba)
  4172. {
  4173. /* Set the logging parameter */
  4174. beiscsi_log_enable_init(phba, beiscsi_log_enable);
  4175. }
  4176. /*
  4177. * beiscsi_quiesce()- Cleanup Driver resources
  4178. * @phba: Instance Priv structure
  4179. *
  4180. * Free the OS and HW resources held by the driver
  4181. **/
  4182. static void beiscsi_quiesce(struct beiscsi_hba *phba)
  4183. {
  4184. struct hwi_controller *phwi_ctrlr;
  4185. struct hwi_context_memory *phwi_context;
  4186. struct be_eq_obj *pbe_eq;
  4187. unsigned int i, msix_vec;
  4188. phwi_ctrlr = phba->phwi_ctrlr;
  4189. phwi_context = phwi_ctrlr->phwi_ctxt;
  4190. hwi_disable_intr(phba);
  4191. if (phba->msix_enabled) {
  4192. for (i = 0; i <= phba->num_cpus; i++) {
  4193. msix_vec = phba->msix_entries[i].vector;
  4194. free_irq(msix_vec, &phwi_context->be_eq[i]);
  4195. kfree(phba->msi_name[i]);
  4196. }
  4197. } else
  4198. if (phba->pcidev->irq)
  4199. free_irq(phba->pcidev->irq, phba);
  4200. pci_disable_msix(phba->pcidev);
  4201. destroy_workqueue(phba->wq);
  4202. if (blk_iopoll_enabled)
  4203. for (i = 0; i < phba->num_cpus; i++) {
  4204. pbe_eq = &phwi_context->be_eq[i];
  4205. blk_iopoll_disable(&pbe_eq->iopoll);
  4206. }
  4207. beiscsi_clean_port(phba);
  4208. beiscsi_free_mem(phba);
  4209. beiscsi_unmap_pci_function(phba);
  4210. pci_free_consistent(phba->pcidev,
  4211. phba->ctrl.mbox_mem_alloced.size,
  4212. phba->ctrl.mbox_mem_alloced.va,
  4213. phba->ctrl.mbox_mem_alloced.dma);
  4214. }
  4215. static void beiscsi_remove(struct pci_dev *pcidev)
  4216. {
  4217. struct beiscsi_hba *phba = NULL;
  4218. phba = pci_get_drvdata(pcidev);
  4219. if (!phba) {
  4220. dev_err(&pcidev->dev, "beiscsi_remove called with no phba\n");
  4221. return;
  4222. }
  4223. beiscsi_destroy_def_ifaces(phba);
  4224. beiscsi_quiesce(phba);
  4225. iscsi_boot_destroy_kset(phba->boot_kset);
  4226. iscsi_host_remove(phba->shost);
  4227. pci_dev_put(phba->pcidev);
  4228. iscsi_host_free(phba->shost);
  4229. pci_disable_device(pcidev);
  4230. }
  4231. static void beiscsi_shutdown(struct pci_dev *pcidev)
  4232. {
  4233. struct beiscsi_hba *phba = NULL;
  4234. phba = (struct beiscsi_hba *)pci_get_drvdata(pcidev);
  4235. if (!phba) {
  4236. dev_err(&pcidev->dev, "beiscsi_shutdown called with no phba\n");
  4237. return;
  4238. }
  4239. beiscsi_quiesce(phba);
  4240. pci_disable_device(pcidev);
  4241. }
  4242. static void beiscsi_msix_enable(struct beiscsi_hba *phba)
  4243. {
  4244. int i, status;
  4245. for (i = 0; i <= phba->num_cpus; i++)
  4246. phba->msix_entries[i].entry = i;
  4247. status = pci_enable_msix(phba->pcidev, phba->msix_entries,
  4248. (phba->num_cpus + 1));
  4249. if (!status)
  4250. phba->msix_enabled = true;
  4251. return;
  4252. }
  4253. static int __devinit beiscsi_dev_probe(struct pci_dev *pcidev,
  4254. const struct pci_device_id *id)
  4255. {
  4256. struct beiscsi_hba *phba = NULL;
  4257. struct hwi_controller *phwi_ctrlr;
  4258. struct hwi_context_memory *phwi_context;
  4259. struct be_eq_obj *pbe_eq;
  4260. int ret, i;
  4261. ret = beiscsi_enable_pci(pcidev);
  4262. if (ret < 0) {
  4263. dev_err(&pcidev->dev,
  4264. "beiscsi_dev_probe - Failed to enable pci device\n");
  4265. return ret;
  4266. }
  4267. phba = beiscsi_hba_alloc(pcidev);
  4268. if (!phba) {
  4269. dev_err(&pcidev->dev,
  4270. "beiscsi_dev_probe - Failed in beiscsi_hba_alloc\n");
  4271. goto disable_pci;
  4272. }
  4273. /* Initialize Driver configuration Paramters */
  4274. beiscsi_hba_attrs_init(phba);
  4275. switch (pcidev->device) {
  4276. case BE_DEVICE_ID1:
  4277. case OC_DEVICE_ID1:
  4278. case OC_DEVICE_ID2:
  4279. phba->generation = BE_GEN2;
  4280. phba->iotask_fn = beiscsi_iotask;
  4281. break;
  4282. case BE_DEVICE_ID2:
  4283. case OC_DEVICE_ID3:
  4284. phba->generation = BE_GEN3;
  4285. phba->iotask_fn = beiscsi_iotask;
  4286. break;
  4287. case OC_SKH_ID1:
  4288. phba->generation = BE_GEN4;
  4289. phba->iotask_fn = beiscsi_iotask_v2;
  4290. default:
  4291. phba->generation = 0;
  4292. }
  4293. if (enable_msix)
  4294. find_num_cpus(phba);
  4295. else
  4296. phba->num_cpus = 1;
  4297. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  4298. "BM_%d : num_cpus = %d\n",
  4299. phba->num_cpus);
  4300. if (enable_msix) {
  4301. beiscsi_msix_enable(phba);
  4302. if (!phba->msix_enabled)
  4303. phba->num_cpus = 1;
  4304. }
  4305. ret = be_ctrl_init(phba, pcidev);
  4306. if (ret) {
  4307. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4308. "BM_%d : beiscsi_dev_probe-"
  4309. "Failed in be_ctrl_init\n");
  4310. goto hba_free;
  4311. }
  4312. ret = beiscsi_cmd_reset_function(phba);
  4313. if (ret) {
  4314. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4315. "BM_%d : Reset Failed. Aborting Crashdump\n");
  4316. goto hba_free;
  4317. }
  4318. ret = be_chk_reset_complete(phba);
  4319. if (ret) {
  4320. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4321. "BM_%d : Failed to get out of reset."
  4322. "Aborting Crashdump\n");
  4323. goto hba_free;
  4324. }
  4325. spin_lock_init(&phba->io_sgl_lock);
  4326. spin_lock_init(&phba->mgmt_sgl_lock);
  4327. spin_lock_init(&phba->isr_lock);
  4328. ret = mgmt_get_fw_config(&phba->ctrl, phba);
  4329. if (ret != 0) {
  4330. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4331. "BM_%d : Error getting fw config\n");
  4332. goto free_port;
  4333. }
  4334. phba->shost->max_id = phba->fw_config.iscsi_cid_count;
  4335. beiscsi_get_params(phba);
  4336. phba->shost->can_queue = phba->params.ios_per_ctrl;
  4337. ret = beiscsi_init_port(phba);
  4338. if (ret < 0) {
  4339. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4340. "BM_%d : beiscsi_dev_probe-"
  4341. "Failed in beiscsi_init_port\n");
  4342. goto free_port;
  4343. }
  4344. for (i = 0; i < MAX_MCC_CMD ; i++) {
  4345. init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]);
  4346. phba->ctrl.mcc_tag[i] = i + 1;
  4347. phba->ctrl.mcc_numtag[i + 1] = 0;
  4348. phba->ctrl.mcc_tag_available++;
  4349. }
  4350. phba->ctrl.mcc_alloc_index = phba->ctrl.mcc_free_index = 0;
  4351. snprintf(phba->wq_name, sizeof(phba->wq_name), "beiscsi_%02x_wq",
  4352. phba->shost->host_no);
  4353. phba->wq = alloc_workqueue(phba->wq_name, WQ_MEM_RECLAIM, 1);
  4354. if (!phba->wq) {
  4355. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4356. "BM_%d : beiscsi_dev_probe-"
  4357. "Failed to allocate work queue\n");
  4358. goto free_twq;
  4359. }
  4360. phwi_ctrlr = phba->phwi_ctrlr;
  4361. phwi_context = phwi_ctrlr->phwi_ctxt;
  4362. if (blk_iopoll_enabled) {
  4363. for (i = 0; i < phba->num_cpus; i++) {
  4364. pbe_eq = &phwi_context->be_eq[i];
  4365. blk_iopoll_init(&pbe_eq->iopoll, be_iopoll_budget,
  4366. be_iopoll);
  4367. blk_iopoll_enable(&pbe_eq->iopoll);
  4368. }
  4369. i = (phba->msix_enabled) ? i : 0;
  4370. /* Work item for MCC handling */
  4371. pbe_eq = &phwi_context->be_eq[i];
  4372. INIT_WORK(&pbe_eq->work_cqs, beiscsi_process_all_cqs);
  4373. } else {
  4374. if (phba->msix_enabled) {
  4375. for (i = 0; i <= phba->num_cpus; i++) {
  4376. pbe_eq = &phwi_context->be_eq[i];
  4377. INIT_WORK(&pbe_eq->work_cqs,
  4378. beiscsi_process_all_cqs);
  4379. }
  4380. } else {
  4381. pbe_eq = &phwi_context->be_eq[0];
  4382. INIT_WORK(&pbe_eq->work_cqs,
  4383. beiscsi_process_all_cqs);
  4384. }
  4385. }
  4386. ret = beiscsi_init_irqs(phba);
  4387. if (ret < 0) {
  4388. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4389. "BM_%d : beiscsi_dev_probe-"
  4390. "Failed to beiscsi_init_irqs\n");
  4391. goto free_blkenbld;
  4392. }
  4393. hwi_enable_intr(phba);
  4394. if (beiscsi_setup_boot_info(phba))
  4395. /*
  4396. * log error but continue, because we may not be using
  4397. * iscsi boot.
  4398. */
  4399. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4400. "BM_%d : Could not set up "
  4401. "iSCSI boot info.\n");
  4402. beiscsi_create_def_ifaces(phba);
  4403. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  4404. "\n\n\n BM_%d : SUCCESS - DRIVER LOADED\n\n\n");
  4405. return 0;
  4406. free_blkenbld:
  4407. destroy_workqueue(phba->wq);
  4408. if (blk_iopoll_enabled)
  4409. for (i = 0; i < phba->num_cpus; i++) {
  4410. pbe_eq = &phwi_context->be_eq[i];
  4411. blk_iopoll_disable(&pbe_eq->iopoll);
  4412. }
  4413. free_twq:
  4414. beiscsi_clean_port(phba);
  4415. beiscsi_free_mem(phba);
  4416. free_port:
  4417. pci_free_consistent(phba->pcidev,
  4418. phba->ctrl.mbox_mem_alloced.size,
  4419. phba->ctrl.mbox_mem_alloced.va,
  4420. phba->ctrl.mbox_mem_alloced.dma);
  4421. beiscsi_unmap_pci_function(phba);
  4422. hba_free:
  4423. if (phba->msix_enabled)
  4424. pci_disable_msix(phba->pcidev);
  4425. iscsi_host_remove(phba->shost);
  4426. pci_dev_put(phba->pcidev);
  4427. iscsi_host_free(phba->shost);
  4428. disable_pci:
  4429. pci_disable_device(pcidev);
  4430. return ret;
  4431. }
  4432. struct iscsi_transport beiscsi_iscsi_transport = {
  4433. .owner = THIS_MODULE,
  4434. .name = DRV_NAME,
  4435. .caps = CAP_RECOVERY_L0 | CAP_HDRDGST | CAP_TEXT_NEGO |
  4436. CAP_MULTI_R2T | CAP_DATADGST | CAP_DATA_PATH_OFFLOAD,
  4437. .create_session = beiscsi_session_create,
  4438. .destroy_session = beiscsi_session_destroy,
  4439. .create_conn = beiscsi_conn_create,
  4440. .bind_conn = beiscsi_conn_bind,
  4441. .destroy_conn = iscsi_conn_teardown,
  4442. .attr_is_visible = be2iscsi_attr_is_visible,
  4443. .set_iface_param = be2iscsi_iface_set_param,
  4444. .get_iface_param = be2iscsi_iface_get_param,
  4445. .set_param = beiscsi_set_param,
  4446. .get_conn_param = iscsi_conn_get_param,
  4447. .get_session_param = iscsi_session_get_param,
  4448. .get_host_param = beiscsi_get_host_param,
  4449. .start_conn = beiscsi_conn_start,
  4450. .stop_conn = iscsi_conn_stop,
  4451. .send_pdu = iscsi_conn_send_pdu,
  4452. .xmit_task = beiscsi_task_xmit,
  4453. .cleanup_task = beiscsi_cleanup_task,
  4454. .alloc_pdu = beiscsi_alloc_pdu,
  4455. .parse_pdu_itt = beiscsi_parse_pdu,
  4456. .get_stats = beiscsi_conn_get_stats,
  4457. .get_ep_param = beiscsi_ep_get_param,
  4458. .ep_connect = beiscsi_ep_connect,
  4459. .ep_poll = beiscsi_ep_poll,
  4460. .ep_disconnect = beiscsi_ep_disconnect,
  4461. .session_recovery_timedout = iscsi_session_recovery_timedout,
  4462. .bsg_request = beiscsi_bsg_request,
  4463. };
  4464. static struct pci_driver beiscsi_pci_driver = {
  4465. .name = DRV_NAME,
  4466. .probe = beiscsi_dev_probe,
  4467. .remove = beiscsi_remove,
  4468. .shutdown = beiscsi_shutdown,
  4469. .id_table = beiscsi_pci_id_table
  4470. };
  4471. static int __init beiscsi_module_init(void)
  4472. {
  4473. int ret;
  4474. beiscsi_scsi_transport =
  4475. iscsi_register_transport(&beiscsi_iscsi_transport);
  4476. if (!beiscsi_scsi_transport) {
  4477. printk(KERN_ERR
  4478. "beiscsi_module_init - Unable to register beiscsi transport.\n");
  4479. return -ENOMEM;
  4480. }
  4481. printk(KERN_INFO "In beiscsi_module_init, tt=%p\n",
  4482. &beiscsi_iscsi_transport);
  4483. ret = pci_register_driver(&beiscsi_pci_driver);
  4484. if (ret) {
  4485. printk(KERN_ERR
  4486. "beiscsi_module_init - Unable to register beiscsi pci driver.\n");
  4487. goto unregister_iscsi_transport;
  4488. }
  4489. return 0;
  4490. unregister_iscsi_transport:
  4491. iscsi_unregister_transport(&beiscsi_iscsi_transport);
  4492. return ret;
  4493. }
  4494. static void __exit beiscsi_module_exit(void)
  4495. {
  4496. pci_unregister_driver(&beiscsi_pci_driver);
  4497. iscsi_unregister_transport(&beiscsi_iscsi_transport);
  4498. }
  4499. module_init(beiscsi_module_init);
  4500. module_exit(beiscsi_module_exit);