bnx2x_stats.c 50 KB

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  1. /* bnx2x_stats.c: Broadcom Everest network driver.
  2. *
  3. * Copyright (c) 2007-2011 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10. * Written by: Eliezer Tamir
  11. * Based on code from Michael Chan's bnx2 driver
  12. * UDP CSUM errata workaround by Arik Gendelman
  13. * Slowpath and fastpath rework by Vladislav Zolotarov
  14. * Statistics and Link management by Yitchak Gertner
  15. *
  16. */
  17. #include "bnx2x_stats.h"
  18. #include "bnx2x_cmn.h"
  19. /* Statistics */
  20. /*
  21. * General service functions
  22. */
  23. static inline long bnx2x_hilo(u32 *hiref)
  24. {
  25. u32 lo = *(hiref + 1);
  26. #if (BITS_PER_LONG == 64)
  27. u32 hi = *hiref;
  28. return HILO_U64(hi, lo);
  29. #else
  30. return lo;
  31. #endif
  32. }
  33. /*
  34. * Init service functions
  35. */
  36. /* Post the next statistics ramrod. Protect it with the spin in
  37. * order to ensure the strict order between statistics ramrods
  38. * (each ramrod has a sequence number passed in a
  39. * bp->fw_stats_req->hdr.drv_stats_counter and ramrods must be
  40. * sent in order).
  41. */
  42. static void bnx2x_storm_stats_post(struct bnx2x *bp)
  43. {
  44. if (!bp->stats_pending) {
  45. int rc;
  46. spin_lock_bh(&bp->stats_lock);
  47. if (bp->stats_pending) {
  48. spin_unlock_bh(&bp->stats_lock);
  49. return;
  50. }
  51. bp->fw_stats_req->hdr.drv_stats_counter =
  52. cpu_to_le16(bp->stats_counter++);
  53. DP(NETIF_MSG_TIMER, "Sending statistics ramrod %d\n",
  54. bp->fw_stats_req->hdr.drv_stats_counter);
  55. /* send FW stats ramrod */
  56. rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_STAT_QUERY, 0,
  57. U64_HI(bp->fw_stats_req_mapping),
  58. U64_LO(bp->fw_stats_req_mapping),
  59. NONE_CONNECTION_TYPE);
  60. if (rc == 0)
  61. bp->stats_pending = 1;
  62. spin_unlock_bh(&bp->stats_lock);
  63. }
  64. }
  65. static void bnx2x_hw_stats_post(struct bnx2x *bp)
  66. {
  67. struct dmae_command *dmae = &bp->stats_dmae;
  68. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  69. *stats_comp = DMAE_COMP_VAL;
  70. if (CHIP_REV_IS_SLOW(bp))
  71. return;
  72. /* loader */
  73. if (bp->executer_idx) {
  74. int loader_idx = PMF_DMAE_C(bp);
  75. u32 opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC,
  76. true, DMAE_COMP_GRC);
  77. opcode = bnx2x_dmae_opcode_clr_src_reset(opcode);
  78. memset(dmae, 0, sizeof(struct dmae_command));
  79. dmae->opcode = opcode;
  80. dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, dmae[0]));
  81. dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, dmae[0]));
  82. dmae->dst_addr_lo = (DMAE_REG_CMD_MEM +
  83. sizeof(struct dmae_command) *
  84. (loader_idx + 1)) >> 2;
  85. dmae->dst_addr_hi = 0;
  86. dmae->len = sizeof(struct dmae_command) >> 2;
  87. if (CHIP_IS_E1(bp))
  88. dmae->len--;
  89. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx + 1] >> 2;
  90. dmae->comp_addr_hi = 0;
  91. dmae->comp_val = 1;
  92. *stats_comp = 0;
  93. bnx2x_post_dmae(bp, dmae, loader_idx);
  94. } else if (bp->func_stx) {
  95. *stats_comp = 0;
  96. bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
  97. }
  98. }
  99. static int bnx2x_stats_comp(struct bnx2x *bp)
  100. {
  101. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  102. int cnt = 10;
  103. might_sleep();
  104. while (*stats_comp != DMAE_COMP_VAL) {
  105. if (!cnt) {
  106. BNX2X_ERR("timeout waiting for stats finished\n");
  107. break;
  108. }
  109. cnt--;
  110. usleep_range(1000, 1000);
  111. }
  112. return 1;
  113. }
  114. /*
  115. * Statistics service functions
  116. */
  117. static void bnx2x_stats_pmf_update(struct bnx2x *bp)
  118. {
  119. struct dmae_command *dmae;
  120. u32 opcode;
  121. int loader_idx = PMF_DMAE_C(bp);
  122. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  123. /* sanity */
  124. if (!IS_MF(bp) || !bp->port.pmf || !bp->port.port_stx) {
  125. BNX2X_ERR("BUG!\n");
  126. return;
  127. }
  128. bp->executer_idx = 0;
  129. opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_GRC, DMAE_DST_PCI, false, 0);
  130. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  131. dmae->opcode = bnx2x_dmae_opcode_add_comp(opcode, DMAE_COMP_GRC);
  132. dmae->src_addr_lo = bp->port.port_stx >> 2;
  133. dmae->src_addr_hi = 0;
  134. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
  135. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
  136. dmae->len = DMAE_LEN32_RD_MAX;
  137. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  138. dmae->comp_addr_hi = 0;
  139. dmae->comp_val = 1;
  140. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  141. dmae->opcode = bnx2x_dmae_opcode_add_comp(opcode, DMAE_COMP_PCI);
  142. dmae->src_addr_lo = (bp->port.port_stx >> 2) + DMAE_LEN32_RD_MAX;
  143. dmae->src_addr_hi = 0;
  144. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats) +
  145. DMAE_LEN32_RD_MAX * 4);
  146. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats) +
  147. DMAE_LEN32_RD_MAX * 4);
  148. dmae->len = (sizeof(struct host_port_stats) >> 2) - DMAE_LEN32_RD_MAX;
  149. dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
  150. dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
  151. dmae->comp_val = DMAE_COMP_VAL;
  152. *stats_comp = 0;
  153. bnx2x_hw_stats_post(bp);
  154. bnx2x_stats_comp(bp);
  155. }
  156. static void bnx2x_port_stats_init(struct bnx2x *bp)
  157. {
  158. struct dmae_command *dmae;
  159. int port = BP_PORT(bp);
  160. u32 opcode;
  161. int loader_idx = PMF_DMAE_C(bp);
  162. u32 mac_addr;
  163. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  164. /* sanity */
  165. if (!bp->link_vars.link_up || !bp->port.pmf) {
  166. BNX2X_ERR("BUG!\n");
  167. return;
  168. }
  169. bp->executer_idx = 0;
  170. /* MCP */
  171. opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC,
  172. true, DMAE_COMP_GRC);
  173. if (bp->port.port_stx) {
  174. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  175. dmae->opcode = opcode;
  176. dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
  177. dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
  178. dmae->dst_addr_lo = bp->port.port_stx >> 2;
  179. dmae->dst_addr_hi = 0;
  180. dmae->len = sizeof(struct host_port_stats) >> 2;
  181. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  182. dmae->comp_addr_hi = 0;
  183. dmae->comp_val = 1;
  184. }
  185. if (bp->func_stx) {
  186. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  187. dmae->opcode = opcode;
  188. dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
  189. dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
  190. dmae->dst_addr_lo = bp->func_stx >> 2;
  191. dmae->dst_addr_hi = 0;
  192. dmae->len = sizeof(struct host_func_stats) >> 2;
  193. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  194. dmae->comp_addr_hi = 0;
  195. dmae->comp_val = 1;
  196. }
  197. /* MAC */
  198. opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_GRC, DMAE_DST_PCI,
  199. true, DMAE_COMP_GRC);
  200. /* EMAC is special */
  201. if (bp->link_vars.mac_type == MAC_TYPE_EMAC) {
  202. mac_addr = (port ? GRCBASE_EMAC1 : GRCBASE_EMAC0);
  203. /* EMAC_REG_EMAC_RX_STAT_AC (EMAC_REG_EMAC_RX_STAT_AC_COUNT)*/
  204. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  205. dmae->opcode = opcode;
  206. dmae->src_addr_lo = (mac_addr +
  207. EMAC_REG_EMAC_RX_STAT_AC) >> 2;
  208. dmae->src_addr_hi = 0;
  209. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
  210. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
  211. dmae->len = EMAC_REG_EMAC_RX_STAT_AC_COUNT;
  212. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  213. dmae->comp_addr_hi = 0;
  214. dmae->comp_val = 1;
  215. /* EMAC_REG_EMAC_RX_STAT_AC_28 */
  216. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  217. dmae->opcode = opcode;
  218. dmae->src_addr_lo = (mac_addr +
  219. EMAC_REG_EMAC_RX_STAT_AC_28) >> 2;
  220. dmae->src_addr_hi = 0;
  221. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
  222. offsetof(struct emac_stats, rx_stat_falsecarriererrors));
  223. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
  224. offsetof(struct emac_stats, rx_stat_falsecarriererrors));
  225. dmae->len = 1;
  226. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  227. dmae->comp_addr_hi = 0;
  228. dmae->comp_val = 1;
  229. /* EMAC_REG_EMAC_TX_STAT_AC (EMAC_REG_EMAC_TX_STAT_AC_COUNT)*/
  230. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  231. dmae->opcode = opcode;
  232. dmae->src_addr_lo = (mac_addr +
  233. EMAC_REG_EMAC_TX_STAT_AC) >> 2;
  234. dmae->src_addr_hi = 0;
  235. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
  236. offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
  237. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
  238. offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
  239. dmae->len = EMAC_REG_EMAC_TX_STAT_AC_COUNT;
  240. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  241. dmae->comp_addr_hi = 0;
  242. dmae->comp_val = 1;
  243. } else {
  244. u32 tx_src_addr_lo, rx_src_addr_lo;
  245. u16 rx_len, tx_len;
  246. /* configure the params according to MAC type */
  247. switch (bp->link_vars.mac_type) {
  248. case MAC_TYPE_BMAC:
  249. mac_addr = (port ? NIG_REG_INGRESS_BMAC1_MEM :
  250. NIG_REG_INGRESS_BMAC0_MEM);
  251. /* BIGMAC_REGISTER_TX_STAT_GTPKT ..
  252. BIGMAC_REGISTER_TX_STAT_GTBYT */
  253. if (CHIP_IS_E1x(bp)) {
  254. tx_src_addr_lo = (mac_addr +
  255. BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
  256. tx_len = (8 + BIGMAC_REGISTER_TX_STAT_GTBYT -
  257. BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
  258. rx_src_addr_lo = (mac_addr +
  259. BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
  260. rx_len = (8 + BIGMAC_REGISTER_RX_STAT_GRIPJ -
  261. BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
  262. } else {
  263. tx_src_addr_lo = (mac_addr +
  264. BIGMAC2_REGISTER_TX_STAT_GTPOK) >> 2;
  265. tx_len = (8 + BIGMAC2_REGISTER_TX_STAT_GTBYT -
  266. BIGMAC2_REGISTER_TX_STAT_GTPOK) >> 2;
  267. rx_src_addr_lo = (mac_addr +
  268. BIGMAC2_REGISTER_RX_STAT_GR64) >> 2;
  269. rx_len = (8 + BIGMAC2_REGISTER_RX_STAT_GRIPJ -
  270. BIGMAC2_REGISTER_RX_STAT_GR64) >> 2;
  271. }
  272. break;
  273. case MAC_TYPE_UMAC: /* handled by MSTAT */
  274. case MAC_TYPE_XMAC: /* handled by MSTAT */
  275. default:
  276. mac_addr = port ? GRCBASE_MSTAT1 : GRCBASE_MSTAT0;
  277. tx_src_addr_lo = (mac_addr +
  278. MSTAT_REG_TX_STAT_GTXPOK_LO) >> 2;
  279. rx_src_addr_lo = (mac_addr +
  280. MSTAT_REG_RX_STAT_GR64_LO) >> 2;
  281. tx_len = sizeof(bp->slowpath->
  282. mac_stats.mstat_stats.stats_tx) >> 2;
  283. rx_len = sizeof(bp->slowpath->
  284. mac_stats.mstat_stats.stats_rx) >> 2;
  285. break;
  286. }
  287. /* TX stats */
  288. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  289. dmae->opcode = opcode;
  290. dmae->src_addr_lo = tx_src_addr_lo;
  291. dmae->src_addr_hi = 0;
  292. dmae->len = tx_len;
  293. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
  294. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
  295. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  296. dmae->comp_addr_hi = 0;
  297. dmae->comp_val = 1;
  298. /* RX stats */
  299. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  300. dmae->opcode = opcode;
  301. dmae->src_addr_hi = 0;
  302. dmae->src_addr_lo = rx_src_addr_lo;
  303. dmae->dst_addr_lo =
  304. U64_LO(bnx2x_sp_mapping(bp, mac_stats) + (tx_len << 2));
  305. dmae->dst_addr_hi =
  306. U64_HI(bnx2x_sp_mapping(bp, mac_stats) + (tx_len << 2));
  307. dmae->len = rx_len;
  308. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  309. dmae->comp_addr_hi = 0;
  310. dmae->comp_val = 1;
  311. }
  312. /* NIG */
  313. if (!CHIP_IS_E3(bp)) {
  314. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  315. dmae->opcode = opcode;
  316. dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT0 :
  317. NIG_REG_STAT0_EGRESS_MAC_PKT0) >> 2;
  318. dmae->src_addr_hi = 0;
  319. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
  320. offsetof(struct nig_stats, egress_mac_pkt0_lo));
  321. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
  322. offsetof(struct nig_stats, egress_mac_pkt0_lo));
  323. dmae->len = (2*sizeof(u32)) >> 2;
  324. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  325. dmae->comp_addr_hi = 0;
  326. dmae->comp_val = 1;
  327. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  328. dmae->opcode = opcode;
  329. dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT1 :
  330. NIG_REG_STAT0_EGRESS_MAC_PKT1) >> 2;
  331. dmae->src_addr_hi = 0;
  332. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
  333. offsetof(struct nig_stats, egress_mac_pkt1_lo));
  334. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
  335. offsetof(struct nig_stats, egress_mac_pkt1_lo));
  336. dmae->len = (2*sizeof(u32)) >> 2;
  337. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  338. dmae->comp_addr_hi = 0;
  339. dmae->comp_val = 1;
  340. }
  341. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  342. dmae->opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_GRC, DMAE_DST_PCI,
  343. true, DMAE_COMP_PCI);
  344. dmae->src_addr_lo = (port ? NIG_REG_STAT1_BRB_DISCARD :
  345. NIG_REG_STAT0_BRB_DISCARD) >> 2;
  346. dmae->src_addr_hi = 0;
  347. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats));
  348. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats));
  349. dmae->len = (sizeof(struct nig_stats) - 4*sizeof(u32)) >> 2;
  350. dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
  351. dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
  352. dmae->comp_val = DMAE_COMP_VAL;
  353. *stats_comp = 0;
  354. }
  355. static void bnx2x_func_stats_init(struct bnx2x *bp)
  356. {
  357. struct dmae_command *dmae = &bp->stats_dmae;
  358. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  359. /* sanity */
  360. if (!bp->func_stx) {
  361. BNX2X_ERR("BUG!\n");
  362. return;
  363. }
  364. bp->executer_idx = 0;
  365. memset(dmae, 0, sizeof(struct dmae_command));
  366. dmae->opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC,
  367. true, DMAE_COMP_PCI);
  368. dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
  369. dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
  370. dmae->dst_addr_lo = bp->func_stx >> 2;
  371. dmae->dst_addr_hi = 0;
  372. dmae->len = sizeof(struct host_func_stats) >> 2;
  373. dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
  374. dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
  375. dmae->comp_val = DMAE_COMP_VAL;
  376. *stats_comp = 0;
  377. }
  378. static void bnx2x_stats_start(struct bnx2x *bp)
  379. {
  380. if (bp->port.pmf)
  381. bnx2x_port_stats_init(bp);
  382. else if (bp->func_stx)
  383. bnx2x_func_stats_init(bp);
  384. bnx2x_hw_stats_post(bp);
  385. bnx2x_storm_stats_post(bp);
  386. }
  387. static void bnx2x_stats_pmf_start(struct bnx2x *bp)
  388. {
  389. bnx2x_stats_comp(bp);
  390. bnx2x_stats_pmf_update(bp);
  391. bnx2x_stats_start(bp);
  392. }
  393. static void bnx2x_stats_restart(struct bnx2x *bp)
  394. {
  395. bnx2x_stats_comp(bp);
  396. bnx2x_stats_start(bp);
  397. }
  398. static void bnx2x_bmac_stats_update(struct bnx2x *bp)
  399. {
  400. struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
  401. struct bnx2x_eth_stats *estats = &bp->eth_stats;
  402. struct {
  403. u32 lo;
  404. u32 hi;
  405. } diff;
  406. if (CHIP_IS_E1x(bp)) {
  407. struct bmac1_stats *new = bnx2x_sp(bp, mac_stats.bmac1_stats);
  408. /* the macros below will use "bmac1_stats" type */
  409. UPDATE_STAT64(rx_stat_grerb, rx_stat_ifhcinbadoctets);
  410. UPDATE_STAT64(rx_stat_grfcs, rx_stat_dot3statsfcserrors);
  411. UPDATE_STAT64(rx_stat_grund, rx_stat_etherstatsundersizepkts);
  412. UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong);
  413. UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments);
  414. UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers);
  415. UPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived);
  416. UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered);
  417. UPDATE_STAT64(rx_stat_grxpf, rx_stat_mac_xpf);
  418. UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent);
  419. UPDATE_STAT64(tx_stat_gtxpf, tx_stat_flowcontroldone);
  420. UPDATE_STAT64(tx_stat_gt64, tx_stat_etherstatspkts64octets);
  421. UPDATE_STAT64(tx_stat_gt127,
  422. tx_stat_etherstatspkts65octetsto127octets);
  423. UPDATE_STAT64(tx_stat_gt255,
  424. tx_stat_etherstatspkts128octetsto255octets);
  425. UPDATE_STAT64(tx_stat_gt511,
  426. tx_stat_etherstatspkts256octetsto511octets);
  427. UPDATE_STAT64(tx_stat_gt1023,
  428. tx_stat_etherstatspkts512octetsto1023octets);
  429. UPDATE_STAT64(tx_stat_gt1518,
  430. tx_stat_etherstatspkts1024octetsto1522octets);
  431. UPDATE_STAT64(tx_stat_gt2047, tx_stat_mac_2047);
  432. UPDATE_STAT64(tx_stat_gt4095, tx_stat_mac_4095);
  433. UPDATE_STAT64(tx_stat_gt9216, tx_stat_mac_9216);
  434. UPDATE_STAT64(tx_stat_gt16383, tx_stat_mac_16383);
  435. UPDATE_STAT64(tx_stat_gterr,
  436. tx_stat_dot3statsinternalmactransmiterrors);
  437. UPDATE_STAT64(tx_stat_gtufl, tx_stat_mac_ufl);
  438. } else {
  439. struct bmac2_stats *new = bnx2x_sp(bp, mac_stats.bmac2_stats);
  440. /* the macros below will use "bmac2_stats" type */
  441. UPDATE_STAT64(rx_stat_grerb, rx_stat_ifhcinbadoctets);
  442. UPDATE_STAT64(rx_stat_grfcs, rx_stat_dot3statsfcserrors);
  443. UPDATE_STAT64(rx_stat_grund, rx_stat_etherstatsundersizepkts);
  444. UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong);
  445. UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments);
  446. UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers);
  447. UPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived);
  448. UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered);
  449. UPDATE_STAT64(rx_stat_grxpf, rx_stat_mac_xpf);
  450. UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent);
  451. UPDATE_STAT64(tx_stat_gtxpf, tx_stat_flowcontroldone);
  452. UPDATE_STAT64(tx_stat_gt64, tx_stat_etherstatspkts64octets);
  453. UPDATE_STAT64(tx_stat_gt127,
  454. tx_stat_etherstatspkts65octetsto127octets);
  455. UPDATE_STAT64(tx_stat_gt255,
  456. tx_stat_etherstatspkts128octetsto255octets);
  457. UPDATE_STAT64(tx_stat_gt511,
  458. tx_stat_etherstatspkts256octetsto511octets);
  459. UPDATE_STAT64(tx_stat_gt1023,
  460. tx_stat_etherstatspkts512octetsto1023octets);
  461. UPDATE_STAT64(tx_stat_gt1518,
  462. tx_stat_etherstatspkts1024octetsto1522octets);
  463. UPDATE_STAT64(tx_stat_gt2047, tx_stat_mac_2047);
  464. UPDATE_STAT64(tx_stat_gt4095, tx_stat_mac_4095);
  465. UPDATE_STAT64(tx_stat_gt9216, tx_stat_mac_9216);
  466. UPDATE_STAT64(tx_stat_gt16383, tx_stat_mac_16383);
  467. UPDATE_STAT64(tx_stat_gterr,
  468. tx_stat_dot3statsinternalmactransmiterrors);
  469. UPDATE_STAT64(tx_stat_gtufl, tx_stat_mac_ufl);
  470. }
  471. estats->pause_frames_received_hi =
  472. pstats->mac_stx[1].rx_stat_mac_xpf_hi;
  473. estats->pause_frames_received_lo =
  474. pstats->mac_stx[1].rx_stat_mac_xpf_lo;
  475. estats->pause_frames_sent_hi =
  476. pstats->mac_stx[1].tx_stat_outxoffsent_hi;
  477. estats->pause_frames_sent_lo =
  478. pstats->mac_stx[1].tx_stat_outxoffsent_lo;
  479. }
  480. static void bnx2x_mstat_stats_update(struct bnx2x *bp)
  481. {
  482. struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
  483. struct bnx2x_eth_stats *estats = &bp->eth_stats;
  484. struct mstat_stats *new = bnx2x_sp(bp, mac_stats.mstat_stats);
  485. ADD_STAT64(stats_rx.rx_grerb, rx_stat_ifhcinbadoctets);
  486. ADD_STAT64(stats_rx.rx_grfcs, rx_stat_dot3statsfcserrors);
  487. ADD_STAT64(stats_rx.rx_grund, rx_stat_etherstatsundersizepkts);
  488. ADD_STAT64(stats_rx.rx_grovr, rx_stat_dot3statsframestoolong);
  489. ADD_STAT64(stats_rx.rx_grfrg, rx_stat_etherstatsfragments);
  490. ADD_STAT64(stats_rx.rx_grxcf, rx_stat_maccontrolframesreceived);
  491. ADD_STAT64(stats_rx.rx_grxpf, rx_stat_xoffstateentered);
  492. ADD_STAT64(stats_rx.rx_grxpf, rx_stat_mac_xpf);
  493. ADD_STAT64(stats_tx.tx_gtxpf, tx_stat_outxoffsent);
  494. ADD_STAT64(stats_tx.tx_gtxpf, tx_stat_flowcontroldone);
  495. ADD_STAT64(stats_tx.tx_gt64, tx_stat_etherstatspkts64octets);
  496. ADD_STAT64(stats_tx.tx_gt127,
  497. tx_stat_etherstatspkts65octetsto127octets);
  498. ADD_STAT64(stats_tx.tx_gt255,
  499. tx_stat_etherstatspkts128octetsto255octets);
  500. ADD_STAT64(stats_tx.tx_gt511,
  501. tx_stat_etherstatspkts256octetsto511octets);
  502. ADD_STAT64(stats_tx.tx_gt1023,
  503. tx_stat_etherstatspkts512octetsto1023octets);
  504. ADD_STAT64(stats_tx.tx_gt1518,
  505. tx_stat_etherstatspkts1024octetsto1522octets);
  506. ADD_STAT64(stats_tx.tx_gt2047, tx_stat_mac_2047);
  507. ADD_STAT64(stats_tx.tx_gt4095, tx_stat_mac_4095);
  508. ADD_STAT64(stats_tx.tx_gt9216, tx_stat_mac_9216);
  509. ADD_STAT64(stats_tx.tx_gt16383, tx_stat_mac_16383);
  510. ADD_STAT64(stats_tx.tx_gterr,
  511. tx_stat_dot3statsinternalmactransmiterrors);
  512. ADD_STAT64(stats_tx.tx_gtufl, tx_stat_mac_ufl);
  513. ADD_64(estats->etherstatspkts1024octetsto1522octets_hi,
  514. new->stats_tx.tx_gt1518_hi,
  515. estats->etherstatspkts1024octetsto1522octets_lo,
  516. new->stats_tx.tx_gt1518_lo);
  517. ADD_64(estats->etherstatspktsover1522octets_hi,
  518. new->stats_tx.tx_gt2047_hi,
  519. estats->etherstatspktsover1522octets_lo,
  520. new->stats_tx.tx_gt2047_lo);
  521. ADD_64(estats->etherstatspktsover1522octets_hi,
  522. new->stats_tx.tx_gt4095_hi,
  523. estats->etherstatspktsover1522octets_lo,
  524. new->stats_tx.tx_gt4095_lo);
  525. ADD_64(estats->etherstatspktsover1522octets_hi,
  526. new->stats_tx.tx_gt9216_hi,
  527. estats->etherstatspktsover1522octets_lo,
  528. new->stats_tx.tx_gt9216_lo);
  529. ADD_64(estats->etherstatspktsover1522octets_hi,
  530. new->stats_tx.tx_gt16383_hi,
  531. estats->etherstatspktsover1522octets_lo,
  532. new->stats_tx.tx_gt16383_lo);
  533. estats->pause_frames_received_hi =
  534. pstats->mac_stx[1].rx_stat_mac_xpf_hi;
  535. estats->pause_frames_received_lo =
  536. pstats->mac_stx[1].rx_stat_mac_xpf_lo;
  537. estats->pause_frames_sent_hi =
  538. pstats->mac_stx[1].tx_stat_outxoffsent_hi;
  539. estats->pause_frames_sent_lo =
  540. pstats->mac_stx[1].tx_stat_outxoffsent_lo;
  541. }
  542. static void bnx2x_emac_stats_update(struct bnx2x *bp)
  543. {
  544. struct emac_stats *new = bnx2x_sp(bp, mac_stats.emac_stats);
  545. struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
  546. struct bnx2x_eth_stats *estats = &bp->eth_stats;
  547. UPDATE_EXTEND_STAT(rx_stat_ifhcinbadoctets);
  548. UPDATE_EXTEND_STAT(tx_stat_ifhcoutbadoctets);
  549. UPDATE_EXTEND_STAT(rx_stat_dot3statsfcserrors);
  550. UPDATE_EXTEND_STAT(rx_stat_dot3statsalignmenterrors);
  551. UPDATE_EXTEND_STAT(rx_stat_dot3statscarriersenseerrors);
  552. UPDATE_EXTEND_STAT(rx_stat_falsecarriererrors);
  553. UPDATE_EXTEND_STAT(rx_stat_etherstatsundersizepkts);
  554. UPDATE_EXTEND_STAT(rx_stat_dot3statsframestoolong);
  555. UPDATE_EXTEND_STAT(rx_stat_etherstatsfragments);
  556. UPDATE_EXTEND_STAT(rx_stat_etherstatsjabbers);
  557. UPDATE_EXTEND_STAT(rx_stat_maccontrolframesreceived);
  558. UPDATE_EXTEND_STAT(rx_stat_xoffstateentered);
  559. UPDATE_EXTEND_STAT(rx_stat_xonpauseframesreceived);
  560. UPDATE_EXTEND_STAT(rx_stat_xoffpauseframesreceived);
  561. UPDATE_EXTEND_STAT(tx_stat_outxonsent);
  562. UPDATE_EXTEND_STAT(tx_stat_outxoffsent);
  563. UPDATE_EXTEND_STAT(tx_stat_flowcontroldone);
  564. UPDATE_EXTEND_STAT(tx_stat_etherstatscollisions);
  565. UPDATE_EXTEND_STAT(tx_stat_dot3statssinglecollisionframes);
  566. UPDATE_EXTEND_STAT(tx_stat_dot3statsmultiplecollisionframes);
  567. UPDATE_EXTEND_STAT(tx_stat_dot3statsdeferredtransmissions);
  568. UPDATE_EXTEND_STAT(tx_stat_dot3statsexcessivecollisions);
  569. UPDATE_EXTEND_STAT(tx_stat_dot3statslatecollisions);
  570. UPDATE_EXTEND_STAT(tx_stat_etherstatspkts64octets);
  571. UPDATE_EXTEND_STAT(tx_stat_etherstatspkts65octetsto127octets);
  572. UPDATE_EXTEND_STAT(tx_stat_etherstatspkts128octetsto255octets);
  573. UPDATE_EXTEND_STAT(tx_stat_etherstatspkts256octetsto511octets);
  574. UPDATE_EXTEND_STAT(tx_stat_etherstatspkts512octetsto1023octets);
  575. UPDATE_EXTEND_STAT(tx_stat_etherstatspkts1024octetsto1522octets);
  576. UPDATE_EXTEND_STAT(tx_stat_etherstatspktsover1522octets);
  577. UPDATE_EXTEND_STAT(tx_stat_dot3statsinternalmactransmiterrors);
  578. estats->pause_frames_received_hi =
  579. pstats->mac_stx[1].rx_stat_xonpauseframesreceived_hi;
  580. estats->pause_frames_received_lo =
  581. pstats->mac_stx[1].rx_stat_xonpauseframesreceived_lo;
  582. ADD_64(estats->pause_frames_received_hi,
  583. pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_hi,
  584. estats->pause_frames_received_lo,
  585. pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_lo);
  586. estats->pause_frames_sent_hi =
  587. pstats->mac_stx[1].tx_stat_outxonsent_hi;
  588. estats->pause_frames_sent_lo =
  589. pstats->mac_stx[1].tx_stat_outxonsent_lo;
  590. ADD_64(estats->pause_frames_sent_hi,
  591. pstats->mac_stx[1].tx_stat_outxoffsent_hi,
  592. estats->pause_frames_sent_lo,
  593. pstats->mac_stx[1].tx_stat_outxoffsent_lo);
  594. }
  595. static int bnx2x_hw_stats_update(struct bnx2x *bp)
  596. {
  597. struct nig_stats *new = bnx2x_sp(bp, nig_stats);
  598. struct nig_stats *old = &(bp->port.old_nig_stats);
  599. struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
  600. struct bnx2x_eth_stats *estats = &bp->eth_stats;
  601. struct {
  602. u32 lo;
  603. u32 hi;
  604. } diff;
  605. switch (bp->link_vars.mac_type) {
  606. case MAC_TYPE_BMAC:
  607. bnx2x_bmac_stats_update(bp);
  608. break;
  609. case MAC_TYPE_EMAC:
  610. bnx2x_emac_stats_update(bp);
  611. break;
  612. case MAC_TYPE_UMAC:
  613. case MAC_TYPE_XMAC:
  614. bnx2x_mstat_stats_update(bp);
  615. break;
  616. case MAC_TYPE_NONE: /* unreached */
  617. DP(BNX2X_MSG_STATS,
  618. "stats updated by DMAE but no MAC active\n");
  619. return -1;
  620. default: /* unreached */
  621. BNX2X_ERR("Unknown MAC type\n");
  622. }
  623. ADD_EXTEND_64(pstats->brb_drop_hi, pstats->brb_drop_lo,
  624. new->brb_discard - old->brb_discard);
  625. ADD_EXTEND_64(estats->brb_truncate_hi, estats->brb_truncate_lo,
  626. new->brb_truncate - old->brb_truncate);
  627. if (!CHIP_IS_E3(bp)) {
  628. UPDATE_STAT64_NIG(egress_mac_pkt0,
  629. etherstatspkts1024octetsto1522octets);
  630. UPDATE_STAT64_NIG(egress_mac_pkt1,
  631. etherstatspktsover1522octets);
  632. }
  633. memcpy(old, new, sizeof(struct nig_stats));
  634. memcpy(&(estats->rx_stat_ifhcinbadoctets_hi), &(pstats->mac_stx[1]),
  635. sizeof(struct mac_stx));
  636. estats->brb_drop_hi = pstats->brb_drop_hi;
  637. estats->brb_drop_lo = pstats->brb_drop_lo;
  638. pstats->host_port_stats_start = ++pstats->host_port_stats_end;
  639. if (!BP_NOMCP(bp)) {
  640. u32 nig_timer_max =
  641. SHMEM_RD(bp, port_mb[BP_PORT(bp)].stat_nig_timer);
  642. if (nig_timer_max != estats->nig_timer_max) {
  643. estats->nig_timer_max = nig_timer_max;
  644. BNX2X_ERR("NIG timer max (%u)\n",
  645. estats->nig_timer_max);
  646. }
  647. }
  648. return 0;
  649. }
  650. static int bnx2x_storm_stats_update(struct bnx2x *bp)
  651. {
  652. struct tstorm_per_port_stats *tport =
  653. &bp->fw_stats_data->port.tstorm_port_statistics;
  654. struct tstorm_per_pf_stats *tfunc =
  655. &bp->fw_stats_data->pf.tstorm_pf_statistics;
  656. struct host_func_stats *fstats = bnx2x_sp(bp, func_stats);
  657. struct bnx2x_eth_stats *estats = &bp->eth_stats;
  658. struct stats_counter *counters = &bp->fw_stats_data->storm_counters;
  659. int i;
  660. u16 cur_stats_counter;
  661. /* Make sure we use the value of the counter
  662. * used for sending the last stats ramrod.
  663. */
  664. spin_lock_bh(&bp->stats_lock);
  665. cur_stats_counter = bp->stats_counter - 1;
  666. spin_unlock_bh(&bp->stats_lock);
  667. /* are storm stats valid? */
  668. if (le16_to_cpu(counters->xstats_counter) != cur_stats_counter) {
  669. DP(BNX2X_MSG_STATS, "stats not updated by xstorm"
  670. " xstorm counter (0x%x) != stats_counter (0x%x)\n",
  671. le16_to_cpu(counters->xstats_counter), bp->stats_counter);
  672. return -EAGAIN;
  673. }
  674. if (le16_to_cpu(counters->ustats_counter) != cur_stats_counter) {
  675. DP(BNX2X_MSG_STATS, "stats not updated by ustorm"
  676. " ustorm counter (0x%x) != stats_counter (0x%x)\n",
  677. le16_to_cpu(counters->ustats_counter), bp->stats_counter);
  678. return -EAGAIN;
  679. }
  680. if (le16_to_cpu(counters->cstats_counter) != cur_stats_counter) {
  681. DP(BNX2X_MSG_STATS, "stats not updated by cstorm"
  682. " cstorm counter (0x%x) != stats_counter (0x%x)\n",
  683. le16_to_cpu(counters->cstats_counter), bp->stats_counter);
  684. return -EAGAIN;
  685. }
  686. if (le16_to_cpu(counters->tstats_counter) != cur_stats_counter) {
  687. DP(BNX2X_MSG_STATS, "stats not updated by tstorm"
  688. " tstorm counter (0x%x) != stats_counter (0x%x)\n",
  689. le16_to_cpu(counters->tstats_counter), bp->stats_counter);
  690. return -EAGAIN;
  691. }
  692. memcpy(&(fstats->total_bytes_received_hi),
  693. &(bnx2x_sp(bp, func_stats_base)->total_bytes_received_hi),
  694. sizeof(struct host_func_stats) - 2*sizeof(u32));
  695. estats->error_bytes_received_hi = 0;
  696. estats->error_bytes_received_lo = 0;
  697. estats->etherstatsoverrsizepkts_hi = 0;
  698. estats->etherstatsoverrsizepkts_lo = 0;
  699. estats->no_buff_discard_hi = 0;
  700. estats->no_buff_discard_lo = 0;
  701. estats->total_tpa_aggregations_hi = 0;
  702. estats->total_tpa_aggregations_lo = 0;
  703. estats->total_tpa_aggregated_frames_hi = 0;
  704. estats->total_tpa_aggregated_frames_lo = 0;
  705. estats->total_tpa_bytes_hi = 0;
  706. estats->total_tpa_bytes_lo = 0;
  707. for_each_eth_queue(bp, i) {
  708. struct bnx2x_fastpath *fp = &bp->fp[i];
  709. struct tstorm_per_queue_stats *tclient =
  710. &bp->fw_stats_data->queue_stats[i].
  711. tstorm_queue_statistics;
  712. struct tstorm_per_queue_stats *old_tclient = &fp->old_tclient;
  713. struct ustorm_per_queue_stats *uclient =
  714. &bp->fw_stats_data->queue_stats[i].
  715. ustorm_queue_statistics;
  716. struct ustorm_per_queue_stats *old_uclient = &fp->old_uclient;
  717. struct xstorm_per_queue_stats *xclient =
  718. &bp->fw_stats_data->queue_stats[i].
  719. xstorm_queue_statistics;
  720. struct xstorm_per_queue_stats *old_xclient = &fp->old_xclient;
  721. struct bnx2x_eth_q_stats *qstats = &fp->eth_q_stats;
  722. u32 diff;
  723. DP(BNX2X_MSG_STATS, "queue[%d]: ucast_sent 0x%x, "
  724. "bcast_sent 0x%x mcast_sent 0x%x\n",
  725. i, xclient->ucast_pkts_sent,
  726. xclient->bcast_pkts_sent, xclient->mcast_pkts_sent);
  727. DP(BNX2X_MSG_STATS, "---------------\n");
  728. qstats->total_broadcast_bytes_received_hi =
  729. le32_to_cpu(tclient->rcv_bcast_bytes.hi);
  730. qstats->total_broadcast_bytes_received_lo =
  731. le32_to_cpu(tclient->rcv_bcast_bytes.lo);
  732. qstats->total_multicast_bytes_received_hi =
  733. le32_to_cpu(tclient->rcv_mcast_bytes.hi);
  734. qstats->total_multicast_bytes_received_lo =
  735. le32_to_cpu(tclient->rcv_mcast_bytes.lo);
  736. qstats->total_unicast_bytes_received_hi =
  737. le32_to_cpu(tclient->rcv_ucast_bytes.hi);
  738. qstats->total_unicast_bytes_received_lo =
  739. le32_to_cpu(tclient->rcv_ucast_bytes.lo);
  740. /*
  741. * sum to total_bytes_received all
  742. * unicast/multicast/broadcast
  743. */
  744. qstats->total_bytes_received_hi =
  745. qstats->total_broadcast_bytes_received_hi;
  746. qstats->total_bytes_received_lo =
  747. qstats->total_broadcast_bytes_received_lo;
  748. ADD_64(qstats->total_bytes_received_hi,
  749. qstats->total_multicast_bytes_received_hi,
  750. qstats->total_bytes_received_lo,
  751. qstats->total_multicast_bytes_received_lo);
  752. ADD_64(qstats->total_bytes_received_hi,
  753. qstats->total_unicast_bytes_received_hi,
  754. qstats->total_bytes_received_lo,
  755. qstats->total_unicast_bytes_received_lo);
  756. qstats->valid_bytes_received_hi =
  757. qstats->total_bytes_received_hi;
  758. qstats->valid_bytes_received_lo =
  759. qstats->total_bytes_received_lo;
  760. UPDATE_EXTEND_TSTAT(rcv_ucast_pkts,
  761. total_unicast_packets_received);
  762. UPDATE_EXTEND_TSTAT(rcv_mcast_pkts,
  763. total_multicast_packets_received);
  764. UPDATE_EXTEND_TSTAT(rcv_bcast_pkts,
  765. total_broadcast_packets_received);
  766. UPDATE_EXTEND_TSTAT(pkts_too_big_discard,
  767. etherstatsoverrsizepkts);
  768. UPDATE_EXTEND_TSTAT(no_buff_discard, no_buff_discard);
  769. SUB_EXTEND_USTAT(ucast_no_buff_pkts,
  770. total_unicast_packets_received);
  771. SUB_EXTEND_USTAT(mcast_no_buff_pkts,
  772. total_multicast_packets_received);
  773. SUB_EXTEND_USTAT(bcast_no_buff_pkts,
  774. total_broadcast_packets_received);
  775. UPDATE_EXTEND_USTAT(ucast_no_buff_pkts, no_buff_discard);
  776. UPDATE_EXTEND_USTAT(mcast_no_buff_pkts, no_buff_discard);
  777. UPDATE_EXTEND_USTAT(bcast_no_buff_pkts, no_buff_discard);
  778. qstats->total_broadcast_bytes_transmitted_hi =
  779. le32_to_cpu(xclient->bcast_bytes_sent.hi);
  780. qstats->total_broadcast_bytes_transmitted_lo =
  781. le32_to_cpu(xclient->bcast_bytes_sent.lo);
  782. qstats->total_multicast_bytes_transmitted_hi =
  783. le32_to_cpu(xclient->mcast_bytes_sent.hi);
  784. qstats->total_multicast_bytes_transmitted_lo =
  785. le32_to_cpu(xclient->mcast_bytes_sent.lo);
  786. qstats->total_unicast_bytes_transmitted_hi =
  787. le32_to_cpu(xclient->ucast_bytes_sent.hi);
  788. qstats->total_unicast_bytes_transmitted_lo =
  789. le32_to_cpu(xclient->ucast_bytes_sent.lo);
  790. /*
  791. * sum to total_bytes_transmitted all
  792. * unicast/multicast/broadcast
  793. */
  794. qstats->total_bytes_transmitted_hi =
  795. qstats->total_unicast_bytes_transmitted_hi;
  796. qstats->total_bytes_transmitted_lo =
  797. qstats->total_unicast_bytes_transmitted_lo;
  798. ADD_64(qstats->total_bytes_transmitted_hi,
  799. qstats->total_broadcast_bytes_transmitted_hi,
  800. qstats->total_bytes_transmitted_lo,
  801. qstats->total_broadcast_bytes_transmitted_lo);
  802. ADD_64(qstats->total_bytes_transmitted_hi,
  803. qstats->total_multicast_bytes_transmitted_hi,
  804. qstats->total_bytes_transmitted_lo,
  805. qstats->total_multicast_bytes_transmitted_lo);
  806. UPDATE_EXTEND_XSTAT(ucast_pkts_sent,
  807. total_unicast_packets_transmitted);
  808. UPDATE_EXTEND_XSTAT(mcast_pkts_sent,
  809. total_multicast_packets_transmitted);
  810. UPDATE_EXTEND_XSTAT(bcast_pkts_sent,
  811. total_broadcast_packets_transmitted);
  812. UPDATE_EXTEND_TSTAT(checksum_discard,
  813. total_packets_received_checksum_discarded);
  814. UPDATE_EXTEND_TSTAT(ttl0_discard,
  815. total_packets_received_ttl0_discarded);
  816. UPDATE_EXTEND_XSTAT(error_drop_pkts,
  817. total_transmitted_dropped_packets_error);
  818. /* TPA aggregations completed */
  819. UPDATE_EXTEND_USTAT(coalesced_events, total_tpa_aggregations);
  820. /* Number of network frames aggregated by TPA */
  821. UPDATE_EXTEND_USTAT(coalesced_pkts,
  822. total_tpa_aggregated_frames);
  823. /* Total number of bytes in completed TPA aggregations */
  824. qstats->total_tpa_bytes_lo =
  825. le32_to_cpu(uclient->coalesced_bytes.lo);
  826. qstats->total_tpa_bytes_hi =
  827. le32_to_cpu(uclient->coalesced_bytes.hi);
  828. /* TPA stats per-function */
  829. ADD_64(estats->total_tpa_aggregations_hi,
  830. qstats->total_tpa_aggregations_hi,
  831. estats->total_tpa_aggregations_lo,
  832. qstats->total_tpa_aggregations_lo);
  833. ADD_64(estats->total_tpa_aggregated_frames_hi,
  834. qstats->total_tpa_aggregated_frames_hi,
  835. estats->total_tpa_aggregated_frames_lo,
  836. qstats->total_tpa_aggregated_frames_lo);
  837. ADD_64(estats->total_tpa_bytes_hi,
  838. qstats->total_tpa_bytes_hi,
  839. estats->total_tpa_bytes_lo,
  840. qstats->total_tpa_bytes_lo);
  841. ADD_64(fstats->total_bytes_received_hi,
  842. qstats->total_bytes_received_hi,
  843. fstats->total_bytes_received_lo,
  844. qstats->total_bytes_received_lo);
  845. ADD_64(fstats->total_bytes_transmitted_hi,
  846. qstats->total_bytes_transmitted_hi,
  847. fstats->total_bytes_transmitted_lo,
  848. qstats->total_bytes_transmitted_lo);
  849. ADD_64(fstats->total_unicast_packets_received_hi,
  850. qstats->total_unicast_packets_received_hi,
  851. fstats->total_unicast_packets_received_lo,
  852. qstats->total_unicast_packets_received_lo);
  853. ADD_64(fstats->total_multicast_packets_received_hi,
  854. qstats->total_multicast_packets_received_hi,
  855. fstats->total_multicast_packets_received_lo,
  856. qstats->total_multicast_packets_received_lo);
  857. ADD_64(fstats->total_broadcast_packets_received_hi,
  858. qstats->total_broadcast_packets_received_hi,
  859. fstats->total_broadcast_packets_received_lo,
  860. qstats->total_broadcast_packets_received_lo);
  861. ADD_64(fstats->total_unicast_packets_transmitted_hi,
  862. qstats->total_unicast_packets_transmitted_hi,
  863. fstats->total_unicast_packets_transmitted_lo,
  864. qstats->total_unicast_packets_transmitted_lo);
  865. ADD_64(fstats->total_multicast_packets_transmitted_hi,
  866. qstats->total_multicast_packets_transmitted_hi,
  867. fstats->total_multicast_packets_transmitted_lo,
  868. qstats->total_multicast_packets_transmitted_lo);
  869. ADD_64(fstats->total_broadcast_packets_transmitted_hi,
  870. qstats->total_broadcast_packets_transmitted_hi,
  871. fstats->total_broadcast_packets_transmitted_lo,
  872. qstats->total_broadcast_packets_transmitted_lo);
  873. ADD_64(fstats->valid_bytes_received_hi,
  874. qstats->valid_bytes_received_hi,
  875. fstats->valid_bytes_received_lo,
  876. qstats->valid_bytes_received_lo);
  877. ADD_64(estats->etherstatsoverrsizepkts_hi,
  878. qstats->etherstatsoverrsizepkts_hi,
  879. estats->etherstatsoverrsizepkts_lo,
  880. qstats->etherstatsoverrsizepkts_lo);
  881. ADD_64(estats->no_buff_discard_hi, qstats->no_buff_discard_hi,
  882. estats->no_buff_discard_lo, qstats->no_buff_discard_lo);
  883. }
  884. ADD_64(fstats->total_bytes_received_hi,
  885. estats->rx_stat_ifhcinbadoctets_hi,
  886. fstats->total_bytes_received_lo,
  887. estats->rx_stat_ifhcinbadoctets_lo);
  888. ADD_64(fstats->total_bytes_received_hi,
  889. tfunc->rcv_error_bytes.hi,
  890. fstats->total_bytes_received_lo,
  891. tfunc->rcv_error_bytes.lo);
  892. memcpy(estats, &(fstats->total_bytes_received_hi),
  893. sizeof(struct host_func_stats) - 2*sizeof(u32));
  894. ADD_64(estats->error_bytes_received_hi,
  895. tfunc->rcv_error_bytes.hi,
  896. estats->error_bytes_received_lo,
  897. tfunc->rcv_error_bytes.lo);
  898. ADD_64(estats->etherstatsoverrsizepkts_hi,
  899. estats->rx_stat_dot3statsframestoolong_hi,
  900. estats->etherstatsoverrsizepkts_lo,
  901. estats->rx_stat_dot3statsframestoolong_lo);
  902. ADD_64(estats->error_bytes_received_hi,
  903. estats->rx_stat_ifhcinbadoctets_hi,
  904. estats->error_bytes_received_lo,
  905. estats->rx_stat_ifhcinbadoctets_lo);
  906. if (bp->port.pmf) {
  907. estats->mac_filter_discard =
  908. le32_to_cpu(tport->mac_filter_discard);
  909. estats->mf_tag_discard =
  910. le32_to_cpu(tport->mf_tag_discard);
  911. estats->brb_truncate_discard =
  912. le32_to_cpu(tport->brb_truncate_discard);
  913. estats->mac_discard = le32_to_cpu(tport->mac_discard);
  914. }
  915. fstats->host_func_stats_start = ++fstats->host_func_stats_end;
  916. bp->stats_pending = 0;
  917. return 0;
  918. }
  919. static void bnx2x_net_stats_update(struct bnx2x *bp)
  920. {
  921. struct bnx2x_eth_stats *estats = &bp->eth_stats;
  922. struct net_device_stats *nstats = &bp->dev->stats;
  923. unsigned long tmp;
  924. int i;
  925. nstats->rx_packets =
  926. bnx2x_hilo(&estats->total_unicast_packets_received_hi) +
  927. bnx2x_hilo(&estats->total_multicast_packets_received_hi) +
  928. bnx2x_hilo(&estats->total_broadcast_packets_received_hi);
  929. nstats->tx_packets =
  930. bnx2x_hilo(&estats->total_unicast_packets_transmitted_hi) +
  931. bnx2x_hilo(&estats->total_multicast_packets_transmitted_hi) +
  932. bnx2x_hilo(&estats->total_broadcast_packets_transmitted_hi);
  933. nstats->rx_bytes = bnx2x_hilo(&estats->total_bytes_received_hi);
  934. nstats->tx_bytes = bnx2x_hilo(&estats->total_bytes_transmitted_hi);
  935. tmp = estats->mac_discard;
  936. for_each_rx_queue(bp, i)
  937. tmp += le32_to_cpu(bp->fp[i].old_tclient.checksum_discard);
  938. nstats->rx_dropped = tmp;
  939. nstats->tx_dropped = 0;
  940. nstats->multicast =
  941. bnx2x_hilo(&estats->total_multicast_packets_received_hi);
  942. nstats->collisions =
  943. bnx2x_hilo(&estats->tx_stat_etherstatscollisions_hi);
  944. nstats->rx_length_errors =
  945. bnx2x_hilo(&estats->rx_stat_etherstatsundersizepkts_hi) +
  946. bnx2x_hilo(&estats->etherstatsoverrsizepkts_hi);
  947. nstats->rx_over_errors = bnx2x_hilo(&estats->brb_drop_hi) +
  948. bnx2x_hilo(&estats->brb_truncate_hi);
  949. nstats->rx_crc_errors =
  950. bnx2x_hilo(&estats->rx_stat_dot3statsfcserrors_hi);
  951. nstats->rx_frame_errors =
  952. bnx2x_hilo(&estats->rx_stat_dot3statsalignmenterrors_hi);
  953. nstats->rx_fifo_errors = bnx2x_hilo(&estats->no_buff_discard_hi);
  954. nstats->rx_missed_errors = 0;
  955. nstats->rx_errors = nstats->rx_length_errors +
  956. nstats->rx_over_errors +
  957. nstats->rx_crc_errors +
  958. nstats->rx_frame_errors +
  959. nstats->rx_fifo_errors +
  960. nstats->rx_missed_errors;
  961. nstats->tx_aborted_errors =
  962. bnx2x_hilo(&estats->tx_stat_dot3statslatecollisions_hi) +
  963. bnx2x_hilo(&estats->tx_stat_dot3statsexcessivecollisions_hi);
  964. nstats->tx_carrier_errors =
  965. bnx2x_hilo(&estats->rx_stat_dot3statscarriersenseerrors_hi);
  966. nstats->tx_fifo_errors = 0;
  967. nstats->tx_heartbeat_errors = 0;
  968. nstats->tx_window_errors = 0;
  969. nstats->tx_errors = nstats->tx_aborted_errors +
  970. nstats->tx_carrier_errors +
  971. bnx2x_hilo(&estats->tx_stat_dot3statsinternalmactransmiterrors_hi);
  972. }
  973. static void bnx2x_drv_stats_update(struct bnx2x *bp)
  974. {
  975. struct bnx2x_eth_stats *estats = &bp->eth_stats;
  976. int i;
  977. estats->driver_xoff = 0;
  978. estats->rx_err_discard_pkt = 0;
  979. estats->rx_skb_alloc_failed = 0;
  980. estats->hw_csum_err = 0;
  981. for_each_queue(bp, i) {
  982. struct bnx2x_eth_q_stats *qstats = &bp->fp[i].eth_q_stats;
  983. estats->driver_xoff += qstats->driver_xoff;
  984. estats->rx_err_discard_pkt += qstats->rx_err_discard_pkt;
  985. estats->rx_skb_alloc_failed += qstats->rx_skb_alloc_failed;
  986. estats->hw_csum_err += qstats->hw_csum_err;
  987. }
  988. }
  989. static bool bnx2x_edebug_stats_stopped(struct bnx2x *bp)
  990. {
  991. u32 val;
  992. if (SHMEM2_HAS(bp, edebug_driver_if[1])) {
  993. val = SHMEM2_RD(bp, edebug_driver_if[1]);
  994. if (val == EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT)
  995. return true;
  996. }
  997. return false;
  998. }
  999. static void bnx2x_stats_update(struct bnx2x *bp)
  1000. {
  1001. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  1002. if (bnx2x_edebug_stats_stopped(bp))
  1003. return;
  1004. if (*stats_comp != DMAE_COMP_VAL)
  1005. return;
  1006. if (bp->port.pmf)
  1007. bnx2x_hw_stats_update(bp);
  1008. if (bnx2x_storm_stats_update(bp) && (bp->stats_pending++ == 3)) {
  1009. BNX2X_ERR("storm stats were not updated for 3 times\n");
  1010. bnx2x_panic();
  1011. return;
  1012. }
  1013. bnx2x_net_stats_update(bp);
  1014. bnx2x_drv_stats_update(bp);
  1015. if (netif_msg_timer(bp)) {
  1016. struct bnx2x_eth_stats *estats = &bp->eth_stats;
  1017. int i, cos;
  1018. netdev_dbg(bp->dev, "brb drops %u brb truncate %u\n",
  1019. estats->brb_drop_lo, estats->brb_truncate_lo);
  1020. for_each_eth_queue(bp, i) {
  1021. struct bnx2x_fastpath *fp = &bp->fp[i];
  1022. struct bnx2x_eth_q_stats *qstats = &fp->eth_q_stats;
  1023. printk(KERN_DEBUG "%s: rx usage(%4u) *rx_cons_sb(%u)"
  1024. " rx pkt(%lu) rx calls(%lu %lu)\n",
  1025. fp->name, (le16_to_cpu(*fp->rx_cons_sb) -
  1026. fp->rx_comp_cons),
  1027. le16_to_cpu(*fp->rx_cons_sb),
  1028. bnx2x_hilo(&qstats->
  1029. total_unicast_packets_received_hi),
  1030. fp->rx_calls, fp->rx_pkt);
  1031. }
  1032. for_each_eth_queue(bp, i) {
  1033. struct bnx2x_fastpath *fp = &bp->fp[i];
  1034. struct bnx2x_fp_txdata *txdata;
  1035. struct bnx2x_eth_q_stats *qstats = &fp->eth_q_stats;
  1036. struct netdev_queue *txq;
  1037. printk(KERN_DEBUG "%s: tx pkt(%lu) (Xoff events %u)",
  1038. fp->name, bnx2x_hilo(
  1039. &qstats->total_unicast_packets_transmitted_hi),
  1040. qstats->driver_xoff);
  1041. for_each_cos_in_tx_queue(fp, cos) {
  1042. txdata = &fp->txdata[cos];
  1043. txq = netdev_get_tx_queue(bp->dev,
  1044. FP_COS_TO_TXQ(fp, cos));
  1045. printk(KERN_DEBUG "%d: tx avail(%4u)"
  1046. " *tx_cons_sb(%u)"
  1047. " tx calls (%lu)"
  1048. " %s\n",
  1049. cos,
  1050. bnx2x_tx_avail(bp, txdata),
  1051. le16_to_cpu(*txdata->tx_cons_sb),
  1052. txdata->tx_pkt,
  1053. (netif_tx_queue_stopped(txq) ?
  1054. "Xoff" : "Xon")
  1055. );
  1056. }
  1057. }
  1058. }
  1059. bnx2x_hw_stats_post(bp);
  1060. bnx2x_storm_stats_post(bp);
  1061. }
  1062. static void bnx2x_port_stats_stop(struct bnx2x *bp)
  1063. {
  1064. struct dmae_command *dmae;
  1065. u32 opcode;
  1066. int loader_idx = PMF_DMAE_C(bp);
  1067. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  1068. bp->executer_idx = 0;
  1069. opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC, false, 0);
  1070. if (bp->port.port_stx) {
  1071. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  1072. if (bp->func_stx)
  1073. dmae->opcode = bnx2x_dmae_opcode_add_comp(
  1074. opcode, DMAE_COMP_GRC);
  1075. else
  1076. dmae->opcode = bnx2x_dmae_opcode_add_comp(
  1077. opcode, DMAE_COMP_PCI);
  1078. dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
  1079. dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
  1080. dmae->dst_addr_lo = bp->port.port_stx >> 2;
  1081. dmae->dst_addr_hi = 0;
  1082. dmae->len = sizeof(struct host_port_stats) >> 2;
  1083. if (bp->func_stx) {
  1084. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  1085. dmae->comp_addr_hi = 0;
  1086. dmae->comp_val = 1;
  1087. } else {
  1088. dmae->comp_addr_lo =
  1089. U64_LO(bnx2x_sp_mapping(bp, stats_comp));
  1090. dmae->comp_addr_hi =
  1091. U64_HI(bnx2x_sp_mapping(bp, stats_comp));
  1092. dmae->comp_val = DMAE_COMP_VAL;
  1093. *stats_comp = 0;
  1094. }
  1095. }
  1096. if (bp->func_stx) {
  1097. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  1098. dmae->opcode =
  1099. bnx2x_dmae_opcode_add_comp(opcode, DMAE_COMP_PCI);
  1100. dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
  1101. dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
  1102. dmae->dst_addr_lo = bp->func_stx >> 2;
  1103. dmae->dst_addr_hi = 0;
  1104. dmae->len = sizeof(struct host_func_stats) >> 2;
  1105. dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
  1106. dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
  1107. dmae->comp_val = DMAE_COMP_VAL;
  1108. *stats_comp = 0;
  1109. }
  1110. }
  1111. static void bnx2x_stats_stop(struct bnx2x *bp)
  1112. {
  1113. int update = 0;
  1114. bnx2x_stats_comp(bp);
  1115. if (bp->port.pmf)
  1116. update = (bnx2x_hw_stats_update(bp) == 0);
  1117. update |= (bnx2x_storm_stats_update(bp) == 0);
  1118. if (update) {
  1119. bnx2x_net_stats_update(bp);
  1120. if (bp->port.pmf)
  1121. bnx2x_port_stats_stop(bp);
  1122. bnx2x_hw_stats_post(bp);
  1123. bnx2x_stats_comp(bp);
  1124. }
  1125. }
  1126. static void bnx2x_stats_do_nothing(struct bnx2x *bp)
  1127. {
  1128. }
  1129. static const struct {
  1130. void (*action)(struct bnx2x *bp);
  1131. enum bnx2x_stats_state next_state;
  1132. } bnx2x_stats_stm[STATS_STATE_MAX][STATS_EVENT_MAX] = {
  1133. /* state event */
  1134. {
  1135. /* DISABLED PMF */ {bnx2x_stats_pmf_update, STATS_STATE_DISABLED},
  1136. /* LINK_UP */ {bnx2x_stats_start, STATS_STATE_ENABLED},
  1137. /* UPDATE */ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED},
  1138. /* STOP */ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED}
  1139. },
  1140. {
  1141. /* ENABLED PMF */ {bnx2x_stats_pmf_start, STATS_STATE_ENABLED},
  1142. /* LINK_UP */ {bnx2x_stats_restart, STATS_STATE_ENABLED},
  1143. /* UPDATE */ {bnx2x_stats_update, STATS_STATE_ENABLED},
  1144. /* STOP */ {bnx2x_stats_stop, STATS_STATE_DISABLED}
  1145. }
  1146. };
  1147. void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event)
  1148. {
  1149. enum bnx2x_stats_state state;
  1150. if (unlikely(bp->panic))
  1151. return;
  1152. bnx2x_stats_stm[bp->stats_state][event].action(bp);
  1153. spin_lock_bh(&bp->stats_lock);
  1154. state = bp->stats_state;
  1155. bp->stats_state = bnx2x_stats_stm[state][event].next_state;
  1156. spin_unlock_bh(&bp->stats_lock);
  1157. if ((event != STATS_EVENT_UPDATE) || netif_msg_timer(bp))
  1158. DP(BNX2X_MSG_STATS, "state %d -> event %d -> state %d\n",
  1159. state, event, bp->stats_state);
  1160. }
  1161. static void bnx2x_port_stats_base_init(struct bnx2x *bp)
  1162. {
  1163. struct dmae_command *dmae;
  1164. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  1165. /* sanity */
  1166. if (!bp->port.pmf || !bp->port.port_stx) {
  1167. BNX2X_ERR("BUG!\n");
  1168. return;
  1169. }
  1170. bp->executer_idx = 0;
  1171. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  1172. dmae->opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC,
  1173. true, DMAE_COMP_PCI);
  1174. dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
  1175. dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
  1176. dmae->dst_addr_lo = bp->port.port_stx >> 2;
  1177. dmae->dst_addr_hi = 0;
  1178. dmae->len = sizeof(struct host_port_stats) >> 2;
  1179. dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
  1180. dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
  1181. dmae->comp_val = DMAE_COMP_VAL;
  1182. *stats_comp = 0;
  1183. bnx2x_hw_stats_post(bp);
  1184. bnx2x_stats_comp(bp);
  1185. }
  1186. static void bnx2x_func_stats_base_init(struct bnx2x *bp)
  1187. {
  1188. int vn, vn_max = IS_MF(bp) ? E1HVN_MAX : E1VN_MAX;
  1189. u32 func_stx;
  1190. /* sanity */
  1191. if (!bp->port.pmf || !bp->func_stx) {
  1192. BNX2X_ERR("BUG!\n");
  1193. return;
  1194. }
  1195. /* save our func_stx */
  1196. func_stx = bp->func_stx;
  1197. for (vn = VN_0; vn < vn_max; vn++) {
  1198. int mb_idx = CHIP_IS_E1x(bp) ? 2*vn + BP_PORT(bp) : vn;
  1199. bp->func_stx = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_param);
  1200. bnx2x_func_stats_init(bp);
  1201. bnx2x_hw_stats_post(bp);
  1202. bnx2x_stats_comp(bp);
  1203. }
  1204. /* restore our func_stx */
  1205. bp->func_stx = func_stx;
  1206. }
  1207. static void bnx2x_func_stats_base_update(struct bnx2x *bp)
  1208. {
  1209. struct dmae_command *dmae = &bp->stats_dmae;
  1210. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  1211. /* sanity */
  1212. if (!bp->func_stx) {
  1213. BNX2X_ERR("BUG!\n");
  1214. return;
  1215. }
  1216. bp->executer_idx = 0;
  1217. memset(dmae, 0, sizeof(struct dmae_command));
  1218. dmae->opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_GRC, DMAE_DST_PCI,
  1219. true, DMAE_COMP_PCI);
  1220. dmae->src_addr_lo = bp->func_stx >> 2;
  1221. dmae->src_addr_hi = 0;
  1222. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats_base));
  1223. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats_base));
  1224. dmae->len = sizeof(struct host_func_stats) >> 2;
  1225. dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
  1226. dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
  1227. dmae->comp_val = DMAE_COMP_VAL;
  1228. *stats_comp = 0;
  1229. bnx2x_hw_stats_post(bp);
  1230. bnx2x_stats_comp(bp);
  1231. }
  1232. /**
  1233. * This function will prepare the statistics ramrod data the way
  1234. * we will only have to increment the statistics counter and
  1235. * send the ramrod each time we have to.
  1236. *
  1237. * @param bp
  1238. */
  1239. static inline void bnx2x_prep_fw_stats_req(struct bnx2x *bp)
  1240. {
  1241. int i;
  1242. struct stats_query_header *stats_hdr = &bp->fw_stats_req->hdr;
  1243. dma_addr_t cur_data_offset;
  1244. struct stats_query_entry *cur_query_entry;
  1245. stats_hdr->cmd_num = bp->fw_stats_num;
  1246. stats_hdr->drv_stats_counter = 0;
  1247. /* storm_counters struct contains the counters of completed
  1248. * statistics requests per storm which are incremented by FW
  1249. * each time it completes hadning a statistics ramrod. We will
  1250. * check these counters in the timer handler and discard a
  1251. * (statistics) ramrod completion.
  1252. */
  1253. cur_data_offset = bp->fw_stats_data_mapping +
  1254. offsetof(struct bnx2x_fw_stats_data, storm_counters);
  1255. stats_hdr->stats_counters_addrs.hi =
  1256. cpu_to_le32(U64_HI(cur_data_offset));
  1257. stats_hdr->stats_counters_addrs.lo =
  1258. cpu_to_le32(U64_LO(cur_data_offset));
  1259. /* prepare to the first stats ramrod (will be completed with
  1260. * the counters equal to zero) - init counters to somethig different.
  1261. */
  1262. memset(&bp->fw_stats_data->storm_counters, 0xff,
  1263. sizeof(struct stats_counter));
  1264. /**** Port FW statistics data ****/
  1265. cur_data_offset = bp->fw_stats_data_mapping +
  1266. offsetof(struct bnx2x_fw_stats_data, port);
  1267. cur_query_entry = &bp->fw_stats_req->query[BNX2X_PORT_QUERY_IDX];
  1268. cur_query_entry->kind = STATS_TYPE_PORT;
  1269. /* For port query index is a DONT CARE */
  1270. cur_query_entry->index = BP_PORT(bp);
  1271. /* For port query funcID is a DONT CARE */
  1272. cur_query_entry->funcID = cpu_to_le16(BP_FUNC(bp));
  1273. cur_query_entry->address.hi = cpu_to_le32(U64_HI(cur_data_offset));
  1274. cur_query_entry->address.lo = cpu_to_le32(U64_LO(cur_data_offset));
  1275. /**** PF FW statistics data ****/
  1276. cur_data_offset = bp->fw_stats_data_mapping +
  1277. offsetof(struct bnx2x_fw_stats_data, pf);
  1278. cur_query_entry = &bp->fw_stats_req->query[BNX2X_PF_QUERY_IDX];
  1279. cur_query_entry->kind = STATS_TYPE_PF;
  1280. /* For PF query index is a DONT CARE */
  1281. cur_query_entry->index = BP_PORT(bp);
  1282. cur_query_entry->funcID = cpu_to_le16(BP_FUNC(bp));
  1283. cur_query_entry->address.hi = cpu_to_le32(U64_HI(cur_data_offset));
  1284. cur_query_entry->address.lo = cpu_to_le32(U64_LO(cur_data_offset));
  1285. /**** Clients' queries ****/
  1286. cur_data_offset = bp->fw_stats_data_mapping +
  1287. offsetof(struct bnx2x_fw_stats_data, queue_stats);
  1288. for_each_eth_queue(bp, i) {
  1289. cur_query_entry =
  1290. &bp->fw_stats_req->
  1291. query[BNX2X_FIRST_QUEUE_QUERY_IDX + i];
  1292. cur_query_entry->kind = STATS_TYPE_QUEUE;
  1293. cur_query_entry->index = bnx2x_stats_id(&bp->fp[i]);
  1294. cur_query_entry->funcID = cpu_to_le16(BP_FUNC(bp));
  1295. cur_query_entry->address.hi =
  1296. cpu_to_le32(U64_HI(cur_data_offset));
  1297. cur_query_entry->address.lo =
  1298. cpu_to_le32(U64_LO(cur_data_offset));
  1299. cur_data_offset += sizeof(struct per_queue_stats);
  1300. }
  1301. }
  1302. void bnx2x_stats_init(struct bnx2x *bp)
  1303. {
  1304. int /*abs*/port = BP_PORT(bp);
  1305. int mb_idx = BP_FW_MB_IDX(bp);
  1306. int i;
  1307. bp->stats_pending = 0;
  1308. bp->executer_idx = 0;
  1309. bp->stats_counter = 0;
  1310. /* port and func stats for management */
  1311. if (!BP_NOMCP(bp)) {
  1312. bp->port.port_stx = SHMEM_RD(bp, port_mb[port].port_stx);
  1313. bp->func_stx = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_param);
  1314. } else {
  1315. bp->port.port_stx = 0;
  1316. bp->func_stx = 0;
  1317. }
  1318. DP(BNX2X_MSG_STATS, "port_stx 0x%x func_stx 0x%x\n",
  1319. bp->port.port_stx, bp->func_stx);
  1320. port = BP_PORT(bp);
  1321. /* port stats */
  1322. memset(&(bp->port.old_nig_stats), 0, sizeof(struct nig_stats));
  1323. bp->port.old_nig_stats.brb_discard =
  1324. REG_RD(bp, NIG_REG_STAT0_BRB_DISCARD + port*0x38);
  1325. bp->port.old_nig_stats.brb_truncate =
  1326. REG_RD(bp, NIG_REG_STAT0_BRB_TRUNCATE + port*0x38);
  1327. if (!CHIP_IS_E3(bp)) {
  1328. REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT0 + port*0x50,
  1329. &(bp->port.old_nig_stats.egress_mac_pkt0_lo), 2);
  1330. REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT1 + port*0x50,
  1331. &(bp->port.old_nig_stats.egress_mac_pkt1_lo), 2);
  1332. }
  1333. /* function stats */
  1334. for_each_queue(bp, i) {
  1335. struct bnx2x_fastpath *fp = &bp->fp[i];
  1336. memset(&fp->old_tclient, 0, sizeof(fp->old_tclient));
  1337. memset(&fp->old_uclient, 0, sizeof(fp->old_uclient));
  1338. memset(&fp->old_xclient, 0, sizeof(fp->old_xclient));
  1339. memset(&fp->eth_q_stats, 0, sizeof(fp->eth_q_stats));
  1340. }
  1341. /* Prepare statistics ramrod data */
  1342. bnx2x_prep_fw_stats_req(bp);
  1343. memset(&bp->dev->stats, 0, sizeof(bp->dev->stats));
  1344. memset(&bp->eth_stats, 0, sizeof(bp->eth_stats));
  1345. bp->stats_state = STATS_STATE_DISABLED;
  1346. if (bp->port.pmf) {
  1347. if (bp->port.port_stx)
  1348. bnx2x_port_stats_base_init(bp);
  1349. if (bp->func_stx)
  1350. bnx2x_func_stats_base_init(bp);
  1351. } else if (bp->func_stx)
  1352. bnx2x_func_stats_base_update(bp);
  1353. }