assembler.h 6.5 KB

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  1. /*
  2. * arch/arm/include/asm/assembler.h
  3. *
  4. * Copyright (C) 1996-2000 Russell King
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * This file contains arm architecture specific defines
  11. * for the different processors.
  12. *
  13. * Do not include any C declarations in this file - it is included by
  14. * assembler source.
  15. */
  16. #ifndef __ASM_ASSEMBLER_H__
  17. #define __ASM_ASSEMBLER_H__
  18. #ifndef __ASSEMBLY__
  19. #error "Only include this from assembly code"
  20. #endif
  21. #include <asm/ptrace.h>
  22. #include <asm/domain.h>
  23. /*
  24. * Endian independent macros for shifting bytes within registers.
  25. */
  26. #ifndef __ARMEB__
  27. #define pull lsr
  28. #define push lsl
  29. #define get_byte_0 lsl #0
  30. #define get_byte_1 lsr #8
  31. #define get_byte_2 lsr #16
  32. #define get_byte_3 lsr #24
  33. #define put_byte_0 lsl #0
  34. #define put_byte_1 lsl #8
  35. #define put_byte_2 lsl #16
  36. #define put_byte_3 lsl #24
  37. #else
  38. #define pull lsl
  39. #define push lsr
  40. #define get_byte_0 lsr #24
  41. #define get_byte_1 lsr #16
  42. #define get_byte_2 lsr #8
  43. #define get_byte_3 lsl #0
  44. #define put_byte_0 lsl #24
  45. #define put_byte_1 lsl #16
  46. #define put_byte_2 lsl #8
  47. #define put_byte_3 lsl #0
  48. #endif
  49. /*
  50. * Data preload for architectures that support it
  51. */
  52. #if __LINUX_ARM_ARCH__ >= 5
  53. #define PLD(code...) code
  54. #else
  55. #define PLD(code...)
  56. #endif
  57. /*
  58. * This can be used to enable code to cacheline align the destination
  59. * pointer when bulk writing to memory. Experiments on StrongARM and
  60. * XScale didn't show this a worthwhile thing to do when the cache is not
  61. * set to write-allocate (this would need further testing on XScale when WA
  62. * is used).
  63. *
  64. * On Feroceon there is much to gain however, regardless of cache mode.
  65. */
  66. #ifdef CONFIG_CPU_FEROCEON
  67. #define CALGN(code...) code
  68. #else
  69. #define CALGN(code...)
  70. #endif
  71. /*
  72. * Enable and disable interrupts
  73. */
  74. #if __LINUX_ARM_ARCH__ >= 6
  75. .macro disable_irq_notrace
  76. cpsid i
  77. .endm
  78. .macro enable_irq_notrace
  79. cpsie i
  80. .endm
  81. #else
  82. .macro disable_irq_notrace
  83. msr cpsr_c, #PSR_I_BIT | SVC_MODE
  84. .endm
  85. .macro enable_irq_notrace
  86. msr cpsr_c, #SVC_MODE
  87. .endm
  88. #endif
  89. .macro asm_trace_hardirqs_off
  90. #if defined(CONFIG_TRACE_IRQFLAGS)
  91. stmdb sp!, {r0-r3, ip, lr}
  92. bl trace_hardirqs_off
  93. ldmia sp!, {r0-r3, ip, lr}
  94. #endif
  95. .endm
  96. .macro asm_trace_hardirqs_on_cond, cond
  97. #if defined(CONFIG_TRACE_IRQFLAGS)
  98. /*
  99. * actually the registers should be pushed and pop'd conditionally, but
  100. * after bl the flags are certainly clobbered
  101. */
  102. stmdb sp!, {r0-r3, ip, lr}
  103. bl\cond trace_hardirqs_on
  104. ldmia sp!, {r0-r3, ip, lr}
  105. #endif
  106. .endm
  107. .macro asm_trace_hardirqs_on
  108. asm_trace_hardirqs_on_cond al
  109. .endm
  110. .macro disable_irq
  111. disable_irq_notrace
  112. asm_trace_hardirqs_off
  113. .endm
  114. .macro enable_irq
  115. asm_trace_hardirqs_on
  116. enable_irq_notrace
  117. .endm
  118. /*
  119. * Save the current IRQ state and disable IRQs. Note that this macro
  120. * assumes FIQs are enabled, and that the processor is in SVC mode.
  121. */
  122. .macro save_and_disable_irqs, oldcpsr
  123. mrs \oldcpsr, cpsr
  124. disable_irq
  125. .endm
  126. /*
  127. * Restore interrupt state previously stored in a register. We don't
  128. * guarantee that this will preserve the flags.
  129. */
  130. .macro restore_irqs_notrace, oldcpsr
  131. msr cpsr_c, \oldcpsr
  132. .endm
  133. .macro restore_irqs, oldcpsr
  134. tst \oldcpsr, #PSR_I_BIT
  135. asm_trace_hardirqs_on_cond eq
  136. restore_irqs_notrace \oldcpsr
  137. .endm
  138. #define USER(x...) \
  139. 9999: x; \
  140. .pushsection __ex_table,"a"; \
  141. .align 3; \
  142. .long 9999b,9001f; \
  143. .popsection
  144. #ifdef CONFIG_SMP
  145. #define ALT_SMP(instr...) \
  146. 9998: instr
  147. /*
  148. * Note: if you get assembler errors from ALT_UP() when building with
  149. * CONFIG_THUMB2_KERNEL, you almost certainly need to use
  150. * ALT_SMP( W(instr) ... )
  151. */
  152. #define ALT_UP(instr...) \
  153. .pushsection ".alt.smp.init", "a" ;\
  154. .long 9998b ;\
  155. 9997: instr ;\
  156. .if . - 9997b != 4 ;\
  157. .error "ALT_UP() content must assemble to exactly 4 bytes";\
  158. .endif ;\
  159. .popsection
  160. #define ALT_UP_B(label) \
  161. .equ up_b_offset, label - 9998b ;\
  162. .pushsection ".alt.smp.init", "a" ;\
  163. .long 9998b ;\
  164. W(b) . + up_b_offset ;\
  165. .popsection
  166. #else
  167. #define ALT_SMP(instr...)
  168. #define ALT_UP(instr...) instr
  169. #define ALT_UP_B(label) b label
  170. #endif
  171. /*
  172. * SMP data memory barrier
  173. */
  174. .macro smp_dmb mode
  175. #ifdef CONFIG_SMP
  176. #if __LINUX_ARM_ARCH__ >= 7
  177. .ifeqs "\mode","arm"
  178. ALT_SMP(dmb)
  179. .else
  180. ALT_SMP(W(dmb))
  181. .endif
  182. #elif __LINUX_ARM_ARCH__ == 6
  183. ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb
  184. #else
  185. #error Incompatible SMP platform
  186. #endif
  187. .ifeqs "\mode","arm"
  188. ALT_UP(nop)
  189. .else
  190. ALT_UP(W(nop))
  191. .endif
  192. #endif
  193. .endm
  194. #ifdef CONFIG_THUMB2_KERNEL
  195. .macro setmode, mode, reg
  196. mov \reg, #\mode
  197. msr cpsr_c, \reg
  198. .endm
  199. #else
  200. .macro setmode, mode, reg
  201. msr cpsr_c, #\mode
  202. .endm
  203. #endif
  204. /*
  205. * STRT/LDRT access macros with ARM and Thumb-2 variants
  206. */
  207. #ifdef CONFIG_THUMB2_KERNEL
  208. .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=T()
  209. 9999:
  210. .if \inc == 1
  211. \instr\cond\()b\()\t\().w \reg, [\ptr, #\off]
  212. .elseif \inc == 4
  213. \instr\cond\()\t\().w \reg, [\ptr, #\off]
  214. .else
  215. .error "Unsupported inc macro argument"
  216. .endif
  217. .pushsection __ex_table,"a"
  218. .align 3
  219. .long 9999b, \abort
  220. .popsection
  221. .endm
  222. .macro usracc, instr, reg, ptr, inc, cond, rept, abort
  223. @ explicit IT instruction needed because of the label
  224. @ introduced by the USER macro
  225. .ifnc \cond,al
  226. .if \rept == 1
  227. itt \cond
  228. .elseif \rept == 2
  229. ittt \cond
  230. .else
  231. .error "Unsupported rept macro argument"
  232. .endif
  233. .endif
  234. @ Slightly optimised to avoid incrementing the pointer twice
  235. usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort
  236. .if \rept == 2
  237. usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort
  238. .endif
  239. add\cond \ptr, #\rept * \inc
  240. .endm
  241. #else /* !CONFIG_THUMB2_KERNEL */
  242. .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=T()
  243. .rept \rept
  244. 9999:
  245. .if \inc == 1
  246. \instr\cond\()b\()\t \reg, [\ptr], #\inc
  247. .elseif \inc == 4
  248. \instr\cond\()\t \reg, [\ptr], #\inc
  249. .else
  250. .error "Unsupported inc macro argument"
  251. .endif
  252. .pushsection __ex_table,"a"
  253. .align 3
  254. .long 9999b, \abort
  255. .popsection
  256. .endr
  257. .endm
  258. #endif /* CONFIG_THUMB2_KERNEL */
  259. .macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
  260. usracc str, \reg, \ptr, \inc, \cond, \rept, \abort
  261. .endm
  262. .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
  263. usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort
  264. .endm
  265. /* Utility macro for declaring string literals */
  266. .macro string name:req, string
  267. .type \name , #object
  268. \name:
  269. .asciz "\string"
  270. .size \name , . - \name
  271. .endm
  272. #endif /* __ASM_ASSEMBLER_H__ */