hdmi_drv.c 29 KB

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  1. /*
  2. * Samsung HDMI interface driver
  3. *
  4. * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  5. *
  6. * Tomasz Stanislawski, <t.stanislaws@samsung.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published
  10. * by the Free Software Foundiation. either version 2 of the License,
  11. * or (at your option) any later version
  12. */
  13. #define pr_fmt(fmt) "s5p-tv (hdmi_drv): " fmt
  14. #ifdef CONFIG_VIDEO_SAMSUNG_S5P_HDMI_DEBUG
  15. #define DEBUG
  16. #endif
  17. #include <linux/kernel.h>
  18. #include <linux/slab.h>
  19. #include <linux/io.h>
  20. #include <linux/i2c.h>
  21. #include <linux/platform_device.h>
  22. #include <media/v4l2-subdev.h>
  23. #include <linux/module.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/irq.h>
  26. #include <linux/delay.h>
  27. #include <linux/bug.h>
  28. #include <linux/pm_runtime.h>
  29. #include <linux/clk.h>
  30. #include <linux/regulator/consumer.h>
  31. #include <linux/v4l2-dv-timings.h>
  32. #include <media/s5p_hdmi.h>
  33. #include <media/v4l2-common.h>
  34. #include <media/v4l2-dev.h>
  35. #include <media/v4l2-device.h>
  36. #include "regs-hdmi.h"
  37. MODULE_AUTHOR("Tomasz Stanislawski, <t.stanislaws@samsung.com>");
  38. MODULE_DESCRIPTION("Samsung HDMI");
  39. MODULE_LICENSE("GPL");
  40. /* default preset configured on probe */
  41. #define HDMI_DEFAULT_PRESET V4L2_DV_480P59_94
  42. struct hdmi_pulse {
  43. u32 beg;
  44. u32 end;
  45. };
  46. struct hdmi_timings {
  47. struct hdmi_pulse hact;
  48. u32 hsyn_pol; /* 0 - high, 1 - low */
  49. struct hdmi_pulse hsyn;
  50. u32 interlaced;
  51. struct hdmi_pulse vact[2];
  52. u32 vsyn_pol; /* 0 - high, 1 - low */
  53. u32 vsyn_off;
  54. struct hdmi_pulse vsyn[2];
  55. };
  56. struct hdmi_resources {
  57. struct clk *hdmi;
  58. struct clk *sclk_hdmi;
  59. struct clk *sclk_pixel;
  60. struct clk *sclk_hdmiphy;
  61. struct clk *hdmiphy;
  62. struct regulator_bulk_data *regul_bulk;
  63. int regul_count;
  64. };
  65. struct hdmi_device {
  66. /** base address of HDMI registers */
  67. void __iomem *regs;
  68. /** HDMI interrupt */
  69. unsigned int irq;
  70. /** pointer to device parent */
  71. struct device *dev;
  72. /** subdev generated by HDMI device */
  73. struct v4l2_subdev sd;
  74. /** V4L2 device structure */
  75. struct v4l2_device v4l2_dev;
  76. /** subdev of HDMIPHY interface */
  77. struct v4l2_subdev *phy_sd;
  78. /** subdev of MHL interface */
  79. struct v4l2_subdev *mhl_sd;
  80. /** configuration of current graphic mode */
  81. const struct hdmi_timings *cur_conf;
  82. /** flag indicating that timings are dirty */
  83. int cur_conf_dirty;
  84. /** current preset */
  85. u32 cur_preset;
  86. /** current timings */
  87. struct v4l2_dv_timings cur_timings;
  88. /** other resources */
  89. struct hdmi_resources res;
  90. };
  91. static struct platform_device_id hdmi_driver_types[] = {
  92. {
  93. .name = "s5pv210-hdmi",
  94. }, {
  95. .name = "exynos4-hdmi",
  96. }, {
  97. /* end node */
  98. }
  99. };
  100. static const struct v4l2_subdev_ops hdmi_sd_ops;
  101. static struct hdmi_device *sd_to_hdmi_dev(struct v4l2_subdev *sd)
  102. {
  103. return container_of(sd, struct hdmi_device, sd);
  104. }
  105. static inline
  106. void hdmi_write(struct hdmi_device *hdev, u32 reg_id, u32 value)
  107. {
  108. writel(value, hdev->regs + reg_id);
  109. }
  110. static inline
  111. void hdmi_write_mask(struct hdmi_device *hdev, u32 reg_id, u32 value, u32 mask)
  112. {
  113. u32 old = readl(hdev->regs + reg_id);
  114. value = (value & mask) | (old & ~mask);
  115. writel(value, hdev->regs + reg_id);
  116. }
  117. static inline
  118. void hdmi_writeb(struct hdmi_device *hdev, u32 reg_id, u8 value)
  119. {
  120. writeb(value, hdev->regs + reg_id);
  121. }
  122. static inline
  123. void hdmi_writebn(struct hdmi_device *hdev, u32 reg_id, int n, u32 value)
  124. {
  125. switch (n) {
  126. default:
  127. writeb(value >> 24, hdev->regs + reg_id + 12);
  128. case 3:
  129. writeb(value >> 16, hdev->regs + reg_id + 8);
  130. case 2:
  131. writeb(value >> 8, hdev->regs + reg_id + 4);
  132. case 1:
  133. writeb(value >> 0, hdev->regs + reg_id + 0);
  134. }
  135. }
  136. static inline u32 hdmi_read(struct hdmi_device *hdev, u32 reg_id)
  137. {
  138. return readl(hdev->regs + reg_id);
  139. }
  140. static irqreturn_t hdmi_irq_handler(int irq, void *dev_data)
  141. {
  142. struct hdmi_device *hdev = dev_data;
  143. u32 intc_flag;
  144. (void)irq;
  145. intc_flag = hdmi_read(hdev, HDMI_INTC_FLAG);
  146. /* clearing flags for HPD plug/unplug */
  147. if (intc_flag & HDMI_INTC_FLAG_HPD_UNPLUG) {
  148. pr_info("unplugged\n");
  149. hdmi_write_mask(hdev, HDMI_INTC_FLAG, ~0,
  150. HDMI_INTC_FLAG_HPD_UNPLUG);
  151. }
  152. if (intc_flag & HDMI_INTC_FLAG_HPD_PLUG) {
  153. pr_info("plugged\n");
  154. hdmi_write_mask(hdev, HDMI_INTC_FLAG, ~0,
  155. HDMI_INTC_FLAG_HPD_PLUG);
  156. }
  157. return IRQ_HANDLED;
  158. }
  159. static void hdmi_reg_init(struct hdmi_device *hdev)
  160. {
  161. /* enable HPD interrupts */
  162. hdmi_write_mask(hdev, HDMI_INTC_CON, ~0, HDMI_INTC_EN_GLOBAL |
  163. HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG);
  164. /* choose DVI mode */
  165. hdmi_write_mask(hdev, HDMI_MODE_SEL,
  166. HDMI_MODE_DVI_EN, HDMI_MODE_MASK);
  167. hdmi_write_mask(hdev, HDMI_CON_2, ~0,
  168. HDMI_DVI_PERAMBLE_EN | HDMI_DVI_BAND_EN);
  169. /* disable bluescreen */
  170. hdmi_write_mask(hdev, HDMI_CON_0, 0, HDMI_BLUE_SCR_EN);
  171. /* choose bluescreen (fecal) color */
  172. hdmi_writeb(hdev, HDMI_BLUE_SCREEN_0, 0x12);
  173. hdmi_writeb(hdev, HDMI_BLUE_SCREEN_1, 0x34);
  174. hdmi_writeb(hdev, HDMI_BLUE_SCREEN_2, 0x56);
  175. }
  176. static void hdmi_timing_apply(struct hdmi_device *hdev,
  177. const struct hdmi_timings *t)
  178. {
  179. /* setting core registers */
  180. hdmi_writebn(hdev, HDMI_H_BLANK_0, 2, t->hact.beg);
  181. hdmi_writebn(hdev, HDMI_H_SYNC_GEN_0, 3,
  182. (t->hsyn_pol << 20) | (t->hsyn.end << 10) | t->hsyn.beg);
  183. hdmi_writeb(hdev, HDMI_VSYNC_POL, t->vsyn_pol);
  184. hdmi_writebn(hdev, HDMI_V_BLANK_0, 3,
  185. (t->vact[0].beg << 11) | t->vact[0].end);
  186. hdmi_writebn(hdev, HDMI_V_SYNC_GEN_1_0, 3,
  187. (t->vsyn[0].beg << 12) | t->vsyn[0].end);
  188. if (t->interlaced) {
  189. u32 vsyn_trans = t->hsyn.beg + t->vsyn_off;
  190. hdmi_writeb(hdev, HDMI_INT_PRO_MODE, 1);
  191. hdmi_writebn(hdev, HDMI_H_V_LINE_0, 3,
  192. (t->hact.end << 12) | t->vact[1].end);
  193. hdmi_writebn(hdev, HDMI_V_BLANK_F_0, 3,
  194. (t->vact[1].end << 11) | t->vact[1].beg);
  195. hdmi_writebn(hdev, HDMI_V_SYNC_GEN_2_0, 3,
  196. (t->vsyn[1].beg << 12) | t->vsyn[1].end);
  197. hdmi_writebn(hdev, HDMI_V_SYNC_GEN_3_0, 3,
  198. (vsyn_trans << 12) | vsyn_trans);
  199. } else {
  200. hdmi_writeb(hdev, HDMI_INT_PRO_MODE, 0);
  201. hdmi_writebn(hdev, HDMI_H_V_LINE_0, 3,
  202. (t->hact.end << 12) | t->vact[0].end);
  203. }
  204. /* Timing generator registers */
  205. hdmi_writebn(hdev, HDMI_TG_H_FSZ_L, 2, t->hact.end);
  206. hdmi_writebn(hdev, HDMI_TG_HACT_ST_L, 2, t->hact.beg);
  207. hdmi_writebn(hdev, HDMI_TG_HACT_SZ_L, 2, t->hact.end - t->hact.beg);
  208. hdmi_writebn(hdev, HDMI_TG_VSYNC_L, 2, t->vsyn[0].beg);
  209. hdmi_writebn(hdev, HDMI_TG_VACT_ST_L, 2, t->vact[0].beg);
  210. hdmi_writebn(hdev, HDMI_TG_VACT_SZ_L, 2,
  211. t->vact[0].end - t->vact[0].beg);
  212. hdmi_writebn(hdev, HDMI_TG_VSYNC_TOP_HDMI_L, 2, t->vsyn[0].beg);
  213. hdmi_writebn(hdev, HDMI_TG_FIELD_TOP_HDMI_L, 2, t->vsyn[0].beg);
  214. if (t->interlaced) {
  215. hdmi_write_mask(hdev, HDMI_TG_CMD, ~0, HDMI_TG_FIELD_EN);
  216. hdmi_writebn(hdev, HDMI_TG_V_FSZ_L, 2, t->vact[1].end);
  217. hdmi_writebn(hdev, HDMI_TG_VSYNC2_L, 2, t->vsyn[1].beg);
  218. hdmi_writebn(hdev, HDMI_TG_FIELD_CHG_L, 2, t->vact[0].end);
  219. hdmi_writebn(hdev, HDMI_TG_VACT_ST2_L, 2, t->vact[1].beg);
  220. hdmi_writebn(hdev, HDMI_TG_VSYNC_BOT_HDMI_L, 2, t->vsyn[1].beg);
  221. hdmi_writebn(hdev, HDMI_TG_FIELD_BOT_HDMI_L, 2, t->vsyn[1].beg);
  222. } else {
  223. hdmi_write_mask(hdev, HDMI_TG_CMD, 0, HDMI_TG_FIELD_EN);
  224. hdmi_writebn(hdev, HDMI_TG_V_FSZ_L, 2, t->vact[0].end);
  225. }
  226. }
  227. static int hdmi_conf_apply(struct hdmi_device *hdmi_dev)
  228. {
  229. struct device *dev = hdmi_dev->dev;
  230. const struct hdmi_timings *conf = hdmi_dev->cur_conf;
  231. struct v4l2_dv_preset preset;
  232. int ret;
  233. dev_dbg(dev, "%s\n", __func__);
  234. /* skip if conf is already synchronized with HW */
  235. if (!hdmi_dev->cur_conf_dirty)
  236. return 0;
  237. /* reset hdmiphy */
  238. hdmi_write_mask(hdmi_dev, HDMI_PHY_RSTOUT, ~0, HDMI_PHY_SW_RSTOUT);
  239. mdelay(10);
  240. hdmi_write_mask(hdmi_dev, HDMI_PHY_RSTOUT, 0, HDMI_PHY_SW_RSTOUT);
  241. mdelay(10);
  242. /* configure presets */
  243. preset.preset = hdmi_dev->cur_preset;
  244. ret = v4l2_subdev_call(hdmi_dev->phy_sd, video, s_dv_preset, &preset);
  245. if (ret) {
  246. dev_err(dev, "failed to set preset (%u)\n", preset.preset);
  247. return ret;
  248. }
  249. /* resetting HDMI core */
  250. hdmi_write_mask(hdmi_dev, HDMI_CORE_RSTOUT, 0, HDMI_CORE_SW_RSTOUT);
  251. mdelay(10);
  252. hdmi_write_mask(hdmi_dev, HDMI_CORE_RSTOUT, ~0, HDMI_CORE_SW_RSTOUT);
  253. mdelay(10);
  254. hdmi_reg_init(hdmi_dev);
  255. /* setting core registers */
  256. hdmi_timing_apply(hdmi_dev, conf);
  257. hdmi_dev->cur_conf_dirty = 0;
  258. return 0;
  259. }
  260. static void hdmi_dumpregs(struct hdmi_device *hdev, char *prefix)
  261. {
  262. #define DUMPREG(reg_id) \
  263. dev_dbg(hdev->dev, "%s:" #reg_id " = %08x\n", prefix, \
  264. readl(hdev->regs + reg_id))
  265. dev_dbg(hdev->dev, "%s: ---- CONTROL REGISTERS ----\n", prefix);
  266. DUMPREG(HDMI_INTC_FLAG);
  267. DUMPREG(HDMI_INTC_CON);
  268. DUMPREG(HDMI_HPD_STATUS);
  269. DUMPREG(HDMI_PHY_RSTOUT);
  270. DUMPREG(HDMI_PHY_VPLL);
  271. DUMPREG(HDMI_PHY_CMU);
  272. DUMPREG(HDMI_CORE_RSTOUT);
  273. dev_dbg(hdev->dev, "%s: ---- CORE REGISTERS ----\n", prefix);
  274. DUMPREG(HDMI_CON_0);
  275. DUMPREG(HDMI_CON_1);
  276. DUMPREG(HDMI_CON_2);
  277. DUMPREG(HDMI_SYS_STATUS);
  278. DUMPREG(HDMI_PHY_STATUS);
  279. DUMPREG(HDMI_STATUS_EN);
  280. DUMPREG(HDMI_HPD);
  281. DUMPREG(HDMI_MODE_SEL);
  282. DUMPREG(HDMI_HPD_GEN);
  283. DUMPREG(HDMI_DC_CONTROL);
  284. DUMPREG(HDMI_VIDEO_PATTERN_GEN);
  285. dev_dbg(hdev->dev, "%s: ---- CORE SYNC REGISTERS ----\n", prefix);
  286. DUMPREG(HDMI_H_BLANK_0);
  287. DUMPREG(HDMI_H_BLANK_1);
  288. DUMPREG(HDMI_V_BLANK_0);
  289. DUMPREG(HDMI_V_BLANK_1);
  290. DUMPREG(HDMI_V_BLANK_2);
  291. DUMPREG(HDMI_H_V_LINE_0);
  292. DUMPREG(HDMI_H_V_LINE_1);
  293. DUMPREG(HDMI_H_V_LINE_2);
  294. DUMPREG(HDMI_VSYNC_POL);
  295. DUMPREG(HDMI_INT_PRO_MODE);
  296. DUMPREG(HDMI_V_BLANK_F_0);
  297. DUMPREG(HDMI_V_BLANK_F_1);
  298. DUMPREG(HDMI_V_BLANK_F_2);
  299. DUMPREG(HDMI_H_SYNC_GEN_0);
  300. DUMPREG(HDMI_H_SYNC_GEN_1);
  301. DUMPREG(HDMI_H_SYNC_GEN_2);
  302. DUMPREG(HDMI_V_SYNC_GEN_1_0);
  303. DUMPREG(HDMI_V_SYNC_GEN_1_1);
  304. DUMPREG(HDMI_V_SYNC_GEN_1_2);
  305. DUMPREG(HDMI_V_SYNC_GEN_2_0);
  306. DUMPREG(HDMI_V_SYNC_GEN_2_1);
  307. DUMPREG(HDMI_V_SYNC_GEN_2_2);
  308. DUMPREG(HDMI_V_SYNC_GEN_3_0);
  309. DUMPREG(HDMI_V_SYNC_GEN_3_1);
  310. DUMPREG(HDMI_V_SYNC_GEN_3_2);
  311. dev_dbg(hdev->dev, "%s: ---- TG REGISTERS ----\n", prefix);
  312. DUMPREG(HDMI_TG_CMD);
  313. DUMPREG(HDMI_TG_H_FSZ_L);
  314. DUMPREG(HDMI_TG_H_FSZ_H);
  315. DUMPREG(HDMI_TG_HACT_ST_L);
  316. DUMPREG(HDMI_TG_HACT_ST_H);
  317. DUMPREG(HDMI_TG_HACT_SZ_L);
  318. DUMPREG(HDMI_TG_HACT_SZ_H);
  319. DUMPREG(HDMI_TG_V_FSZ_L);
  320. DUMPREG(HDMI_TG_V_FSZ_H);
  321. DUMPREG(HDMI_TG_VSYNC_L);
  322. DUMPREG(HDMI_TG_VSYNC_H);
  323. DUMPREG(HDMI_TG_VSYNC2_L);
  324. DUMPREG(HDMI_TG_VSYNC2_H);
  325. DUMPREG(HDMI_TG_VACT_ST_L);
  326. DUMPREG(HDMI_TG_VACT_ST_H);
  327. DUMPREG(HDMI_TG_VACT_SZ_L);
  328. DUMPREG(HDMI_TG_VACT_SZ_H);
  329. DUMPREG(HDMI_TG_FIELD_CHG_L);
  330. DUMPREG(HDMI_TG_FIELD_CHG_H);
  331. DUMPREG(HDMI_TG_VACT_ST2_L);
  332. DUMPREG(HDMI_TG_VACT_ST2_H);
  333. DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
  334. DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
  335. DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
  336. DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
  337. DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
  338. DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
  339. DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
  340. DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
  341. #undef DUMPREG
  342. }
  343. static const struct hdmi_timings hdmi_timings_480p = {
  344. .hact = { .beg = 138, .end = 858 },
  345. .hsyn_pol = 1,
  346. .hsyn = { .beg = 16, .end = 16 + 62 },
  347. .interlaced = 0,
  348. .vact[0] = { .beg = 42 + 3, .end = 522 + 3 },
  349. .vsyn_pol = 1,
  350. .vsyn[0] = { .beg = 6 + 3, .end = 12 + 3},
  351. };
  352. static const struct hdmi_timings hdmi_timings_576p50 = {
  353. .hact = { .beg = 144, .end = 864 },
  354. .hsyn_pol = 1,
  355. .hsyn = { .beg = 12, .end = 12 + 64 },
  356. .interlaced = 0,
  357. .vact[0] = { .beg = 44 + 5, .end = 620 + 5 },
  358. .vsyn_pol = 1,
  359. .vsyn[0] = { .beg = 0 + 5, .end = 5 + 5},
  360. };
  361. static const struct hdmi_timings hdmi_timings_720p60 = {
  362. .hact = { .beg = 370, .end = 1650 },
  363. .hsyn_pol = 0,
  364. .hsyn = { .beg = 110, .end = 110 + 40 },
  365. .interlaced = 0,
  366. .vact[0] = { .beg = 25 + 5, .end = 745 + 5 },
  367. .vsyn_pol = 0,
  368. .vsyn[0] = { .beg = 0 + 5, .end = 5 + 5},
  369. };
  370. static const struct hdmi_timings hdmi_timings_720p50 = {
  371. .hact = { .beg = 700, .end = 1980 },
  372. .hsyn_pol = 0,
  373. .hsyn = { .beg = 440, .end = 440 + 40 },
  374. .interlaced = 0,
  375. .vact[0] = { .beg = 25 + 5, .end = 745 + 5 },
  376. .vsyn_pol = 0,
  377. .vsyn[0] = { .beg = 0 + 5, .end = 5 + 5},
  378. };
  379. static const struct hdmi_timings hdmi_timings_1080p24 = {
  380. .hact = { .beg = 830, .end = 2750 },
  381. .hsyn_pol = 0,
  382. .hsyn = { .beg = 638, .end = 638 + 44 },
  383. .interlaced = 0,
  384. .vact[0] = { .beg = 41 + 4, .end = 1121 + 4 },
  385. .vsyn_pol = 0,
  386. .vsyn[0] = { .beg = 0 + 4, .end = 5 + 4},
  387. };
  388. static const struct hdmi_timings hdmi_timings_1080p60 = {
  389. .hact = { .beg = 280, .end = 2200 },
  390. .hsyn_pol = 0,
  391. .hsyn = { .beg = 88, .end = 88 + 44 },
  392. .interlaced = 0,
  393. .vact[0] = { .beg = 41 + 4, .end = 1121 + 4 },
  394. .vsyn_pol = 0,
  395. .vsyn[0] = { .beg = 0 + 4, .end = 5 + 4},
  396. };
  397. static const struct hdmi_timings hdmi_timings_1080i60 = {
  398. .hact = { .beg = 280, .end = 2200 },
  399. .hsyn_pol = 0,
  400. .hsyn = { .beg = 88, .end = 88 + 44 },
  401. .interlaced = 1,
  402. .vact[0] = { .beg = 20 + 2, .end = 560 + 2 },
  403. .vact[1] = { .beg = 583 + 2, .end = 1123 + 2 },
  404. .vsyn_pol = 0,
  405. .vsyn_off = 1100,
  406. .vsyn[0] = { .beg = 0 + 2, .end = 5 + 2},
  407. .vsyn[1] = { .beg = 562 + 2, .end = 567 + 2},
  408. };
  409. static const struct hdmi_timings hdmi_timings_1080i50 = {
  410. .hact = { .beg = 720, .end = 2640 },
  411. .hsyn_pol = 0,
  412. .hsyn = { .beg = 528, .end = 528 + 44 },
  413. .interlaced = 1,
  414. .vact[0] = { .beg = 20 + 2, .end = 560 + 2 },
  415. .vact[1] = { .beg = 583 + 2, .end = 1123 + 2 },
  416. .vsyn_pol = 0,
  417. .vsyn_off = 1320,
  418. .vsyn[0] = { .beg = 0 + 2, .end = 5 + 2},
  419. .vsyn[1] = { .beg = 562 + 2, .end = 567 + 2},
  420. };
  421. static const struct hdmi_timings hdmi_timings_1080p50 = {
  422. .hact = { .beg = 720, .end = 2640 },
  423. .hsyn_pol = 0,
  424. .hsyn = { .beg = 528, .end = 528 + 44 },
  425. .interlaced = 0,
  426. .vact[0] = { .beg = 41 + 4, .end = 1121 + 4 },
  427. .vsyn_pol = 0,
  428. .vsyn[0] = { .beg = 0 + 4, .end = 5 + 4},
  429. };
  430. static const struct {
  431. u32 preset;
  432. bool reduced_fps;
  433. const struct v4l2_dv_timings dv_timings;
  434. const struct hdmi_timings *hdmi_timings;
  435. } hdmi_timings[] = {
  436. { V4L2_DV_480P59_94, false, V4L2_DV_BT_CEA_720X480P59_94, &hdmi_timings_480p },
  437. { V4L2_DV_576P50, false, V4L2_DV_BT_CEA_720X576P50, &hdmi_timings_576p50 },
  438. { V4L2_DV_720P50, false, V4L2_DV_BT_CEA_1280X720P50, &hdmi_timings_720p50 },
  439. { V4L2_DV_720P59_94, true, V4L2_DV_BT_CEA_1280X720P60, &hdmi_timings_720p60 },
  440. { V4L2_DV_720P60, false, V4L2_DV_BT_CEA_1280X720P60, &hdmi_timings_720p60 },
  441. { V4L2_DV_1080P24, false, V4L2_DV_BT_CEA_1920X1080P24, &hdmi_timings_1080p24 },
  442. { V4L2_DV_1080P30, false, V4L2_DV_BT_CEA_1920X1080P30, &hdmi_timings_1080p60 },
  443. { V4L2_DV_1080P50, false, V4L2_DV_BT_CEA_1920X1080P50, &hdmi_timings_1080p50 },
  444. { V4L2_DV_1080I50, false, V4L2_DV_BT_CEA_1920X1080I50, &hdmi_timings_1080i50 },
  445. { V4L2_DV_1080I60, false, V4L2_DV_BT_CEA_1920X1080I60, &hdmi_timings_1080i60 },
  446. { V4L2_DV_1080P60, false, V4L2_DV_BT_CEA_1920X1080P60, &hdmi_timings_1080p60 },
  447. };
  448. static const struct hdmi_timings *hdmi_preset2timings(u32 preset)
  449. {
  450. int i;
  451. for (i = 0; i < ARRAY_SIZE(hdmi_timings); ++i)
  452. if (hdmi_timings[i].preset == preset)
  453. return hdmi_timings[i].hdmi_timings;
  454. return NULL;
  455. }
  456. static int hdmi_streamon(struct hdmi_device *hdev)
  457. {
  458. struct device *dev = hdev->dev;
  459. struct hdmi_resources *res = &hdev->res;
  460. int ret, tries;
  461. dev_dbg(dev, "%s\n", __func__);
  462. ret = hdmi_conf_apply(hdev);
  463. if (ret)
  464. return ret;
  465. ret = v4l2_subdev_call(hdev->phy_sd, video, s_stream, 1);
  466. if (ret)
  467. return ret;
  468. /* waiting for HDMIPHY's PLL to get to steady state */
  469. for (tries = 100; tries; --tries) {
  470. u32 val = hdmi_read(hdev, HDMI_PHY_STATUS);
  471. if (val & HDMI_PHY_STATUS_READY)
  472. break;
  473. mdelay(1);
  474. }
  475. /* steady state not achieved */
  476. if (tries == 0) {
  477. dev_err(dev, "hdmiphy's pll could not reach steady state.\n");
  478. v4l2_subdev_call(hdev->phy_sd, video, s_stream, 0);
  479. hdmi_dumpregs(hdev, "hdmiphy - s_stream");
  480. return -EIO;
  481. }
  482. /* starting MHL */
  483. ret = v4l2_subdev_call(hdev->mhl_sd, video, s_stream, 1);
  484. if (hdev->mhl_sd && ret) {
  485. v4l2_subdev_call(hdev->phy_sd, video, s_stream, 0);
  486. hdmi_dumpregs(hdev, "mhl - s_stream");
  487. return -EIO;
  488. }
  489. /* hdmiphy clock is used for HDMI in streaming mode */
  490. clk_disable(res->sclk_hdmi);
  491. clk_set_parent(res->sclk_hdmi, res->sclk_hdmiphy);
  492. clk_enable(res->sclk_hdmi);
  493. /* enable HDMI and timing generator */
  494. hdmi_write_mask(hdev, HDMI_CON_0, ~0, HDMI_EN);
  495. hdmi_write_mask(hdev, HDMI_TG_CMD, ~0, HDMI_TG_EN);
  496. hdmi_dumpregs(hdev, "streamon");
  497. return 0;
  498. }
  499. static int hdmi_streamoff(struct hdmi_device *hdev)
  500. {
  501. struct device *dev = hdev->dev;
  502. struct hdmi_resources *res = &hdev->res;
  503. dev_dbg(dev, "%s\n", __func__);
  504. hdmi_write_mask(hdev, HDMI_CON_0, 0, HDMI_EN);
  505. hdmi_write_mask(hdev, HDMI_TG_CMD, 0, HDMI_TG_EN);
  506. /* pixel(vpll) clock is used for HDMI in config mode */
  507. clk_disable(res->sclk_hdmi);
  508. clk_set_parent(res->sclk_hdmi, res->sclk_pixel);
  509. clk_enable(res->sclk_hdmi);
  510. v4l2_subdev_call(hdev->mhl_sd, video, s_stream, 0);
  511. v4l2_subdev_call(hdev->phy_sd, video, s_stream, 0);
  512. hdmi_dumpregs(hdev, "streamoff");
  513. return 0;
  514. }
  515. static int hdmi_s_stream(struct v4l2_subdev *sd, int enable)
  516. {
  517. struct hdmi_device *hdev = sd_to_hdmi_dev(sd);
  518. struct device *dev = hdev->dev;
  519. dev_dbg(dev, "%s(%d)\n", __func__, enable);
  520. if (enable)
  521. return hdmi_streamon(hdev);
  522. return hdmi_streamoff(hdev);
  523. }
  524. static void hdmi_resource_poweron(struct hdmi_resources *res)
  525. {
  526. /* turn HDMI power on */
  527. regulator_bulk_enable(res->regul_count, res->regul_bulk);
  528. /* power-on hdmi physical interface */
  529. clk_enable(res->hdmiphy);
  530. /* use VPP as parent clock; HDMIPHY is not working yet */
  531. clk_set_parent(res->sclk_hdmi, res->sclk_pixel);
  532. /* turn clocks on */
  533. clk_enable(res->sclk_hdmi);
  534. }
  535. static void hdmi_resource_poweroff(struct hdmi_resources *res)
  536. {
  537. /* turn clocks off */
  538. clk_disable(res->sclk_hdmi);
  539. /* power-off hdmiphy */
  540. clk_disable(res->hdmiphy);
  541. /* turn HDMI power off */
  542. regulator_bulk_disable(res->regul_count, res->regul_bulk);
  543. }
  544. static int hdmi_s_power(struct v4l2_subdev *sd, int on)
  545. {
  546. struct hdmi_device *hdev = sd_to_hdmi_dev(sd);
  547. int ret;
  548. if (on)
  549. ret = pm_runtime_get_sync(hdev->dev);
  550. else
  551. ret = pm_runtime_put_sync(hdev->dev);
  552. /* only values < 0 indicate errors */
  553. return IS_ERR_VALUE(ret) ? ret : 0;
  554. }
  555. static int hdmi_s_dv_preset(struct v4l2_subdev *sd,
  556. struct v4l2_dv_preset *preset)
  557. {
  558. struct hdmi_device *hdev = sd_to_hdmi_dev(sd);
  559. struct device *dev = hdev->dev;
  560. const struct hdmi_timings *conf;
  561. conf = hdmi_preset2timings(preset->preset);
  562. if (conf == NULL) {
  563. dev_err(dev, "preset (%u) not supported\n", preset->preset);
  564. return -EINVAL;
  565. }
  566. hdev->cur_conf = conf;
  567. hdev->cur_conf_dirty = 1;
  568. hdev->cur_preset = preset->preset;
  569. return 0;
  570. }
  571. static int hdmi_g_dv_preset(struct v4l2_subdev *sd,
  572. struct v4l2_dv_preset *preset)
  573. {
  574. memset(preset, 0, sizeof(*preset));
  575. preset->preset = sd_to_hdmi_dev(sd)->cur_preset;
  576. return 0;
  577. }
  578. static int hdmi_s_dv_timings(struct v4l2_subdev *sd,
  579. struct v4l2_dv_timings *timings)
  580. {
  581. struct hdmi_device *hdev = sd_to_hdmi_dev(sd);
  582. struct device *dev = hdev->dev;
  583. int i;
  584. for (i = 0; i < ARRAY_SIZE(hdmi_timings); i++)
  585. if (v4l_match_dv_timings(&hdmi_timings[i].dv_timings,
  586. timings, 0))
  587. break;
  588. if (i == ARRAY_SIZE(hdmi_timings)) {
  589. dev_err(dev, "timings not supported\n");
  590. return -EINVAL;
  591. }
  592. hdev->cur_conf = hdmi_timings[i].hdmi_timings;
  593. hdev->cur_conf_dirty = 1;
  594. hdev->cur_timings = *timings;
  595. if (!hdmi_timings[i].reduced_fps)
  596. hdev->cur_timings.bt.flags &= ~V4L2_DV_FL_CAN_REDUCE_FPS;
  597. return 0;
  598. }
  599. static int hdmi_g_dv_timings(struct v4l2_subdev *sd,
  600. struct v4l2_dv_timings *timings)
  601. {
  602. *timings = sd_to_hdmi_dev(sd)->cur_timings;
  603. return 0;
  604. }
  605. static int hdmi_g_mbus_fmt(struct v4l2_subdev *sd,
  606. struct v4l2_mbus_framefmt *fmt)
  607. {
  608. struct hdmi_device *hdev = sd_to_hdmi_dev(sd);
  609. const struct hdmi_timings *t = hdev->cur_conf;
  610. dev_dbg(hdev->dev, "%s\n", __func__);
  611. if (!hdev->cur_conf)
  612. return -EINVAL;
  613. memset(fmt, 0, sizeof(*fmt));
  614. fmt->width = t->hact.end - t->hact.beg;
  615. fmt->height = t->vact[0].end - t->vact[0].beg;
  616. fmt->code = V4L2_MBUS_FMT_FIXED; /* means RGB888 */
  617. fmt->colorspace = V4L2_COLORSPACE_SRGB;
  618. if (t->interlaced) {
  619. fmt->field = V4L2_FIELD_INTERLACED;
  620. fmt->height *= 2;
  621. } else {
  622. fmt->field = V4L2_FIELD_NONE;
  623. }
  624. return 0;
  625. }
  626. static int hdmi_enum_dv_presets(struct v4l2_subdev *sd,
  627. struct v4l2_dv_enum_preset *preset)
  628. {
  629. if (preset->index >= ARRAY_SIZE(hdmi_timings))
  630. return -EINVAL;
  631. return v4l_fill_dv_preset_info(hdmi_timings[preset->index].preset,
  632. preset);
  633. }
  634. static int hdmi_enum_dv_timings(struct v4l2_subdev *sd,
  635. struct v4l2_enum_dv_timings *timings)
  636. {
  637. if (timings->index >= ARRAY_SIZE(hdmi_timings))
  638. return -EINVAL;
  639. timings->timings = hdmi_timings[timings->index].dv_timings;
  640. if (!hdmi_timings[timings->index].reduced_fps)
  641. timings->timings.bt.flags &= ~V4L2_DV_FL_CAN_REDUCE_FPS;
  642. return 0;
  643. }
  644. static int hdmi_dv_timings_cap(struct v4l2_subdev *sd,
  645. struct v4l2_dv_timings_cap *cap)
  646. {
  647. struct hdmi_device *hdev = sd_to_hdmi_dev(sd);
  648. /* Let the phy fill in the pixelclock range */
  649. v4l2_subdev_call(hdev->phy_sd, video, dv_timings_cap, cap);
  650. cap->type = V4L2_DV_BT_656_1120;
  651. cap->bt.min_width = 720;
  652. cap->bt.max_width = 1920;
  653. cap->bt.min_height = 480;
  654. cap->bt.max_height = 1080;
  655. cap->bt.standards = V4L2_DV_BT_STD_CEA861;
  656. cap->bt.capabilities = V4L2_DV_BT_CAP_INTERLACED |
  657. V4L2_DV_BT_CAP_PROGRESSIVE;
  658. return 0;
  659. }
  660. static const struct v4l2_subdev_core_ops hdmi_sd_core_ops = {
  661. .s_power = hdmi_s_power,
  662. };
  663. static const struct v4l2_subdev_video_ops hdmi_sd_video_ops = {
  664. .s_dv_preset = hdmi_s_dv_preset,
  665. .g_dv_preset = hdmi_g_dv_preset,
  666. .enum_dv_presets = hdmi_enum_dv_presets,
  667. .s_dv_timings = hdmi_s_dv_timings,
  668. .g_dv_timings = hdmi_g_dv_timings,
  669. .enum_dv_timings = hdmi_enum_dv_timings,
  670. .dv_timings_cap = hdmi_dv_timings_cap,
  671. .g_mbus_fmt = hdmi_g_mbus_fmt,
  672. .s_stream = hdmi_s_stream,
  673. };
  674. static const struct v4l2_subdev_ops hdmi_sd_ops = {
  675. .core = &hdmi_sd_core_ops,
  676. .video = &hdmi_sd_video_ops,
  677. };
  678. static int hdmi_runtime_suspend(struct device *dev)
  679. {
  680. struct v4l2_subdev *sd = dev_get_drvdata(dev);
  681. struct hdmi_device *hdev = sd_to_hdmi_dev(sd);
  682. dev_dbg(dev, "%s\n", __func__);
  683. v4l2_subdev_call(hdev->mhl_sd, core, s_power, 0);
  684. hdmi_resource_poweroff(&hdev->res);
  685. /* flag that device context is lost */
  686. hdev->cur_conf_dirty = 1;
  687. return 0;
  688. }
  689. static int hdmi_runtime_resume(struct device *dev)
  690. {
  691. struct v4l2_subdev *sd = dev_get_drvdata(dev);
  692. struct hdmi_device *hdev = sd_to_hdmi_dev(sd);
  693. int ret = 0;
  694. dev_dbg(dev, "%s\n", __func__);
  695. hdmi_resource_poweron(&hdev->res);
  696. /* starting MHL */
  697. ret = v4l2_subdev_call(hdev->mhl_sd, core, s_power, 1);
  698. if (hdev->mhl_sd && ret)
  699. goto fail;
  700. dev_dbg(dev, "poweron succeed\n");
  701. return 0;
  702. fail:
  703. hdmi_resource_poweroff(&hdev->res);
  704. dev_err(dev, "poweron failed\n");
  705. return ret;
  706. }
  707. static const struct dev_pm_ops hdmi_pm_ops = {
  708. .runtime_suspend = hdmi_runtime_suspend,
  709. .runtime_resume = hdmi_runtime_resume,
  710. };
  711. static void hdmi_resources_cleanup(struct hdmi_device *hdev)
  712. {
  713. struct hdmi_resources *res = &hdev->res;
  714. dev_dbg(hdev->dev, "HDMI resource cleanup\n");
  715. /* put clocks, power */
  716. if (res->regul_count)
  717. regulator_bulk_free(res->regul_count, res->regul_bulk);
  718. /* kfree is NULL-safe */
  719. kfree(res->regul_bulk);
  720. if (!IS_ERR_OR_NULL(res->hdmiphy))
  721. clk_put(res->hdmiphy);
  722. if (!IS_ERR_OR_NULL(res->sclk_hdmiphy))
  723. clk_put(res->sclk_hdmiphy);
  724. if (!IS_ERR_OR_NULL(res->sclk_pixel))
  725. clk_put(res->sclk_pixel);
  726. if (!IS_ERR_OR_NULL(res->sclk_hdmi))
  727. clk_put(res->sclk_hdmi);
  728. if (!IS_ERR_OR_NULL(res->hdmi))
  729. clk_put(res->hdmi);
  730. memset(res, 0, sizeof(*res));
  731. }
  732. static int hdmi_resources_init(struct hdmi_device *hdev)
  733. {
  734. struct device *dev = hdev->dev;
  735. struct hdmi_resources *res = &hdev->res;
  736. static char *supply[] = {
  737. "hdmi-en",
  738. "vdd",
  739. "vdd_osc",
  740. "vdd_pll",
  741. };
  742. int i, ret;
  743. dev_dbg(dev, "HDMI resource init\n");
  744. memset(res, 0, sizeof(*res));
  745. /* get clocks, power */
  746. res->hdmi = clk_get(dev, "hdmi");
  747. if (IS_ERR(res->hdmi)) {
  748. dev_err(dev, "failed to get clock 'hdmi'\n");
  749. goto fail;
  750. }
  751. res->sclk_hdmi = clk_get(dev, "sclk_hdmi");
  752. if (IS_ERR(res->sclk_hdmi)) {
  753. dev_err(dev, "failed to get clock 'sclk_hdmi'\n");
  754. goto fail;
  755. }
  756. res->sclk_pixel = clk_get(dev, "sclk_pixel");
  757. if (IS_ERR(res->sclk_pixel)) {
  758. dev_err(dev, "failed to get clock 'sclk_pixel'\n");
  759. goto fail;
  760. }
  761. res->sclk_hdmiphy = clk_get(dev, "sclk_hdmiphy");
  762. if (IS_ERR(res->sclk_hdmiphy)) {
  763. dev_err(dev, "failed to get clock 'sclk_hdmiphy'\n");
  764. goto fail;
  765. }
  766. res->hdmiphy = clk_get(dev, "hdmiphy");
  767. if (IS_ERR(res->hdmiphy)) {
  768. dev_err(dev, "failed to get clock 'hdmiphy'\n");
  769. goto fail;
  770. }
  771. res->regul_bulk = kcalloc(ARRAY_SIZE(supply),
  772. sizeof(res->regul_bulk[0]), GFP_KERNEL);
  773. if (!res->regul_bulk) {
  774. dev_err(dev, "failed to get memory for regulators\n");
  775. goto fail;
  776. }
  777. for (i = 0; i < ARRAY_SIZE(supply); ++i) {
  778. res->regul_bulk[i].supply = supply[i];
  779. res->regul_bulk[i].consumer = NULL;
  780. }
  781. ret = regulator_bulk_get(dev, ARRAY_SIZE(supply), res->regul_bulk);
  782. if (ret) {
  783. dev_err(dev, "failed to get regulators\n");
  784. goto fail;
  785. }
  786. res->regul_count = ARRAY_SIZE(supply);
  787. return 0;
  788. fail:
  789. dev_err(dev, "HDMI resource init - failed\n");
  790. hdmi_resources_cleanup(hdev);
  791. return -ENODEV;
  792. }
  793. static int hdmi_probe(struct platform_device *pdev)
  794. {
  795. struct device *dev = &pdev->dev;
  796. struct resource *res;
  797. struct i2c_adapter *adapter;
  798. struct v4l2_subdev *sd;
  799. struct hdmi_device *hdmi_dev = NULL;
  800. struct s5p_hdmi_platform_data *pdata = dev->platform_data;
  801. int ret;
  802. dev_dbg(dev, "probe start\n");
  803. if (!pdata) {
  804. dev_err(dev, "platform data is missing\n");
  805. ret = -ENODEV;
  806. goto fail;
  807. }
  808. hdmi_dev = devm_kzalloc(&pdev->dev, sizeof(*hdmi_dev), GFP_KERNEL);
  809. if (!hdmi_dev) {
  810. dev_err(dev, "out of memory\n");
  811. ret = -ENOMEM;
  812. goto fail;
  813. }
  814. hdmi_dev->dev = dev;
  815. ret = hdmi_resources_init(hdmi_dev);
  816. if (ret)
  817. goto fail;
  818. /* mapping HDMI registers */
  819. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  820. if (res == NULL) {
  821. dev_err(dev, "get memory resource failed.\n");
  822. ret = -ENXIO;
  823. goto fail_init;
  824. }
  825. hdmi_dev->regs = devm_ioremap(&pdev->dev, res->start,
  826. resource_size(res));
  827. if (hdmi_dev->regs == NULL) {
  828. dev_err(dev, "register mapping failed.\n");
  829. ret = -ENXIO;
  830. goto fail_init;
  831. }
  832. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  833. if (res == NULL) {
  834. dev_err(dev, "get interrupt resource failed.\n");
  835. ret = -ENXIO;
  836. goto fail_init;
  837. }
  838. ret = devm_request_irq(&pdev->dev, res->start, hdmi_irq_handler, 0,
  839. "hdmi", hdmi_dev);
  840. if (ret) {
  841. dev_err(dev, "request interrupt failed.\n");
  842. goto fail_init;
  843. }
  844. hdmi_dev->irq = res->start;
  845. /* setting v4l2 name to prevent WARN_ON in v4l2_device_register */
  846. strlcpy(hdmi_dev->v4l2_dev.name, dev_name(dev),
  847. sizeof(hdmi_dev->v4l2_dev.name));
  848. /* passing NULL owner prevents driver from erasing drvdata */
  849. ret = v4l2_device_register(NULL, &hdmi_dev->v4l2_dev);
  850. if (ret) {
  851. dev_err(dev, "could not register v4l2 device.\n");
  852. goto fail_init;
  853. }
  854. /* testing if hdmiphy info is present */
  855. if (!pdata->hdmiphy_info) {
  856. dev_err(dev, "hdmiphy info is missing in platform data\n");
  857. ret = -ENXIO;
  858. goto fail_vdev;
  859. }
  860. adapter = i2c_get_adapter(pdata->hdmiphy_bus);
  861. if (adapter == NULL) {
  862. dev_err(dev, "hdmiphy adapter request failed\n");
  863. ret = -ENXIO;
  864. goto fail_vdev;
  865. }
  866. hdmi_dev->phy_sd = v4l2_i2c_new_subdev_board(&hdmi_dev->v4l2_dev,
  867. adapter, pdata->hdmiphy_info, NULL);
  868. /* on failure or not adapter is no longer useful */
  869. i2c_put_adapter(adapter);
  870. if (hdmi_dev->phy_sd == NULL) {
  871. dev_err(dev, "missing subdev for hdmiphy\n");
  872. ret = -ENODEV;
  873. goto fail_vdev;
  874. }
  875. /* initialization of MHL interface if present */
  876. if (pdata->mhl_info) {
  877. adapter = i2c_get_adapter(pdata->mhl_bus);
  878. if (adapter == NULL) {
  879. dev_err(dev, "MHL adapter request failed\n");
  880. ret = -ENXIO;
  881. goto fail_vdev;
  882. }
  883. hdmi_dev->mhl_sd = v4l2_i2c_new_subdev_board(
  884. &hdmi_dev->v4l2_dev, adapter,
  885. pdata->mhl_info, NULL);
  886. /* on failure or not adapter is no longer useful */
  887. i2c_put_adapter(adapter);
  888. if (hdmi_dev->mhl_sd == NULL) {
  889. dev_err(dev, "missing subdev for MHL\n");
  890. ret = -ENODEV;
  891. goto fail_vdev;
  892. }
  893. }
  894. clk_enable(hdmi_dev->res.hdmi);
  895. pm_runtime_enable(dev);
  896. sd = &hdmi_dev->sd;
  897. v4l2_subdev_init(sd, &hdmi_sd_ops);
  898. sd->owner = THIS_MODULE;
  899. strlcpy(sd->name, "s5p-hdmi", sizeof(sd->name));
  900. hdmi_dev->cur_preset = HDMI_DEFAULT_PRESET;
  901. /* FIXME: missing fail preset is not supported */
  902. hdmi_dev->cur_conf = hdmi_preset2timings(hdmi_dev->cur_preset);
  903. hdmi_dev->cur_conf_dirty = 1;
  904. /* storing subdev for call that have only access to struct device */
  905. dev_set_drvdata(dev, sd);
  906. dev_info(dev, "probe successful\n");
  907. return 0;
  908. fail_vdev:
  909. v4l2_device_unregister(&hdmi_dev->v4l2_dev);
  910. fail_init:
  911. hdmi_resources_cleanup(hdmi_dev);
  912. fail:
  913. dev_err(dev, "probe failed\n");
  914. return ret;
  915. }
  916. static int hdmi_remove(struct platform_device *pdev)
  917. {
  918. struct device *dev = &pdev->dev;
  919. struct v4l2_subdev *sd = dev_get_drvdata(dev);
  920. struct hdmi_device *hdmi_dev = sd_to_hdmi_dev(sd);
  921. pm_runtime_disable(dev);
  922. clk_disable(hdmi_dev->res.hdmi);
  923. v4l2_device_unregister(&hdmi_dev->v4l2_dev);
  924. disable_irq(hdmi_dev->irq);
  925. hdmi_resources_cleanup(hdmi_dev);
  926. dev_info(dev, "remove successful\n");
  927. return 0;
  928. }
  929. static struct platform_driver hdmi_driver __refdata = {
  930. .probe = hdmi_probe,
  931. .remove = hdmi_remove,
  932. .id_table = hdmi_driver_types,
  933. .driver = {
  934. .name = "s5p-hdmi",
  935. .owner = THIS_MODULE,
  936. .pm = &hdmi_pm_ops,
  937. }
  938. };
  939. module_platform_driver(hdmi_driver);