intel_sideband.c 6.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241
  1. /*
  2. * Copyright © 2013 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. */
  24. #include "i915_drv.h"
  25. #include "intel_drv.h"
  26. /* IOSF sideband */
  27. static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn,
  28. u32 port, u32 opcode, u32 addr, u32 *val)
  29. {
  30. u32 cmd, be = 0xf, bar = 0;
  31. bool is_read = (opcode == PUNIT_OPCODE_REG_READ ||
  32. opcode == DPIO_OPCODE_REG_READ);
  33. cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
  34. (port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) |
  35. (bar << IOSF_BAR_SHIFT);
  36. WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
  37. if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) {
  38. DRM_DEBUG_DRIVER("IOSF sideband idle wait (%s) timed out\n",
  39. is_read ? "read" : "write");
  40. return -EAGAIN;
  41. }
  42. I915_WRITE(VLV_IOSF_ADDR, addr);
  43. if (!is_read)
  44. I915_WRITE(VLV_IOSF_DATA, *val);
  45. I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);
  46. if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) {
  47. DRM_DEBUG_DRIVER("IOSF sideband finish wait (%s) timed out\n",
  48. is_read ? "read" : "write");
  49. return -ETIMEDOUT;
  50. }
  51. if (is_read)
  52. *val = I915_READ(VLV_IOSF_DATA);
  53. I915_WRITE(VLV_IOSF_DATA, 0);
  54. return 0;
  55. }
  56. u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr)
  57. {
  58. u32 val = 0;
  59. WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
  60. mutex_lock(&dev_priv->dpio_lock);
  61. vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT,
  62. PUNIT_OPCODE_REG_READ, addr, &val);
  63. mutex_unlock(&dev_priv->dpio_lock);
  64. return val;
  65. }
  66. void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
  67. {
  68. WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
  69. mutex_lock(&dev_priv->dpio_lock);
  70. vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT,
  71. PUNIT_OPCODE_REG_WRITE, addr, &val);
  72. mutex_unlock(&dev_priv->dpio_lock);
  73. }
  74. u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
  75. {
  76. u32 val = 0;
  77. WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
  78. mutex_lock(&dev_priv->dpio_lock);
  79. vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_NC,
  80. PUNIT_OPCODE_REG_READ, addr, &val);
  81. mutex_unlock(&dev_priv->dpio_lock);
  82. return val;
  83. }
  84. u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg)
  85. {
  86. u32 val = 0;
  87. vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPIO_NC,
  88. PUNIT_OPCODE_REG_READ, reg, &val);
  89. return val;
  90. }
  91. void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
  92. {
  93. vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPIO_NC,
  94. PUNIT_OPCODE_REG_WRITE, reg, &val);
  95. }
  96. u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg)
  97. {
  98. u32 val = 0;
  99. vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCK,
  100. PUNIT_OPCODE_REG_READ, reg, &val);
  101. return val;
  102. }
  103. void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
  104. {
  105. vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCK,
  106. PUNIT_OPCODE_REG_WRITE, reg, &val);
  107. }
  108. u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg)
  109. {
  110. u32 val = 0;
  111. vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCU,
  112. PUNIT_OPCODE_REG_READ, reg, &val);
  113. return val;
  114. }
  115. void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
  116. {
  117. vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCU,
  118. PUNIT_OPCODE_REG_WRITE, reg, &val);
  119. }
  120. u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg)
  121. {
  122. u32 val = 0;
  123. vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPS_CORE,
  124. PUNIT_OPCODE_REG_READ, reg, &val);
  125. return val;
  126. }
  127. void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
  128. {
  129. vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPS_CORE,
  130. PUNIT_OPCODE_REG_WRITE, reg, &val);
  131. }
  132. static u32 vlv_get_phy_port(enum pipe pipe)
  133. {
  134. u32 port = IOSF_PORT_DPIO;
  135. WARN_ON ((pipe != PIPE_A) && (pipe != PIPE_B));
  136. return port;
  137. }
  138. u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg)
  139. {
  140. u32 val = 0;
  141. vlv_sideband_rw(dev_priv, DPIO_DEVFN, vlv_get_phy_port(pipe),
  142. DPIO_OPCODE_REG_READ, reg, &val);
  143. return val;
  144. }
  145. void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val)
  146. {
  147. vlv_sideband_rw(dev_priv, DPIO_DEVFN, vlv_get_phy_port(pipe),
  148. DPIO_OPCODE_REG_WRITE, reg, &val);
  149. }
  150. /* SBI access */
  151. u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
  152. enum intel_sbi_destination destination)
  153. {
  154. u32 value = 0;
  155. WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
  156. if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
  157. 100)) {
  158. DRM_ERROR("timeout waiting for SBI to become ready\n");
  159. return 0;
  160. }
  161. I915_WRITE(SBI_ADDR, (reg << 16));
  162. if (destination == SBI_ICLK)
  163. value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
  164. else
  165. value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
  166. I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
  167. if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
  168. 100)) {
  169. DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
  170. return 0;
  171. }
  172. return I915_READ(SBI_DATA);
  173. }
  174. void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
  175. enum intel_sbi_destination destination)
  176. {
  177. u32 tmp;
  178. WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
  179. if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
  180. 100)) {
  181. DRM_ERROR("timeout waiting for SBI to become ready\n");
  182. return;
  183. }
  184. I915_WRITE(SBI_ADDR, (reg << 16));
  185. I915_WRITE(SBI_DATA, value);
  186. if (destination == SBI_ICLK)
  187. tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
  188. else
  189. tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
  190. I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
  191. if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
  192. 100)) {
  193. DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
  194. return;
  195. }
  196. }