intel_dp.c 100 KB

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  1. /*
  2. * Copyright © 2008 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Keith Packard <keithp@keithp.com>
  25. *
  26. */
  27. #include <linux/i2c.h>
  28. #include <linux/slab.h>
  29. #include <linux/export.h>
  30. #include <drm/drmP.h>
  31. #include <drm/drm_crtc.h>
  32. #include <drm/drm_crtc_helper.h>
  33. #include <drm/drm_edid.h>
  34. #include "intel_drv.h"
  35. #include <drm/i915_drm.h>
  36. #include "i915_drv.h"
  37. #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
  38. struct dp_link_dpll {
  39. int link_bw;
  40. struct dpll dpll;
  41. };
  42. static const struct dp_link_dpll gen4_dpll[] = {
  43. { DP_LINK_BW_1_62,
  44. { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  45. { DP_LINK_BW_2_7,
  46. { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  47. };
  48. static const struct dp_link_dpll pch_dpll[] = {
  49. { DP_LINK_BW_1_62,
  50. { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  51. { DP_LINK_BW_2_7,
  52. { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  53. };
  54. static const struct dp_link_dpll vlv_dpll[] = {
  55. { DP_LINK_BW_1_62,
  56. { .p1 = 3, .p2 = 2, .n = 5, .m1 = 5, .m2 = 3 } },
  57. { DP_LINK_BW_2_7,
  58. { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  59. };
  60. /**
  61. * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  62. * @intel_dp: DP struct
  63. *
  64. * If a CPU or PCH DP output is attached to an eDP panel, this function
  65. * will return true, and false otherwise.
  66. */
  67. static bool is_edp(struct intel_dp *intel_dp)
  68. {
  69. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  70. return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
  71. }
  72. static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
  73. {
  74. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  75. return intel_dig_port->base.base.dev;
  76. }
  77. static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  78. {
  79. return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
  80. }
  81. static void intel_dp_link_down(struct intel_dp *intel_dp);
  82. static int
  83. intel_dp_max_link_bw(struct intel_dp *intel_dp)
  84. {
  85. int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
  86. switch (max_link_bw) {
  87. case DP_LINK_BW_1_62:
  88. case DP_LINK_BW_2_7:
  89. break;
  90. case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
  91. max_link_bw = DP_LINK_BW_2_7;
  92. break;
  93. default:
  94. WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
  95. max_link_bw);
  96. max_link_bw = DP_LINK_BW_1_62;
  97. break;
  98. }
  99. return max_link_bw;
  100. }
  101. /*
  102. * The units on the numbers in the next two are... bizarre. Examples will
  103. * make it clearer; this one parallels an example in the eDP spec.
  104. *
  105. * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
  106. *
  107. * 270000 * 1 * 8 / 10 == 216000
  108. *
  109. * The actual data capacity of that configuration is 2.16Gbit/s, so the
  110. * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
  111. * or equivalently, kilopixels per second - so for 1680x1050R it'd be
  112. * 119000. At 18bpp that's 2142000 kilobits per second.
  113. *
  114. * Thus the strange-looking division by 10 in intel_dp_link_required, to
  115. * get the result in decakilobits instead of kilobits.
  116. */
  117. static int
  118. intel_dp_link_required(int pixel_clock, int bpp)
  119. {
  120. return (pixel_clock * bpp + 9) / 10;
  121. }
  122. static int
  123. intel_dp_max_data_rate(int max_link_clock, int max_lanes)
  124. {
  125. return (max_link_clock * max_lanes * 8) / 10;
  126. }
  127. static int
  128. intel_dp_mode_valid(struct drm_connector *connector,
  129. struct drm_display_mode *mode)
  130. {
  131. struct intel_dp *intel_dp = intel_attached_dp(connector);
  132. struct intel_connector *intel_connector = to_intel_connector(connector);
  133. struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
  134. int target_clock = mode->clock;
  135. int max_rate, mode_rate, max_lanes, max_link_clock;
  136. if (is_edp(intel_dp) && fixed_mode) {
  137. if (mode->hdisplay > fixed_mode->hdisplay)
  138. return MODE_PANEL;
  139. if (mode->vdisplay > fixed_mode->vdisplay)
  140. return MODE_PANEL;
  141. target_clock = fixed_mode->clock;
  142. }
  143. max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
  144. max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
  145. max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
  146. mode_rate = intel_dp_link_required(target_clock, 18);
  147. if (mode_rate > max_rate)
  148. return MODE_CLOCK_HIGH;
  149. if (mode->clock < 10000)
  150. return MODE_CLOCK_LOW;
  151. if (mode->flags & DRM_MODE_FLAG_DBLCLK)
  152. return MODE_H_ILLEGAL;
  153. return MODE_OK;
  154. }
  155. static uint32_t
  156. pack_aux(uint8_t *src, int src_bytes)
  157. {
  158. int i;
  159. uint32_t v = 0;
  160. if (src_bytes > 4)
  161. src_bytes = 4;
  162. for (i = 0; i < src_bytes; i++)
  163. v |= ((uint32_t) src[i]) << ((3-i) * 8);
  164. return v;
  165. }
  166. static void
  167. unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
  168. {
  169. int i;
  170. if (dst_bytes > 4)
  171. dst_bytes = 4;
  172. for (i = 0; i < dst_bytes; i++)
  173. dst[i] = src >> ((3-i) * 8);
  174. }
  175. /* hrawclock is 1/4 the FSB frequency */
  176. static int
  177. intel_hrawclk(struct drm_device *dev)
  178. {
  179. struct drm_i915_private *dev_priv = dev->dev_private;
  180. uint32_t clkcfg;
  181. /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
  182. if (IS_VALLEYVIEW(dev))
  183. return 200;
  184. clkcfg = I915_READ(CLKCFG);
  185. switch (clkcfg & CLKCFG_FSB_MASK) {
  186. case CLKCFG_FSB_400:
  187. return 100;
  188. case CLKCFG_FSB_533:
  189. return 133;
  190. case CLKCFG_FSB_667:
  191. return 166;
  192. case CLKCFG_FSB_800:
  193. return 200;
  194. case CLKCFG_FSB_1067:
  195. return 266;
  196. case CLKCFG_FSB_1333:
  197. return 333;
  198. /* these two are just a guess; one of them might be right */
  199. case CLKCFG_FSB_1600:
  200. case CLKCFG_FSB_1600_ALT:
  201. return 400;
  202. default:
  203. return 133;
  204. }
  205. }
  206. static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
  207. {
  208. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  209. struct drm_i915_private *dev_priv = dev->dev_private;
  210. u32 pp_stat_reg;
  211. pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
  212. return (I915_READ(pp_stat_reg) & PP_ON) != 0;
  213. }
  214. static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
  215. {
  216. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  217. struct drm_i915_private *dev_priv = dev->dev_private;
  218. u32 pp_ctrl_reg;
  219. pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
  220. return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
  221. }
  222. static void
  223. intel_dp_check_edp(struct intel_dp *intel_dp)
  224. {
  225. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  226. struct drm_i915_private *dev_priv = dev->dev_private;
  227. u32 pp_stat_reg, pp_ctrl_reg;
  228. if (!is_edp(intel_dp))
  229. return;
  230. pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
  231. pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
  232. if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
  233. WARN(1, "eDP powered off while attempting aux channel communication.\n");
  234. DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
  235. I915_READ(pp_stat_reg),
  236. I915_READ(pp_ctrl_reg));
  237. }
  238. }
  239. static uint32_t
  240. intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
  241. {
  242. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  243. struct drm_device *dev = intel_dig_port->base.base.dev;
  244. struct drm_i915_private *dev_priv = dev->dev_private;
  245. uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
  246. uint32_t status;
  247. bool done;
  248. #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
  249. if (has_aux_irq)
  250. done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
  251. msecs_to_jiffies_timeout(10));
  252. else
  253. done = wait_for_atomic(C, 10) == 0;
  254. if (!done)
  255. DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
  256. has_aux_irq);
  257. #undef C
  258. return status;
  259. }
  260. static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp,
  261. int index)
  262. {
  263. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  264. struct drm_device *dev = intel_dig_port->base.base.dev;
  265. struct drm_i915_private *dev_priv = dev->dev_private;
  266. /* The clock divider is based off the hrawclk,
  267. * and would like to run at 2MHz. So, take the
  268. * hrawclk value and divide by 2 and use that
  269. *
  270. * Note that PCH attached eDP panels should use a 125MHz input
  271. * clock divider.
  272. */
  273. if (IS_VALLEYVIEW(dev)) {
  274. return index ? 0 : 100;
  275. } else if (intel_dig_port->port == PORT_A) {
  276. if (index)
  277. return 0;
  278. if (HAS_DDI(dev))
  279. return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
  280. else if (IS_GEN6(dev) || IS_GEN7(dev))
  281. return 200; /* SNB & IVB eDP input clock at 400Mhz */
  282. else
  283. return 225; /* eDP input clock at 450Mhz */
  284. } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
  285. /* Workaround for non-ULT HSW */
  286. switch (index) {
  287. case 0: return 63;
  288. case 1: return 72;
  289. default: return 0;
  290. }
  291. } else if (HAS_PCH_SPLIT(dev)) {
  292. return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
  293. } else {
  294. return index ? 0 :intel_hrawclk(dev) / 2;
  295. }
  296. }
  297. static int
  298. intel_dp_aux_ch(struct intel_dp *intel_dp,
  299. uint8_t *send, int send_bytes,
  300. uint8_t *recv, int recv_size)
  301. {
  302. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  303. struct drm_device *dev = intel_dig_port->base.base.dev;
  304. struct drm_i915_private *dev_priv = dev->dev_private;
  305. uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
  306. uint32_t ch_data = ch_ctl + 4;
  307. uint32_t aux_clock_divider;
  308. int i, ret, recv_bytes;
  309. uint32_t status;
  310. int try, precharge, clock = 0;
  311. bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
  312. /* dp aux is extremely sensitive to irq latency, hence request the
  313. * lowest possible wakeup latency and so prevent the cpu from going into
  314. * deep sleep states.
  315. */
  316. pm_qos_update_request(&dev_priv->pm_qos, 0);
  317. intel_dp_check_edp(intel_dp);
  318. if (IS_GEN6(dev))
  319. precharge = 3;
  320. else
  321. precharge = 5;
  322. intel_aux_display_runtime_get(dev_priv);
  323. /* Try to wait for any previous AUX channel activity */
  324. for (try = 0; try < 3; try++) {
  325. status = I915_READ_NOTRACE(ch_ctl);
  326. if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
  327. break;
  328. msleep(1);
  329. }
  330. if (try == 3) {
  331. WARN(1, "dp_aux_ch not started status 0x%08x\n",
  332. I915_READ(ch_ctl));
  333. ret = -EBUSY;
  334. goto out;
  335. }
  336. while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) {
  337. /* Must try at least 3 times according to DP spec */
  338. for (try = 0; try < 5; try++) {
  339. /* Load the send data into the aux channel data registers */
  340. for (i = 0; i < send_bytes; i += 4)
  341. I915_WRITE(ch_data + i,
  342. pack_aux(send + i, send_bytes - i));
  343. /* Send the command and wait for it to complete */
  344. I915_WRITE(ch_ctl,
  345. DP_AUX_CH_CTL_SEND_BUSY |
  346. (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
  347. DP_AUX_CH_CTL_TIME_OUT_400us |
  348. (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
  349. (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
  350. (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
  351. DP_AUX_CH_CTL_DONE |
  352. DP_AUX_CH_CTL_TIME_OUT_ERROR |
  353. DP_AUX_CH_CTL_RECEIVE_ERROR);
  354. status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
  355. /* Clear done status and any errors */
  356. I915_WRITE(ch_ctl,
  357. status |
  358. DP_AUX_CH_CTL_DONE |
  359. DP_AUX_CH_CTL_TIME_OUT_ERROR |
  360. DP_AUX_CH_CTL_RECEIVE_ERROR);
  361. if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
  362. DP_AUX_CH_CTL_RECEIVE_ERROR))
  363. continue;
  364. if (status & DP_AUX_CH_CTL_DONE)
  365. break;
  366. }
  367. if (status & DP_AUX_CH_CTL_DONE)
  368. break;
  369. }
  370. if ((status & DP_AUX_CH_CTL_DONE) == 0) {
  371. DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
  372. ret = -EBUSY;
  373. goto out;
  374. }
  375. /* Check for timeout or receive error.
  376. * Timeouts occur when the sink is not connected
  377. */
  378. if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
  379. DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
  380. ret = -EIO;
  381. goto out;
  382. }
  383. /* Timeouts occur when the device isn't connected, so they're
  384. * "normal" -- don't fill the kernel log with these */
  385. if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
  386. DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
  387. ret = -ETIMEDOUT;
  388. goto out;
  389. }
  390. /* Unload any bytes sent back from the other side */
  391. recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
  392. DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
  393. if (recv_bytes > recv_size)
  394. recv_bytes = recv_size;
  395. for (i = 0; i < recv_bytes; i += 4)
  396. unpack_aux(I915_READ(ch_data + i),
  397. recv + i, recv_bytes - i);
  398. ret = recv_bytes;
  399. out:
  400. pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
  401. intel_aux_display_runtime_put(dev_priv);
  402. return ret;
  403. }
  404. /* Write data to the aux channel in native mode */
  405. static int
  406. intel_dp_aux_native_write(struct intel_dp *intel_dp,
  407. uint16_t address, uint8_t *send, int send_bytes)
  408. {
  409. int ret;
  410. uint8_t msg[20];
  411. int msg_bytes;
  412. uint8_t ack;
  413. intel_dp_check_edp(intel_dp);
  414. if (send_bytes > 16)
  415. return -1;
  416. msg[0] = AUX_NATIVE_WRITE << 4;
  417. msg[1] = address >> 8;
  418. msg[2] = address & 0xff;
  419. msg[3] = send_bytes - 1;
  420. memcpy(&msg[4], send, send_bytes);
  421. msg_bytes = send_bytes + 4;
  422. for (;;) {
  423. ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
  424. if (ret < 0)
  425. return ret;
  426. if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
  427. break;
  428. else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
  429. udelay(100);
  430. else
  431. return -EIO;
  432. }
  433. return send_bytes;
  434. }
  435. /* Write a single byte to the aux channel in native mode */
  436. static int
  437. intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
  438. uint16_t address, uint8_t byte)
  439. {
  440. return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
  441. }
  442. /* read bytes from a native aux channel */
  443. static int
  444. intel_dp_aux_native_read(struct intel_dp *intel_dp,
  445. uint16_t address, uint8_t *recv, int recv_bytes)
  446. {
  447. uint8_t msg[4];
  448. int msg_bytes;
  449. uint8_t reply[20];
  450. int reply_bytes;
  451. uint8_t ack;
  452. int ret;
  453. intel_dp_check_edp(intel_dp);
  454. msg[0] = AUX_NATIVE_READ << 4;
  455. msg[1] = address >> 8;
  456. msg[2] = address & 0xff;
  457. msg[3] = recv_bytes - 1;
  458. msg_bytes = 4;
  459. reply_bytes = recv_bytes + 1;
  460. for (;;) {
  461. ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
  462. reply, reply_bytes);
  463. if (ret == 0)
  464. return -EPROTO;
  465. if (ret < 0)
  466. return ret;
  467. ack = reply[0];
  468. if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
  469. memcpy(recv, reply + 1, ret - 1);
  470. return ret - 1;
  471. }
  472. else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
  473. udelay(100);
  474. else
  475. return -EIO;
  476. }
  477. }
  478. static int
  479. intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
  480. uint8_t write_byte, uint8_t *read_byte)
  481. {
  482. struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
  483. struct intel_dp *intel_dp = container_of(adapter,
  484. struct intel_dp,
  485. adapter);
  486. uint16_t address = algo_data->address;
  487. uint8_t msg[5];
  488. uint8_t reply[2];
  489. unsigned retry;
  490. int msg_bytes;
  491. int reply_bytes;
  492. int ret;
  493. intel_dp_check_edp(intel_dp);
  494. /* Set up the command byte */
  495. if (mode & MODE_I2C_READ)
  496. msg[0] = AUX_I2C_READ << 4;
  497. else
  498. msg[0] = AUX_I2C_WRITE << 4;
  499. if (!(mode & MODE_I2C_STOP))
  500. msg[0] |= AUX_I2C_MOT << 4;
  501. msg[1] = address >> 8;
  502. msg[2] = address;
  503. switch (mode) {
  504. case MODE_I2C_WRITE:
  505. msg[3] = 0;
  506. msg[4] = write_byte;
  507. msg_bytes = 5;
  508. reply_bytes = 1;
  509. break;
  510. case MODE_I2C_READ:
  511. msg[3] = 0;
  512. msg_bytes = 4;
  513. reply_bytes = 2;
  514. break;
  515. default:
  516. msg_bytes = 3;
  517. reply_bytes = 1;
  518. break;
  519. }
  520. for (retry = 0; retry < 5; retry++) {
  521. ret = intel_dp_aux_ch(intel_dp,
  522. msg, msg_bytes,
  523. reply, reply_bytes);
  524. if (ret < 0) {
  525. DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
  526. return ret;
  527. }
  528. switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
  529. case AUX_NATIVE_REPLY_ACK:
  530. /* I2C-over-AUX Reply field is only valid
  531. * when paired with AUX ACK.
  532. */
  533. break;
  534. case AUX_NATIVE_REPLY_NACK:
  535. DRM_DEBUG_KMS("aux_ch native nack\n");
  536. return -EREMOTEIO;
  537. case AUX_NATIVE_REPLY_DEFER:
  538. udelay(100);
  539. continue;
  540. default:
  541. DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
  542. reply[0]);
  543. return -EREMOTEIO;
  544. }
  545. switch (reply[0] & AUX_I2C_REPLY_MASK) {
  546. case AUX_I2C_REPLY_ACK:
  547. if (mode == MODE_I2C_READ) {
  548. *read_byte = reply[1];
  549. }
  550. return reply_bytes - 1;
  551. case AUX_I2C_REPLY_NACK:
  552. DRM_DEBUG_KMS("aux_i2c nack\n");
  553. return -EREMOTEIO;
  554. case AUX_I2C_REPLY_DEFER:
  555. DRM_DEBUG_KMS("aux_i2c defer\n");
  556. udelay(100);
  557. break;
  558. default:
  559. DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
  560. return -EREMOTEIO;
  561. }
  562. }
  563. DRM_ERROR("too many retries, giving up\n");
  564. return -EREMOTEIO;
  565. }
  566. static int
  567. intel_dp_i2c_init(struct intel_dp *intel_dp,
  568. struct intel_connector *intel_connector, const char *name)
  569. {
  570. int ret;
  571. DRM_DEBUG_KMS("i2c_init %s\n", name);
  572. intel_dp->algo.running = false;
  573. intel_dp->algo.address = 0;
  574. intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
  575. memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
  576. intel_dp->adapter.owner = THIS_MODULE;
  577. intel_dp->adapter.class = I2C_CLASS_DDC;
  578. strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
  579. intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
  580. intel_dp->adapter.algo_data = &intel_dp->algo;
  581. intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
  582. ironlake_edp_panel_vdd_on(intel_dp);
  583. ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
  584. ironlake_edp_panel_vdd_off(intel_dp, false);
  585. return ret;
  586. }
  587. static void
  588. intel_dp_set_clock(struct intel_encoder *encoder,
  589. struct intel_crtc_config *pipe_config, int link_bw)
  590. {
  591. struct drm_device *dev = encoder->base.dev;
  592. const struct dp_link_dpll *divisor = NULL;
  593. int i, count = 0;
  594. if (IS_G4X(dev)) {
  595. divisor = gen4_dpll;
  596. count = ARRAY_SIZE(gen4_dpll);
  597. } else if (IS_HASWELL(dev)) {
  598. /* Haswell has special-purpose DP DDI clocks. */
  599. } else if (HAS_PCH_SPLIT(dev)) {
  600. divisor = pch_dpll;
  601. count = ARRAY_SIZE(pch_dpll);
  602. } else if (IS_VALLEYVIEW(dev)) {
  603. divisor = vlv_dpll;
  604. count = ARRAY_SIZE(vlv_dpll);
  605. }
  606. if (divisor && count) {
  607. for (i = 0; i < count; i++) {
  608. if (link_bw == divisor[i].link_bw) {
  609. pipe_config->dpll = divisor[i].dpll;
  610. pipe_config->clock_set = true;
  611. break;
  612. }
  613. }
  614. }
  615. }
  616. bool
  617. intel_dp_compute_config(struct intel_encoder *encoder,
  618. struct intel_crtc_config *pipe_config)
  619. {
  620. struct drm_device *dev = encoder->base.dev;
  621. struct drm_i915_private *dev_priv = dev->dev_private;
  622. struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
  623. struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
  624. enum port port = dp_to_dig_port(intel_dp)->port;
  625. struct intel_crtc *intel_crtc = encoder->new_crtc;
  626. struct intel_connector *intel_connector = intel_dp->attached_connector;
  627. int lane_count, clock;
  628. int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
  629. int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
  630. int bpp, mode_rate;
  631. static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
  632. int link_avail, link_clock;
  633. if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
  634. pipe_config->has_pch_encoder = true;
  635. pipe_config->has_dp_encoder = true;
  636. if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
  637. intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
  638. adjusted_mode);
  639. if (!HAS_PCH_SPLIT(dev))
  640. intel_gmch_panel_fitting(intel_crtc, pipe_config,
  641. intel_connector->panel.fitting_mode);
  642. else
  643. intel_pch_panel_fitting(intel_crtc, pipe_config,
  644. intel_connector->panel.fitting_mode);
  645. }
  646. if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
  647. return false;
  648. DRM_DEBUG_KMS("DP link computation with max lane count %i "
  649. "max bw %02x pixel clock %iKHz\n",
  650. max_lane_count, bws[max_clock], adjusted_mode->clock);
  651. /* Walk through all bpp values. Luckily they're all nicely spaced with 2
  652. * bpc in between. */
  653. bpp = pipe_config->pipe_bpp;
  654. if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp) {
  655. DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
  656. dev_priv->vbt.edp_bpp);
  657. bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp);
  658. }
  659. for (; bpp >= 6*3; bpp -= 2*3) {
  660. mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
  661. for (clock = 0; clock <= max_clock; clock++) {
  662. for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
  663. link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
  664. link_avail = intel_dp_max_data_rate(link_clock,
  665. lane_count);
  666. if (mode_rate <= link_avail) {
  667. goto found;
  668. }
  669. }
  670. }
  671. }
  672. return false;
  673. found:
  674. if (intel_dp->color_range_auto) {
  675. /*
  676. * See:
  677. * CEA-861-E - 5.1 Default Encoding Parameters
  678. * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
  679. */
  680. if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
  681. intel_dp->color_range = DP_COLOR_RANGE_16_235;
  682. else
  683. intel_dp->color_range = 0;
  684. }
  685. if (intel_dp->color_range)
  686. pipe_config->limited_color_range = true;
  687. intel_dp->link_bw = bws[clock];
  688. intel_dp->lane_count = lane_count;
  689. pipe_config->pipe_bpp = bpp;
  690. pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
  691. DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
  692. intel_dp->link_bw, intel_dp->lane_count,
  693. pipe_config->port_clock, bpp);
  694. DRM_DEBUG_KMS("DP link bw required %i available %i\n",
  695. mode_rate, link_avail);
  696. intel_link_compute_m_n(bpp, lane_count,
  697. adjusted_mode->clock, pipe_config->port_clock,
  698. &pipe_config->dp_m_n);
  699. intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
  700. return true;
  701. }
  702. void intel_dp_init_link_config(struct intel_dp *intel_dp)
  703. {
  704. memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
  705. intel_dp->link_configuration[0] = intel_dp->link_bw;
  706. intel_dp->link_configuration[1] = intel_dp->lane_count;
  707. intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
  708. /*
  709. * Check for DPCD version > 1.1 and enhanced framing support
  710. */
  711. if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
  712. (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
  713. intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
  714. }
  715. }
  716. static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
  717. {
  718. struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
  719. struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
  720. struct drm_device *dev = crtc->base.dev;
  721. struct drm_i915_private *dev_priv = dev->dev_private;
  722. u32 dpa_ctl;
  723. DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
  724. dpa_ctl = I915_READ(DP_A);
  725. dpa_ctl &= ~DP_PLL_FREQ_MASK;
  726. if (crtc->config.port_clock == 162000) {
  727. /* For a long time we've carried around a ILK-DevA w/a for the
  728. * 160MHz clock. If we're really unlucky, it's still required.
  729. */
  730. DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
  731. dpa_ctl |= DP_PLL_FREQ_160MHZ;
  732. intel_dp->DP |= DP_PLL_FREQ_160MHZ;
  733. } else {
  734. dpa_ctl |= DP_PLL_FREQ_270MHZ;
  735. intel_dp->DP |= DP_PLL_FREQ_270MHZ;
  736. }
  737. I915_WRITE(DP_A, dpa_ctl);
  738. POSTING_READ(DP_A);
  739. udelay(500);
  740. }
  741. static void intel_dp_mode_set(struct intel_encoder *encoder)
  742. {
  743. struct drm_device *dev = encoder->base.dev;
  744. struct drm_i915_private *dev_priv = dev->dev_private;
  745. struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
  746. enum port port = dp_to_dig_port(intel_dp)->port;
  747. struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
  748. struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
  749. /*
  750. * There are four kinds of DP registers:
  751. *
  752. * IBX PCH
  753. * SNB CPU
  754. * IVB CPU
  755. * CPT PCH
  756. *
  757. * IBX PCH and CPU are the same for almost everything,
  758. * except that the CPU DP PLL is configured in this
  759. * register
  760. *
  761. * CPT PCH is quite different, having many bits moved
  762. * to the TRANS_DP_CTL register instead. That
  763. * configuration happens (oddly) in ironlake_pch_enable
  764. */
  765. /* Preserve the BIOS-computed detected bit. This is
  766. * supposed to be read-only.
  767. */
  768. intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
  769. /* Handle DP bits in common between all three register formats */
  770. intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
  771. intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
  772. if (intel_dp->has_audio) {
  773. DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
  774. pipe_name(crtc->pipe));
  775. intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
  776. intel_write_eld(&encoder->base, adjusted_mode);
  777. }
  778. intel_dp_init_link_config(intel_dp);
  779. /* Split out the IBX/CPU vs CPT settings */
  780. if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
  781. if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  782. intel_dp->DP |= DP_SYNC_HS_HIGH;
  783. if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  784. intel_dp->DP |= DP_SYNC_VS_HIGH;
  785. intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
  786. if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
  787. intel_dp->DP |= DP_ENHANCED_FRAMING;
  788. intel_dp->DP |= crtc->pipe << 29;
  789. } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
  790. if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
  791. intel_dp->DP |= intel_dp->color_range;
  792. if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  793. intel_dp->DP |= DP_SYNC_HS_HIGH;
  794. if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  795. intel_dp->DP |= DP_SYNC_VS_HIGH;
  796. intel_dp->DP |= DP_LINK_TRAIN_OFF;
  797. if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
  798. intel_dp->DP |= DP_ENHANCED_FRAMING;
  799. if (crtc->pipe == 1)
  800. intel_dp->DP |= DP_PIPEB_SELECT;
  801. } else {
  802. intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
  803. }
  804. if (port == PORT_A && !IS_VALLEYVIEW(dev))
  805. ironlake_set_pll_cpu_edp(intel_dp);
  806. }
  807. #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
  808. #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
  809. #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
  810. #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
  811. #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
  812. #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
  813. static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
  814. u32 mask,
  815. u32 value)
  816. {
  817. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  818. struct drm_i915_private *dev_priv = dev->dev_private;
  819. u32 pp_stat_reg, pp_ctrl_reg;
  820. pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
  821. pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
  822. DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
  823. mask, value,
  824. I915_READ(pp_stat_reg),
  825. I915_READ(pp_ctrl_reg));
  826. if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
  827. DRM_ERROR("Panel status timeout: status %08x control %08x\n",
  828. I915_READ(pp_stat_reg),
  829. I915_READ(pp_ctrl_reg));
  830. }
  831. }
  832. static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
  833. {
  834. DRM_DEBUG_KMS("Wait for panel power on\n");
  835. ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
  836. }
  837. static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
  838. {
  839. DRM_DEBUG_KMS("Wait for panel power off time\n");
  840. ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
  841. }
  842. static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
  843. {
  844. DRM_DEBUG_KMS("Wait for panel power cycle\n");
  845. ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
  846. }
  847. /* Read the current pp_control value, unlocking the register if it
  848. * is locked
  849. */
  850. static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
  851. {
  852. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  853. struct drm_i915_private *dev_priv = dev->dev_private;
  854. u32 control;
  855. u32 pp_ctrl_reg;
  856. pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
  857. control = I915_READ(pp_ctrl_reg);
  858. control &= ~PANEL_UNLOCK_MASK;
  859. control |= PANEL_UNLOCK_REGS;
  860. return control;
  861. }
  862. void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
  863. {
  864. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  865. struct drm_i915_private *dev_priv = dev->dev_private;
  866. u32 pp;
  867. u32 pp_stat_reg, pp_ctrl_reg;
  868. if (!is_edp(intel_dp))
  869. return;
  870. DRM_DEBUG_KMS("Turn eDP VDD on\n");
  871. WARN(intel_dp->want_panel_vdd,
  872. "eDP VDD already requested on\n");
  873. intel_dp->want_panel_vdd = true;
  874. if (ironlake_edp_have_panel_vdd(intel_dp)) {
  875. DRM_DEBUG_KMS("eDP VDD already on\n");
  876. return;
  877. }
  878. if (!ironlake_edp_have_panel_power(intel_dp))
  879. ironlake_wait_panel_power_cycle(intel_dp);
  880. pp = ironlake_get_pp_control(intel_dp);
  881. pp |= EDP_FORCE_VDD;
  882. pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
  883. pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
  884. I915_WRITE(pp_ctrl_reg, pp);
  885. POSTING_READ(pp_ctrl_reg);
  886. DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
  887. I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
  888. /*
  889. * If the panel wasn't on, delay before accessing aux channel
  890. */
  891. if (!ironlake_edp_have_panel_power(intel_dp)) {
  892. DRM_DEBUG_KMS("eDP was not running\n");
  893. msleep(intel_dp->panel_power_up_delay);
  894. }
  895. }
  896. static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
  897. {
  898. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  899. struct drm_i915_private *dev_priv = dev->dev_private;
  900. u32 pp;
  901. u32 pp_stat_reg, pp_ctrl_reg;
  902. WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
  903. if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
  904. pp = ironlake_get_pp_control(intel_dp);
  905. pp &= ~EDP_FORCE_VDD;
  906. pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
  907. pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
  908. I915_WRITE(pp_ctrl_reg, pp);
  909. POSTING_READ(pp_ctrl_reg);
  910. /* Make sure sequencer is idle before allowing subsequent activity */
  911. DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
  912. I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
  913. msleep(intel_dp->panel_power_down_delay);
  914. }
  915. }
  916. static void ironlake_panel_vdd_work(struct work_struct *__work)
  917. {
  918. struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
  919. struct intel_dp, panel_vdd_work);
  920. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  921. mutex_lock(&dev->mode_config.mutex);
  922. ironlake_panel_vdd_off_sync(intel_dp);
  923. mutex_unlock(&dev->mode_config.mutex);
  924. }
  925. void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
  926. {
  927. if (!is_edp(intel_dp))
  928. return;
  929. DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
  930. WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
  931. intel_dp->want_panel_vdd = false;
  932. if (sync) {
  933. ironlake_panel_vdd_off_sync(intel_dp);
  934. } else {
  935. /*
  936. * Queue the timer to fire a long
  937. * time from now (relative to the power down delay)
  938. * to keep the panel power up across a sequence of operations
  939. */
  940. schedule_delayed_work(&intel_dp->panel_vdd_work,
  941. msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
  942. }
  943. }
  944. void ironlake_edp_panel_on(struct intel_dp *intel_dp)
  945. {
  946. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  947. struct drm_i915_private *dev_priv = dev->dev_private;
  948. u32 pp;
  949. u32 pp_ctrl_reg;
  950. if (!is_edp(intel_dp))
  951. return;
  952. DRM_DEBUG_KMS("Turn eDP power on\n");
  953. if (ironlake_edp_have_panel_power(intel_dp)) {
  954. DRM_DEBUG_KMS("eDP power already on\n");
  955. return;
  956. }
  957. ironlake_wait_panel_power_cycle(intel_dp);
  958. pp = ironlake_get_pp_control(intel_dp);
  959. if (IS_GEN5(dev)) {
  960. /* ILK workaround: disable reset around power sequence */
  961. pp &= ~PANEL_POWER_RESET;
  962. I915_WRITE(PCH_PP_CONTROL, pp);
  963. POSTING_READ(PCH_PP_CONTROL);
  964. }
  965. pp |= POWER_TARGET_ON;
  966. if (!IS_GEN5(dev))
  967. pp |= PANEL_POWER_RESET;
  968. pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
  969. I915_WRITE(pp_ctrl_reg, pp);
  970. POSTING_READ(pp_ctrl_reg);
  971. ironlake_wait_panel_on(intel_dp);
  972. if (IS_GEN5(dev)) {
  973. pp |= PANEL_POWER_RESET; /* restore panel reset bit */
  974. I915_WRITE(PCH_PP_CONTROL, pp);
  975. POSTING_READ(PCH_PP_CONTROL);
  976. }
  977. }
  978. void ironlake_edp_panel_off(struct intel_dp *intel_dp)
  979. {
  980. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  981. struct drm_i915_private *dev_priv = dev->dev_private;
  982. u32 pp;
  983. u32 pp_ctrl_reg;
  984. if (!is_edp(intel_dp))
  985. return;
  986. DRM_DEBUG_KMS("Turn eDP power off\n");
  987. WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
  988. pp = ironlake_get_pp_control(intel_dp);
  989. /* We need to switch off panel power _and_ force vdd, for otherwise some
  990. * panels get very unhappy and cease to work. */
  991. pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
  992. pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
  993. I915_WRITE(pp_ctrl_reg, pp);
  994. POSTING_READ(pp_ctrl_reg);
  995. intel_dp->want_panel_vdd = false;
  996. ironlake_wait_panel_off(intel_dp);
  997. }
  998. void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
  999. {
  1000. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  1001. struct drm_device *dev = intel_dig_port->base.base.dev;
  1002. struct drm_i915_private *dev_priv = dev->dev_private;
  1003. int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
  1004. u32 pp;
  1005. u32 pp_ctrl_reg;
  1006. if (!is_edp(intel_dp))
  1007. return;
  1008. DRM_DEBUG_KMS("\n");
  1009. /*
  1010. * If we enable the backlight right away following a panel power
  1011. * on, we may see slight flicker as the panel syncs with the eDP
  1012. * link. So delay a bit to make sure the image is solid before
  1013. * allowing it to appear.
  1014. */
  1015. msleep(intel_dp->backlight_on_delay);
  1016. pp = ironlake_get_pp_control(intel_dp);
  1017. pp |= EDP_BLC_ENABLE;
  1018. pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
  1019. I915_WRITE(pp_ctrl_reg, pp);
  1020. POSTING_READ(pp_ctrl_reg);
  1021. intel_panel_enable_backlight(dev, pipe);
  1022. }
  1023. void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
  1024. {
  1025. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  1026. struct drm_i915_private *dev_priv = dev->dev_private;
  1027. u32 pp;
  1028. u32 pp_ctrl_reg;
  1029. if (!is_edp(intel_dp))
  1030. return;
  1031. intel_panel_disable_backlight(dev);
  1032. DRM_DEBUG_KMS("\n");
  1033. pp = ironlake_get_pp_control(intel_dp);
  1034. pp &= ~EDP_BLC_ENABLE;
  1035. pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
  1036. I915_WRITE(pp_ctrl_reg, pp);
  1037. POSTING_READ(pp_ctrl_reg);
  1038. msleep(intel_dp->backlight_off_delay);
  1039. }
  1040. static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
  1041. {
  1042. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  1043. struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
  1044. struct drm_device *dev = crtc->dev;
  1045. struct drm_i915_private *dev_priv = dev->dev_private;
  1046. u32 dpa_ctl;
  1047. assert_pipe_disabled(dev_priv,
  1048. to_intel_crtc(crtc)->pipe);
  1049. DRM_DEBUG_KMS("\n");
  1050. dpa_ctl = I915_READ(DP_A);
  1051. WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
  1052. WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
  1053. /* We don't adjust intel_dp->DP while tearing down the link, to
  1054. * facilitate link retraining (e.g. after hotplug). Hence clear all
  1055. * enable bits here to ensure that we don't enable too much. */
  1056. intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
  1057. intel_dp->DP |= DP_PLL_ENABLE;
  1058. I915_WRITE(DP_A, intel_dp->DP);
  1059. POSTING_READ(DP_A);
  1060. udelay(200);
  1061. }
  1062. static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
  1063. {
  1064. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  1065. struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
  1066. struct drm_device *dev = crtc->dev;
  1067. struct drm_i915_private *dev_priv = dev->dev_private;
  1068. u32 dpa_ctl;
  1069. assert_pipe_disabled(dev_priv,
  1070. to_intel_crtc(crtc)->pipe);
  1071. dpa_ctl = I915_READ(DP_A);
  1072. WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
  1073. "dp pll off, should be on\n");
  1074. WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
  1075. /* We can't rely on the value tracked for the DP register in
  1076. * intel_dp->DP because link_down must not change that (otherwise link
  1077. * re-training will fail. */
  1078. dpa_ctl &= ~DP_PLL_ENABLE;
  1079. I915_WRITE(DP_A, dpa_ctl);
  1080. POSTING_READ(DP_A);
  1081. udelay(200);
  1082. }
  1083. /* If the sink supports it, try to set the power state appropriately */
  1084. void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
  1085. {
  1086. int ret, i;
  1087. /* Should have a valid DPCD by this point */
  1088. if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
  1089. return;
  1090. if (mode != DRM_MODE_DPMS_ON) {
  1091. ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
  1092. DP_SET_POWER_D3);
  1093. if (ret != 1)
  1094. DRM_DEBUG_DRIVER("failed to write sink power state\n");
  1095. } else {
  1096. /*
  1097. * When turning on, we need to retry for 1ms to give the sink
  1098. * time to wake up.
  1099. */
  1100. for (i = 0; i < 3; i++) {
  1101. ret = intel_dp_aux_native_write_1(intel_dp,
  1102. DP_SET_POWER,
  1103. DP_SET_POWER_D0);
  1104. if (ret == 1)
  1105. break;
  1106. msleep(1);
  1107. }
  1108. }
  1109. }
  1110. static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
  1111. enum pipe *pipe)
  1112. {
  1113. struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
  1114. enum port port = dp_to_dig_port(intel_dp)->port;
  1115. struct drm_device *dev = encoder->base.dev;
  1116. struct drm_i915_private *dev_priv = dev->dev_private;
  1117. u32 tmp = I915_READ(intel_dp->output_reg);
  1118. if (!(tmp & DP_PORT_EN))
  1119. return false;
  1120. if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
  1121. *pipe = PORT_TO_PIPE_CPT(tmp);
  1122. } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
  1123. *pipe = PORT_TO_PIPE(tmp);
  1124. } else {
  1125. u32 trans_sel;
  1126. u32 trans_dp;
  1127. int i;
  1128. switch (intel_dp->output_reg) {
  1129. case PCH_DP_B:
  1130. trans_sel = TRANS_DP_PORT_SEL_B;
  1131. break;
  1132. case PCH_DP_C:
  1133. trans_sel = TRANS_DP_PORT_SEL_C;
  1134. break;
  1135. case PCH_DP_D:
  1136. trans_sel = TRANS_DP_PORT_SEL_D;
  1137. break;
  1138. default:
  1139. return true;
  1140. }
  1141. for_each_pipe(i) {
  1142. trans_dp = I915_READ(TRANS_DP_CTL(i));
  1143. if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
  1144. *pipe = i;
  1145. return true;
  1146. }
  1147. }
  1148. DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
  1149. intel_dp->output_reg);
  1150. }
  1151. return true;
  1152. }
  1153. static void intel_dp_get_config(struct intel_encoder *encoder,
  1154. struct intel_crtc_config *pipe_config)
  1155. {
  1156. struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
  1157. u32 tmp, flags = 0;
  1158. struct drm_device *dev = encoder->base.dev;
  1159. struct drm_i915_private *dev_priv = dev->dev_private;
  1160. enum port port = dp_to_dig_port(intel_dp)->port;
  1161. struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
  1162. if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
  1163. tmp = I915_READ(intel_dp->output_reg);
  1164. if (tmp & DP_SYNC_HS_HIGH)
  1165. flags |= DRM_MODE_FLAG_PHSYNC;
  1166. else
  1167. flags |= DRM_MODE_FLAG_NHSYNC;
  1168. if (tmp & DP_SYNC_VS_HIGH)
  1169. flags |= DRM_MODE_FLAG_PVSYNC;
  1170. else
  1171. flags |= DRM_MODE_FLAG_NVSYNC;
  1172. } else {
  1173. tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
  1174. if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
  1175. flags |= DRM_MODE_FLAG_PHSYNC;
  1176. else
  1177. flags |= DRM_MODE_FLAG_NHSYNC;
  1178. if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
  1179. flags |= DRM_MODE_FLAG_PVSYNC;
  1180. else
  1181. flags |= DRM_MODE_FLAG_NVSYNC;
  1182. }
  1183. pipe_config->adjusted_mode.flags |= flags;
  1184. if (dp_to_dig_port(intel_dp)->port == PORT_A) {
  1185. if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
  1186. pipe_config->port_clock = 162000;
  1187. else
  1188. pipe_config->port_clock = 270000;
  1189. }
  1190. }
  1191. static bool is_edp_psr(struct intel_dp *intel_dp)
  1192. {
  1193. return is_edp(intel_dp) &&
  1194. intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
  1195. }
  1196. static bool intel_edp_is_psr_enabled(struct drm_device *dev)
  1197. {
  1198. struct drm_i915_private *dev_priv = dev->dev_private;
  1199. if (!IS_HASWELL(dev))
  1200. return false;
  1201. return I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
  1202. }
  1203. static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
  1204. struct edp_vsc_psr *vsc_psr)
  1205. {
  1206. struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
  1207. struct drm_device *dev = dig_port->base.base.dev;
  1208. struct drm_i915_private *dev_priv = dev->dev_private;
  1209. struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
  1210. u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
  1211. u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
  1212. uint32_t *data = (uint32_t *) vsc_psr;
  1213. unsigned int i;
  1214. /* As per BSPec (Pipe Video Data Island Packet), we need to disable
  1215. the video DIP being updated before program video DIP data buffer
  1216. registers for DIP being updated. */
  1217. I915_WRITE(ctl_reg, 0);
  1218. POSTING_READ(ctl_reg);
  1219. for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
  1220. if (i < sizeof(struct edp_vsc_psr))
  1221. I915_WRITE(data_reg + i, *data++);
  1222. else
  1223. I915_WRITE(data_reg + i, 0);
  1224. }
  1225. I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
  1226. POSTING_READ(ctl_reg);
  1227. }
  1228. static void intel_edp_psr_setup(struct intel_dp *intel_dp)
  1229. {
  1230. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  1231. struct drm_i915_private *dev_priv = dev->dev_private;
  1232. struct edp_vsc_psr psr_vsc;
  1233. if (intel_dp->psr_setup_done)
  1234. return;
  1235. /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
  1236. memset(&psr_vsc, 0, sizeof(psr_vsc));
  1237. psr_vsc.sdp_header.HB0 = 0;
  1238. psr_vsc.sdp_header.HB1 = 0x7;
  1239. psr_vsc.sdp_header.HB2 = 0x2;
  1240. psr_vsc.sdp_header.HB3 = 0x8;
  1241. intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
  1242. /* Avoid continuous PSR exit by masking memup and hpd */
  1243. I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |
  1244. EDP_PSR_DEBUG_MASK_HPD);
  1245. intel_dp->psr_setup_done = true;
  1246. }
  1247. static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
  1248. {
  1249. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  1250. struct drm_i915_private *dev_priv = dev->dev_private;
  1251. uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0);
  1252. int precharge = 0x3;
  1253. int msg_size = 5; /* Header(4) + Message(1) */
  1254. /* Enable PSR in sink */
  1255. if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
  1256. intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
  1257. DP_PSR_ENABLE &
  1258. ~DP_PSR_MAIN_LINK_ACTIVE);
  1259. else
  1260. intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
  1261. DP_PSR_ENABLE |
  1262. DP_PSR_MAIN_LINK_ACTIVE);
  1263. /* Setup AUX registers */
  1264. I915_WRITE(EDP_PSR_AUX_DATA1, EDP_PSR_DPCD_COMMAND);
  1265. I915_WRITE(EDP_PSR_AUX_DATA2, EDP_PSR_DPCD_NORMAL_OPERATION);
  1266. I915_WRITE(EDP_PSR_AUX_CTL,
  1267. DP_AUX_CH_CTL_TIME_OUT_400us |
  1268. (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
  1269. (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
  1270. (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
  1271. }
  1272. static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
  1273. {
  1274. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  1275. struct drm_i915_private *dev_priv = dev->dev_private;
  1276. uint32_t max_sleep_time = 0x1f;
  1277. uint32_t idle_frames = 1;
  1278. uint32_t val = 0x0;
  1279. if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
  1280. val |= EDP_PSR_LINK_STANDBY;
  1281. val |= EDP_PSR_TP2_TP3_TIME_0us;
  1282. val |= EDP_PSR_TP1_TIME_0us;
  1283. val |= EDP_PSR_SKIP_AUX_EXIT;
  1284. } else
  1285. val |= EDP_PSR_LINK_DISABLE;
  1286. I915_WRITE(EDP_PSR_CTL, val |
  1287. EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES |
  1288. max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
  1289. idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
  1290. EDP_PSR_ENABLE);
  1291. }
  1292. static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
  1293. {
  1294. struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
  1295. struct drm_device *dev = dig_port->base.base.dev;
  1296. struct drm_i915_private *dev_priv = dev->dev_private;
  1297. struct drm_crtc *crtc = dig_port->base.base.crtc;
  1298. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1299. struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
  1300. struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
  1301. if (!IS_HASWELL(dev)) {
  1302. DRM_DEBUG_KMS("PSR not supported on this platform\n");
  1303. dev_priv->no_psr_reason = PSR_NO_SOURCE;
  1304. return false;
  1305. }
  1306. if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
  1307. (dig_port->port != PORT_A)) {
  1308. DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
  1309. dev_priv->no_psr_reason = PSR_HSW_NOT_DDIA;
  1310. return false;
  1311. }
  1312. if (!is_edp_psr(intel_dp)) {
  1313. DRM_DEBUG_KMS("PSR not supported by this panel\n");
  1314. dev_priv->no_psr_reason = PSR_NO_SINK;
  1315. return false;
  1316. }
  1317. if (!i915_enable_psr) {
  1318. DRM_DEBUG_KMS("PSR disable by flag\n");
  1319. dev_priv->no_psr_reason = PSR_MODULE_PARAM;
  1320. return false;
  1321. }
  1322. crtc = dig_port->base.base.crtc;
  1323. if (crtc == NULL) {
  1324. DRM_DEBUG_KMS("crtc not active for PSR\n");
  1325. dev_priv->no_psr_reason = PSR_CRTC_NOT_ACTIVE;
  1326. return false;
  1327. }
  1328. intel_crtc = to_intel_crtc(crtc);
  1329. if (!intel_crtc->active || !crtc->fb || !crtc->mode.clock) {
  1330. DRM_DEBUG_KMS("crtc not active for PSR\n");
  1331. dev_priv->no_psr_reason = PSR_CRTC_NOT_ACTIVE;
  1332. return false;
  1333. }
  1334. obj = to_intel_framebuffer(crtc->fb)->obj;
  1335. if (obj->tiling_mode != I915_TILING_X ||
  1336. obj->fence_reg == I915_FENCE_REG_NONE) {
  1337. DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
  1338. dev_priv->no_psr_reason = PSR_NOT_TILED;
  1339. return false;
  1340. }
  1341. if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
  1342. DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
  1343. dev_priv->no_psr_reason = PSR_SPRITE_ENABLED;
  1344. return false;
  1345. }
  1346. if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
  1347. S3D_ENABLE) {
  1348. DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
  1349. dev_priv->no_psr_reason = PSR_S3D_ENABLED;
  1350. return false;
  1351. }
  1352. if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) {
  1353. DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
  1354. dev_priv->no_psr_reason = PSR_INTERLACED_ENABLED;
  1355. return false;
  1356. }
  1357. return true;
  1358. }
  1359. static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
  1360. {
  1361. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  1362. if (!intel_edp_psr_match_conditions(intel_dp) ||
  1363. intel_edp_is_psr_enabled(dev))
  1364. return;
  1365. /* Setup PSR once */
  1366. intel_edp_psr_setup(intel_dp);
  1367. /* Enable PSR on the panel */
  1368. intel_edp_psr_enable_sink(intel_dp);
  1369. /* Enable PSR on the host */
  1370. intel_edp_psr_enable_source(intel_dp);
  1371. }
  1372. void intel_edp_psr_enable(struct intel_dp *intel_dp)
  1373. {
  1374. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  1375. if (intel_edp_psr_match_conditions(intel_dp) &&
  1376. !intel_edp_is_psr_enabled(dev))
  1377. intel_edp_psr_do_enable(intel_dp);
  1378. }
  1379. void intel_edp_psr_disable(struct intel_dp *intel_dp)
  1380. {
  1381. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  1382. struct drm_i915_private *dev_priv = dev->dev_private;
  1383. if (!intel_edp_is_psr_enabled(dev))
  1384. return;
  1385. I915_WRITE(EDP_PSR_CTL, I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
  1386. /* Wait till PSR is idle */
  1387. if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
  1388. EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
  1389. DRM_ERROR("Timed out waiting for PSR Idle State\n");
  1390. }
  1391. void intel_edp_psr_update(struct drm_device *dev)
  1392. {
  1393. struct intel_encoder *encoder;
  1394. struct intel_dp *intel_dp = NULL;
  1395. list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
  1396. if (encoder->type == INTEL_OUTPUT_EDP) {
  1397. intel_dp = enc_to_intel_dp(&encoder->base);
  1398. if (!is_edp_psr(intel_dp))
  1399. return;
  1400. if (!intel_edp_psr_match_conditions(intel_dp))
  1401. intel_edp_psr_disable(intel_dp);
  1402. else
  1403. if (!intel_edp_is_psr_enabled(dev))
  1404. intel_edp_psr_do_enable(intel_dp);
  1405. }
  1406. }
  1407. static void intel_disable_dp(struct intel_encoder *encoder)
  1408. {
  1409. struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
  1410. enum port port = dp_to_dig_port(intel_dp)->port;
  1411. struct drm_device *dev = encoder->base.dev;
  1412. /* Make sure the panel is off before trying to change the mode. But also
  1413. * ensure that we have vdd while we switch off the panel. */
  1414. ironlake_edp_panel_vdd_on(intel_dp);
  1415. ironlake_edp_backlight_off(intel_dp);
  1416. intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
  1417. ironlake_edp_panel_off(intel_dp);
  1418. /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
  1419. if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
  1420. intel_dp_link_down(intel_dp);
  1421. }
  1422. static void intel_post_disable_dp(struct intel_encoder *encoder)
  1423. {
  1424. struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
  1425. enum port port = dp_to_dig_port(intel_dp)->port;
  1426. struct drm_device *dev = encoder->base.dev;
  1427. if (port == PORT_A || IS_VALLEYVIEW(dev)) {
  1428. intel_dp_link_down(intel_dp);
  1429. if (!IS_VALLEYVIEW(dev))
  1430. ironlake_edp_pll_off(intel_dp);
  1431. }
  1432. }
  1433. static void intel_enable_dp(struct intel_encoder *encoder)
  1434. {
  1435. struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
  1436. struct drm_device *dev = encoder->base.dev;
  1437. struct drm_i915_private *dev_priv = dev->dev_private;
  1438. uint32_t dp_reg = I915_READ(intel_dp->output_reg);
  1439. if (WARN_ON(dp_reg & DP_PORT_EN))
  1440. return;
  1441. ironlake_edp_panel_vdd_on(intel_dp);
  1442. intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
  1443. intel_dp_start_link_train(intel_dp);
  1444. ironlake_edp_panel_on(intel_dp);
  1445. ironlake_edp_panel_vdd_off(intel_dp, true);
  1446. intel_dp_complete_link_train(intel_dp);
  1447. intel_dp_stop_link_train(intel_dp);
  1448. ironlake_edp_backlight_on(intel_dp);
  1449. }
  1450. static void vlv_enable_dp(struct intel_encoder *encoder)
  1451. {
  1452. }
  1453. static void intel_pre_enable_dp(struct intel_encoder *encoder)
  1454. {
  1455. struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
  1456. struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
  1457. if (dport->port == PORT_A)
  1458. ironlake_edp_pll_on(intel_dp);
  1459. }
  1460. static void vlv_pre_enable_dp(struct intel_encoder *encoder)
  1461. {
  1462. struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
  1463. struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
  1464. struct drm_device *dev = encoder->base.dev;
  1465. struct drm_i915_private *dev_priv = dev->dev_private;
  1466. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
  1467. int port = vlv_dport_to_channel(dport);
  1468. int pipe = intel_crtc->pipe;
  1469. u32 val;
  1470. mutex_lock(&dev_priv->dpio_lock);
  1471. val = vlv_dpio_read(dev_priv, pipe, DPIO_DATA_LANE_A(port));
  1472. val = 0;
  1473. if (pipe)
  1474. val |= (1<<21);
  1475. else
  1476. val &= ~(1<<21);
  1477. val |= 0x001000c4;
  1478. vlv_dpio_write(dev_priv, pipe, DPIO_DATA_CHANNEL(port), val);
  1479. vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF0(port), 0x00760018);
  1480. vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF8(port), 0x00400888);
  1481. mutex_unlock(&dev_priv->dpio_lock);
  1482. intel_enable_dp(encoder);
  1483. vlv_wait_port_ready(dev_priv, port);
  1484. }
  1485. static void intel_dp_pre_pll_enable(struct intel_encoder *encoder)
  1486. {
  1487. struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
  1488. struct drm_device *dev = encoder->base.dev;
  1489. struct drm_i915_private *dev_priv = dev->dev_private;
  1490. struct intel_crtc *intel_crtc =
  1491. to_intel_crtc(encoder->base.crtc);
  1492. int port = vlv_dport_to_channel(dport);
  1493. int pipe = intel_crtc->pipe;
  1494. if (!IS_VALLEYVIEW(dev))
  1495. return;
  1496. /* Program Tx lane resets to default */
  1497. mutex_lock(&dev_priv->dpio_lock);
  1498. vlv_dpio_write(dev_priv, pipe, DPIO_PCS_TX(port),
  1499. DPIO_PCS_TX_LANE2_RESET |
  1500. DPIO_PCS_TX_LANE1_RESET);
  1501. vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLK(port),
  1502. DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
  1503. DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
  1504. (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
  1505. DPIO_PCS_CLK_SOFT_RESET);
  1506. /* Fix up inter-pair skew failure */
  1507. vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER1(port), 0x00750f00);
  1508. vlv_dpio_write(dev_priv, pipe, DPIO_TX_CTL(port), 0x00001500);
  1509. vlv_dpio_write(dev_priv, pipe, DPIO_TX_LANE(port), 0x40400000);
  1510. mutex_unlock(&dev_priv->dpio_lock);
  1511. }
  1512. /*
  1513. * Native read with retry for link status and receiver capability reads for
  1514. * cases where the sink may still be asleep.
  1515. */
  1516. static bool
  1517. intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
  1518. uint8_t *recv, int recv_bytes)
  1519. {
  1520. int ret, i;
  1521. /*
  1522. * Sinks are *supposed* to come up within 1ms from an off state,
  1523. * but we're also supposed to retry 3 times per the spec.
  1524. */
  1525. for (i = 0; i < 3; i++) {
  1526. ret = intel_dp_aux_native_read(intel_dp, address, recv,
  1527. recv_bytes);
  1528. if (ret == recv_bytes)
  1529. return true;
  1530. msleep(1);
  1531. }
  1532. return false;
  1533. }
  1534. /*
  1535. * Fetch AUX CH registers 0x202 - 0x207 which contain
  1536. * link status information
  1537. */
  1538. static bool
  1539. intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
  1540. {
  1541. return intel_dp_aux_native_read_retry(intel_dp,
  1542. DP_LANE0_1_STATUS,
  1543. link_status,
  1544. DP_LINK_STATUS_SIZE);
  1545. }
  1546. #if 0
  1547. static char *voltage_names[] = {
  1548. "0.4V", "0.6V", "0.8V", "1.2V"
  1549. };
  1550. static char *pre_emph_names[] = {
  1551. "0dB", "3.5dB", "6dB", "9.5dB"
  1552. };
  1553. static char *link_train_names[] = {
  1554. "pattern 1", "pattern 2", "idle", "off"
  1555. };
  1556. #endif
  1557. /*
  1558. * These are source-specific values; current Intel hardware supports
  1559. * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
  1560. */
  1561. static uint8_t
  1562. intel_dp_voltage_max(struct intel_dp *intel_dp)
  1563. {
  1564. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  1565. enum port port = dp_to_dig_port(intel_dp)->port;
  1566. if (IS_VALLEYVIEW(dev))
  1567. return DP_TRAIN_VOLTAGE_SWING_1200;
  1568. else if (IS_GEN7(dev) && port == PORT_A)
  1569. return DP_TRAIN_VOLTAGE_SWING_800;
  1570. else if (HAS_PCH_CPT(dev) && port != PORT_A)
  1571. return DP_TRAIN_VOLTAGE_SWING_1200;
  1572. else
  1573. return DP_TRAIN_VOLTAGE_SWING_800;
  1574. }
  1575. static uint8_t
  1576. intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
  1577. {
  1578. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  1579. enum port port = dp_to_dig_port(intel_dp)->port;
  1580. if (HAS_DDI(dev)) {
  1581. switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
  1582. case DP_TRAIN_VOLTAGE_SWING_400:
  1583. return DP_TRAIN_PRE_EMPHASIS_9_5;
  1584. case DP_TRAIN_VOLTAGE_SWING_600:
  1585. return DP_TRAIN_PRE_EMPHASIS_6;
  1586. case DP_TRAIN_VOLTAGE_SWING_800:
  1587. return DP_TRAIN_PRE_EMPHASIS_3_5;
  1588. case DP_TRAIN_VOLTAGE_SWING_1200:
  1589. default:
  1590. return DP_TRAIN_PRE_EMPHASIS_0;
  1591. }
  1592. } else if (IS_VALLEYVIEW(dev)) {
  1593. switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
  1594. case DP_TRAIN_VOLTAGE_SWING_400:
  1595. return DP_TRAIN_PRE_EMPHASIS_9_5;
  1596. case DP_TRAIN_VOLTAGE_SWING_600:
  1597. return DP_TRAIN_PRE_EMPHASIS_6;
  1598. case DP_TRAIN_VOLTAGE_SWING_800:
  1599. return DP_TRAIN_PRE_EMPHASIS_3_5;
  1600. case DP_TRAIN_VOLTAGE_SWING_1200:
  1601. default:
  1602. return DP_TRAIN_PRE_EMPHASIS_0;
  1603. }
  1604. } else if (IS_GEN7(dev) && port == PORT_A) {
  1605. switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
  1606. case DP_TRAIN_VOLTAGE_SWING_400:
  1607. return DP_TRAIN_PRE_EMPHASIS_6;
  1608. case DP_TRAIN_VOLTAGE_SWING_600:
  1609. case DP_TRAIN_VOLTAGE_SWING_800:
  1610. return DP_TRAIN_PRE_EMPHASIS_3_5;
  1611. default:
  1612. return DP_TRAIN_PRE_EMPHASIS_0;
  1613. }
  1614. } else {
  1615. switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
  1616. case DP_TRAIN_VOLTAGE_SWING_400:
  1617. return DP_TRAIN_PRE_EMPHASIS_6;
  1618. case DP_TRAIN_VOLTAGE_SWING_600:
  1619. return DP_TRAIN_PRE_EMPHASIS_6;
  1620. case DP_TRAIN_VOLTAGE_SWING_800:
  1621. return DP_TRAIN_PRE_EMPHASIS_3_5;
  1622. case DP_TRAIN_VOLTAGE_SWING_1200:
  1623. default:
  1624. return DP_TRAIN_PRE_EMPHASIS_0;
  1625. }
  1626. }
  1627. }
  1628. static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
  1629. {
  1630. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  1631. struct drm_i915_private *dev_priv = dev->dev_private;
  1632. struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
  1633. struct intel_crtc *intel_crtc =
  1634. to_intel_crtc(dport->base.base.crtc);
  1635. unsigned long demph_reg_value, preemph_reg_value,
  1636. uniqtranscale_reg_value;
  1637. uint8_t train_set = intel_dp->train_set[0];
  1638. int port = vlv_dport_to_channel(dport);
  1639. int pipe = intel_crtc->pipe;
  1640. switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
  1641. case DP_TRAIN_PRE_EMPHASIS_0:
  1642. preemph_reg_value = 0x0004000;
  1643. switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
  1644. case DP_TRAIN_VOLTAGE_SWING_400:
  1645. demph_reg_value = 0x2B405555;
  1646. uniqtranscale_reg_value = 0x552AB83A;
  1647. break;
  1648. case DP_TRAIN_VOLTAGE_SWING_600:
  1649. demph_reg_value = 0x2B404040;
  1650. uniqtranscale_reg_value = 0x5548B83A;
  1651. break;
  1652. case DP_TRAIN_VOLTAGE_SWING_800:
  1653. demph_reg_value = 0x2B245555;
  1654. uniqtranscale_reg_value = 0x5560B83A;
  1655. break;
  1656. case DP_TRAIN_VOLTAGE_SWING_1200:
  1657. demph_reg_value = 0x2B405555;
  1658. uniqtranscale_reg_value = 0x5598DA3A;
  1659. break;
  1660. default:
  1661. return 0;
  1662. }
  1663. break;
  1664. case DP_TRAIN_PRE_EMPHASIS_3_5:
  1665. preemph_reg_value = 0x0002000;
  1666. switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
  1667. case DP_TRAIN_VOLTAGE_SWING_400:
  1668. demph_reg_value = 0x2B404040;
  1669. uniqtranscale_reg_value = 0x5552B83A;
  1670. break;
  1671. case DP_TRAIN_VOLTAGE_SWING_600:
  1672. demph_reg_value = 0x2B404848;
  1673. uniqtranscale_reg_value = 0x5580B83A;
  1674. break;
  1675. case DP_TRAIN_VOLTAGE_SWING_800:
  1676. demph_reg_value = 0x2B404040;
  1677. uniqtranscale_reg_value = 0x55ADDA3A;
  1678. break;
  1679. default:
  1680. return 0;
  1681. }
  1682. break;
  1683. case DP_TRAIN_PRE_EMPHASIS_6:
  1684. preemph_reg_value = 0x0000000;
  1685. switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
  1686. case DP_TRAIN_VOLTAGE_SWING_400:
  1687. demph_reg_value = 0x2B305555;
  1688. uniqtranscale_reg_value = 0x5570B83A;
  1689. break;
  1690. case DP_TRAIN_VOLTAGE_SWING_600:
  1691. demph_reg_value = 0x2B2B4040;
  1692. uniqtranscale_reg_value = 0x55ADDA3A;
  1693. break;
  1694. default:
  1695. return 0;
  1696. }
  1697. break;
  1698. case DP_TRAIN_PRE_EMPHASIS_9_5:
  1699. preemph_reg_value = 0x0006000;
  1700. switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
  1701. case DP_TRAIN_VOLTAGE_SWING_400:
  1702. demph_reg_value = 0x1B405555;
  1703. uniqtranscale_reg_value = 0x55ADDA3A;
  1704. break;
  1705. default:
  1706. return 0;
  1707. }
  1708. break;
  1709. default:
  1710. return 0;
  1711. }
  1712. mutex_lock(&dev_priv->dpio_lock);
  1713. vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0x00000000);
  1714. vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL4(port), demph_reg_value);
  1715. vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL2(port),
  1716. uniqtranscale_reg_value);
  1717. vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL3(port), 0x0C782040);
  1718. vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER0(port), 0x00030000);
  1719. vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
  1720. vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0x80000000);
  1721. mutex_unlock(&dev_priv->dpio_lock);
  1722. return 0;
  1723. }
  1724. static void
  1725. intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
  1726. {
  1727. uint8_t v = 0;
  1728. uint8_t p = 0;
  1729. int lane;
  1730. uint8_t voltage_max;
  1731. uint8_t preemph_max;
  1732. for (lane = 0; lane < intel_dp->lane_count; lane++) {
  1733. uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
  1734. uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
  1735. if (this_v > v)
  1736. v = this_v;
  1737. if (this_p > p)
  1738. p = this_p;
  1739. }
  1740. voltage_max = intel_dp_voltage_max(intel_dp);
  1741. if (v >= voltage_max)
  1742. v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
  1743. preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
  1744. if (p >= preemph_max)
  1745. p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
  1746. for (lane = 0; lane < 4; lane++)
  1747. intel_dp->train_set[lane] = v | p;
  1748. }
  1749. static uint32_t
  1750. intel_gen4_signal_levels(uint8_t train_set)
  1751. {
  1752. uint32_t signal_levels = 0;
  1753. switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
  1754. case DP_TRAIN_VOLTAGE_SWING_400:
  1755. default:
  1756. signal_levels |= DP_VOLTAGE_0_4;
  1757. break;
  1758. case DP_TRAIN_VOLTAGE_SWING_600:
  1759. signal_levels |= DP_VOLTAGE_0_6;
  1760. break;
  1761. case DP_TRAIN_VOLTAGE_SWING_800:
  1762. signal_levels |= DP_VOLTAGE_0_8;
  1763. break;
  1764. case DP_TRAIN_VOLTAGE_SWING_1200:
  1765. signal_levels |= DP_VOLTAGE_1_2;
  1766. break;
  1767. }
  1768. switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
  1769. case DP_TRAIN_PRE_EMPHASIS_0:
  1770. default:
  1771. signal_levels |= DP_PRE_EMPHASIS_0;
  1772. break;
  1773. case DP_TRAIN_PRE_EMPHASIS_3_5:
  1774. signal_levels |= DP_PRE_EMPHASIS_3_5;
  1775. break;
  1776. case DP_TRAIN_PRE_EMPHASIS_6:
  1777. signal_levels |= DP_PRE_EMPHASIS_6;
  1778. break;
  1779. case DP_TRAIN_PRE_EMPHASIS_9_5:
  1780. signal_levels |= DP_PRE_EMPHASIS_9_5;
  1781. break;
  1782. }
  1783. return signal_levels;
  1784. }
  1785. /* Gen6's DP voltage swing and pre-emphasis control */
  1786. static uint32_t
  1787. intel_gen6_edp_signal_levels(uint8_t train_set)
  1788. {
  1789. int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
  1790. DP_TRAIN_PRE_EMPHASIS_MASK);
  1791. switch (signal_levels) {
  1792. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
  1793. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
  1794. return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
  1795. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
  1796. return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
  1797. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
  1798. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
  1799. return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
  1800. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
  1801. case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
  1802. return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
  1803. case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
  1804. case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
  1805. return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
  1806. default:
  1807. DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
  1808. "0x%x\n", signal_levels);
  1809. return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
  1810. }
  1811. }
  1812. /* Gen7's DP voltage swing and pre-emphasis control */
  1813. static uint32_t
  1814. intel_gen7_edp_signal_levels(uint8_t train_set)
  1815. {
  1816. int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
  1817. DP_TRAIN_PRE_EMPHASIS_MASK);
  1818. switch (signal_levels) {
  1819. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
  1820. return EDP_LINK_TRAIN_400MV_0DB_IVB;
  1821. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
  1822. return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
  1823. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
  1824. return EDP_LINK_TRAIN_400MV_6DB_IVB;
  1825. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
  1826. return EDP_LINK_TRAIN_600MV_0DB_IVB;
  1827. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
  1828. return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
  1829. case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
  1830. return EDP_LINK_TRAIN_800MV_0DB_IVB;
  1831. case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
  1832. return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
  1833. default:
  1834. DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
  1835. "0x%x\n", signal_levels);
  1836. return EDP_LINK_TRAIN_500MV_0DB_IVB;
  1837. }
  1838. }
  1839. /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
  1840. static uint32_t
  1841. intel_hsw_signal_levels(uint8_t train_set)
  1842. {
  1843. int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
  1844. DP_TRAIN_PRE_EMPHASIS_MASK);
  1845. switch (signal_levels) {
  1846. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
  1847. return DDI_BUF_EMP_400MV_0DB_HSW;
  1848. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
  1849. return DDI_BUF_EMP_400MV_3_5DB_HSW;
  1850. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
  1851. return DDI_BUF_EMP_400MV_6DB_HSW;
  1852. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
  1853. return DDI_BUF_EMP_400MV_9_5DB_HSW;
  1854. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
  1855. return DDI_BUF_EMP_600MV_0DB_HSW;
  1856. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
  1857. return DDI_BUF_EMP_600MV_3_5DB_HSW;
  1858. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
  1859. return DDI_BUF_EMP_600MV_6DB_HSW;
  1860. case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
  1861. return DDI_BUF_EMP_800MV_0DB_HSW;
  1862. case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
  1863. return DDI_BUF_EMP_800MV_3_5DB_HSW;
  1864. default:
  1865. DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
  1866. "0x%x\n", signal_levels);
  1867. return DDI_BUF_EMP_400MV_0DB_HSW;
  1868. }
  1869. }
  1870. /* Properly updates "DP" with the correct signal levels. */
  1871. static void
  1872. intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
  1873. {
  1874. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  1875. enum port port = intel_dig_port->port;
  1876. struct drm_device *dev = intel_dig_port->base.base.dev;
  1877. uint32_t signal_levels, mask;
  1878. uint8_t train_set = intel_dp->train_set[0];
  1879. if (HAS_DDI(dev)) {
  1880. signal_levels = intel_hsw_signal_levels(train_set);
  1881. mask = DDI_BUF_EMP_MASK;
  1882. } else if (IS_VALLEYVIEW(dev)) {
  1883. signal_levels = intel_vlv_signal_levels(intel_dp);
  1884. mask = 0;
  1885. } else if (IS_GEN7(dev) && port == PORT_A) {
  1886. signal_levels = intel_gen7_edp_signal_levels(train_set);
  1887. mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
  1888. } else if (IS_GEN6(dev) && port == PORT_A) {
  1889. signal_levels = intel_gen6_edp_signal_levels(train_set);
  1890. mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
  1891. } else {
  1892. signal_levels = intel_gen4_signal_levels(train_set);
  1893. mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
  1894. }
  1895. DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
  1896. *DP = (*DP & ~mask) | signal_levels;
  1897. }
  1898. static bool
  1899. intel_dp_set_link_train(struct intel_dp *intel_dp,
  1900. uint32_t dp_reg_value,
  1901. uint8_t dp_train_pat)
  1902. {
  1903. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  1904. struct drm_device *dev = intel_dig_port->base.base.dev;
  1905. struct drm_i915_private *dev_priv = dev->dev_private;
  1906. enum port port = intel_dig_port->port;
  1907. int ret;
  1908. if (HAS_DDI(dev)) {
  1909. uint32_t temp = I915_READ(DP_TP_CTL(port));
  1910. if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
  1911. temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
  1912. else
  1913. temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
  1914. temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
  1915. switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
  1916. case DP_TRAINING_PATTERN_DISABLE:
  1917. temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
  1918. break;
  1919. case DP_TRAINING_PATTERN_1:
  1920. temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
  1921. break;
  1922. case DP_TRAINING_PATTERN_2:
  1923. temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
  1924. break;
  1925. case DP_TRAINING_PATTERN_3:
  1926. temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
  1927. break;
  1928. }
  1929. I915_WRITE(DP_TP_CTL(port), temp);
  1930. } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
  1931. dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
  1932. switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
  1933. case DP_TRAINING_PATTERN_DISABLE:
  1934. dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
  1935. break;
  1936. case DP_TRAINING_PATTERN_1:
  1937. dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
  1938. break;
  1939. case DP_TRAINING_PATTERN_2:
  1940. dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
  1941. break;
  1942. case DP_TRAINING_PATTERN_3:
  1943. DRM_ERROR("DP training pattern 3 not supported\n");
  1944. dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
  1945. break;
  1946. }
  1947. } else {
  1948. dp_reg_value &= ~DP_LINK_TRAIN_MASK;
  1949. switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
  1950. case DP_TRAINING_PATTERN_DISABLE:
  1951. dp_reg_value |= DP_LINK_TRAIN_OFF;
  1952. break;
  1953. case DP_TRAINING_PATTERN_1:
  1954. dp_reg_value |= DP_LINK_TRAIN_PAT_1;
  1955. break;
  1956. case DP_TRAINING_PATTERN_2:
  1957. dp_reg_value |= DP_LINK_TRAIN_PAT_2;
  1958. break;
  1959. case DP_TRAINING_PATTERN_3:
  1960. DRM_ERROR("DP training pattern 3 not supported\n");
  1961. dp_reg_value |= DP_LINK_TRAIN_PAT_2;
  1962. break;
  1963. }
  1964. }
  1965. I915_WRITE(intel_dp->output_reg, dp_reg_value);
  1966. POSTING_READ(intel_dp->output_reg);
  1967. intel_dp_aux_native_write_1(intel_dp,
  1968. DP_TRAINING_PATTERN_SET,
  1969. dp_train_pat);
  1970. if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
  1971. DP_TRAINING_PATTERN_DISABLE) {
  1972. ret = intel_dp_aux_native_write(intel_dp,
  1973. DP_TRAINING_LANE0_SET,
  1974. intel_dp->train_set,
  1975. intel_dp->lane_count);
  1976. if (ret != intel_dp->lane_count)
  1977. return false;
  1978. }
  1979. return true;
  1980. }
  1981. static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
  1982. {
  1983. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  1984. struct drm_device *dev = intel_dig_port->base.base.dev;
  1985. struct drm_i915_private *dev_priv = dev->dev_private;
  1986. enum port port = intel_dig_port->port;
  1987. uint32_t val;
  1988. if (!HAS_DDI(dev))
  1989. return;
  1990. val = I915_READ(DP_TP_CTL(port));
  1991. val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
  1992. val |= DP_TP_CTL_LINK_TRAIN_IDLE;
  1993. I915_WRITE(DP_TP_CTL(port), val);
  1994. /*
  1995. * On PORT_A we can have only eDP in SST mode. There the only reason
  1996. * we need to set idle transmission mode is to work around a HW issue
  1997. * where we enable the pipe while not in idle link-training mode.
  1998. * In this case there is requirement to wait for a minimum number of
  1999. * idle patterns to be sent.
  2000. */
  2001. if (port == PORT_A)
  2002. return;
  2003. if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
  2004. 1))
  2005. DRM_ERROR("Timed out waiting for DP idle patterns\n");
  2006. }
  2007. /* Enable corresponding port and start training pattern 1 */
  2008. void
  2009. intel_dp_start_link_train(struct intel_dp *intel_dp)
  2010. {
  2011. struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
  2012. struct drm_device *dev = encoder->dev;
  2013. int i;
  2014. uint8_t voltage;
  2015. int voltage_tries, loop_tries;
  2016. uint32_t DP = intel_dp->DP;
  2017. if (HAS_DDI(dev))
  2018. intel_ddi_prepare_link_retrain(encoder);
  2019. /* Write the link configuration data */
  2020. intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
  2021. intel_dp->link_configuration,
  2022. DP_LINK_CONFIGURATION_SIZE);
  2023. DP |= DP_PORT_EN;
  2024. memset(intel_dp->train_set, 0, 4);
  2025. voltage = 0xff;
  2026. voltage_tries = 0;
  2027. loop_tries = 0;
  2028. for (;;) {
  2029. /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
  2030. uint8_t link_status[DP_LINK_STATUS_SIZE];
  2031. intel_dp_set_signal_levels(intel_dp, &DP);
  2032. /* Set training pattern 1 */
  2033. if (!intel_dp_set_link_train(intel_dp, DP,
  2034. DP_TRAINING_PATTERN_1 |
  2035. DP_LINK_SCRAMBLING_DISABLE))
  2036. break;
  2037. drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
  2038. if (!intel_dp_get_link_status(intel_dp, link_status)) {
  2039. DRM_ERROR("failed to get link status\n");
  2040. break;
  2041. }
  2042. if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
  2043. DRM_DEBUG_KMS("clock recovery OK\n");
  2044. break;
  2045. }
  2046. /* Check to see if we've tried the max voltage */
  2047. for (i = 0; i < intel_dp->lane_count; i++)
  2048. if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
  2049. break;
  2050. if (i == intel_dp->lane_count) {
  2051. ++loop_tries;
  2052. if (loop_tries == 5) {
  2053. DRM_DEBUG_KMS("too many full retries, give up\n");
  2054. break;
  2055. }
  2056. memset(intel_dp->train_set, 0, 4);
  2057. voltage_tries = 0;
  2058. continue;
  2059. }
  2060. /* Check to see if we've tried the same voltage 5 times */
  2061. if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
  2062. ++voltage_tries;
  2063. if (voltage_tries == 5) {
  2064. DRM_DEBUG_KMS("too many voltage retries, give up\n");
  2065. break;
  2066. }
  2067. } else
  2068. voltage_tries = 0;
  2069. voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
  2070. /* Compute new intel_dp->train_set as requested by target */
  2071. intel_get_adjust_train(intel_dp, link_status);
  2072. }
  2073. intel_dp->DP = DP;
  2074. }
  2075. void
  2076. intel_dp_complete_link_train(struct intel_dp *intel_dp)
  2077. {
  2078. bool channel_eq = false;
  2079. int tries, cr_tries;
  2080. uint32_t DP = intel_dp->DP;
  2081. /* channel equalization */
  2082. tries = 0;
  2083. cr_tries = 0;
  2084. channel_eq = false;
  2085. for (;;) {
  2086. uint8_t link_status[DP_LINK_STATUS_SIZE];
  2087. if (cr_tries > 5) {
  2088. DRM_ERROR("failed to train DP, aborting\n");
  2089. intel_dp_link_down(intel_dp);
  2090. break;
  2091. }
  2092. intel_dp_set_signal_levels(intel_dp, &DP);
  2093. /* channel eq pattern */
  2094. if (!intel_dp_set_link_train(intel_dp, DP,
  2095. DP_TRAINING_PATTERN_2 |
  2096. DP_LINK_SCRAMBLING_DISABLE))
  2097. break;
  2098. drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
  2099. if (!intel_dp_get_link_status(intel_dp, link_status))
  2100. break;
  2101. /* Make sure clock is still ok */
  2102. if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
  2103. intel_dp_start_link_train(intel_dp);
  2104. cr_tries++;
  2105. continue;
  2106. }
  2107. if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
  2108. channel_eq = true;
  2109. break;
  2110. }
  2111. /* Try 5 times, then try clock recovery if that fails */
  2112. if (tries > 5) {
  2113. intel_dp_link_down(intel_dp);
  2114. intel_dp_start_link_train(intel_dp);
  2115. tries = 0;
  2116. cr_tries++;
  2117. continue;
  2118. }
  2119. /* Compute new intel_dp->train_set as requested by target */
  2120. intel_get_adjust_train(intel_dp, link_status);
  2121. ++tries;
  2122. }
  2123. intel_dp_set_idle_link_train(intel_dp);
  2124. intel_dp->DP = DP;
  2125. if (channel_eq)
  2126. DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
  2127. }
  2128. void intel_dp_stop_link_train(struct intel_dp *intel_dp)
  2129. {
  2130. intel_dp_set_link_train(intel_dp, intel_dp->DP,
  2131. DP_TRAINING_PATTERN_DISABLE);
  2132. }
  2133. static void
  2134. intel_dp_link_down(struct intel_dp *intel_dp)
  2135. {
  2136. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  2137. enum port port = intel_dig_port->port;
  2138. struct drm_device *dev = intel_dig_port->base.base.dev;
  2139. struct drm_i915_private *dev_priv = dev->dev_private;
  2140. struct intel_crtc *intel_crtc =
  2141. to_intel_crtc(intel_dig_port->base.base.crtc);
  2142. uint32_t DP = intel_dp->DP;
  2143. /*
  2144. * DDI code has a strict mode set sequence and we should try to respect
  2145. * it, otherwise we might hang the machine in many different ways. So we
  2146. * really should be disabling the port only on a complete crtc_disable
  2147. * sequence. This function is just called under two conditions on DDI
  2148. * code:
  2149. * - Link train failed while doing crtc_enable, and on this case we
  2150. * really should respect the mode set sequence and wait for a
  2151. * crtc_disable.
  2152. * - Someone turned the monitor off and intel_dp_check_link_status
  2153. * called us. We don't need to disable the whole port on this case, so
  2154. * when someone turns the monitor on again,
  2155. * intel_ddi_prepare_link_retrain will take care of redoing the link
  2156. * train.
  2157. */
  2158. if (HAS_DDI(dev))
  2159. return;
  2160. if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
  2161. return;
  2162. DRM_DEBUG_KMS("\n");
  2163. if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
  2164. DP &= ~DP_LINK_TRAIN_MASK_CPT;
  2165. I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
  2166. } else {
  2167. DP &= ~DP_LINK_TRAIN_MASK;
  2168. I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
  2169. }
  2170. POSTING_READ(intel_dp->output_reg);
  2171. /* We don't really know why we're doing this */
  2172. intel_wait_for_vblank(dev, intel_crtc->pipe);
  2173. if (HAS_PCH_IBX(dev) &&
  2174. I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
  2175. struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
  2176. /* Hardware workaround: leaving our transcoder select
  2177. * set to transcoder B while it's off will prevent the
  2178. * corresponding HDMI output on transcoder A.
  2179. *
  2180. * Combine this with another hardware workaround:
  2181. * transcoder select bit can only be cleared while the
  2182. * port is enabled.
  2183. */
  2184. DP &= ~DP_PIPEB_SELECT;
  2185. I915_WRITE(intel_dp->output_reg, DP);
  2186. /* Changes to enable or select take place the vblank
  2187. * after being written.
  2188. */
  2189. if (WARN_ON(crtc == NULL)) {
  2190. /* We should never try to disable a port without a crtc
  2191. * attached. For paranoia keep the code around for a
  2192. * bit. */
  2193. POSTING_READ(intel_dp->output_reg);
  2194. msleep(50);
  2195. } else
  2196. intel_wait_for_vblank(dev, intel_crtc->pipe);
  2197. }
  2198. DP &= ~DP_AUDIO_OUTPUT_ENABLE;
  2199. I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
  2200. POSTING_READ(intel_dp->output_reg);
  2201. msleep(intel_dp->panel_power_down_delay);
  2202. }
  2203. static bool
  2204. intel_dp_get_dpcd(struct intel_dp *intel_dp)
  2205. {
  2206. char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
  2207. if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
  2208. sizeof(intel_dp->dpcd)) == 0)
  2209. return false; /* aux transfer failed */
  2210. hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
  2211. 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
  2212. DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
  2213. if (intel_dp->dpcd[DP_DPCD_REV] == 0)
  2214. return false; /* DPCD not present */
  2215. /* Check if the panel supports PSR */
  2216. memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
  2217. intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
  2218. intel_dp->psr_dpcd,
  2219. sizeof(intel_dp->psr_dpcd));
  2220. if (is_edp_psr(intel_dp))
  2221. DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
  2222. if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
  2223. DP_DWN_STRM_PORT_PRESENT))
  2224. return true; /* native DP sink */
  2225. if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
  2226. return true; /* no per-port downstream info */
  2227. if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
  2228. intel_dp->downstream_ports,
  2229. DP_MAX_DOWNSTREAM_PORTS) == 0)
  2230. return false; /* downstream port status fetch failed */
  2231. return true;
  2232. }
  2233. static void
  2234. intel_dp_probe_oui(struct intel_dp *intel_dp)
  2235. {
  2236. u8 buf[3];
  2237. if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
  2238. return;
  2239. ironlake_edp_panel_vdd_on(intel_dp);
  2240. if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
  2241. DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
  2242. buf[0], buf[1], buf[2]);
  2243. if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
  2244. DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
  2245. buf[0], buf[1], buf[2]);
  2246. ironlake_edp_panel_vdd_off(intel_dp, false);
  2247. }
  2248. static bool
  2249. intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
  2250. {
  2251. int ret;
  2252. ret = intel_dp_aux_native_read_retry(intel_dp,
  2253. DP_DEVICE_SERVICE_IRQ_VECTOR,
  2254. sink_irq_vector, 1);
  2255. if (!ret)
  2256. return false;
  2257. return true;
  2258. }
  2259. static void
  2260. intel_dp_handle_test_request(struct intel_dp *intel_dp)
  2261. {
  2262. /* NAK by default */
  2263. intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
  2264. }
  2265. /*
  2266. * According to DP spec
  2267. * 5.1.2:
  2268. * 1. Read DPCD
  2269. * 2. Configure link according to Receiver Capabilities
  2270. * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
  2271. * 4. Check link status on receipt of hot-plug interrupt
  2272. */
  2273. void
  2274. intel_dp_check_link_status(struct intel_dp *intel_dp)
  2275. {
  2276. struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
  2277. u8 sink_irq_vector;
  2278. u8 link_status[DP_LINK_STATUS_SIZE];
  2279. if (!intel_encoder->connectors_active)
  2280. return;
  2281. if (WARN_ON(!intel_encoder->base.crtc))
  2282. return;
  2283. /* Try to read receiver status if the link appears to be up */
  2284. if (!intel_dp_get_link_status(intel_dp, link_status)) {
  2285. intel_dp_link_down(intel_dp);
  2286. return;
  2287. }
  2288. /* Now read the DPCD to see if it's actually running */
  2289. if (!intel_dp_get_dpcd(intel_dp)) {
  2290. intel_dp_link_down(intel_dp);
  2291. return;
  2292. }
  2293. /* Try to read the source of the interrupt */
  2294. if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
  2295. intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
  2296. /* Clear interrupt source */
  2297. intel_dp_aux_native_write_1(intel_dp,
  2298. DP_DEVICE_SERVICE_IRQ_VECTOR,
  2299. sink_irq_vector);
  2300. if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
  2301. intel_dp_handle_test_request(intel_dp);
  2302. if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
  2303. DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
  2304. }
  2305. if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
  2306. DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
  2307. drm_get_encoder_name(&intel_encoder->base));
  2308. intel_dp_start_link_train(intel_dp);
  2309. intel_dp_complete_link_train(intel_dp);
  2310. intel_dp_stop_link_train(intel_dp);
  2311. }
  2312. }
  2313. /* XXX this is probably wrong for multiple downstream ports */
  2314. static enum drm_connector_status
  2315. intel_dp_detect_dpcd(struct intel_dp *intel_dp)
  2316. {
  2317. uint8_t *dpcd = intel_dp->dpcd;
  2318. bool hpd;
  2319. uint8_t type;
  2320. if (!intel_dp_get_dpcd(intel_dp))
  2321. return connector_status_disconnected;
  2322. /* if there's no downstream port, we're done */
  2323. if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
  2324. return connector_status_connected;
  2325. /* If we're HPD-aware, SINK_COUNT changes dynamically */
  2326. hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
  2327. if (hpd) {
  2328. uint8_t reg;
  2329. if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
  2330. &reg, 1))
  2331. return connector_status_unknown;
  2332. return DP_GET_SINK_COUNT(reg) ? connector_status_connected
  2333. : connector_status_disconnected;
  2334. }
  2335. /* If no HPD, poke DDC gently */
  2336. if (drm_probe_ddc(&intel_dp->adapter))
  2337. return connector_status_connected;
  2338. /* Well we tried, say unknown for unreliable port types */
  2339. type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
  2340. if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
  2341. return connector_status_unknown;
  2342. /* Anything else is out of spec, warn and ignore */
  2343. DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
  2344. return connector_status_disconnected;
  2345. }
  2346. static enum drm_connector_status
  2347. ironlake_dp_detect(struct intel_dp *intel_dp)
  2348. {
  2349. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  2350. struct drm_i915_private *dev_priv = dev->dev_private;
  2351. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  2352. enum drm_connector_status status;
  2353. /* Can't disconnect eDP, but you can close the lid... */
  2354. if (is_edp(intel_dp)) {
  2355. status = intel_panel_detect(dev);
  2356. if (status == connector_status_unknown)
  2357. status = connector_status_connected;
  2358. return status;
  2359. }
  2360. if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
  2361. return connector_status_disconnected;
  2362. return intel_dp_detect_dpcd(intel_dp);
  2363. }
  2364. static enum drm_connector_status
  2365. g4x_dp_detect(struct intel_dp *intel_dp)
  2366. {
  2367. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  2368. struct drm_i915_private *dev_priv = dev->dev_private;
  2369. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  2370. uint32_t bit;
  2371. /* Can't disconnect eDP, but you can close the lid... */
  2372. if (is_edp(intel_dp)) {
  2373. enum drm_connector_status status;
  2374. status = intel_panel_detect(dev);
  2375. if (status == connector_status_unknown)
  2376. status = connector_status_connected;
  2377. return status;
  2378. }
  2379. switch (intel_dig_port->port) {
  2380. case PORT_B:
  2381. bit = PORTB_HOTPLUG_LIVE_STATUS;
  2382. break;
  2383. case PORT_C:
  2384. bit = PORTC_HOTPLUG_LIVE_STATUS;
  2385. break;
  2386. case PORT_D:
  2387. bit = PORTD_HOTPLUG_LIVE_STATUS;
  2388. break;
  2389. default:
  2390. return connector_status_unknown;
  2391. }
  2392. if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
  2393. return connector_status_disconnected;
  2394. return intel_dp_detect_dpcd(intel_dp);
  2395. }
  2396. static struct edid *
  2397. intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
  2398. {
  2399. struct intel_connector *intel_connector = to_intel_connector(connector);
  2400. /* use cached edid if we have one */
  2401. if (intel_connector->edid) {
  2402. struct edid *edid;
  2403. int size;
  2404. /* invalid edid */
  2405. if (IS_ERR(intel_connector->edid))
  2406. return NULL;
  2407. size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
  2408. edid = kmemdup(intel_connector->edid, size, GFP_KERNEL);
  2409. if (!edid)
  2410. return NULL;
  2411. return edid;
  2412. }
  2413. return drm_get_edid(connector, adapter);
  2414. }
  2415. static int
  2416. intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
  2417. {
  2418. struct intel_connector *intel_connector = to_intel_connector(connector);
  2419. /* use cached edid if we have one */
  2420. if (intel_connector->edid) {
  2421. /* invalid edid */
  2422. if (IS_ERR(intel_connector->edid))
  2423. return 0;
  2424. return intel_connector_update_modes(connector,
  2425. intel_connector->edid);
  2426. }
  2427. return intel_ddc_get_modes(connector, adapter);
  2428. }
  2429. static enum drm_connector_status
  2430. intel_dp_detect(struct drm_connector *connector, bool force)
  2431. {
  2432. struct intel_dp *intel_dp = intel_attached_dp(connector);
  2433. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  2434. struct intel_encoder *intel_encoder = &intel_dig_port->base;
  2435. struct drm_device *dev = connector->dev;
  2436. enum drm_connector_status status;
  2437. struct edid *edid = NULL;
  2438. DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
  2439. connector->base.id, drm_get_connector_name(connector));
  2440. intel_dp->has_audio = false;
  2441. if (HAS_PCH_SPLIT(dev))
  2442. status = ironlake_dp_detect(intel_dp);
  2443. else
  2444. status = g4x_dp_detect(intel_dp);
  2445. if (status != connector_status_connected)
  2446. return status;
  2447. intel_dp_probe_oui(intel_dp);
  2448. if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
  2449. intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
  2450. } else {
  2451. edid = intel_dp_get_edid(connector, &intel_dp->adapter);
  2452. if (edid) {
  2453. intel_dp->has_audio = drm_detect_monitor_audio(edid);
  2454. kfree(edid);
  2455. }
  2456. }
  2457. if (intel_encoder->type != INTEL_OUTPUT_EDP)
  2458. intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
  2459. return connector_status_connected;
  2460. }
  2461. static int intel_dp_get_modes(struct drm_connector *connector)
  2462. {
  2463. struct intel_dp *intel_dp = intel_attached_dp(connector);
  2464. struct intel_connector *intel_connector = to_intel_connector(connector);
  2465. struct drm_device *dev = connector->dev;
  2466. int ret;
  2467. /* We should parse the EDID data and find out if it has an audio sink
  2468. */
  2469. ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
  2470. if (ret)
  2471. return ret;
  2472. /* if eDP has no EDID, fall back to fixed mode */
  2473. if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
  2474. struct drm_display_mode *mode;
  2475. mode = drm_mode_duplicate(dev,
  2476. intel_connector->panel.fixed_mode);
  2477. if (mode) {
  2478. drm_mode_probed_add(connector, mode);
  2479. return 1;
  2480. }
  2481. }
  2482. return 0;
  2483. }
  2484. static bool
  2485. intel_dp_detect_audio(struct drm_connector *connector)
  2486. {
  2487. struct intel_dp *intel_dp = intel_attached_dp(connector);
  2488. struct edid *edid;
  2489. bool has_audio = false;
  2490. edid = intel_dp_get_edid(connector, &intel_dp->adapter);
  2491. if (edid) {
  2492. has_audio = drm_detect_monitor_audio(edid);
  2493. kfree(edid);
  2494. }
  2495. return has_audio;
  2496. }
  2497. static int
  2498. intel_dp_set_property(struct drm_connector *connector,
  2499. struct drm_property *property,
  2500. uint64_t val)
  2501. {
  2502. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  2503. struct intel_connector *intel_connector = to_intel_connector(connector);
  2504. struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
  2505. struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
  2506. int ret;
  2507. ret = drm_object_property_set_value(&connector->base, property, val);
  2508. if (ret)
  2509. return ret;
  2510. if (property == dev_priv->force_audio_property) {
  2511. int i = val;
  2512. bool has_audio;
  2513. if (i == intel_dp->force_audio)
  2514. return 0;
  2515. intel_dp->force_audio = i;
  2516. if (i == HDMI_AUDIO_AUTO)
  2517. has_audio = intel_dp_detect_audio(connector);
  2518. else
  2519. has_audio = (i == HDMI_AUDIO_ON);
  2520. if (has_audio == intel_dp->has_audio)
  2521. return 0;
  2522. intel_dp->has_audio = has_audio;
  2523. goto done;
  2524. }
  2525. if (property == dev_priv->broadcast_rgb_property) {
  2526. bool old_auto = intel_dp->color_range_auto;
  2527. uint32_t old_range = intel_dp->color_range;
  2528. switch (val) {
  2529. case INTEL_BROADCAST_RGB_AUTO:
  2530. intel_dp->color_range_auto = true;
  2531. break;
  2532. case INTEL_BROADCAST_RGB_FULL:
  2533. intel_dp->color_range_auto = false;
  2534. intel_dp->color_range = 0;
  2535. break;
  2536. case INTEL_BROADCAST_RGB_LIMITED:
  2537. intel_dp->color_range_auto = false;
  2538. intel_dp->color_range = DP_COLOR_RANGE_16_235;
  2539. break;
  2540. default:
  2541. return -EINVAL;
  2542. }
  2543. if (old_auto == intel_dp->color_range_auto &&
  2544. old_range == intel_dp->color_range)
  2545. return 0;
  2546. goto done;
  2547. }
  2548. if (is_edp(intel_dp) &&
  2549. property == connector->dev->mode_config.scaling_mode_property) {
  2550. if (val == DRM_MODE_SCALE_NONE) {
  2551. DRM_DEBUG_KMS("no scaling not supported\n");
  2552. return -EINVAL;
  2553. }
  2554. if (intel_connector->panel.fitting_mode == val) {
  2555. /* the eDP scaling property is not changed */
  2556. return 0;
  2557. }
  2558. intel_connector->panel.fitting_mode = val;
  2559. goto done;
  2560. }
  2561. return -EINVAL;
  2562. done:
  2563. if (intel_encoder->base.crtc)
  2564. intel_crtc_restore_mode(intel_encoder->base.crtc);
  2565. return 0;
  2566. }
  2567. static void
  2568. intel_dp_connector_destroy(struct drm_connector *connector)
  2569. {
  2570. struct intel_connector *intel_connector = to_intel_connector(connector);
  2571. if (!IS_ERR_OR_NULL(intel_connector->edid))
  2572. kfree(intel_connector->edid);
  2573. /* Can't call is_edp() since the encoder may have been destroyed
  2574. * already. */
  2575. if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
  2576. intel_panel_fini(&intel_connector->panel);
  2577. drm_sysfs_connector_remove(connector);
  2578. drm_connector_cleanup(connector);
  2579. kfree(connector);
  2580. }
  2581. void intel_dp_encoder_destroy(struct drm_encoder *encoder)
  2582. {
  2583. struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
  2584. struct intel_dp *intel_dp = &intel_dig_port->dp;
  2585. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  2586. i2c_del_adapter(&intel_dp->adapter);
  2587. drm_encoder_cleanup(encoder);
  2588. if (is_edp(intel_dp)) {
  2589. cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
  2590. mutex_lock(&dev->mode_config.mutex);
  2591. ironlake_panel_vdd_off_sync(intel_dp);
  2592. mutex_unlock(&dev->mode_config.mutex);
  2593. }
  2594. kfree(intel_dig_port);
  2595. }
  2596. static const struct drm_connector_funcs intel_dp_connector_funcs = {
  2597. .dpms = intel_connector_dpms,
  2598. .detect = intel_dp_detect,
  2599. .fill_modes = drm_helper_probe_single_connector_modes,
  2600. .set_property = intel_dp_set_property,
  2601. .destroy = intel_dp_connector_destroy,
  2602. };
  2603. static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
  2604. .get_modes = intel_dp_get_modes,
  2605. .mode_valid = intel_dp_mode_valid,
  2606. .best_encoder = intel_best_encoder,
  2607. };
  2608. static const struct drm_encoder_funcs intel_dp_enc_funcs = {
  2609. .destroy = intel_dp_encoder_destroy,
  2610. };
  2611. static void
  2612. intel_dp_hot_plug(struct intel_encoder *intel_encoder)
  2613. {
  2614. struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
  2615. intel_dp_check_link_status(intel_dp);
  2616. }
  2617. /* Return which DP Port should be selected for Transcoder DP control */
  2618. int
  2619. intel_trans_dp_port_sel(struct drm_crtc *crtc)
  2620. {
  2621. struct drm_device *dev = crtc->dev;
  2622. struct intel_encoder *intel_encoder;
  2623. struct intel_dp *intel_dp;
  2624. for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
  2625. intel_dp = enc_to_intel_dp(&intel_encoder->base);
  2626. if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
  2627. intel_encoder->type == INTEL_OUTPUT_EDP)
  2628. return intel_dp->output_reg;
  2629. }
  2630. return -1;
  2631. }
  2632. /* check the VBT to see whether the eDP is on DP-D port */
  2633. bool intel_dpd_is_edp(struct drm_device *dev)
  2634. {
  2635. struct drm_i915_private *dev_priv = dev->dev_private;
  2636. struct child_device_config *p_child;
  2637. int i;
  2638. if (!dev_priv->vbt.child_dev_num)
  2639. return false;
  2640. for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
  2641. p_child = dev_priv->vbt.child_dev + i;
  2642. if (p_child->dvo_port == PORT_IDPD &&
  2643. p_child->device_type == DEVICE_TYPE_eDP)
  2644. return true;
  2645. }
  2646. return false;
  2647. }
  2648. static void
  2649. intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
  2650. {
  2651. struct intel_connector *intel_connector = to_intel_connector(connector);
  2652. intel_attach_force_audio_property(connector);
  2653. intel_attach_broadcast_rgb_property(connector);
  2654. intel_dp->color_range_auto = true;
  2655. if (is_edp(intel_dp)) {
  2656. drm_mode_create_scaling_mode_property(connector->dev);
  2657. drm_object_attach_property(
  2658. &connector->base,
  2659. connector->dev->mode_config.scaling_mode_property,
  2660. DRM_MODE_SCALE_ASPECT);
  2661. intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
  2662. }
  2663. }
  2664. static void
  2665. intel_dp_init_panel_power_sequencer(struct drm_device *dev,
  2666. struct intel_dp *intel_dp,
  2667. struct edp_power_seq *out)
  2668. {
  2669. struct drm_i915_private *dev_priv = dev->dev_private;
  2670. struct edp_power_seq cur, vbt, spec, final;
  2671. u32 pp_on, pp_off, pp_div, pp;
  2672. int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
  2673. if (HAS_PCH_SPLIT(dev)) {
  2674. pp_control_reg = PCH_PP_CONTROL;
  2675. pp_on_reg = PCH_PP_ON_DELAYS;
  2676. pp_off_reg = PCH_PP_OFF_DELAYS;
  2677. pp_div_reg = PCH_PP_DIVISOR;
  2678. } else {
  2679. pp_control_reg = PIPEA_PP_CONTROL;
  2680. pp_on_reg = PIPEA_PP_ON_DELAYS;
  2681. pp_off_reg = PIPEA_PP_OFF_DELAYS;
  2682. pp_div_reg = PIPEA_PP_DIVISOR;
  2683. }
  2684. /* Workaround: Need to write PP_CONTROL with the unlock key as
  2685. * the very first thing. */
  2686. pp = ironlake_get_pp_control(intel_dp);
  2687. I915_WRITE(pp_control_reg, pp);
  2688. pp_on = I915_READ(pp_on_reg);
  2689. pp_off = I915_READ(pp_off_reg);
  2690. pp_div = I915_READ(pp_div_reg);
  2691. /* Pull timing values out of registers */
  2692. cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
  2693. PANEL_POWER_UP_DELAY_SHIFT;
  2694. cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
  2695. PANEL_LIGHT_ON_DELAY_SHIFT;
  2696. cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
  2697. PANEL_LIGHT_OFF_DELAY_SHIFT;
  2698. cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
  2699. PANEL_POWER_DOWN_DELAY_SHIFT;
  2700. cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
  2701. PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
  2702. DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
  2703. cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
  2704. vbt = dev_priv->vbt.edp_pps;
  2705. /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
  2706. * our hw here, which are all in 100usec. */
  2707. spec.t1_t3 = 210 * 10;
  2708. spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
  2709. spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
  2710. spec.t10 = 500 * 10;
  2711. /* This one is special and actually in units of 100ms, but zero
  2712. * based in the hw (so we need to add 100 ms). But the sw vbt
  2713. * table multiplies it with 1000 to make it in units of 100usec,
  2714. * too. */
  2715. spec.t11_t12 = (510 + 100) * 10;
  2716. DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
  2717. vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
  2718. /* Use the max of the register settings and vbt. If both are
  2719. * unset, fall back to the spec limits. */
  2720. #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
  2721. spec.field : \
  2722. max(cur.field, vbt.field))
  2723. assign_final(t1_t3);
  2724. assign_final(t8);
  2725. assign_final(t9);
  2726. assign_final(t10);
  2727. assign_final(t11_t12);
  2728. #undef assign_final
  2729. #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
  2730. intel_dp->panel_power_up_delay = get_delay(t1_t3);
  2731. intel_dp->backlight_on_delay = get_delay(t8);
  2732. intel_dp->backlight_off_delay = get_delay(t9);
  2733. intel_dp->panel_power_down_delay = get_delay(t10);
  2734. intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
  2735. #undef get_delay
  2736. DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
  2737. intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
  2738. intel_dp->panel_power_cycle_delay);
  2739. DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
  2740. intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
  2741. if (out)
  2742. *out = final;
  2743. }
  2744. static void
  2745. intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
  2746. struct intel_dp *intel_dp,
  2747. struct edp_power_seq *seq)
  2748. {
  2749. struct drm_i915_private *dev_priv = dev->dev_private;
  2750. u32 pp_on, pp_off, pp_div, port_sel = 0;
  2751. int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
  2752. int pp_on_reg, pp_off_reg, pp_div_reg;
  2753. if (HAS_PCH_SPLIT(dev)) {
  2754. pp_on_reg = PCH_PP_ON_DELAYS;
  2755. pp_off_reg = PCH_PP_OFF_DELAYS;
  2756. pp_div_reg = PCH_PP_DIVISOR;
  2757. } else {
  2758. pp_on_reg = PIPEA_PP_ON_DELAYS;
  2759. pp_off_reg = PIPEA_PP_OFF_DELAYS;
  2760. pp_div_reg = PIPEA_PP_DIVISOR;
  2761. }
  2762. /* And finally store the new values in the power sequencer. */
  2763. pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
  2764. (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
  2765. pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
  2766. (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
  2767. /* Compute the divisor for the pp clock, simply match the Bspec
  2768. * formula. */
  2769. pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
  2770. pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
  2771. << PANEL_POWER_CYCLE_DELAY_SHIFT);
  2772. /* Haswell doesn't have any port selection bits for the panel
  2773. * power sequencer any more. */
  2774. if (IS_VALLEYVIEW(dev)) {
  2775. port_sel = I915_READ(pp_on_reg) & 0xc0000000;
  2776. } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
  2777. if (dp_to_dig_port(intel_dp)->port == PORT_A)
  2778. port_sel = PANEL_POWER_PORT_DP_A;
  2779. else
  2780. port_sel = PANEL_POWER_PORT_DP_D;
  2781. }
  2782. pp_on |= port_sel;
  2783. I915_WRITE(pp_on_reg, pp_on);
  2784. I915_WRITE(pp_off_reg, pp_off);
  2785. I915_WRITE(pp_div_reg, pp_div);
  2786. DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
  2787. I915_READ(pp_on_reg),
  2788. I915_READ(pp_off_reg),
  2789. I915_READ(pp_div_reg));
  2790. }
  2791. static bool intel_edp_init_connector(struct intel_dp *intel_dp,
  2792. struct intel_connector *intel_connector)
  2793. {
  2794. struct drm_connector *connector = &intel_connector->base;
  2795. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  2796. struct drm_device *dev = intel_dig_port->base.base.dev;
  2797. struct drm_i915_private *dev_priv = dev->dev_private;
  2798. struct drm_display_mode *fixed_mode = NULL;
  2799. struct edp_power_seq power_seq = { 0 };
  2800. bool has_dpcd;
  2801. struct drm_display_mode *scan;
  2802. struct edid *edid;
  2803. if (!is_edp(intel_dp))
  2804. return true;
  2805. intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
  2806. /* Cache DPCD and EDID for edp. */
  2807. ironlake_edp_panel_vdd_on(intel_dp);
  2808. has_dpcd = intel_dp_get_dpcd(intel_dp);
  2809. ironlake_edp_panel_vdd_off(intel_dp, false);
  2810. if (has_dpcd) {
  2811. if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
  2812. dev_priv->no_aux_handshake =
  2813. intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
  2814. DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
  2815. } else {
  2816. /* if this fails, presume the device is a ghost */
  2817. DRM_INFO("failed to retrieve link info, disabling eDP\n");
  2818. return false;
  2819. }
  2820. /* We now know it's not a ghost, init power sequence regs. */
  2821. intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
  2822. &power_seq);
  2823. ironlake_edp_panel_vdd_on(intel_dp);
  2824. edid = drm_get_edid(connector, &intel_dp->adapter);
  2825. if (edid) {
  2826. if (drm_add_edid_modes(connector, edid)) {
  2827. drm_mode_connector_update_edid_property(connector,
  2828. edid);
  2829. drm_edid_to_eld(connector, edid);
  2830. } else {
  2831. kfree(edid);
  2832. edid = ERR_PTR(-EINVAL);
  2833. }
  2834. } else {
  2835. edid = ERR_PTR(-ENOENT);
  2836. }
  2837. intel_connector->edid = edid;
  2838. /* prefer fixed mode from EDID if available */
  2839. list_for_each_entry(scan, &connector->probed_modes, head) {
  2840. if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
  2841. fixed_mode = drm_mode_duplicate(dev, scan);
  2842. break;
  2843. }
  2844. }
  2845. /* fallback to VBT if available for eDP */
  2846. if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
  2847. fixed_mode = drm_mode_duplicate(dev,
  2848. dev_priv->vbt.lfp_lvds_vbt_mode);
  2849. if (fixed_mode)
  2850. fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
  2851. }
  2852. ironlake_edp_panel_vdd_off(intel_dp, false);
  2853. intel_panel_init(&intel_connector->panel, fixed_mode);
  2854. intel_panel_setup_backlight(connector);
  2855. return true;
  2856. }
  2857. bool
  2858. intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
  2859. struct intel_connector *intel_connector)
  2860. {
  2861. struct drm_connector *connector = &intel_connector->base;
  2862. struct intel_dp *intel_dp = &intel_dig_port->dp;
  2863. struct intel_encoder *intel_encoder = &intel_dig_port->base;
  2864. struct drm_device *dev = intel_encoder->base.dev;
  2865. struct drm_i915_private *dev_priv = dev->dev_private;
  2866. enum port port = intel_dig_port->port;
  2867. const char *name = NULL;
  2868. int type, error;
  2869. /* Preserve the current hw state. */
  2870. intel_dp->DP = I915_READ(intel_dp->output_reg);
  2871. intel_dp->attached_connector = intel_connector;
  2872. type = DRM_MODE_CONNECTOR_DisplayPort;
  2873. /*
  2874. * FIXME : We need to initialize built-in panels before external panels.
  2875. * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
  2876. */
  2877. switch (port) {
  2878. case PORT_A:
  2879. type = DRM_MODE_CONNECTOR_eDP;
  2880. break;
  2881. case PORT_C:
  2882. if (IS_VALLEYVIEW(dev))
  2883. type = DRM_MODE_CONNECTOR_eDP;
  2884. break;
  2885. case PORT_D:
  2886. if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev))
  2887. type = DRM_MODE_CONNECTOR_eDP;
  2888. break;
  2889. default: /* silence GCC warning */
  2890. break;
  2891. }
  2892. /*
  2893. * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
  2894. * for DP the encoder type can be set by the caller to
  2895. * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
  2896. */
  2897. if (type == DRM_MODE_CONNECTOR_eDP)
  2898. intel_encoder->type = INTEL_OUTPUT_EDP;
  2899. DRM_DEBUG_KMS("Adding %s connector on port %c\n",
  2900. type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
  2901. port_name(port));
  2902. drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
  2903. drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
  2904. connector->interlace_allowed = true;
  2905. connector->doublescan_allowed = 0;
  2906. INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
  2907. ironlake_panel_vdd_work);
  2908. intel_connector_attach_encoder(intel_connector, intel_encoder);
  2909. drm_sysfs_connector_add(connector);
  2910. if (HAS_DDI(dev))
  2911. intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
  2912. else
  2913. intel_connector->get_hw_state = intel_connector_get_hw_state;
  2914. intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
  2915. if (HAS_DDI(dev)) {
  2916. switch (intel_dig_port->port) {
  2917. case PORT_A:
  2918. intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
  2919. break;
  2920. case PORT_B:
  2921. intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
  2922. break;
  2923. case PORT_C:
  2924. intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
  2925. break;
  2926. case PORT_D:
  2927. intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
  2928. break;
  2929. default:
  2930. BUG();
  2931. }
  2932. }
  2933. /* Set up the DDC bus. */
  2934. switch (port) {
  2935. case PORT_A:
  2936. intel_encoder->hpd_pin = HPD_PORT_A;
  2937. name = "DPDDC-A";
  2938. break;
  2939. case PORT_B:
  2940. intel_encoder->hpd_pin = HPD_PORT_B;
  2941. name = "DPDDC-B";
  2942. break;
  2943. case PORT_C:
  2944. intel_encoder->hpd_pin = HPD_PORT_C;
  2945. name = "DPDDC-C";
  2946. break;
  2947. case PORT_D:
  2948. intel_encoder->hpd_pin = HPD_PORT_D;
  2949. name = "DPDDC-D";
  2950. break;
  2951. default:
  2952. BUG();
  2953. }
  2954. error = intel_dp_i2c_init(intel_dp, intel_connector, name);
  2955. WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
  2956. error, port_name(port));
  2957. intel_dp->psr_setup_done = false;
  2958. if (!intel_edp_init_connector(intel_dp, intel_connector)) {
  2959. i2c_del_adapter(&intel_dp->adapter);
  2960. if (is_edp(intel_dp)) {
  2961. cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
  2962. mutex_lock(&dev->mode_config.mutex);
  2963. ironlake_panel_vdd_off_sync(intel_dp);
  2964. mutex_unlock(&dev->mode_config.mutex);
  2965. }
  2966. drm_sysfs_connector_remove(connector);
  2967. drm_connector_cleanup(connector);
  2968. return false;
  2969. }
  2970. intel_dp_add_properties(intel_dp, connector);
  2971. /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
  2972. * 0xd. Failure to do so will result in spurious interrupts being
  2973. * generated on the port when a cable is not attached.
  2974. */
  2975. if (IS_G4X(dev) && !IS_GM45(dev)) {
  2976. u32 temp = I915_READ(PEG_BAND_GAP_DATA);
  2977. I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
  2978. }
  2979. return true;
  2980. }
  2981. void
  2982. intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
  2983. {
  2984. struct intel_digital_port *intel_dig_port;
  2985. struct intel_encoder *intel_encoder;
  2986. struct drm_encoder *encoder;
  2987. struct intel_connector *intel_connector;
  2988. intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
  2989. if (!intel_dig_port)
  2990. return;
  2991. intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
  2992. if (!intel_connector) {
  2993. kfree(intel_dig_port);
  2994. return;
  2995. }
  2996. intel_encoder = &intel_dig_port->base;
  2997. encoder = &intel_encoder->base;
  2998. drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
  2999. DRM_MODE_ENCODER_TMDS);
  3000. intel_encoder->compute_config = intel_dp_compute_config;
  3001. intel_encoder->mode_set = intel_dp_mode_set;
  3002. intel_encoder->disable = intel_disable_dp;
  3003. intel_encoder->post_disable = intel_post_disable_dp;
  3004. intel_encoder->get_hw_state = intel_dp_get_hw_state;
  3005. intel_encoder->get_config = intel_dp_get_config;
  3006. if (IS_VALLEYVIEW(dev)) {
  3007. intel_encoder->pre_pll_enable = intel_dp_pre_pll_enable;
  3008. intel_encoder->pre_enable = vlv_pre_enable_dp;
  3009. intel_encoder->enable = vlv_enable_dp;
  3010. } else {
  3011. intel_encoder->pre_enable = intel_pre_enable_dp;
  3012. intel_encoder->enable = intel_enable_dp;
  3013. }
  3014. intel_dig_port->port = port;
  3015. intel_dig_port->dp.output_reg = output_reg;
  3016. intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
  3017. intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
  3018. intel_encoder->cloneable = false;
  3019. intel_encoder->hot_plug = intel_dp_hot_plug;
  3020. if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
  3021. drm_encoder_cleanup(encoder);
  3022. kfree(intel_dig_port);
  3023. kfree(intel_connector);
  3024. }
  3025. }