tegra20.dtsi 5.3 KB

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  1. /include/ "skeleton.dtsi"
  2. / {
  3. compatible = "nvidia,tegra20";
  4. interrupt-parent = <&intc>;
  5. cache-controller@50043000 {
  6. compatible = "arm,pl310-cache";
  7. reg = <0x50043000 0x1000>;
  8. arm,data-latency = <5 5 2>;
  9. arm,tag-latency = <4 4 2>;
  10. cache-unified;
  11. cache-level = <2>;
  12. };
  13. intc: interrupt-controller {
  14. compatible = "arm,cortex-a9-gic";
  15. reg = <0x50041000 0x1000
  16. 0x50040100 0x0100>;
  17. interrupt-controller;
  18. #interrupt-cells = <3>;
  19. };
  20. apbdma: dma {
  21. compatible = "nvidia,tegra20-apbdma";
  22. reg = <0x6000a000 0x1200>;
  23. interrupts = <0 104 0x04
  24. 0 105 0x04
  25. 0 106 0x04
  26. 0 107 0x04
  27. 0 108 0x04
  28. 0 109 0x04
  29. 0 110 0x04
  30. 0 111 0x04
  31. 0 112 0x04
  32. 0 113 0x04
  33. 0 114 0x04
  34. 0 115 0x04
  35. 0 116 0x04
  36. 0 117 0x04
  37. 0 118 0x04
  38. 0 119 0x04>;
  39. };
  40. ahb {
  41. compatible = "nvidia,tegra20-ahb";
  42. reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
  43. };
  44. gpio: gpio {
  45. compatible = "nvidia,tegra20-gpio";
  46. reg = <0x6000d000 0x1000>;
  47. interrupts = <0 32 0x04
  48. 0 33 0x04
  49. 0 34 0x04
  50. 0 35 0x04
  51. 0 55 0x04
  52. 0 87 0x04
  53. 0 89 0x04>;
  54. #gpio-cells = <2>;
  55. gpio-controller;
  56. #interrupt-cells = <2>;
  57. interrupt-controller;
  58. };
  59. pinmux: pinmux {
  60. compatible = "nvidia,tegra20-pinmux";
  61. reg = <0x70000014 0x10 /* Tri-state registers */
  62. 0x70000080 0x20 /* Mux registers */
  63. 0x700000a0 0x14 /* Pull-up/down registers */
  64. 0x70000868 0xa8>; /* Pad control registers */
  65. };
  66. das {
  67. compatible = "nvidia,tegra20-das";
  68. reg = <0x70000c00 0x80>;
  69. };
  70. tegra_i2s1: i2s@70002800 {
  71. compatible = "nvidia,tegra20-i2s";
  72. reg = <0x70002800 0x200>;
  73. interrupts = <0 13 0x04>;
  74. nvidia,dma-request-selector = <&apbdma 2>;
  75. status = "disabled";
  76. };
  77. tegra_i2s2: i2s@70002a00 {
  78. compatible = "nvidia,tegra20-i2s";
  79. reg = <0x70002a00 0x200>;
  80. interrupts = <0 3 0x04>;
  81. nvidia,dma-request-selector = <&apbdma 1>;
  82. status = "disabled";
  83. };
  84. serial@70006000 {
  85. compatible = "nvidia,tegra20-uart";
  86. reg = <0x70006000 0x40>;
  87. reg-shift = <2>;
  88. interrupts = <0 36 0x04>;
  89. status = "disabled";
  90. };
  91. serial@70006040 {
  92. compatible = "nvidia,tegra20-uart";
  93. reg = <0x70006040 0x40>;
  94. reg-shift = <2>;
  95. interrupts = <0 37 0x04>;
  96. status = "disabled";
  97. };
  98. serial@70006200 {
  99. compatible = "nvidia,tegra20-uart";
  100. reg = <0x70006200 0x100>;
  101. reg-shift = <2>;
  102. interrupts = <0 46 0x04>;
  103. status = "disabled";
  104. };
  105. serial@70006300 {
  106. compatible = "nvidia,tegra20-uart";
  107. reg = <0x70006300 0x100>;
  108. reg-shift = <2>;
  109. interrupts = <0 90 0x04>;
  110. status = "disabled";
  111. };
  112. serial@70006400 {
  113. compatible = "nvidia,tegra20-uart";
  114. reg = <0x70006400 0x100>;
  115. reg-shift = <2>;
  116. interrupts = <0 91 0x04>;
  117. status = "disabled";
  118. };
  119. pwm: pwm {
  120. compatible = "nvidia,tegra20-pwm";
  121. reg = <0x7000a000 0x100>;
  122. #pwm-cells = <2>;
  123. };
  124. i2c@7000c000 {
  125. compatible = "nvidia,tegra20-i2c";
  126. reg = <0x7000c000 0x100>;
  127. interrupts = <0 38 0x04>;
  128. #address-cells = <1>;
  129. #size-cells = <0>;
  130. status = "disabled";
  131. };
  132. i2c@7000c400 {
  133. compatible = "nvidia,tegra20-i2c";
  134. reg = <0x7000c400 0x100>;
  135. interrupts = <0 84 0x04>;
  136. #address-cells = <1>;
  137. #size-cells = <0>;
  138. status = "disabled";
  139. };
  140. i2c@7000c500 {
  141. compatible = "nvidia,tegra20-i2c";
  142. reg = <0x7000c500 0x100>;
  143. interrupts = <0 92 0x04>;
  144. #address-cells = <1>;
  145. #size-cells = <0>;
  146. status = "disabled";
  147. };
  148. i2c@7000d000 {
  149. compatible = "nvidia,tegra20-i2c-dvc";
  150. reg = <0x7000d000 0x200>;
  151. interrupts = <0 53 0x04>;
  152. #address-cells = <1>;
  153. #size-cells = <0>;
  154. status = "disabled";
  155. };
  156. pmc {
  157. compatible = "nvidia,tegra20-pmc";
  158. reg = <0x7000e400 0x400>;
  159. };
  160. memory-controller@7000f000 {
  161. compatible = "nvidia,tegra20-mc";
  162. reg = <0x7000f000 0x024
  163. 0x7000f03c 0x3c4>;
  164. interrupts = <0 77 0x04>;
  165. };
  166. gart {
  167. compatible = "nvidia,tegra20-gart";
  168. reg = <0x7000f024 0x00000018 /* controller registers */
  169. 0x58000000 0x02000000>; /* GART aperture */
  170. };
  171. memory-controller@7000f400 {
  172. compatible = "nvidia,tegra20-emc";
  173. reg = <0x7000f400 0x200>;
  174. #address-cells = <1>;
  175. #size-cells = <0>;
  176. };
  177. usb@c5000000 {
  178. compatible = "nvidia,tegra20-ehci", "usb-ehci";
  179. reg = <0xc5000000 0x4000>;
  180. interrupts = <0 20 0x04>;
  181. phy_type = "utmi";
  182. nvidia,has-legacy-mode;
  183. status = "disabled";
  184. };
  185. usb@c5004000 {
  186. compatible = "nvidia,tegra20-ehci", "usb-ehci";
  187. reg = <0xc5004000 0x4000>;
  188. interrupts = <0 21 0x04>;
  189. phy_type = "ulpi";
  190. status = "disabled";
  191. };
  192. usb@c5008000 {
  193. compatible = "nvidia,tegra20-ehci", "usb-ehci";
  194. reg = <0xc5008000 0x4000>;
  195. interrupts = <0 97 0x04>;
  196. phy_type = "utmi";
  197. status = "disabled";
  198. };
  199. sdhci@c8000000 {
  200. compatible = "nvidia,tegra20-sdhci";
  201. reg = <0xc8000000 0x200>;
  202. interrupts = <0 14 0x04>;
  203. status = "disabled";
  204. };
  205. sdhci@c8000200 {
  206. compatible = "nvidia,tegra20-sdhci";
  207. reg = <0xc8000200 0x200>;
  208. interrupts = <0 15 0x04>;
  209. status = "disabled";
  210. };
  211. sdhci@c8000400 {
  212. compatible = "nvidia,tegra20-sdhci";
  213. reg = <0xc8000400 0x200>;
  214. interrupts = <0 19 0x04>;
  215. status = "disabled";
  216. };
  217. sdhci@c8000600 {
  218. compatible = "nvidia,tegra20-sdhci";
  219. reg = <0xc8000600 0x200>;
  220. interrupts = <0 31 0x04>;
  221. status = "disabled";
  222. };
  223. pmu {
  224. compatible = "arm,cortex-a9-pmu";
  225. interrupts = <0 56 0x04
  226. 0 57 0x04>;
  227. };
  228. };