core.c 18 KB

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  1. /*
  2. * Copyright (c) 2005-2011 Atheros Communications Inc.
  3. * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16. */
  17. #include <linux/module.h>
  18. #include <linux/firmware.h>
  19. #include "core.h"
  20. #include "mac.h"
  21. #include "htc.h"
  22. #include "hif.h"
  23. #include "wmi.h"
  24. #include "bmi.h"
  25. #include "debug.h"
  26. #include "htt.h"
  27. unsigned int ath10k_debug_mask;
  28. static bool uart_print;
  29. static unsigned int ath10k_p2p;
  30. module_param_named(debug_mask, ath10k_debug_mask, uint, 0644);
  31. module_param(uart_print, bool, 0644);
  32. module_param_named(p2p, ath10k_p2p, uint, 0644);
  33. MODULE_PARM_DESC(debug_mask, "Debugging mask");
  34. MODULE_PARM_DESC(uart_print, "Uart target debugging");
  35. MODULE_PARM_DESC(p2p, "Enable ath10k P2P support");
  36. static const struct ath10k_hw_params ath10k_hw_params_list[] = {
  37. {
  38. .id = QCA988X_HW_2_0_VERSION,
  39. .name = "qca988x hw2.0",
  40. .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR,
  41. .fw = {
  42. .dir = QCA988X_HW_2_0_FW_DIR,
  43. .fw = QCA988X_HW_2_0_FW_FILE,
  44. .otp = QCA988X_HW_2_0_OTP_FILE,
  45. .board = QCA988X_HW_2_0_BOARD_DATA_FILE,
  46. },
  47. },
  48. };
  49. static void ath10k_send_suspend_complete(struct ath10k *ar)
  50. {
  51. ath10k_dbg(ATH10K_DBG_BOOT, "boot suspend complete\n");
  52. ar->is_target_paused = true;
  53. wake_up(&ar->event_queue);
  54. }
  55. static int ath10k_init_connect_htc(struct ath10k *ar)
  56. {
  57. int status;
  58. status = ath10k_wmi_connect_htc_service(ar);
  59. if (status)
  60. goto conn_fail;
  61. /* Start HTC */
  62. status = ath10k_htc_start(&ar->htc);
  63. if (status)
  64. goto conn_fail;
  65. /* Wait for WMI event to be ready */
  66. status = ath10k_wmi_wait_for_service_ready(ar);
  67. if (status <= 0) {
  68. ath10k_warn("wmi service ready event not received");
  69. status = -ETIMEDOUT;
  70. goto timeout;
  71. }
  72. ath10k_dbg(ATH10K_DBG_BOOT, "boot wmi ready\n");
  73. return 0;
  74. timeout:
  75. ath10k_htc_stop(&ar->htc);
  76. conn_fail:
  77. return status;
  78. }
  79. static int ath10k_init_configure_target(struct ath10k *ar)
  80. {
  81. u32 param_host;
  82. int ret;
  83. /* tell target which HTC version it is used*/
  84. ret = ath10k_bmi_write32(ar, hi_app_host_interest,
  85. HTC_PROTOCOL_VERSION);
  86. if (ret) {
  87. ath10k_err("settings HTC version failed\n");
  88. return ret;
  89. }
  90. /* set the firmware mode to STA/IBSS/AP */
  91. ret = ath10k_bmi_read32(ar, hi_option_flag, &param_host);
  92. if (ret) {
  93. ath10k_err("setting firmware mode (1/2) failed\n");
  94. return ret;
  95. }
  96. /* TODO following parameters need to be re-visited. */
  97. /* num_device */
  98. param_host |= (1 << HI_OPTION_NUM_DEV_SHIFT);
  99. /* Firmware mode */
  100. /* FIXME: Why FW_MODE_AP ??.*/
  101. param_host |= (HI_OPTION_FW_MODE_AP << HI_OPTION_FW_MODE_SHIFT);
  102. /* mac_addr_method */
  103. param_host |= (1 << HI_OPTION_MAC_ADDR_METHOD_SHIFT);
  104. /* firmware_bridge */
  105. param_host |= (0 << HI_OPTION_FW_BRIDGE_SHIFT);
  106. /* fwsubmode */
  107. param_host |= (0 << HI_OPTION_FW_SUBMODE_SHIFT);
  108. ret = ath10k_bmi_write32(ar, hi_option_flag, param_host);
  109. if (ret) {
  110. ath10k_err("setting firmware mode (2/2) failed\n");
  111. return ret;
  112. }
  113. /* We do all byte-swapping on the host */
  114. ret = ath10k_bmi_write32(ar, hi_be, 0);
  115. if (ret) {
  116. ath10k_err("setting host CPU BE mode failed\n");
  117. return ret;
  118. }
  119. /* FW descriptor/Data swap flags */
  120. ret = ath10k_bmi_write32(ar, hi_fw_swap, 0);
  121. if (ret) {
  122. ath10k_err("setting FW data/desc swap flags failed\n");
  123. return ret;
  124. }
  125. return 0;
  126. }
  127. static const struct firmware *ath10k_fetch_fw_file(struct ath10k *ar,
  128. const char *dir,
  129. const char *file)
  130. {
  131. char filename[100];
  132. const struct firmware *fw;
  133. int ret;
  134. if (file == NULL)
  135. return ERR_PTR(-ENOENT);
  136. if (dir == NULL)
  137. dir = ".";
  138. snprintf(filename, sizeof(filename), "%s/%s", dir, file);
  139. ret = request_firmware(&fw, filename, ar->dev);
  140. if (ret)
  141. return ERR_PTR(ret);
  142. return fw;
  143. }
  144. static int ath10k_push_board_ext_data(struct ath10k *ar,
  145. const struct firmware *fw)
  146. {
  147. u32 board_data_size = QCA988X_BOARD_DATA_SZ;
  148. u32 board_ext_data_size = QCA988X_BOARD_EXT_DATA_SZ;
  149. u32 board_ext_data_addr;
  150. int ret;
  151. ret = ath10k_bmi_read32(ar, hi_board_ext_data, &board_ext_data_addr);
  152. if (ret) {
  153. ath10k_err("could not read board ext data addr (%d)\n", ret);
  154. return ret;
  155. }
  156. ath10k_dbg(ATH10K_DBG_BOOT,
  157. "boot push board extended data addr 0x%x\n",
  158. board_ext_data_addr);
  159. if (board_ext_data_addr == 0)
  160. return 0;
  161. if (fw->size != (board_data_size + board_ext_data_size)) {
  162. ath10k_err("invalid board (ext) data sizes %zu != %d+%d\n",
  163. fw->size, board_data_size, board_ext_data_size);
  164. return -EINVAL;
  165. }
  166. ret = ath10k_bmi_write_memory(ar, board_ext_data_addr,
  167. fw->data + board_data_size,
  168. board_ext_data_size);
  169. if (ret) {
  170. ath10k_err("could not write board ext data (%d)\n", ret);
  171. return ret;
  172. }
  173. ret = ath10k_bmi_write32(ar, hi_board_ext_data_config,
  174. (board_ext_data_size << 16) | 1);
  175. if (ret) {
  176. ath10k_err("could not write board ext data bit (%d)\n", ret);
  177. return ret;
  178. }
  179. return 0;
  180. }
  181. static int ath10k_download_board_data(struct ath10k *ar)
  182. {
  183. const struct firmware *fw = ar->board_data;
  184. u32 board_data_size = QCA988X_BOARD_DATA_SZ;
  185. u32 address;
  186. int ret;
  187. ret = ath10k_push_board_ext_data(ar, fw);
  188. if (ret) {
  189. ath10k_err("could not push board ext data (%d)\n", ret);
  190. goto exit;
  191. }
  192. ret = ath10k_bmi_read32(ar, hi_board_data, &address);
  193. if (ret) {
  194. ath10k_err("could not read board data addr (%d)\n", ret);
  195. goto exit;
  196. }
  197. ret = ath10k_bmi_write_memory(ar, address, fw->data,
  198. min_t(u32, board_data_size, fw->size));
  199. if (ret) {
  200. ath10k_err("could not write board data (%d)\n", ret);
  201. goto exit;
  202. }
  203. ret = ath10k_bmi_write32(ar, hi_board_data_initialized, 1);
  204. if (ret) {
  205. ath10k_err("could not write board data bit (%d)\n", ret);
  206. goto exit;
  207. }
  208. exit:
  209. return ret;
  210. }
  211. static int ath10k_download_and_run_otp(struct ath10k *ar)
  212. {
  213. const struct firmware *fw = ar->otp;
  214. u32 address = ar->hw_params.patch_load_addr;
  215. u32 exec_param;
  216. int ret;
  217. /* OTP is optional */
  218. if (!ar->otp)
  219. return 0;
  220. ret = ath10k_bmi_fast_download(ar, address, fw->data, fw->size);
  221. if (ret) {
  222. ath10k_err("could not write otp (%d)\n", ret);
  223. goto exit;
  224. }
  225. exec_param = 0;
  226. ret = ath10k_bmi_execute(ar, address, &exec_param);
  227. if (ret) {
  228. ath10k_err("could not execute otp (%d)\n", ret);
  229. goto exit;
  230. }
  231. exit:
  232. return ret;
  233. }
  234. static int ath10k_download_fw(struct ath10k *ar)
  235. {
  236. const struct firmware *fw = ar->firmware;
  237. u32 address;
  238. int ret;
  239. address = ar->hw_params.patch_load_addr;
  240. ret = ath10k_bmi_fast_download(ar, address, fw->data, fw->size);
  241. if (ret) {
  242. ath10k_err("could not write fw (%d)\n", ret);
  243. goto exit;
  244. }
  245. exit:
  246. return ret;
  247. }
  248. static void ath10k_core_free_firmware_files(struct ath10k *ar)
  249. {
  250. if (ar->board_data && !IS_ERR(ar->board_data))
  251. release_firmware(ar->board_data);
  252. if (ar->otp && !IS_ERR(ar->otp))
  253. release_firmware(ar->otp);
  254. if (ar->firmware && !IS_ERR(ar->firmware))
  255. release_firmware(ar->firmware);
  256. ar->board_data = NULL;
  257. ar->otp = NULL;
  258. ar->firmware = NULL;
  259. }
  260. static int ath10k_core_fetch_firmware_files(struct ath10k *ar)
  261. {
  262. int ret = 0;
  263. if (ar->hw_params.fw.fw == NULL) {
  264. ath10k_err("firmware file not defined\n");
  265. return -EINVAL;
  266. }
  267. if (ar->hw_params.fw.board == NULL) {
  268. ath10k_err("board data file not defined");
  269. return -EINVAL;
  270. }
  271. ar->board_data = ath10k_fetch_fw_file(ar,
  272. ar->hw_params.fw.dir,
  273. ar->hw_params.fw.board);
  274. if (IS_ERR(ar->board_data)) {
  275. ret = PTR_ERR(ar->board_data);
  276. ath10k_err("could not fetch board data (%d)\n", ret);
  277. goto err;
  278. }
  279. ar->firmware = ath10k_fetch_fw_file(ar,
  280. ar->hw_params.fw.dir,
  281. ar->hw_params.fw.fw);
  282. if (IS_ERR(ar->firmware)) {
  283. ret = PTR_ERR(ar->firmware);
  284. ath10k_err("could not fetch firmware (%d)\n", ret);
  285. goto err;
  286. }
  287. /* OTP may be undefined. If so, don't fetch it at all */
  288. if (ar->hw_params.fw.otp == NULL)
  289. return 0;
  290. ar->otp = ath10k_fetch_fw_file(ar,
  291. ar->hw_params.fw.dir,
  292. ar->hw_params.fw.otp);
  293. if (IS_ERR(ar->otp)) {
  294. ret = PTR_ERR(ar->otp);
  295. ath10k_err("could not fetch otp (%d)\n", ret);
  296. goto err;
  297. }
  298. return 0;
  299. err:
  300. ath10k_core_free_firmware_files(ar);
  301. return ret;
  302. }
  303. static int ath10k_init_download_firmware(struct ath10k *ar)
  304. {
  305. int ret;
  306. ret = ath10k_download_board_data(ar);
  307. if (ret)
  308. return ret;
  309. ret = ath10k_download_and_run_otp(ar);
  310. if (ret)
  311. return ret;
  312. ret = ath10k_download_fw(ar);
  313. if (ret)
  314. return ret;
  315. return ret;
  316. }
  317. static int ath10k_init_uart(struct ath10k *ar)
  318. {
  319. int ret;
  320. /*
  321. * Explicitly setting UART prints to zero as target turns it on
  322. * based on scratch registers.
  323. */
  324. ret = ath10k_bmi_write32(ar, hi_serial_enable, 0);
  325. if (ret) {
  326. ath10k_warn("could not disable UART prints (%d)\n", ret);
  327. return ret;
  328. }
  329. if (!uart_print) {
  330. ath10k_info("UART prints disabled\n");
  331. return 0;
  332. }
  333. ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin, 7);
  334. if (ret) {
  335. ath10k_warn("could not enable UART prints (%d)\n", ret);
  336. return ret;
  337. }
  338. ret = ath10k_bmi_write32(ar, hi_serial_enable, 1);
  339. if (ret) {
  340. ath10k_warn("could not enable UART prints (%d)\n", ret);
  341. return ret;
  342. }
  343. /* Set the UART baud rate to 19200. */
  344. ret = ath10k_bmi_write32(ar, hi_desired_baud_rate, 19200);
  345. if (ret) {
  346. ath10k_warn("could not set the baud rate (%d)\n", ret);
  347. return ret;
  348. }
  349. ath10k_info("UART prints enabled\n");
  350. return 0;
  351. }
  352. static int ath10k_init_hw_params(struct ath10k *ar)
  353. {
  354. const struct ath10k_hw_params *uninitialized_var(hw_params);
  355. int i;
  356. for (i = 0; i < ARRAY_SIZE(ath10k_hw_params_list); i++) {
  357. hw_params = &ath10k_hw_params_list[i];
  358. if (hw_params->id == ar->target_version)
  359. break;
  360. }
  361. if (i == ARRAY_SIZE(ath10k_hw_params_list)) {
  362. ath10k_err("Unsupported hardware version: 0x%x\n",
  363. ar->target_version);
  364. return -EINVAL;
  365. }
  366. ar->hw_params = *hw_params;
  367. ath10k_info("Hardware name %s version 0x%x\n",
  368. ar->hw_params.name, ar->target_version);
  369. return 0;
  370. }
  371. static void ath10k_core_restart(struct work_struct *work)
  372. {
  373. struct ath10k *ar = container_of(work, struct ath10k, restart_work);
  374. mutex_lock(&ar->conf_mutex);
  375. switch (ar->state) {
  376. case ATH10K_STATE_ON:
  377. ath10k_halt(ar);
  378. ar->state = ATH10K_STATE_RESTARTING;
  379. ieee80211_restart_hw(ar->hw);
  380. break;
  381. case ATH10K_STATE_OFF:
  382. /* this can happen if driver is being unloaded */
  383. ath10k_warn("cannot restart a device that hasn't been started\n");
  384. break;
  385. case ATH10K_STATE_RESTARTING:
  386. case ATH10K_STATE_RESTARTED:
  387. ar->state = ATH10K_STATE_WEDGED;
  388. /* fall through */
  389. case ATH10K_STATE_WEDGED:
  390. ath10k_warn("device is wedged, will not restart\n");
  391. break;
  392. }
  393. mutex_unlock(&ar->conf_mutex);
  394. }
  395. struct ath10k *ath10k_core_create(void *hif_priv, struct device *dev,
  396. const struct ath10k_hif_ops *hif_ops)
  397. {
  398. struct ath10k *ar;
  399. ar = ath10k_mac_create();
  400. if (!ar)
  401. return NULL;
  402. ar->ath_common.priv = ar;
  403. ar->ath_common.hw = ar->hw;
  404. ar->p2p = !!ath10k_p2p;
  405. ar->dev = dev;
  406. ar->hif.priv = hif_priv;
  407. ar->hif.ops = hif_ops;
  408. init_completion(&ar->scan.started);
  409. init_completion(&ar->scan.completed);
  410. init_completion(&ar->scan.on_channel);
  411. init_completion(&ar->install_key_done);
  412. init_completion(&ar->vdev_setup_done);
  413. setup_timer(&ar->scan.timeout, ath10k_reset_scan, (unsigned long)ar);
  414. ar->workqueue = create_singlethread_workqueue("ath10k_wq");
  415. if (!ar->workqueue)
  416. goto err_wq;
  417. mutex_init(&ar->conf_mutex);
  418. spin_lock_init(&ar->data_lock);
  419. INIT_LIST_HEAD(&ar->peers);
  420. init_waitqueue_head(&ar->peer_mapping_wq);
  421. init_completion(&ar->offchan_tx_completed);
  422. INIT_WORK(&ar->offchan_tx_work, ath10k_offchan_tx_work);
  423. skb_queue_head_init(&ar->offchan_tx_queue);
  424. INIT_WORK(&ar->wmi_mgmt_tx_work, ath10k_mgmt_over_wmi_tx_work);
  425. skb_queue_head_init(&ar->wmi_mgmt_tx_queue);
  426. init_waitqueue_head(&ar->event_queue);
  427. INIT_WORK(&ar->restart_work, ath10k_core_restart);
  428. return ar;
  429. err_wq:
  430. ath10k_mac_destroy(ar);
  431. return NULL;
  432. }
  433. EXPORT_SYMBOL(ath10k_core_create);
  434. void ath10k_core_destroy(struct ath10k *ar)
  435. {
  436. flush_workqueue(ar->workqueue);
  437. destroy_workqueue(ar->workqueue);
  438. ath10k_mac_destroy(ar);
  439. }
  440. EXPORT_SYMBOL(ath10k_core_destroy);
  441. int ath10k_core_start(struct ath10k *ar)
  442. {
  443. int status;
  444. ath10k_bmi_start(ar);
  445. if (ath10k_init_configure_target(ar)) {
  446. status = -EINVAL;
  447. goto err;
  448. }
  449. status = ath10k_init_download_firmware(ar);
  450. if (status)
  451. goto err;
  452. status = ath10k_init_uart(ar);
  453. if (status)
  454. goto err;
  455. ar->htc.htc_ops.target_send_suspend_complete =
  456. ath10k_send_suspend_complete;
  457. status = ath10k_htc_init(ar);
  458. if (status) {
  459. ath10k_err("could not init HTC (%d)\n", status);
  460. goto err;
  461. }
  462. status = ath10k_bmi_done(ar);
  463. if (status)
  464. goto err;
  465. status = ath10k_wmi_attach(ar);
  466. if (status) {
  467. ath10k_err("WMI attach failed: %d\n", status);
  468. goto err;
  469. }
  470. status = ath10k_htc_wait_target(&ar->htc);
  471. if (status)
  472. goto err_wmi_detach;
  473. status = ath10k_htt_attach(ar);
  474. if (status) {
  475. ath10k_err("could not attach htt (%d)\n", status);
  476. goto err_wmi_detach;
  477. }
  478. status = ath10k_init_connect_htc(ar);
  479. if (status)
  480. goto err_htt_detach;
  481. ath10k_info("firmware %s booted\n", ar->hw->wiphy->fw_version);
  482. status = ath10k_wmi_cmd_init(ar);
  483. if (status) {
  484. ath10k_err("could not send WMI init command (%d)\n", status);
  485. goto err_disconnect_htc;
  486. }
  487. status = ath10k_wmi_wait_for_unified_ready(ar);
  488. if (status <= 0) {
  489. ath10k_err("wmi unified ready event not received\n");
  490. status = -ETIMEDOUT;
  491. goto err_disconnect_htc;
  492. }
  493. status = ath10k_htt_attach_target(&ar->htt);
  494. if (status)
  495. goto err_disconnect_htc;
  496. status = ath10k_debug_start(ar);
  497. if (status)
  498. goto err_disconnect_htc;
  499. ar->free_vdev_map = (1 << TARGET_NUM_VDEVS) - 1;
  500. return 0;
  501. err_disconnect_htc:
  502. ath10k_htc_stop(&ar->htc);
  503. err_htt_detach:
  504. ath10k_htt_detach(&ar->htt);
  505. err_wmi_detach:
  506. ath10k_wmi_detach(ar);
  507. err:
  508. return status;
  509. }
  510. EXPORT_SYMBOL(ath10k_core_start);
  511. void ath10k_core_stop(struct ath10k *ar)
  512. {
  513. ath10k_debug_stop(ar);
  514. ath10k_htc_stop(&ar->htc);
  515. ath10k_htt_detach(&ar->htt);
  516. ath10k_wmi_detach(ar);
  517. }
  518. EXPORT_SYMBOL(ath10k_core_stop);
  519. /* mac80211 manages fw/hw initialization through start/stop hooks. However in
  520. * order to know what hw capabilities should be advertised to mac80211 it is
  521. * necessary to load the firmware (and tear it down immediately since start
  522. * hook will try to init it again) before registering */
  523. static int ath10k_core_probe_fw(struct ath10k *ar)
  524. {
  525. struct bmi_target_info target_info;
  526. int ret = 0;
  527. ret = ath10k_hif_power_up(ar);
  528. if (ret) {
  529. ath10k_err("could not start pci hif (%d)\n", ret);
  530. return ret;
  531. }
  532. memset(&target_info, 0, sizeof(target_info));
  533. ret = ath10k_bmi_get_target_info(ar, &target_info);
  534. if (ret) {
  535. ath10k_err("could not get target info (%d)\n", ret);
  536. ath10k_hif_power_down(ar);
  537. return ret;
  538. }
  539. ar->target_version = target_info.version;
  540. ar->hw->wiphy->hw_version = target_info.version;
  541. ret = ath10k_init_hw_params(ar);
  542. if (ret) {
  543. ath10k_err("could not get hw params (%d)\n", ret);
  544. ath10k_hif_power_down(ar);
  545. return ret;
  546. }
  547. ret = ath10k_core_fetch_firmware_files(ar);
  548. if (ret) {
  549. ath10k_err("could not fetch firmware files (%d)\n", ret);
  550. ath10k_hif_power_down(ar);
  551. return ret;
  552. }
  553. ret = ath10k_core_start(ar);
  554. if (ret) {
  555. ath10k_err("could not init core (%d)\n", ret);
  556. ath10k_core_free_firmware_files(ar);
  557. ath10k_hif_power_down(ar);
  558. return ret;
  559. }
  560. ath10k_core_stop(ar);
  561. ath10k_hif_power_down(ar);
  562. return 0;
  563. }
  564. static int ath10k_core_check_chip_id(struct ath10k *ar)
  565. {
  566. u32 hw_revision = MS(ar->chip_id, SOC_CHIP_ID_REV);
  567. ath10k_dbg(ATH10K_DBG_BOOT, "boot chip_id 0x%08x hw_revision 0x%x\n",
  568. ar->chip_id, hw_revision);
  569. /* Check that we are not using hw1.0 (some of them have same pci id
  570. * as hw2.0) before doing anything else as ath10k crashes horribly
  571. * due to missing hw1.0 workarounds. */
  572. switch (hw_revision) {
  573. case QCA988X_HW_1_0_CHIP_ID_REV:
  574. ath10k_err("ERROR: qca988x hw1.0 is not supported\n");
  575. return -EOPNOTSUPP;
  576. case QCA988X_HW_2_0_CHIP_ID_REV:
  577. /* known hardware revision, continue normally */
  578. return 0;
  579. default:
  580. ath10k_warn("Warning: hardware revision unknown (0x%x), expect problems\n",
  581. ar->chip_id);
  582. return 0;
  583. }
  584. return 0;
  585. }
  586. int ath10k_core_register(struct ath10k *ar, u32 chip_id)
  587. {
  588. int status;
  589. ar->chip_id = chip_id;
  590. status = ath10k_core_check_chip_id(ar);
  591. if (status) {
  592. ath10k_err("Unsupported chip id 0x%08x\n", ar->chip_id);
  593. return status;
  594. }
  595. status = ath10k_core_probe_fw(ar);
  596. if (status) {
  597. ath10k_err("could not probe fw (%d)\n", status);
  598. return status;
  599. }
  600. status = ath10k_mac_register(ar);
  601. if (status) {
  602. ath10k_err("could not register to mac80211 (%d)\n", status);
  603. goto err_release_fw;
  604. }
  605. status = ath10k_debug_create(ar);
  606. if (status) {
  607. ath10k_err("unable to initialize debugfs\n");
  608. goto err_unregister_mac;
  609. }
  610. return 0;
  611. err_unregister_mac:
  612. ath10k_mac_unregister(ar);
  613. err_release_fw:
  614. ath10k_core_free_firmware_files(ar);
  615. return status;
  616. }
  617. EXPORT_SYMBOL(ath10k_core_register);
  618. void ath10k_core_unregister(struct ath10k *ar)
  619. {
  620. /* We must unregister from mac80211 before we stop HTC and HIF.
  621. * Otherwise we will fail to submit commands to FW and mac80211 will be
  622. * unhappy about callback failures. */
  623. ath10k_mac_unregister(ar);
  624. ath10k_core_free_firmware_files(ar);
  625. }
  626. EXPORT_SYMBOL(ath10k_core_unregister);
  627. MODULE_AUTHOR("Qualcomm Atheros");
  628. MODULE_DESCRIPTION("Core module for QCA988X PCIe devices.");
  629. MODULE_LICENSE("Dual BSD/GPL");