pci.c 48 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2009-2010 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * wlanfae <wlanfae@realtek.com>
  23. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24. * Hsinchu 300, Taiwan.
  25. *
  26. * Larry Finger <Larry.Finger@lwfinger.net>
  27. *
  28. *****************************************************************************/
  29. #include "core.h"
  30. #include "wifi.h"
  31. #include "pci.h"
  32. #include "base.h"
  33. #include "ps.h"
  34. static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
  35. INTEL_VENDOR_ID,
  36. ATI_VENDOR_ID,
  37. AMD_VENDOR_ID,
  38. SIS_VENDOR_ID
  39. };
  40. /* Update PCI dependent default settings*/
  41. static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
  42. {
  43. struct rtl_priv *rtlpriv = rtl_priv(hw);
  44. struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
  45. struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  46. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  47. u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
  48. ppsc->reg_rfps_level = 0;
  49. ppsc->support_aspm = 0;
  50. /*Update PCI ASPM setting */
  51. ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
  52. switch (rtlpci->const_pci_aspm) {
  53. case 0:
  54. /*No ASPM */
  55. break;
  56. case 1:
  57. /*ASPM dynamically enabled/disable. */
  58. ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
  59. break;
  60. case 2:
  61. /*ASPM with Clock Req dynamically enabled/disable. */
  62. ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
  63. RT_RF_OFF_LEVL_CLK_REQ);
  64. break;
  65. case 3:
  66. /*
  67. * Always enable ASPM and Clock Req
  68. * from initialization to halt.
  69. * */
  70. ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
  71. ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
  72. RT_RF_OFF_LEVL_CLK_REQ);
  73. break;
  74. case 4:
  75. /*
  76. * Always enable ASPM without Clock Req
  77. * from initialization to halt.
  78. * */
  79. ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
  80. RT_RF_OFF_LEVL_CLK_REQ);
  81. ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
  82. break;
  83. }
  84. ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
  85. /*Update Radio OFF setting */
  86. switch (rtlpci->const_hwsw_rfoff_d3) {
  87. case 1:
  88. if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
  89. ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
  90. break;
  91. case 2:
  92. if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
  93. ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
  94. ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
  95. break;
  96. case 3:
  97. ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
  98. break;
  99. }
  100. /*Set HW definition to determine if it supports ASPM. */
  101. switch (rtlpci->const_support_pciaspm) {
  102. case 0:{
  103. /*Not support ASPM. */
  104. bool support_aspm = false;
  105. ppsc->support_aspm = support_aspm;
  106. break;
  107. }
  108. case 1:{
  109. /*Support ASPM. */
  110. bool support_aspm = true;
  111. bool support_backdoor = true;
  112. ppsc->support_aspm = support_aspm;
  113. /*if(priv->oem_id == RT_CID_TOSHIBA &&
  114. !priv->ndis_adapter.amd_l1_patch)
  115. support_backdoor = false; */
  116. ppsc->support_backdoor = support_backdoor;
  117. break;
  118. }
  119. case 2:
  120. /*ASPM value set by chipset. */
  121. if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) {
  122. bool support_aspm = true;
  123. ppsc->support_aspm = support_aspm;
  124. }
  125. break;
  126. default:
  127. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  128. ("switch case not process\n"));
  129. break;
  130. }
  131. }
  132. static bool _rtl_pci_platform_switch_device_pci_aspm(
  133. struct ieee80211_hw *hw,
  134. u8 value)
  135. {
  136. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  137. bool bresult = false;
  138. value |= 0x40;
  139. pci_write_config_byte(rtlpci->pdev, 0x80, value);
  140. return bresult;
  141. }
  142. /*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/
  143. static bool _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
  144. {
  145. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  146. u8 buffer;
  147. bool bresult = false;
  148. buffer = value;
  149. pci_write_config_byte(rtlpci->pdev, 0x81, value);
  150. bresult = true;
  151. return bresult;
  152. }
  153. /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
  154. static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
  155. {
  156. struct rtl_priv *rtlpriv = rtl_priv(hw);
  157. struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
  158. struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  159. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  160. u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
  161. u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
  162. u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
  163. /*Retrieve original configuration settings. */
  164. u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
  165. u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.
  166. pcibridge_linkctrlreg;
  167. u16 aspmlevel = 0;
  168. if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
  169. RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
  170. ("PCI(Bridge) UNKNOWN.\n"));
  171. return;
  172. }
  173. if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
  174. RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
  175. _rtl_pci_switch_clk_req(hw, 0x0);
  176. }
  177. if (1) {
  178. /*for promising device will in L0 state after an I/O. */
  179. u8 tmp_u1b;
  180. pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
  181. }
  182. /*Set corresponding value. */
  183. aspmlevel |= BIT(0) | BIT(1);
  184. linkctrl_reg &= ~aspmlevel;
  185. pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
  186. _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
  187. udelay(50);
  188. /*4 Disable Pci Bridge ASPM */
  189. rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
  190. pcicfg_addrport + (num4bytes << 2));
  191. rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, pcibridge_linkctrlreg);
  192. udelay(50);
  193. }
  194. /*
  195. *Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
  196. *power saving We should follow the sequence to enable
  197. *RTL8192SE first then enable Pci Bridge ASPM
  198. *or the system will show bluescreen.
  199. */
  200. static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
  201. {
  202. struct rtl_priv *rtlpriv = rtl_priv(hw);
  203. struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
  204. struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  205. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  206. u8 pcibridge_busnum = pcipriv->ndis_adapter.pcibridge_busnum;
  207. u8 pcibridge_devnum = pcipriv->ndis_adapter.pcibridge_devnum;
  208. u8 pcibridge_funcnum = pcipriv->ndis_adapter.pcibridge_funcnum;
  209. u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
  210. u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
  211. u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
  212. u16 aspmlevel;
  213. u8 u_pcibridge_aspmsetting;
  214. u8 u_device_aspmsetting;
  215. if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
  216. RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
  217. ("PCI(Bridge) UNKNOWN.\n"));
  218. return;
  219. }
  220. /*4 Enable Pci Bridge ASPM */
  221. rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
  222. pcicfg_addrport + (num4bytes << 2));
  223. u_pcibridge_aspmsetting =
  224. pcipriv->ndis_adapter.pcibridge_linkctrlreg |
  225. rtlpci->const_hostpci_aspm_setting;
  226. if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
  227. u_pcibridge_aspmsetting &= ~BIT(0);
  228. rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, u_pcibridge_aspmsetting);
  229. RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
  230. ("PlatformEnableASPM():PciBridge busnumber[%x], "
  231. "DevNumbe[%x], funcnumber[%x], Write reg[%x] = %x\n",
  232. pcibridge_busnum, pcibridge_devnum, pcibridge_funcnum,
  233. (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
  234. u_pcibridge_aspmsetting));
  235. udelay(50);
  236. /*Get ASPM level (with/without Clock Req) */
  237. aspmlevel = rtlpci->const_devicepci_aspm_setting;
  238. u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
  239. /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
  240. /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
  241. u_device_aspmsetting |= aspmlevel;
  242. _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
  243. if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
  244. _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
  245. RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
  246. RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
  247. }
  248. udelay(200);
  249. }
  250. static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
  251. {
  252. struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
  253. u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
  254. bool status = false;
  255. u8 offset_e0;
  256. unsigned offset_e4;
  257. rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
  258. pcicfg_addrport + 0xE0);
  259. rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, 0xA0);
  260. rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
  261. pcicfg_addrport + 0xE0);
  262. rtl_pci_raw_read_port_uchar(PCI_CONF_DATA, &offset_e0);
  263. if (offset_e0 == 0xA0) {
  264. rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
  265. pcicfg_addrport + 0xE4);
  266. rtl_pci_raw_read_port_ulong(PCI_CONF_DATA, &offset_e4);
  267. if (offset_e4 & BIT(23))
  268. status = true;
  269. }
  270. return status;
  271. }
  272. static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
  273. {
  274. struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
  275. u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
  276. u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
  277. u8 linkctrl_reg;
  278. u8 num4bBytes;
  279. num4bBytes = (capabilityoffset + 0x10) / 4;
  280. /*Read Link Control Register */
  281. rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
  282. pcicfg_addrport + (num4bBytes << 2));
  283. rtl_pci_raw_read_port_uchar(PCI_CONF_DATA, &linkctrl_reg);
  284. pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
  285. }
  286. static void rtl_pci_parse_configuration(struct pci_dev *pdev,
  287. struct ieee80211_hw *hw)
  288. {
  289. struct rtl_priv *rtlpriv = rtl_priv(hw);
  290. struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
  291. u8 tmp;
  292. int pos;
  293. u8 linkctrl_reg;
  294. /*Link Control Register */
  295. pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
  296. pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &linkctrl_reg);
  297. pcipriv->ndis_adapter.linkctrl_reg = linkctrl_reg;
  298. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  299. ("Link Control Register =%x\n",
  300. pcipriv->ndis_adapter.linkctrl_reg));
  301. pci_read_config_byte(pdev, 0x98, &tmp);
  302. tmp |= BIT(4);
  303. pci_write_config_byte(pdev, 0x98, tmp);
  304. tmp = 0x17;
  305. pci_write_config_byte(pdev, 0x70f, tmp);
  306. }
  307. static void _rtl_pci_initialize_adapter_common(struct ieee80211_hw *hw)
  308. {
  309. struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  310. _rtl_pci_update_default_setting(hw);
  311. if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
  312. /*Always enable ASPM & Clock Req. */
  313. rtl_pci_enable_aspm(hw);
  314. RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
  315. }
  316. }
  317. static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
  318. {
  319. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  320. /*close ASPM for AMD defaultly */
  321. rtlpci->const_amdpci_aspm = 0;
  322. /*
  323. * ASPM PS mode.
  324. * 0 - Disable ASPM,
  325. * 1 - Enable ASPM without Clock Req,
  326. * 2 - Enable ASPM with Clock Req,
  327. * 3 - Alwyas Enable ASPM with Clock Req,
  328. * 4 - Always Enable ASPM without Clock Req.
  329. * set defult to RTL8192CE:3 RTL8192E:2
  330. * */
  331. rtlpci->const_pci_aspm = 3;
  332. /*Setting for PCI-E device */
  333. rtlpci->const_devicepci_aspm_setting = 0x03;
  334. /*Setting for PCI-E bridge */
  335. rtlpci->const_hostpci_aspm_setting = 0x02;
  336. /*
  337. * In Hw/Sw Radio Off situation.
  338. * 0 - Default,
  339. * 1 - From ASPM setting without low Mac Pwr,
  340. * 2 - From ASPM setting with low Mac Pwr,
  341. * 3 - Bus D3
  342. * set default to RTL8192CE:0 RTL8192SE:2
  343. */
  344. rtlpci->const_hwsw_rfoff_d3 = 0;
  345. /*
  346. * This setting works for those device with
  347. * backdoor ASPM setting such as EPHY setting.
  348. * 0 - Not support ASPM,
  349. * 1 - Support ASPM,
  350. * 2 - According to chipset.
  351. */
  352. rtlpci->const_support_pciaspm = 1;
  353. _rtl_pci_initialize_adapter_common(hw);
  354. }
  355. static void _rtl_pci_io_handler_init(struct device *dev,
  356. struct ieee80211_hw *hw)
  357. {
  358. struct rtl_priv *rtlpriv = rtl_priv(hw);
  359. rtlpriv->io.dev = dev;
  360. rtlpriv->io.write8_async = pci_write8_async;
  361. rtlpriv->io.write16_async = pci_write16_async;
  362. rtlpriv->io.write32_async = pci_write32_async;
  363. rtlpriv->io.read8_sync = pci_read8_sync;
  364. rtlpriv->io.read16_sync = pci_read16_sync;
  365. rtlpriv->io.read32_sync = pci_read32_sync;
  366. }
  367. static void _rtl_pci_io_handler_release(struct ieee80211_hw *hw)
  368. {
  369. }
  370. static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
  371. {
  372. struct rtl_priv *rtlpriv = rtl_priv(hw);
  373. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  374. struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
  375. while (skb_queue_len(&ring->queue)) {
  376. struct rtl_tx_desc *entry = &ring->desc[ring->idx];
  377. struct sk_buff *skb;
  378. struct ieee80211_tx_info *info;
  379. u8 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) entry, true,
  380. HW_DESC_OWN);
  381. /*
  382. *beacon packet will only use the first
  383. *descriptor defautly,and the own may not
  384. *be cleared by the hardware
  385. */
  386. if (own)
  387. return;
  388. ring->idx = (ring->idx + 1) % ring->entries;
  389. skb = __skb_dequeue(&ring->queue);
  390. pci_unmap_single(rtlpci->pdev,
  391. rtlpriv->cfg->ops->
  392. get_desc((u8 *) entry, true,
  393. HW_DESC_TXBUFF_ADDR),
  394. skb->len, PCI_DMA_TODEVICE);
  395. RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
  396. ("new ring->idx:%d, "
  397. "free: skb_queue_len:%d, free: seq:%x\n",
  398. ring->idx,
  399. skb_queue_len(&ring->queue),
  400. *(u16 *) (skb->data + 22)));
  401. info = IEEE80211_SKB_CB(skb);
  402. ieee80211_tx_info_clear_status(info);
  403. info->flags |= IEEE80211_TX_STAT_ACK;
  404. /*info->status.rates[0].count = 1; */
  405. ieee80211_tx_status_irqsafe(hw, skb);
  406. if ((ring->entries - skb_queue_len(&ring->queue))
  407. == 2) {
  408. RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
  409. ("more desc left, wake"
  410. "skb_queue@%d,ring->idx = %d,"
  411. "skb_queue_len = 0x%d\n",
  412. prio, ring->idx,
  413. skb_queue_len(&ring->queue)));
  414. ieee80211_wake_queue(hw,
  415. skb_get_queue_mapping
  416. (skb));
  417. }
  418. skb = NULL;
  419. }
  420. if (((rtlpriv->link_info.num_rx_inperiod +
  421. rtlpriv->link_info.num_tx_inperiod) > 8) ||
  422. (rtlpriv->link_info.num_rx_inperiod > 2)) {
  423. rtl_lps_leave(hw);
  424. }
  425. }
  426. static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
  427. {
  428. struct rtl_priv *rtlpriv = rtl_priv(hw);
  429. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  430. int rx_queue_idx = RTL_PCI_RX_MPDU_QUEUE;
  431. struct ieee80211_rx_status rx_status = { 0 };
  432. unsigned int count = rtlpci->rxringcount;
  433. u8 own;
  434. u8 tmp_one;
  435. u32 bufferaddress;
  436. bool unicast = false;
  437. struct rtl_stats stats = {
  438. .signal = 0,
  439. .noise = -98,
  440. .rate = 0,
  441. };
  442. /*RX NORMAL PKT */
  443. while (count--) {
  444. /*rx descriptor */
  445. struct rtl_rx_desc *pdesc = &rtlpci->rx_ring[rx_queue_idx].desc[
  446. rtlpci->rx_ring[rx_queue_idx].idx];
  447. /*rx pkt */
  448. struct sk_buff *skb = rtlpci->rx_ring[rx_queue_idx].rx_buf[
  449. rtlpci->rx_ring[rx_queue_idx].idx];
  450. own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
  451. false, HW_DESC_OWN);
  452. if (own) {
  453. /*wait data to be filled by hardware */
  454. return;
  455. } else {
  456. struct ieee80211_hdr *hdr;
  457. __le16 fc;
  458. struct sk_buff *new_skb = NULL;
  459. rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
  460. &rx_status,
  461. (u8 *) pdesc, skb);
  462. pci_unmap_single(rtlpci->pdev,
  463. *((dma_addr_t *) skb->cb),
  464. rtlpci->rxbuffersize,
  465. PCI_DMA_FROMDEVICE);
  466. skb_put(skb, rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
  467. false,
  468. HW_DESC_RXPKT_LEN));
  469. skb_reserve(skb,
  470. stats.rx_drvinfo_size + stats.rx_bufshift);
  471. /*
  472. *NOTICE This can not be use for mac80211,
  473. *this is done in mac80211 code,
  474. *if you done here sec DHCP will fail
  475. *skb_trim(skb, skb->len - 4);
  476. */
  477. hdr = (struct ieee80211_hdr *)(skb->data);
  478. fc = hdr->frame_control;
  479. if (!stats.crc) {
  480. memcpy(IEEE80211_SKB_RXCB(skb), &rx_status,
  481. sizeof(rx_status));
  482. if (is_broadcast_ether_addr(hdr->addr1))
  483. ;/*TODO*/
  484. else {
  485. if (is_multicast_ether_addr(hdr->addr1))
  486. ;/*TODO*/
  487. else {
  488. unicast = true;
  489. rtlpriv->stats.rxbytesunicast +=
  490. skb->len;
  491. }
  492. }
  493. rtl_is_special_data(hw, skb, false);
  494. if (ieee80211_is_data(fc)) {
  495. rtlpriv->cfg->ops->led_control(hw,
  496. LED_CTL_RX);
  497. if (unicast)
  498. rtlpriv->link_info.
  499. num_rx_inperiod++;
  500. }
  501. if (unlikely(!rtl_action_proc(hw, skb,
  502. false))) {
  503. dev_kfree_skb_any(skb);
  504. } else {
  505. struct sk_buff *uskb = NULL;
  506. u8 *pdata;
  507. uskb = dev_alloc_skb(skb->len + 128);
  508. if (!uskb) {
  509. RT_TRACE(rtlpriv,
  510. (COMP_INTR | COMP_RECV),
  511. DBG_EMERG,
  512. ("can't alloc rx skb\n"));
  513. goto done;
  514. }
  515. memcpy(IEEE80211_SKB_RXCB(uskb),
  516. &rx_status,
  517. sizeof(rx_status));
  518. pdata = (u8 *)skb_put(uskb, skb->len);
  519. memcpy(pdata, skb->data, skb->len);
  520. dev_kfree_skb_any(skb);
  521. ieee80211_rx_irqsafe(hw, uskb);
  522. }
  523. } else {
  524. dev_kfree_skb_any(skb);
  525. }
  526. if (((rtlpriv->link_info.num_rx_inperiod +
  527. rtlpriv->link_info.num_tx_inperiod) > 8) ||
  528. (rtlpriv->link_info.num_rx_inperiod > 2)) {
  529. rtl_lps_leave(hw);
  530. }
  531. new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
  532. if (unlikely(!new_skb)) {
  533. RT_TRACE(rtlpriv, (COMP_INTR | COMP_RECV),
  534. DBG_EMERG,
  535. ("can't alloc skb for rx\n"));
  536. goto done;
  537. }
  538. skb = new_skb;
  539. /*skb->dev = dev; */
  540. rtlpci->rx_ring[rx_queue_idx].rx_buf[rtlpci->
  541. rx_ring
  542. [rx_queue_idx].
  543. idx] = skb;
  544. *((dma_addr_t *) skb->cb) =
  545. pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
  546. rtlpci->rxbuffersize,
  547. PCI_DMA_FROMDEVICE);
  548. }
  549. done:
  550. bufferaddress = (u32)(*((dma_addr_t *) skb->cb));
  551. tmp_one = 1;
  552. rtlpriv->cfg->ops->set_desc((u8 *) pdesc, false,
  553. HW_DESC_RXBUFF_ADDR,
  554. (u8 *)&bufferaddress);
  555. rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false, HW_DESC_RXOWN,
  556. (u8 *)&tmp_one);
  557. rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
  558. HW_DESC_RXPKT_LEN,
  559. (u8 *)&rtlpci->rxbuffersize);
  560. if (rtlpci->rx_ring[rx_queue_idx].idx ==
  561. rtlpci->rxringcount - 1)
  562. rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
  563. HW_DESC_RXERO,
  564. (u8 *)&tmp_one);
  565. rtlpci->rx_ring[rx_queue_idx].idx =
  566. (rtlpci->rx_ring[rx_queue_idx].idx + 1) %
  567. rtlpci->rxringcount;
  568. }
  569. }
  570. static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
  571. {
  572. struct ieee80211_hw *hw = dev_id;
  573. struct rtl_priv *rtlpriv = rtl_priv(hw);
  574. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  575. unsigned long flags;
  576. u32 inta = 0;
  577. u32 intb = 0;
  578. if (rtlpci->irq_enabled == 0)
  579. return IRQ_HANDLED;
  580. spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
  581. /*read ISR: 4/8bytes */
  582. rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb);
  583. /*Shared IRQ or HW disappared */
  584. if (!inta || inta == 0xffff)
  585. goto done;
  586. /*<1> beacon related */
  587. if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) {
  588. RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
  589. ("beacon ok interrupt!\n"));
  590. }
  591. if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) {
  592. RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
  593. ("beacon err interrupt!\n"));
  594. }
  595. if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) {
  596. RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
  597. ("beacon interrupt!\n"));
  598. }
  599. if (inta & rtlpriv->cfg->maps[RTL_IMR_BcnInt]) {
  600. RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
  601. ("prepare beacon for interrupt!\n"));
  602. tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
  603. }
  604. /*<3> Tx related */
  605. if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
  606. RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, ("IMR_TXFOVW!\n"));
  607. if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
  608. RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
  609. ("Manage ok interrupt!\n"));
  610. _rtl_pci_tx_isr(hw, MGNT_QUEUE);
  611. }
  612. if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
  613. RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
  614. ("HIGH_QUEUE ok interrupt!\n"));
  615. _rtl_pci_tx_isr(hw, HIGH_QUEUE);
  616. }
  617. if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
  618. rtlpriv->link_info.num_tx_inperiod++;
  619. RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
  620. ("BK Tx OK interrupt!\n"));
  621. _rtl_pci_tx_isr(hw, BK_QUEUE);
  622. }
  623. if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
  624. rtlpriv->link_info.num_tx_inperiod++;
  625. RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
  626. ("BE TX OK interrupt!\n"));
  627. _rtl_pci_tx_isr(hw, BE_QUEUE);
  628. }
  629. if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
  630. rtlpriv->link_info.num_tx_inperiod++;
  631. RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
  632. ("VI TX OK interrupt!\n"));
  633. _rtl_pci_tx_isr(hw, VI_QUEUE);
  634. }
  635. if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
  636. rtlpriv->link_info.num_tx_inperiod++;
  637. RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
  638. ("Vo TX OK interrupt!\n"));
  639. _rtl_pci_tx_isr(hw, VO_QUEUE);
  640. }
  641. /*<2> Rx related */
  642. if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
  643. RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, ("Rx ok interrupt!\n"));
  644. tasklet_schedule(&rtlpriv->works.irq_tasklet);
  645. }
  646. if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
  647. RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
  648. ("rx descriptor unavailable!\n"));
  649. tasklet_schedule(&rtlpriv->works.irq_tasklet);
  650. }
  651. if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
  652. RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, ("rx overflow !\n"));
  653. tasklet_schedule(&rtlpriv->works.irq_tasklet);
  654. }
  655. spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
  656. return IRQ_HANDLED;
  657. done:
  658. spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
  659. return IRQ_HANDLED;
  660. }
  661. static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw)
  662. {
  663. _rtl_pci_rx_interrupt(hw);
  664. }
  665. static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw)
  666. {
  667. struct rtl_priv *rtlpriv = rtl_priv(hw);
  668. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  669. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  670. struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
  671. struct ieee80211_hdr *hdr = NULL;
  672. struct ieee80211_tx_info *info = NULL;
  673. struct sk_buff *pskb = NULL;
  674. struct rtl_tx_desc *pdesc = NULL;
  675. unsigned int queue_index;
  676. u8 temp_one = 1;
  677. ring = &rtlpci->tx_ring[BEACON_QUEUE];
  678. pskb = __skb_dequeue(&ring->queue);
  679. if (pskb)
  680. kfree_skb(pskb);
  681. /*NB: the beacon data buffer must be 32-bit aligned. */
  682. pskb = ieee80211_beacon_get(hw, mac->vif);
  683. if (pskb == NULL)
  684. return;
  685. hdr = (struct ieee80211_hdr *)(pskb->data);
  686. info = IEEE80211_SKB_CB(pskb);
  687. queue_index = BEACON_QUEUE;
  688. pdesc = &ring->desc[0];
  689. rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *) pdesc,
  690. info, pskb, queue_index);
  691. __skb_queue_tail(&ring->queue, pskb);
  692. rtlpriv->cfg->ops->set_desc((u8 *) pdesc, true, HW_DESC_OWN,
  693. (u8 *)&temp_one);
  694. return;
  695. }
  696. static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
  697. {
  698. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  699. u8 i;
  700. for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
  701. rtlpci->txringcount[i] = RT_TXDESC_NUM;
  702. /*
  703. *we just alloc 2 desc for beacon queue,
  704. *because we just need first desc in hw beacon.
  705. */
  706. rtlpci->txringcount[BEACON_QUEUE] = 2;
  707. /*
  708. *BE queue need more descriptor for performance
  709. *consideration or, No more tx desc will happen,
  710. *and may cause mac80211 mem leakage.
  711. */
  712. rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
  713. rtlpci->rxbuffersize = 9100; /*2048/1024; */
  714. rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */
  715. }
  716. static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
  717. struct pci_dev *pdev)
  718. {
  719. struct rtl_priv *rtlpriv = rtl_priv(hw);
  720. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  721. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  722. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  723. struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  724. rtlpci->up_first_time = true;
  725. rtlpci->being_init_adapter = false;
  726. rtlhal->hw = hw;
  727. rtlpci->pdev = pdev;
  728. ppsc->inactiveps = false;
  729. ppsc->leisure_ps = true;
  730. ppsc->fwctrl_lps = true;
  731. ppsc->reg_fwctrl_lps = 3;
  732. ppsc->reg_max_lps_awakeintvl = 5;
  733. if (ppsc->reg_fwctrl_lps == 1)
  734. ppsc->fwctrl_psmode = FW_PS_MIN_MODE;
  735. else if (ppsc->reg_fwctrl_lps == 2)
  736. ppsc->fwctrl_psmode = FW_PS_MAX_MODE;
  737. else if (ppsc->reg_fwctrl_lps == 3)
  738. ppsc->fwctrl_psmode = FW_PS_DTIM_MODE;
  739. /*Tx/Rx related var */
  740. _rtl_pci_init_trx_var(hw);
  741. /*IBSS*/ mac->beacon_interval = 100;
  742. /*AMPDU*/ mac->min_space_cfg = 0;
  743. mac->max_mss_density = 0;
  744. /*set sane AMPDU defaults */
  745. mac->current_ampdu_density = 7;
  746. mac->current_ampdu_factor = 3;
  747. /*QOS*/ rtlpci->acm_method = eAcmWay2_SW;
  748. /*task */
  749. tasklet_init(&rtlpriv->works.irq_tasklet,
  750. (void (*)(unsigned long))_rtl_pci_irq_tasklet,
  751. (unsigned long)hw);
  752. tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet,
  753. (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet,
  754. (unsigned long)hw);
  755. }
  756. static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
  757. unsigned int prio, unsigned int entries)
  758. {
  759. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  760. struct rtl_priv *rtlpriv = rtl_priv(hw);
  761. struct rtl_tx_desc *ring;
  762. dma_addr_t dma;
  763. u32 nextdescaddress;
  764. int i;
  765. ring = pci_alloc_consistent(rtlpci->pdev,
  766. sizeof(*ring) * entries, &dma);
  767. if (!ring || (unsigned long)ring & 0xFF) {
  768. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  769. ("Cannot allocate TX ring (prio = %d)\n", prio));
  770. return -ENOMEM;
  771. }
  772. memset(ring, 0, sizeof(*ring) * entries);
  773. rtlpci->tx_ring[prio].desc = ring;
  774. rtlpci->tx_ring[prio].dma = dma;
  775. rtlpci->tx_ring[prio].idx = 0;
  776. rtlpci->tx_ring[prio].entries = entries;
  777. skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
  778. RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
  779. ("queue:%d, ring_addr:%p\n", prio, ring));
  780. for (i = 0; i < entries; i++) {
  781. nextdescaddress = (u32) dma + ((i + 1) % entries) *
  782. sizeof(*ring);
  783. rtlpriv->cfg->ops->set_desc((u8 *)&(ring[i]),
  784. true, HW_DESC_TX_NEXTDESC_ADDR,
  785. (u8 *)&nextdescaddress);
  786. }
  787. return 0;
  788. }
  789. static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw)
  790. {
  791. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  792. struct rtl_priv *rtlpriv = rtl_priv(hw);
  793. struct rtl_rx_desc *entry = NULL;
  794. int i, rx_queue_idx;
  795. u8 tmp_one = 1;
  796. /*
  797. *rx_queue_idx 0:RX_MPDU_QUEUE
  798. *rx_queue_idx 1:RX_CMD_QUEUE
  799. */
  800. for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
  801. rx_queue_idx++) {
  802. rtlpci->rx_ring[rx_queue_idx].desc =
  803. pci_alloc_consistent(rtlpci->pdev,
  804. sizeof(*rtlpci->rx_ring[rx_queue_idx].
  805. desc) * rtlpci->rxringcount,
  806. &rtlpci->rx_ring[rx_queue_idx].dma);
  807. if (!rtlpci->rx_ring[rx_queue_idx].desc ||
  808. (unsigned long)rtlpci->rx_ring[rx_queue_idx].desc & 0xFF) {
  809. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  810. ("Cannot allocate RX ring\n"));
  811. return -ENOMEM;
  812. }
  813. memset(rtlpci->rx_ring[rx_queue_idx].desc, 0,
  814. sizeof(*rtlpci->rx_ring[rx_queue_idx].desc) *
  815. rtlpci->rxringcount);
  816. rtlpci->rx_ring[rx_queue_idx].idx = 0;
  817. for (i = 0; i < rtlpci->rxringcount; i++) {
  818. struct sk_buff *skb =
  819. dev_alloc_skb(rtlpci->rxbuffersize);
  820. u32 bufferaddress;
  821. if (!skb)
  822. return 0;
  823. entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
  824. /*skb->dev = dev; */
  825. rtlpci->rx_ring[rx_queue_idx].rx_buf[i] = skb;
  826. /*
  827. *just set skb->cb to mapping addr
  828. *for pci_unmap_single use
  829. */
  830. *((dma_addr_t *) skb->cb) =
  831. pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
  832. rtlpci->rxbuffersize,
  833. PCI_DMA_FROMDEVICE);
  834. bufferaddress = (u32)(*((dma_addr_t *)skb->cb));
  835. rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
  836. HW_DESC_RXBUFF_ADDR,
  837. (u8 *)&bufferaddress);
  838. rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
  839. HW_DESC_RXPKT_LEN,
  840. (u8 *)&rtlpci->
  841. rxbuffersize);
  842. rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
  843. HW_DESC_RXOWN,
  844. (u8 *)&tmp_one);
  845. }
  846. rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
  847. HW_DESC_RXERO, (u8 *)&tmp_one);
  848. }
  849. return 0;
  850. }
  851. static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
  852. unsigned int prio)
  853. {
  854. struct rtl_priv *rtlpriv = rtl_priv(hw);
  855. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  856. struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
  857. while (skb_queue_len(&ring->queue)) {
  858. struct rtl_tx_desc *entry = &ring->desc[ring->idx];
  859. struct sk_buff *skb = __skb_dequeue(&ring->queue);
  860. pci_unmap_single(rtlpci->pdev,
  861. rtlpriv->cfg->
  862. ops->get_desc((u8 *) entry, true,
  863. HW_DESC_TXBUFF_ADDR),
  864. skb->len, PCI_DMA_TODEVICE);
  865. kfree_skb(skb);
  866. ring->idx = (ring->idx + 1) % ring->entries;
  867. }
  868. pci_free_consistent(rtlpci->pdev,
  869. sizeof(*ring->desc) * ring->entries,
  870. ring->desc, ring->dma);
  871. ring->desc = NULL;
  872. }
  873. static void _rtl_pci_free_rx_ring(struct rtl_pci *rtlpci)
  874. {
  875. int i, rx_queue_idx;
  876. /*rx_queue_idx 0:RX_MPDU_QUEUE */
  877. /*rx_queue_idx 1:RX_CMD_QUEUE */
  878. for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
  879. rx_queue_idx++) {
  880. for (i = 0; i < rtlpci->rxringcount; i++) {
  881. struct sk_buff *skb =
  882. rtlpci->rx_ring[rx_queue_idx].rx_buf[i];
  883. if (!skb)
  884. continue;
  885. pci_unmap_single(rtlpci->pdev,
  886. *((dma_addr_t *) skb->cb),
  887. rtlpci->rxbuffersize,
  888. PCI_DMA_FROMDEVICE);
  889. kfree_skb(skb);
  890. }
  891. pci_free_consistent(rtlpci->pdev,
  892. sizeof(*rtlpci->rx_ring[rx_queue_idx].
  893. desc) * rtlpci->rxringcount,
  894. rtlpci->rx_ring[rx_queue_idx].desc,
  895. rtlpci->rx_ring[rx_queue_idx].dma);
  896. rtlpci->rx_ring[rx_queue_idx].desc = NULL;
  897. }
  898. }
  899. static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
  900. {
  901. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  902. int ret;
  903. int i;
  904. ret = _rtl_pci_init_rx_ring(hw);
  905. if (ret)
  906. return ret;
  907. for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
  908. ret = _rtl_pci_init_tx_ring(hw, i,
  909. rtlpci->txringcount[i]);
  910. if (ret)
  911. goto err_free_rings;
  912. }
  913. return 0;
  914. err_free_rings:
  915. _rtl_pci_free_rx_ring(rtlpci);
  916. for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
  917. if (rtlpci->tx_ring[i].desc)
  918. _rtl_pci_free_tx_ring(hw, i);
  919. return 1;
  920. }
  921. static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
  922. {
  923. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  924. u32 i;
  925. /*free rx rings */
  926. _rtl_pci_free_rx_ring(rtlpci);
  927. /*free tx rings */
  928. for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
  929. _rtl_pci_free_tx_ring(hw, i);
  930. return 0;
  931. }
  932. int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
  933. {
  934. struct rtl_priv *rtlpriv = rtl_priv(hw);
  935. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  936. int i, rx_queue_idx;
  937. unsigned long flags;
  938. u8 tmp_one = 1;
  939. /*rx_queue_idx 0:RX_MPDU_QUEUE */
  940. /*rx_queue_idx 1:RX_CMD_QUEUE */
  941. for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
  942. rx_queue_idx++) {
  943. /*
  944. *force the rx_ring[RX_MPDU_QUEUE/
  945. *RX_CMD_QUEUE].idx to the first one
  946. */
  947. if (rtlpci->rx_ring[rx_queue_idx].desc) {
  948. struct rtl_rx_desc *entry = NULL;
  949. for (i = 0; i < rtlpci->rxringcount; i++) {
  950. entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
  951. rtlpriv->cfg->ops->set_desc((u8 *) entry,
  952. false,
  953. HW_DESC_RXOWN,
  954. (u8 *)&tmp_one);
  955. }
  956. rtlpci->rx_ring[rx_queue_idx].idx = 0;
  957. }
  958. }
  959. /*
  960. *after reset, release previous pending packet,
  961. *and force the tx idx to the first one
  962. */
  963. spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
  964. for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
  965. if (rtlpci->tx_ring[i].desc) {
  966. struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
  967. while (skb_queue_len(&ring->queue)) {
  968. struct rtl_tx_desc *entry =
  969. &ring->desc[ring->idx];
  970. struct sk_buff *skb =
  971. __skb_dequeue(&ring->queue);
  972. pci_unmap_single(rtlpci->pdev,
  973. rtlpriv->cfg->ops->
  974. get_desc((u8 *)
  975. entry,
  976. true,
  977. HW_DESC_TXBUFF_ADDR),
  978. skb->len, PCI_DMA_TODEVICE);
  979. kfree_skb(skb);
  980. ring->idx = (ring->idx + 1) % ring->entries;
  981. }
  982. ring->idx = 0;
  983. }
  984. }
  985. spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
  986. return 0;
  987. }
  988. static unsigned int _rtl_mac_to_hwqueue(__le16 fc,
  989. unsigned int mac80211_queue_index)
  990. {
  991. unsigned int hw_queue_index;
  992. if (unlikely(ieee80211_is_beacon(fc))) {
  993. hw_queue_index = BEACON_QUEUE;
  994. goto out;
  995. }
  996. if (ieee80211_is_mgmt(fc)) {
  997. hw_queue_index = MGNT_QUEUE;
  998. goto out;
  999. }
  1000. switch (mac80211_queue_index) {
  1001. case 0:
  1002. hw_queue_index = VO_QUEUE;
  1003. break;
  1004. case 1:
  1005. hw_queue_index = VI_QUEUE;
  1006. break;
  1007. case 2:
  1008. hw_queue_index = BE_QUEUE;;
  1009. break;
  1010. case 3:
  1011. hw_queue_index = BK_QUEUE;
  1012. break;
  1013. default:
  1014. hw_queue_index = BE_QUEUE;
  1015. RT_ASSERT(false, ("QSLT_BE queue, skb_queue:%d\n",
  1016. mac80211_queue_index));
  1017. break;
  1018. }
  1019. out:
  1020. return hw_queue_index;
  1021. }
  1022. static int rtl_pci_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  1023. {
  1024. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1025. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  1026. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  1027. struct rtl8192_tx_ring *ring;
  1028. struct rtl_tx_desc *pdesc;
  1029. u8 idx;
  1030. unsigned int queue_index, hw_queue;
  1031. unsigned long flags;
  1032. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data);
  1033. __le16 fc = hdr->frame_control;
  1034. u8 *pda_addr = hdr->addr1;
  1035. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  1036. /*ssn */
  1037. u8 *qc = NULL;
  1038. u8 tid = 0;
  1039. u16 seq_number = 0;
  1040. u8 own;
  1041. u8 temp_one = 1;
  1042. if (ieee80211_is_mgmt(fc))
  1043. rtl_tx_mgmt_proc(hw, skb);
  1044. rtl_action_proc(hw, skb, true);
  1045. queue_index = skb_get_queue_mapping(skb);
  1046. hw_queue = _rtl_mac_to_hwqueue(fc, queue_index);
  1047. if (is_multicast_ether_addr(pda_addr))
  1048. rtlpriv->stats.txbytesmulticast += skb->len;
  1049. else if (is_broadcast_ether_addr(pda_addr))
  1050. rtlpriv->stats.txbytesbroadcast += skb->len;
  1051. else
  1052. rtlpriv->stats.txbytesunicast += skb->len;
  1053. spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
  1054. ring = &rtlpci->tx_ring[hw_queue];
  1055. if (hw_queue != BEACON_QUEUE)
  1056. idx = (ring->idx + skb_queue_len(&ring->queue)) %
  1057. ring->entries;
  1058. else
  1059. idx = 0;
  1060. pdesc = &ring->desc[idx];
  1061. own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
  1062. true, HW_DESC_OWN);
  1063. if ((own == 1) && (hw_queue != BEACON_QUEUE)) {
  1064. RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
  1065. ("No more TX desc@%d, ring->idx = %d,"
  1066. "idx = %d, skb_queue_len = 0x%d\n",
  1067. hw_queue, ring->idx, idx,
  1068. skb_queue_len(&ring->queue)));
  1069. spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
  1070. return skb->len;
  1071. }
  1072. /*
  1073. *if(ieee80211_is_nullfunc(fc)) {
  1074. * spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
  1075. * return 1;
  1076. *}
  1077. */
  1078. if (ieee80211_is_data_qos(fc)) {
  1079. qc = ieee80211_get_qos_ctl(hdr);
  1080. tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
  1081. seq_number = mac->tids[tid].seq_number;
  1082. seq_number &= IEEE80211_SCTL_SEQ;
  1083. /*
  1084. *hdr->seq_ctrl = hdr->seq_ctrl &
  1085. *cpu_to_le16(IEEE80211_SCTL_FRAG);
  1086. *hdr->seq_ctrl |= cpu_to_le16(seq_number);
  1087. */
  1088. seq_number += 1;
  1089. }
  1090. if (ieee80211_is_data(fc))
  1091. rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
  1092. rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *) pdesc,
  1093. info, skb, hw_queue);
  1094. __skb_queue_tail(&ring->queue, skb);
  1095. rtlpriv->cfg->ops->set_desc((u8 *) pdesc, true,
  1096. HW_DESC_OWN, (u8 *)&temp_one);
  1097. if (!ieee80211_has_morefrags(hdr->frame_control)) {
  1098. if (qc)
  1099. mac->tids[tid].seq_number = seq_number;
  1100. }
  1101. if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
  1102. hw_queue != BEACON_QUEUE) {
  1103. RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
  1104. ("less desc left, stop skb_queue@%d, "
  1105. "ring->idx = %d,"
  1106. "idx = %d, skb_queue_len = 0x%d\n",
  1107. hw_queue, ring->idx, idx,
  1108. skb_queue_len(&ring->queue)));
  1109. ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
  1110. }
  1111. spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
  1112. rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
  1113. return 0;
  1114. }
  1115. static void rtl_pci_deinit(struct ieee80211_hw *hw)
  1116. {
  1117. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1118. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  1119. _rtl_pci_deinit_trx_ring(hw);
  1120. synchronize_irq(rtlpci->pdev->irq);
  1121. tasklet_kill(&rtlpriv->works.irq_tasklet);
  1122. flush_workqueue(rtlpriv->works.rtl_wq);
  1123. destroy_workqueue(rtlpriv->works.rtl_wq);
  1124. }
  1125. static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
  1126. {
  1127. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1128. int err;
  1129. _rtl_pci_init_struct(hw, pdev);
  1130. err = _rtl_pci_init_trx_ring(hw);
  1131. if (err) {
  1132. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  1133. ("tx ring initialization failed"));
  1134. return err;
  1135. }
  1136. return 1;
  1137. }
  1138. static int rtl_pci_start(struct ieee80211_hw *hw)
  1139. {
  1140. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1141. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  1142. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  1143. struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  1144. int err;
  1145. rtl_pci_reset_trx_ring(hw);
  1146. rtlpci->driver_is_goingto_unload = false;
  1147. err = rtlpriv->cfg->ops->hw_init(hw);
  1148. if (err) {
  1149. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  1150. ("Failed to config hardware!\n"));
  1151. return err;
  1152. }
  1153. rtlpriv->cfg->ops->enable_interrupt(hw);
  1154. RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("enable_interrupt OK\n"));
  1155. rtl_init_rx_config(hw);
  1156. /*should after adapter start and interrupt enable. */
  1157. set_hal_start(rtlhal);
  1158. RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
  1159. rtlpci->up_first_time = false;
  1160. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("OK\n"));
  1161. return 0;
  1162. }
  1163. static void rtl_pci_stop(struct ieee80211_hw *hw)
  1164. {
  1165. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1166. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  1167. struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  1168. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  1169. unsigned long flags;
  1170. u8 RFInProgressTimeOut = 0;
  1171. /*
  1172. *should before disable interrrupt&adapter
  1173. *and will do it immediately.
  1174. */
  1175. set_hal_stop(rtlhal);
  1176. rtlpriv->cfg->ops->disable_interrupt(hw);
  1177. spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
  1178. while (ppsc->rfchange_inprogress) {
  1179. spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
  1180. if (RFInProgressTimeOut > 100) {
  1181. spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
  1182. break;
  1183. }
  1184. mdelay(1);
  1185. RFInProgressTimeOut++;
  1186. spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
  1187. }
  1188. ppsc->rfchange_inprogress = true;
  1189. spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
  1190. rtlpci->driver_is_goingto_unload = true;
  1191. rtlpriv->cfg->ops->hw_disable(hw);
  1192. rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
  1193. spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
  1194. ppsc->rfchange_inprogress = false;
  1195. spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
  1196. rtl_pci_enable_aspm(hw);
  1197. }
  1198. static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
  1199. struct ieee80211_hw *hw)
  1200. {
  1201. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1202. struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
  1203. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  1204. struct pci_dev *bridge_pdev = pdev->bus->self;
  1205. u16 venderid;
  1206. u16 deviceid;
  1207. u8 revisionid;
  1208. u16 irqline;
  1209. u8 tmp;
  1210. venderid = pdev->vendor;
  1211. deviceid = pdev->device;
  1212. pci_read_config_byte(pdev, 0x8, &revisionid);
  1213. pci_read_config_word(pdev, 0x3C, &irqline);
  1214. if (deviceid == RTL_PCI_8192_DID ||
  1215. deviceid == RTL_PCI_0044_DID ||
  1216. deviceid == RTL_PCI_0047_DID ||
  1217. deviceid == RTL_PCI_8192SE_DID ||
  1218. deviceid == RTL_PCI_8174_DID ||
  1219. deviceid == RTL_PCI_8173_DID ||
  1220. deviceid == RTL_PCI_8172_DID ||
  1221. deviceid == RTL_PCI_8171_DID) {
  1222. switch (revisionid) {
  1223. case RTL_PCI_REVISION_ID_8192PCIE:
  1224. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  1225. ("8192 PCI-E is found - "
  1226. "vid/did=%x/%x\n", venderid, deviceid));
  1227. rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
  1228. break;
  1229. case RTL_PCI_REVISION_ID_8192SE:
  1230. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  1231. ("8192SE is found - "
  1232. "vid/did=%x/%x\n", venderid, deviceid));
  1233. rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
  1234. break;
  1235. default:
  1236. RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
  1237. ("Err: Unknown device - "
  1238. "vid/did=%x/%x\n", venderid, deviceid));
  1239. rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
  1240. break;
  1241. }
  1242. } else if (deviceid == RTL_PCI_8192CET_DID ||
  1243. deviceid == RTL_PCI_8192CE_DID ||
  1244. deviceid == RTL_PCI_8191CE_DID ||
  1245. deviceid == RTL_PCI_8188CE_DID) {
  1246. rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
  1247. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  1248. ("8192C PCI-E is found - "
  1249. "vid/did=%x/%x\n", venderid, deviceid));
  1250. } else {
  1251. RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
  1252. ("Err: Unknown device -"
  1253. " vid/did=%x/%x\n", venderid, deviceid));
  1254. rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
  1255. }
  1256. /*find bus info */
  1257. pcipriv->ndis_adapter.busnumber = pdev->bus->number;
  1258. pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
  1259. pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
  1260. /*find bridge info */
  1261. pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
  1262. for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
  1263. if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
  1264. pcipriv->ndis_adapter.pcibridge_vendor = tmp;
  1265. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  1266. ("Pci Bridge Vendor is found index: %d\n",
  1267. tmp));
  1268. break;
  1269. }
  1270. }
  1271. if (pcipriv->ndis_adapter.pcibridge_vendor !=
  1272. PCI_BRIDGE_VENDOR_UNKNOWN) {
  1273. pcipriv->ndis_adapter.pcibridge_busnum =
  1274. bridge_pdev->bus->number;
  1275. pcipriv->ndis_adapter.pcibridge_devnum =
  1276. PCI_SLOT(bridge_pdev->devfn);
  1277. pcipriv->ndis_adapter.pcibridge_funcnum =
  1278. PCI_FUNC(bridge_pdev->devfn);
  1279. pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
  1280. pci_pcie_cap(bridge_pdev);
  1281. pcipriv->ndis_adapter.pcicfg_addrport =
  1282. (pcipriv->ndis_adapter.pcibridge_busnum << 16) |
  1283. (pcipriv->ndis_adapter.pcibridge_devnum << 11) |
  1284. (pcipriv->ndis_adapter.pcibridge_funcnum << 8) | (1 << 31);
  1285. pcipriv->ndis_adapter.num4bytes =
  1286. (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
  1287. rtl_pci_get_linkcontrol_field(hw);
  1288. if (pcipriv->ndis_adapter.pcibridge_vendor ==
  1289. PCI_BRIDGE_VENDOR_AMD) {
  1290. pcipriv->ndis_adapter.amd_l1_patch =
  1291. rtl_pci_get_amd_l1_patch(hw);
  1292. }
  1293. }
  1294. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  1295. ("pcidev busnumber:devnumber:funcnumber:"
  1296. "vendor:link_ctl %d:%d:%d:%x:%x\n",
  1297. pcipriv->ndis_adapter.busnumber,
  1298. pcipriv->ndis_adapter.devnumber,
  1299. pcipriv->ndis_adapter.funcnumber,
  1300. pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg));
  1301. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  1302. ("pci_bridge busnumber:devnumber:funcnumber:vendor:"
  1303. "pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
  1304. pcipriv->ndis_adapter.pcibridge_busnum,
  1305. pcipriv->ndis_adapter.pcibridge_devnum,
  1306. pcipriv->ndis_adapter.pcibridge_funcnum,
  1307. pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
  1308. pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
  1309. pcipriv->ndis_adapter.pcibridge_linkctrlreg,
  1310. pcipriv->ndis_adapter.amd_l1_patch));
  1311. rtl_pci_parse_configuration(pdev, hw);
  1312. return true;
  1313. }
  1314. int __devinit rtl_pci_probe(struct pci_dev *pdev,
  1315. const struct pci_device_id *id)
  1316. {
  1317. struct ieee80211_hw *hw = NULL;
  1318. struct rtl_priv *rtlpriv = NULL;
  1319. struct rtl_pci_priv *pcipriv = NULL;
  1320. struct rtl_pci *rtlpci;
  1321. unsigned long pmem_start, pmem_len, pmem_flags;
  1322. int err;
  1323. err = pci_enable_device(pdev);
  1324. if (err) {
  1325. RT_ASSERT(false,
  1326. ("%s : Cannot enable new PCI device\n",
  1327. pci_name(pdev)));
  1328. return err;
  1329. }
  1330. if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
  1331. if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
  1332. RT_ASSERT(false, ("Unable to obtain 32bit DMA "
  1333. "for consistent allocations\n"));
  1334. pci_disable_device(pdev);
  1335. return -ENOMEM;
  1336. }
  1337. }
  1338. pci_set_master(pdev);
  1339. hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
  1340. sizeof(struct rtl_priv), &rtl_ops);
  1341. if (!hw) {
  1342. RT_ASSERT(false,
  1343. ("%s : ieee80211 alloc failed\n", pci_name(pdev)));
  1344. err = -ENOMEM;
  1345. goto fail1;
  1346. }
  1347. SET_IEEE80211_DEV(hw, &pdev->dev);
  1348. pci_set_drvdata(pdev, hw);
  1349. rtlpriv = hw->priv;
  1350. pcipriv = (void *)rtlpriv->priv;
  1351. pcipriv->dev.pdev = pdev;
  1352. /*
  1353. *init dbgp flags before all
  1354. *other functions, because we will
  1355. *use it in other funtions like
  1356. *RT_TRACE/RT_PRINT/RTL_PRINT_DATA
  1357. *you can not use these macro
  1358. *before this
  1359. */
  1360. rtl_dbgp_flag_init(hw);
  1361. /* MEM map */
  1362. err = pci_request_regions(pdev, KBUILD_MODNAME);
  1363. if (err) {
  1364. RT_ASSERT(false, ("Can't obtain PCI resources\n"));
  1365. return err;
  1366. }
  1367. pmem_start = pci_resource_start(pdev, 2);
  1368. pmem_len = pci_resource_len(pdev, 2);
  1369. pmem_flags = pci_resource_flags(pdev, 2);
  1370. /*shared mem start */
  1371. rtlpriv->io.pci_mem_start =
  1372. (unsigned long)pci_iomap(pdev, 2, pmem_len);
  1373. if (rtlpriv->io.pci_mem_start == 0) {
  1374. RT_ASSERT(false, ("Can't map PCI mem\n"));
  1375. goto fail2;
  1376. }
  1377. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  1378. ("mem mapped space: start: 0x%08lx len:%08lx "
  1379. "flags:%08lx, after map:0x%08lx\n",
  1380. pmem_start, pmem_len, pmem_flags,
  1381. rtlpriv->io.pci_mem_start));
  1382. /* Disable Clk Request */
  1383. pci_write_config_byte(pdev, 0x81, 0);
  1384. /* leave D3 mode */
  1385. pci_write_config_byte(pdev, 0x44, 0);
  1386. pci_write_config_byte(pdev, 0x04, 0x06);
  1387. pci_write_config_byte(pdev, 0x04, 0x07);
  1388. /* init cfg & intf_ops */
  1389. rtlpriv->rtlhal.interface = INTF_PCI;
  1390. rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
  1391. rtlpriv->intf_ops = &rtl_pci_ops;
  1392. /* find adapter */
  1393. _rtl_pci_find_adapter(pdev, hw);
  1394. /* Init IO handler */
  1395. _rtl_pci_io_handler_init(&pdev->dev, hw);
  1396. /*like read eeprom and so on */
  1397. rtlpriv->cfg->ops->read_eeprom_info(hw);
  1398. if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
  1399. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  1400. ("Can't init_sw_vars.\n"));
  1401. goto fail3;
  1402. }
  1403. rtlpriv->cfg->ops->init_sw_leds(hw);
  1404. /*aspm */
  1405. rtl_pci_init_aspm(hw);
  1406. /* Init mac80211 sw */
  1407. err = rtl_init_core(hw);
  1408. if (err) {
  1409. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  1410. ("Can't allocate sw for mac80211.\n"));
  1411. goto fail3;
  1412. }
  1413. /* Init PCI sw */
  1414. err = !rtl_pci_init(hw, pdev);
  1415. if (err) {
  1416. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  1417. ("Failed to init PCI.\n"));
  1418. goto fail3;
  1419. }
  1420. err = ieee80211_register_hw(hw);
  1421. if (err) {
  1422. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  1423. ("Can't register mac80211 hw.\n"));
  1424. goto fail3;
  1425. } else {
  1426. rtlpriv->mac80211.mac80211_registered = 1;
  1427. }
  1428. err = sysfs_create_group(&pdev->dev.kobj, &rtl_attribute_group);
  1429. if (err) {
  1430. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  1431. ("failed to create sysfs device attributes\n"));
  1432. goto fail3;
  1433. }
  1434. /*init rfkill */
  1435. rtl_init_rfkill(hw);
  1436. rtlpci = rtl_pcidev(pcipriv);
  1437. err = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
  1438. IRQF_SHARED, KBUILD_MODNAME, hw);
  1439. if (err) {
  1440. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  1441. ("%s: failed to register IRQ handler\n",
  1442. wiphy_name(hw->wiphy)));
  1443. goto fail3;
  1444. } else {
  1445. rtlpci->irq_alloc = 1;
  1446. }
  1447. set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
  1448. return 0;
  1449. fail3:
  1450. pci_set_drvdata(pdev, NULL);
  1451. rtl_deinit_core(hw);
  1452. _rtl_pci_io_handler_release(hw);
  1453. ieee80211_free_hw(hw);
  1454. if (rtlpriv->io.pci_mem_start != 0)
  1455. pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
  1456. fail2:
  1457. pci_release_regions(pdev);
  1458. fail1:
  1459. pci_disable_device(pdev);
  1460. return -ENODEV;
  1461. }
  1462. EXPORT_SYMBOL(rtl_pci_probe);
  1463. void rtl_pci_disconnect(struct pci_dev *pdev)
  1464. {
  1465. struct ieee80211_hw *hw = pci_get_drvdata(pdev);
  1466. struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
  1467. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1468. struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
  1469. struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
  1470. clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
  1471. sysfs_remove_group(&pdev->dev.kobj, &rtl_attribute_group);
  1472. /*ieee80211_unregister_hw will call ops_stop */
  1473. if (rtlmac->mac80211_registered == 1) {
  1474. ieee80211_unregister_hw(hw);
  1475. rtlmac->mac80211_registered = 0;
  1476. } else {
  1477. rtl_deinit_deferred_work(hw);
  1478. rtlpriv->intf_ops->adapter_stop(hw);
  1479. }
  1480. /*deinit rfkill */
  1481. rtl_deinit_rfkill(hw);
  1482. rtl_pci_deinit(hw);
  1483. rtl_deinit_core(hw);
  1484. rtlpriv->cfg->ops->deinit_sw_leds(hw);
  1485. _rtl_pci_io_handler_release(hw);
  1486. rtlpriv->cfg->ops->deinit_sw_vars(hw);
  1487. if (rtlpci->irq_alloc) {
  1488. free_irq(rtlpci->pdev->irq, hw);
  1489. rtlpci->irq_alloc = 0;
  1490. }
  1491. if (rtlpriv->io.pci_mem_start != 0) {
  1492. pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
  1493. pci_release_regions(pdev);
  1494. }
  1495. pci_disable_device(pdev);
  1496. pci_set_drvdata(pdev, NULL);
  1497. ieee80211_free_hw(hw);
  1498. }
  1499. EXPORT_SYMBOL(rtl_pci_disconnect);
  1500. /***************************************
  1501. kernel pci power state define:
  1502. PCI_D0 ((pci_power_t __force) 0)
  1503. PCI_D1 ((pci_power_t __force) 1)
  1504. PCI_D2 ((pci_power_t __force) 2)
  1505. PCI_D3hot ((pci_power_t __force) 3)
  1506. PCI_D3cold ((pci_power_t __force) 4)
  1507. PCI_UNKNOWN ((pci_power_t __force) 5)
  1508. This function is called when system
  1509. goes into suspend state mac80211 will
  1510. call rtl_mac_stop() from the mac80211
  1511. suspend function first, So there is
  1512. no need to call hw_disable here.
  1513. ****************************************/
  1514. int rtl_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  1515. {
  1516. pci_save_state(pdev);
  1517. pci_disable_device(pdev);
  1518. pci_set_power_state(pdev, PCI_D3hot);
  1519. return 0;
  1520. }
  1521. EXPORT_SYMBOL(rtl_pci_suspend);
  1522. int rtl_pci_resume(struct pci_dev *pdev)
  1523. {
  1524. int ret;
  1525. pci_set_power_state(pdev, PCI_D0);
  1526. ret = pci_enable_device(pdev);
  1527. if (ret) {
  1528. RT_ASSERT(false, ("ERR: <======\n"));
  1529. return ret;
  1530. }
  1531. pci_restore_state(pdev);
  1532. return 0;
  1533. }
  1534. EXPORT_SYMBOL(rtl_pci_resume);
  1535. struct rtl_intf_ops rtl_pci_ops = {
  1536. .adapter_start = rtl_pci_start,
  1537. .adapter_stop = rtl_pci_stop,
  1538. .adapter_tx = rtl_pci_tx,
  1539. .reset_trx_ring = rtl_pci_reset_trx_ring,
  1540. .disable_aspm = rtl_pci_disable_aspm,
  1541. .enable_aspm = rtl_pci_enable_aspm,
  1542. };