armada-370-xp.dtsi 5.2 KB

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  1. /*
  2. * Device Tree Include file for Marvell Armada 370 and Armada XP SoC
  3. *
  4. * Copyright (C) 2012 Marvell
  5. *
  6. * Lior Amsalem <alior@marvell.com>
  7. * Gregory CLEMENT <gregory.clement@free-electrons.com>
  8. * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  9. * Ben Dooks <ben.dooks@codethink.co.uk>
  10. *
  11. * This file is licensed under the terms of the GNU General Public
  12. * License version 2. This program is licensed "as is" without any
  13. * warranty of any kind, whether express or implied.
  14. *
  15. * This file contains the definitions that are common to the Armada
  16. * 370 and Armada XP SoC.
  17. */
  18. /include/ "skeleton64.dtsi"
  19. / {
  20. model = "Marvell Armada 370 and XP SoC";
  21. compatible = "marvell,armada-370-xp";
  22. aliases {
  23. eth0 = &eth0;
  24. eth1 = &eth1;
  25. };
  26. cpus {
  27. #address-cells = <1>;
  28. #size-cells = <0>;
  29. cpu@0 {
  30. compatible = "marvell,sheeva-v7";
  31. device_type = "cpu";
  32. reg = <0>;
  33. };
  34. };
  35. soc {
  36. #address-cells = <1>;
  37. #size-cells = <1>;
  38. compatible = "simple-bus";
  39. interrupt-parent = <&mpic>;
  40. ranges = <0 0 0xd0000000 0x0100000 /* internal registers */
  41. 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */>;
  42. internal-regs {
  43. compatible = "simple-bus";
  44. #address-cells = <1>;
  45. #size-cells = <1>;
  46. ranges;
  47. mpic: interrupt-controller@20000 {
  48. compatible = "marvell,mpic";
  49. #interrupt-cells = <1>;
  50. #size-cells = <1>;
  51. interrupt-controller;
  52. };
  53. coherency-fabric@20200 {
  54. compatible = "marvell,coherency-fabric";
  55. reg = <0x20200 0xb0>, <0x21810 0x1c>;
  56. };
  57. serial@12000 {
  58. compatible = "snps,dw-apb-uart";
  59. reg = <0x12000 0x100>;
  60. reg-shift = <2>;
  61. interrupts = <41>;
  62. reg-io-width = <1>;
  63. status = "disabled";
  64. };
  65. serial@12100 {
  66. compatible = "snps,dw-apb-uart";
  67. reg = <0x12100 0x100>;
  68. reg-shift = <2>;
  69. interrupts = <42>;
  70. reg-io-width = <1>;
  71. status = "disabled";
  72. };
  73. timer@20300 {
  74. reg = <0x20300 0x30>, <0x21040 0x30>;
  75. interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
  76. };
  77. sata@a0000 {
  78. compatible = "marvell,orion-sata";
  79. reg = <0xa0000 0x5000>;
  80. interrupts = <55>;
  81. clocks = <&gateclk 15>, <&gateclk 30>;
  82. clock-names = "0", "1";
  83. status = "disabled";
  84. };
  85. mdio {
  86. #address-cells = <1>;
  87. #size-cells = <0>;
  88. compatible = "marvell,orion-mdio";
  89. reg = <0x72004 0x4>;
  90. };
  91. eth0: ethernet@70000 {
  92. compatible = "marvell,armada-370-neta";
  93. reg = <0x70000 0x4000>;
  94. interrupts = <8>;
  95. clocks = <&gateclk 4>;
  96. status = "disabled";
  97. };
  98. eth1: ethernet@74000 {
  99. compatible = "marvell,armada-370-neta";
  100. reg = <0x74000 0x4000>;
  101. interrupts = <10>;
  102. clocks = <&gateclk 3>;
  103. status = "disabled";
  104. };
  105. i2c0: i2c@11000 {
  106. compatible = "marvell,mv64xxx-i2c";
  107. reg = <0x11000 0x20>;
  108. #address-cells = <1>;
  109. #size-cells = <0>;
  110. interrupts = <31>;
  111. timeout-ms = <1000>;
  112. clocks = <&coreclk 0>;
  113. status = "disabled";
  114. };
  115. i2c1: i2c@11100 {
  116. compatible = "marvell,mv64xxx-i2c";
  117. reg = <0x11100 0x20>;
  118. #address-cells = <1>;
  119. #size-cells = <0>;
  120. interrupts = <32>;
  121. timeout-ms = <1000>;
  122. clocks = <&coreclk 0>;
  123. status = "disabled";
  124. };
  125. rtc@10300 {
  126. compatible = "marvell,orion-rtc";
  127. reg = <0x10300 0x20>;
  128. interrupts = <50>;
  129. };
  130. mvsdio@d4000 {
  131. compatible = "marvell,orion-sdio";
  132. reg = <0xd4000 0x200>;
  133. interrupts = <54>;
  134. clocks = <&gateclk 17>;
  135. bus-width = <4>;
  136. cap-sdio-irq;
  137. cap-sd-highspeed;
  138. cap-mmc-highspeed;
  139. status = "disabled";
  140. };
  141. usb@50000 {
  142. compatible = "marvell,orion-ehci";
  143. reg = <0x50000 0x500>;
  144. interrupts = <45>;
  145. status = "disabled";
  146. };
  147. usb@51000 {
  148. compatible = "marvell,orion-ehci";
  149. reg = <0x51000 0x500>;
  150. interrupts = <46>;
  151. status = "disabled";
  152. };
  153. spi0: spi@10600 {
  154. compatible = "marvell,orion-spi";
  155. reg = <0x10600 0x28>;
  156. #address-cells = <1>;
  157. #size-cells = <0>;
  158. cell-index = <0>;
  159. interrupts = <30>;
  160. clocks = <&coreclk 0>;
  161. status = "disabled";
  162. };
  163. spi1: spi@10680 {
  164. compatible = "marvell,orion-spi";
  165. reg = <0x10680 0x28>;
  166. #address-cells = <1>;
  167. #size-cells = <0>;
  168. cell-index = <1>;
  169. interrupts = <92>;
  170. clocks = <&coreclk 0>;
  171. status = "disabled";
  172. };
  173. devbus-bootcs@10400 {
  174. compatible = "marvell,mvebu-devbus";
  175. reg = <0x10400 0x8>;
  176. #address-cells = <1>;
  177. #size-cells = <1>;
  178. clocks = <&coreclk 0>;
  179. status = "disabled";
  180. };
  181. devbus-cs0@10408 {
  182. compatible = "marvell,mvebu-devbus";
  183. reg = <0x10408 0x8>;
  184. #address-cells = <1>;
  185. #size-cells = <1>;
  186. clocks = <&coreclk 0>;
  187. status = "disabled";
  188. };
  189. devbus-cs1@10410 {
  190. compatible = "marvell,mvebu-devbus";
  191. reg = <0x10410 0x8>;
  192. #address-cells = <1>;
  193. #size-cells = <1>;
  194. clocks = <&coreclk 0>;
  195. status = "disabled";
  196. };
  197. devbus-cs2@10418 {
  198. compatible = "marvell,mvebu-devbus";
  199. reg = <0x10418 0x8>;
  200. #address-cells = <1>;
  201. #size-cells = <1>;
  202. clocks = <&coreclk 0>;
  203. status = "disabled";
  204. };
  205. devbus-cs3@10420 {
  206. compatible = "marvell,mvebu-devbus";
  207. reg = <0x10420 0x8>;
  208. #address-cells = <1>;
  209. #size-cells = <1>;
  210. clocks = <&coreclk 0>;
  211. status = "disabled";
  212. };
  213. };
  214. };
  215. };