mx3_camera.c 34 KB

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  1. /*
  2. * V4L2 Driver for i.MX3x camera host
  3. *
  4. * Copyright (C) 2008
  5. * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/init.h>
  12. #include <linux/module.h>
  13. #include <linux/version.h>
  14. #include <linux/videodev2.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/clk.h>
  17. #include <linux/vmalloc.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/sched.h>
  20. #include <media/v4l2-common.h>
  21. #include <media/v4l2-dev.h>
  22. #include <media/videobuf-dma-contig.h>
  23. #include <media/soc_camera.h>
  24. #include <mach/ipu.h>
  25. #include <mach/mx3_camera.h>
  26. #define MX3_CAM_DRV_NAME "mx3-camera"
  27. /* CMOS Sensor Interface Registers */
  28. #define CSI_REG_START 0x60
  29. #define CSI_SENS_CONF (0x60 - CSI_REG_START)
  30. #define CSI_SENS_FRM_SIZE (0x64 - CSI_REG_START)
  31. #define CSI_ACT_FRM_SIZE (0x68 - CSI_REG_START)
  32. #define CSI_OUT_FRM_CTRL (0x6C - CSI_REG_START)
  33. #define CSI_TST_CTRL (0x70 - CSI_REG_START)
  34. #define CSI_CCIR_CODE_1 (0x74 - CSI_REG_START)
  35. #define CSI_CCIR_CODE_2 (0x78 - CSI_REG_START)
  36. #define CSI_CCIR_CODE_3 (0x7C - CSI_REG_START)
  37. #define CSI_FLASH_STROBE_1 (0x80 - CSI_REG_START)
  38. #define CSI_FLASH_STROBE_2 (0x84 - CSI_REG_START)
  39. #define CSI_SENS_CONF_VSYNC_POL_SHIFT 0
  40. #define CSI_SENS_CONF_HSYNC_POL_SHIFT 1
  41. #define CSI_SENS_CONF_DATA_POL_SHIFT 2
  42. #define CSI_SENS_CONF_PIX_CLK_POL_SHIFT 3
  43. #define CSI_SENS_CONF_SENS_PRTCL_SHIFT 4
  44. #define CSI_SENS_CONF_SENS_CLKSRC_SHIFT 7
  45. #define CSI_SENS_CONF_DATA_FMT_SHIFT 8
  46. #define CSI_SENS_CONF_DATA_WIDTH_SHIFT 10
  47. #define CSI_SENS_CONF_EXT_VSYNC_SHIFT 15
  48. #define CSI_SENS_CONF_DIVRATIO_SHIFT 16
  49. #define CSI_SENS_CONF_DATA_FMT_RGB_YUV444 (0UL << CSI_SENS_CONF_DATA_FMT_SHIFT)
  50. #define CSI_SENS_CONF_DATA_FMT_YUV422 (2UL << CSI_SENS_CONF_DATA_FMT_SHIFT)
  51. #define CSI_SENS_CONF_DATA_FMT_BAYER (3UL << CSI_SENS_CONF_DATA_FMT_SHIFT)
  52. #define MAX_VIDEO_MEM 16
  53. struct mx3_camera_buffer {
  54. /* common v4l buffer stuff -- must be first */
  55. struct videobuf_buffer vb;
  56. const struct soc_camera_data_format *fmt;
  57. /* One descriptot per scatterlist (per frame) */
  58. struct dma_async_tx_descriptor *txd;
  59. /* We have to "build" a scatterlist ourselves - one element per frame */
  60. struct scatterlist sg;
  61. };
  62. /**
  63. * struct mx3_camera_dev - i.MX3x camera (CSI) object
  64. * @dev: camera device, to which the coherent buffer is attached
  65. * @icd: currently attached camera sensor
  66. * @clk: pointer to clock
  67. * @base: remapped register base address
  68. * @pdata: platform data
  69. * @platform_flags: platform flags
  70. * @mclk: master clock frequency in Hz
  71. * @capture: list of capture videobuffers
  72. * @lock: protects video buffer lists
  73. * @active: active video buffer
  74. * @idmac_channel: array of pointers to IPU DMAC DMA channels
  75. * @soc_host: embedded soc_host object
  76. */
  77. struct mx3_camera_dev {
  78. /*
  79. * i.MX3x is only supposed to handle one camera on its Camera Sensor
  80. * Interface. If anyone ever builds hardware to enable more than one
  81. * camera _simultaneously_, they will have to modify this driver too
  82. */
  83. struct soc_camera_device *icd;
  84. struct clk *clk;
  85. void __iomem *base;
  86. struct mx3_camera_pdata *pdata;
  87. unsigned long platform_flags;
  88. unsigned long mclk;
  89. struct list_head capture;
  90. spinlock_t lock; /* Protects video buffer lists */
  91. struct mx3_camera_buffer *active;
  92. /* IDMAC / dmaengine interface */
  93. struct idmac_channel *idmac_channel[1]; /* We need one channel */
  94. struct soc_camera_host soc_host;
  95. };
  96. struct dma_chan_request {
  97. struct mx3_camera_dev *mx3_cam;
  98. enum ipu_channel id;
  99. };
  100. static int mx3_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt);
  101. static u32 csi_reg_read(struct mx3_camera_dev *mx3, off_t reg)
  102. {
  103. return __raw_readl(mx3->base + reg);
  104. }
  105. static void csi_reg_write(struct mx3_camera_dev *mx3, u32 value, off_t reg)
  106. {
  107. __raw_writel(value, mx3->base + reg);
  108. }
  109. /* Called from the IPU IDMAC ISR */
  110. static void mx3_cam_dma_done(void *arg)
  111. {
  112. struct idmac_tx_desc *desc = to_tx_desc(arg);
  113. struct dma_chan *chan = desc->txd.chan;
  114. struct idmac_channel *ichannel = to_idmac_chan(chan);
  115. struct mx3_camera_dev *mx3_cam = ichannel->client;
  116. struct videobuf_buffer *vb;
  117. dev_dbg(chan->device->dev, "callback cookie %d, active DMA 0x%08x\n",
  118. desc->txd.cookie, mx3_cam->active ? sg_dma_address(&mx3_cam->active->sg) : 0);
  119. spin_lock(&mx3_cam->lock);
  120. if (mx3_cam->active) {
  121. vb = &mx3_cam->active->vb;
  122. list_del_init(&vb->queue);
  123. vb->state = VIDEOBUF_DONE;
  124. do_gettimeofday(&vb->ts);
  125. vb->field_count++;
  126. wake_up(&vb->done);
  127. }
  128. if (list_empty(&mx3_cam->capture)) {
  129. mx3_cam->active = NULL;
  130. spin_unlock(&mx3_cam->lock);
  131. /*
  132. * stop capture - without further buffers IPU_CHA_BUF0_RDY will
  133. * not get updated
  134. */
  135. return;
  136. }
  137. mx3_cam->active = list_entry(mx3_cam->capture.next,
  138. struct mx3_camera_buffer, vb.queue);
  139. mx3_cam->active->vb.state = VIDEOBUF_ACTIVE;
  140. spin_unlock(&mx3_cam->lock);
  141. }
  142. static void free_buffer(struct videobuf_queue *vq, struct mx3_camera_buffer *buf)
  143. {
  144. struct soc_camera_device *icd = vq->priv_data;
  145. struct videobuf_buffer *vb = &buf->vb;
  146. struct dma_async_tx_descriptor *txd = buf->txd;
  147. struct idmac_channel *ichan;
  148. BUG_ON(in_interrupt());
  149. dev_dbg(icd->dev.parent, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
  150. vb, vb->baddr, vb->bsize);
  151. /*
  152. * This waits until this buffer is out of danger, i.e., until it is no
  153. * longer in STATE_QUEUED or STATE_ACTIVE
  154. */
  155. videobuf_waiton(vb, 0, 0);
  156. if (txd) {
  157. ichan = to_idmac_chan(txd->chan);
  158. async_tx_ack(txd);
  159. }
  160. videobuf_dma_contig_free(vq, vb);
  161. buf->txd = NULL;
  162. vb->state = VIDEOBUF_NEEDS_INIT;
  163. }
  164. /*
  165. * Videobuf operations
  166. */
  167. /*
  168. * Calculate the __buffer__ (not data) size and number of buffers.
  169. * Called with .vb_lock held
  170. */
  171. static int mx3_videobuf_setup(struct videobuf_queue *vq, unsigned int *count,
  172. unsigned int *size)
  173. {
  174. struct soc_camera_device *icd = vq->priv_data;
  175. struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
  176. struct mx3_camera_dev *mx3_cam = ici->priv;
  177. /*
  178. * bits-per-pixel (depth) as specified in camera's pixel format does
  179. * not necessarily match what the camera interface writes to RAM, but
  180. * it should be good enough for now.
  181. */
  182. unsigned int bpp = DIV_ROUND_UP(icd->current_fmt->depth, 8);
  183. if (!mx3_cam->idmac_channel[0])
  184. return -EINVAL;
  185. *size = icd->user_width * icd->user_height * bpp;
  186. if (!*count)
  187. *count = 32;
  188. if (*size * *count > MAX_VIDEO_MEM * 1024 * 1024)
  189. *count = MAX_VIDEO_MEM * 1024 * 1024 / *size;
  190. return 0;
  191. }
  192. /* Called with .vb_lock held */
  193. static int mx3_videobuf_prepare(struct videobuf_queue *vq,
  194. struct videobuf_buffer *vb, enum v4l2_field field)
  195. {
  196. struct soc_camera_device *icd = vq->priv_data;
  197. struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
  198. struct mx3_camera_dev *mx3_cam = ici->priv;
  199. struct mx3_camera_buffer *buf =
  200. container_of(vb, struct mx3_camera_buffer, vb);
  201. /* current_fmt _must_ always be set */
  202. size_t new_size = icd->user_width * icd->user_height *
  203. ((icd->current_fmt->depth + 7) >> 3);
  204. int ret;
  205. /*
  206. * I think, in buf_prepare you only have to protect global data,
  207. * the actual buffer is yours
  208. */
  209. if (buf->fmt != icd->current_fmt ||
  210. vb->width != icd->user_width ||
  211. vb->height != icd->user_height ||
  212. vb->field != field) {
  213. buf->fmt = icd->current_fmt;
  214. vb->width = icd->user_width;
  215. vb->height = icd->user_height;
  216. vb->field = field;
  217. if (vb->state != VIDEOBUF_NEEDS_INIT)
  218. free_buffer(vq, buf);
  219. }
  220. if (vb->baddr && vb->bsize < new_size) {
  221. /* User provided buffer, but it is too small */
  222. ret = -ENOMEM;
  223. goto out;
  224. }
  225. if (vb->state == VIDEOBUF_NEEDS_INIT) {
  226. struct idmac_channel *ichan = mx3_cam->idmac_channel[0];
  227. struct scatterlist *sg = &buf->sg;
  228. /*
  229. * The total size of video-buffers that will be allocated / mapped.
  230. * *size that we calculated in videobuf_setup gets assigned to
  231. * vb->bsize, and now we use the same calculation to get vb->size.
  232. */
  233. vb->size = new_size;
  234. /* This actually (allocates and) maps buffers */
  235. ret = videobuf_iolock(vq, vb, NULL);
  236. if (ret)
  237. goto fail;
  238. /*
  239. * We will have to configure the IDMAC channel. It has two slots
  240. * for DMA buffers, we shall enter the first two buffers there,
  241. * and then submit new buffers in DMA-ready interrupts
  242. */
  243. sg_init_table(sg, 1);
  244. sg_dma_address(sg) = videobuf_to_dma_contig(vb);
  245. sg_dma_len(sg) = vb->size;
  246. buf->txd = ichan->dma_chan.device->device_prep_slave_sg(
  247. &ichan->dma_chan, sg, 1, DMA_FROM_DEVICE,
  248. DMA_PREP_INTERRUPT);
  249. if (!buf->txd) {
  250. ret = -EIO;
  251. goto fail;
  252. }
  253. buf->txd->callback_param = buf->txd;
  254. buf->txd->callback = mx3_cam_dma_done;
  255. vb->state = VIDEOBUF_PREPARED;
  256. }
  257. return 0;
  258. fail:
  259. free_buffer(vq, buf);
  260. out:
  261. return ret;
  262. }
  263. static enum pixel_fmt fourcc_to_ipu_pix(__u32 fourcc)
  264. {
  265. /* Add more formats as need arises and test possibilities appear... */
  266. switch (fourcc) {
  267. case V4L2_PIX_FMT_RGB565:
  268. return IPU_PIX_FMT_RGB565;
  269. case V4L2_PIX_FMT_RGB24:
  270. return IPU_PIX_FMT_RGB24;
  271. case V4L2_PIX_FMT_RGB332:
  272. return IPU_PIX_FMT_RGB332;
  273. case V4L2_PIX_FMT_YUV422P:
  274. return IPU_PIX_FMT_YVU422P;
  275. default:
  276. return IPU_PIX_FMT_GENERIC;
  277. }
  278. }
  279. /*
  280. * Called with .vb_lock mutex held and
  281. * under spinlock_irqsave(&mx3_cam->lock, ...)
  282. */
  283. static void mx3_videobuf_queue(struct videobuf_queue *vq,
  284. struct videobuf_buffer *vb)
  285. {
  286. struct soc_camera_device *icd = vq->priv_data;
  287. struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
  288. struct mx3_camera_dev *mx3_cam = ici->priv;
  289. struct mx3_camera_buffer *buf =
  290. container_of(vb, struct mx3_camera_buffer, vb);
  291. struct dma_async_tx_descriptor *txd = buf->txd;
  292. struct idmac_channel *ichan = to_idmac_chan(txd->chan);
  293. struct idmac_video_param *video = &ichan->params.video;
  294. const struct soc_camera_data_format *data_fmt = icd->current_fmt;
  295. dma_cookie_t cookie;
  296. BUG_ON(!irqs_disabled());
  297. /* This is the configuration of one sg-element */
  298. video->out_pixel_fmt = fourcc_to_ipu_pix(data_fmt->fourcc);
  299. video->out_width = icd->user_width;
  300. video->out_height = icd->user_height;
  301. video->out_stride = icd->user_width;
  302. #ifdef DEBUG
  303. /* helps to see what DMA actually has written */
  304. memset((void *)vb->baddr, 0xaa, vb->bsize);
  305. #endif
  306. list_add_tail(&vb->queue, &mx3_cam->capture);
  307. if (!mx3_cam->active) {
  308. mx3_cam->active = buf;
  309. vb->state = VIDEOBUF_ACTIVE;
  310. } else {
  311. vb->state = VIDEOBUF_QUEUED;
  312. }
  313. spin_unlock_irq(&mx3_cam->lock);
  314. cookie = txd->tx_submit(txd);
  315. dev_dbg(icd->dev.parent, "Submitted cookie %d DMA 0x%08x\n",
  316. cookie, sg_dma_address(&buf->sg));
  317. spin_lock_irq(&mx3_cam->lock);
  318. if (cookie >= 0)
  319. return;
  320. /* Submit error */
  321. vb->state = VIDEOBUF_PREPARED;
  322. list_del_init(&vb->queue);
  323. if (mx3_cam->active == buf)
  324. mx3_cam->active = NULL;
  325. }
  326. /* Called with .vb_lock held */
  327. static void mx3_videobuf_release(struct videobuf_queue *vq,
  328. struct videobuf_buffer *vb)
  329. {
  330. struct soc_camera_device *icd = vq->priv_data;
  331. struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
  332. struct mx3_camera_dev *mx3_cam = ici->priv;
  333. struct mx3_camera_buffer *buf =
  334. container_of(vb, struct mx3_camera_buffer, vb);
  335. unsigned long flags;
  336. dev_dbg(icd->dev.parent,
  337. "Release%s DMA 0x%08x (state %d), queue %sempty\n",
  338. mx3_cam->active == buf ? " active" : "", sg_dma_address(&buf->sg),
  339. vb->state, list_empty(&vb->queue) ? "" : "not ");
  340. spin_lock_irqsave(&mx3_cam->lock, flags);
  341. if ((vb->state == VIDEOBUF_ACTIVE || vb->state == VIDEOBUF_QUEUED) &&
  342. !list_empty(&vb->queue)) {
  343. vb->state = VIDEOBUF_ERROR;
  344. list_del_init(&vb->queue);
  345. if (mx3_cam->active == buf)
  346. mx3_cam->active = NULL;
  347. }
  348. spin_unlock_irqrestore(&mx3_cam->lock, flags);
  349. free_buffer(vq, buf);
  350. }
  351. static struct videobuf_queue_ops mx3_videobuf_ops = {
  352. .buf_setup = mx3_videobuf_setup,
  353. .buf_prepare = mx3_videobuf_prepare,
  354. .buf_queue = mx3_videobuf_queue,
  355. .buf_release = mx3_videobuf_release,
  356. };
  357. static void mx3_camera_init_videobuf(struct videobuf_queue *q,
  358. struct soc_camera_device *icd)
  359. {
  360. struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
  361. struct mx3_camera_dev *mx3_cam = ici->priv;
  362. videobuf_queue_dma_contig_init(q, &mx3_videobuf_ops, icd->dev.parent,
  363. &mx3_cam->lock,
  364. V4L2_BUF_TYPE_VIDEO_CAPTURE,
  365. V4L2_FIELD_NONE,
  366. sizeof(struct mx3_camera_buffer), icd);
  367. }
  368. /* First part of ipu_csi_init_interface() */
  369. static void mx3_camera_activate(struct mx3_camera_dev *mx3_cam,
  370. struct soc_camera_device *icd)
  371. {
  372. u32 conf;
  373. long rate;
  374. /* Set default size: ipu_csi_set_window_size() */
  375. csi_reg_write(mx3_cam, (640 - 1) | ((480 - 1) << 16), CSI_ACT_FRM_SIZE);
  376. /* ...and position to 0:0: ipu_csi_set_window_pos() */
  377. conf = csi_reg_read(mx3_cam, CSI_OUT_FRM_CTRL) & 0xffff0000;
  378. csi_reg_write(mx3_cam, conf, CSI_OUT_FRM_CTRL);
  379. /* We use only gated clock synchronisation mode so far */
  380. conf = 0 << CSI_SENS_CONF_SENS_PRTCL_SHIFT;
  381. /* Set generic data, platform-biggest bus-width */
  382. conf |= CSI_SENS_CONF_DATA_FMT_BAYER;
  383. if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_15)
  384. conf |= 3 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
  385. else if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_10)
  386. conf |= 2 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
  387. else if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_8)
  388. conf |= 1 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
  389. else/* if (mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_4)*/
  390. conf |= 0 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
  391. if (mx3_cam->platform_flags & MX3_CAMERA_CLK_SRC)
  392. conf |= 1 << CSI_SENS_CONF_SENS_CLKSRC_SHIFT;
  393. if (mx3_cam->platform_flags & MX3_CAMERA_EXT_VSYNC)
  394. conf |= 1 << CSI_SENS_CONF_EXT_VSYNC_SHIFT;
  395. if (mx3_cam->platform_flags & MX3_CAMERA_DP)
  396. conf |= 1 << CSI_SENS_CONF_DATA_POL_SHIFT;
  397. if (mx3_cam->platform_flags & MX3_CAMERA_PCP)
  398. conf |= 1 << CSI_SENS_CONF_PIX_CLK_POL_SHIFT;
  399. if (mx3_cam->platform_flags & MX3_CAMERA_HSP)
  400. conf |= 1 << CSI_SENS_CONF_HSYNC_POL_SHIFT;
  401. if (mx3_cam->platform_flags & MX3_CAMERA_VSP)
  402. conf |= 1 << CSI_SENS_CONF_VSYNC_POL_SHIFT;
  403. /* ipu_csi_init_interface() */
  404. csi_reg_write(mx3_cam, conf, CSI_SENS_CONF);
  405. clk_enable(mx3_cam->clk);
  406. rate = clk_round_rate(mx3_cam->clk, mx3_cam->mclk);
  407. dev_dbg(icd->dev.parent, "Set SENS_CONF to %x, rate %ld\n", conf, rate);
  408. if (rate)
  409. clk_set_rate(mx3_cam->clk, rate);
  410. }
  411. /* Called with .video_lock held */
  412. static int mx3_camera_add_device(struct soc_camera_device *icd)
  413. {
  414. struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
  415. struct mx3_camera_dev *mx3_cam = ici->priv;
  416. if (mx3_cam->icd)
  417. return -EBUSY;
  418. mx3_camera_activate(mx3_cam, icd);
  419. mx3_cam->icd = icd;
  420. dev_info(icd->dev.parent, "MX3 Camera driver attached to camera %d\n",
  421. icd->devnum);
  422. return 0;
  423. }
  424. /* Called with .video_lock held */
  425. static void mx3_camera_remove_device(struct soc_camera_device *icd)
  426. {
  427. struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
  428. struct mx3_camera_dev *mx3_cam = ici->priv;
  429. struct idmac_channel **ichan = &mx3_cam->idmac_channel[0];
  430. BUG_ON(icd != mx3_cam->icd);
  431. if (*ichan) {
  432. dma_release_channel(&(*ichan)->dma_chan);
  433. *ichan = NULL;
  434. }
  435. clk_disable(mx3_cam->clk);
  436. mx3_cam->icd = NULL;
  437. dev_info(icd->dev.parent, "MX3 Camera driver detached from camera %d\n",
  438. icd->devnum);
  439. }
  440. static bool channel_change_requested(struct soc_camera_device *icd,
  441. struct v4l2_rect *rect)
  442. {
  443. struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
  444. struct mx3_camera_dev *mx3_cam = ici->priv;
  445. struct idmac_channel *ichan = mx3_cam->idmac_channel[0];
  446. /* Do buffers have to be re-allocated or channel re-configured? */
  447. return ichan && rect->width * rect->height >
  448. icd->user_width * icd->user_height;
  449. }
  450. static int test_platform_param(struct mx3_camera_dev *mx3_cam,
  451. unsigned char buswidth, unsigned long *flags)
  452. {
  453. /*
  454. * Platform specified synchronization and pixel clock polarities are
  455. * only a recommendation and are only used during probing. MX3x
  456. * camera interface only works in master mode, i.e., uses HSYNC and
  457. * VSYNC signals from the sensor
  458. */
  459. *flags = SOCAM_MASTER |
  460. SOCAM_HSYNC_ACTIVE_HIGH |
  461. SOCAM_HSYNC_ACTIVE_LOW |
  462. SOCAM_VSYNC_ACTIVE_HIGH |
  463. SOCAM_VSYNC_ACTIVE_LOW |
  464. SOCAM_PCLK_SAMPLE_RISING |
  465. SOCAM_PCLK_SAMPLE_FALLING |
  466. SOCAM_DATA_ACTIVE_HIGH |
  467. SOCAM_DATA_ACTIVE_LOW;
  468. /*
  469. * If requested data width is supported by the platform, use it or any
  470. * possible lower value - i.MX31 is smart enough to schift bits
  471. */
  472. switch (buswidth) {
  473. case 15:
  474. if (!(mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_15))
  475. return -EINVAL;
  476. *flags |= SOCAM_DATAWIDTH_15 | SOCAM_DATAWIDTH_10 |
  477. SOCAM_DATAWIDTH_8 | SOCAM_DATAWIDTH_4;
  478. break;
  479. case 10:
  480. if (!(mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_10))
  481. return -EINVAL;
  482. *flags |= SOCAM_DATAWIDTH_10 | SOCAM_DATAWIDTH_8 |
  483. SOCAM_DATAWIDTH_4;
  484. break;
  485. case 8:
  486. if (!(mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_8))
  487. return -EINVAL;
  488. *flags |= SOCAM_DATAWIDTH_8 | SOCAM_DATAWIDTH_4;
  489. break;
  490. case 4:
  491. if (!(mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_4))
  492. return -EINVAL;
  493. *flags |= SOCAM_DATAWIDTH_4;
  494. break;
  495. default:
  496. dev_warn(mx3_cam->soc_host.v4l2_dev.dev,
  497. "Unsupported bus width %d\n", buswidth);
  498. return -EINVAL;
  499. }
  500. return 0;
  501. }
  502. static int mx3_camera_try_bus_param(struct soc_camera_device *icd,
  503. const unsigned int depth)
  504. {
  505. struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
  506. struct mx3_camera_dev *mx3_cam = ici->priv;
  507. unsigned long bus_flags, camera_flags;
  508. int ret = test_platform_param(mx3_cam, depth, &bus_flags);
  509. dev_dbg(icd->dev.parent, "request bus width %d bit: %d\n", depth, ret);
  510. if (ret < 0)
  511. return ret;
  512. camera_flags = icd->ops->query_bus_param(icd);
  513. ret = soc_camera_bus_param_compatible(camera_flags, bus_flags);
  514. if (ret < 0)
  515. dev_warn(icd->dev.parent,
  516. "Flags incompatible: camera %lx, host %lx\n",
  517. camera_flags, bus_flags);
  518. return ret;
  519. }
  520. static bool chan_filter(struct dma_chan *chan, void *arg)
  521. {
  522. struct dma_chan_request *rq = arg;
  523. struct mx3_camera_pdata *pdata;
  524. if (!rq)
  525. return false;
  526. pdata = rq->mx3_cam->soc_host.v4l2_dev.dev->platform_data;
  527. return rq->id == chan->chan_id &&
  528. pdata->dma_dev == chan->device->dev;
  529. }
  530. static const struct soc_camera_data_format mx3_camera_formats[] = {
  531. {
  532. .name = "Bayer (sRGB) 8 bit",
  533. .depth = 8,
  534. .fourcc = V4L2_PIX_FMT_SBGGR8,
  535. .colorspace = V4L2_COLORSPACE_SRGB,
  536. }, {
  537. .name = "Monochrome 8 bit",
  538. .depth = 8,
  539. .fourcc = V4L2_PIX_FMT_GREY,
  540. .colorspace = V4L2_COLORSPACE_JPEG,
  541. },
  542. };
  543. static bool buswidth_supported(struct soc_camera_host *ici, int depth)
  544. {
  545. struct mx3_camera_dev *mx3_cam = ici->priv;
  546. switch (depth) {
  547. case 4:
  548. return !!(mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_4);
  549. case 8:
  550. return !!(mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_8);
  551. case 10:
  552. return !!(mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_10);
  553. case 15:
  554. return !!(mx3_cam->platform_flags & MX3_CAMERA_DATAWIDTH_15);
  555. }
  556. return false;
  557. }
  558. static int mx3_camera_get_formats(struct soc_camera_device *icd, int idx,
  559. struct soc_camera_format_xlate *xlate)
  560. {
  561. struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
  562. int formats = 0, buswidth, ret;
  563. buswidth = icd->formats[idx].depth;
  564. if (!buswidth_supported(ici, buswidth))
  565. return 0;
  566. ret = mx3_camera_try_bus_param(icd, buswidth);
  567. if (ret < 0)
  568. return 0;
  569. switch (icd->formats[idx].fourcc) {
  570. case V4L2_PIX_FMT_SGRBG10:
  571. formats++;
  572. if (xlate) {
  573. xlate->host_fmt = &mx3_camera_formats[0];
  574. xlate->cam_fmt = icd->formats + idx;
  575. xlate->buswidth = buswidth;
  576. xlate++;
  577. dev_dbg(icd->dev.parent,
  578. "Providing format %s using %s\n",
  579. mx3_camera_formats[0].name,
  580. icd->formats[idx].name);
  581. }
  582. goto passthrough;
  583. case V4L2_PIX_FMT_Y16:
  584. formats++;
  585. if (xlate) {
  586. xlate->host_fmt = &mx3_camera_formats[1];
  587. xlate->cam_fmt = icd->formats + idx;
  588. xlate->buswidth = buswidth;
  589. xlate++;
  590. dev_dbg(icd->dev.parent,
  591. "Providing format %s using %s\n",
  592. mx3_camera_formats[0].name,
  593. icd->formats[idx].name);
  594. }
  595. default:
  596. passthrough:
  597. /* Generic pass-through */
  598. formats++;
  599. if (xlate) {
  600. xlate->host_fmt = icd->formats + idx;
  601. xlate->cam_fmt = icd->formats + idx;
  602. xlate->buswidth = buswidth;
  603. xlate++;
  604. dev_dbg(icd->dev.parent,
  605. "Providing format %s in pass-through mode\n",
  606. icd->formats[idx].name);
  607. }
  608. }
  609. return formats;
  610. }
  611. static void configure_geometry(struct mx3_camera_dev *mx3_cam,
  612. unsigned int width, unsigned int height)
  613. {
  614. u32 ctrl, width_field, height_field;
  615. /* Setup frame size - this cannot be changed on-the-fly... */
  616. width_field = width - 1;
  617. height_field = height - 1;
  618. csi_reg_write(mx3_cam, width_field | (height_field << 16), CSI_SENS_FRM_SIZE);
  619. csi_reg_write(mx3_cam, width_field << 16, CSI_FLASH_STROBE_1);
  620. csi_reg_write(mx3_cam, (height_field << 16) | 0x22, CSI_FLASH_STROBE_2);
  621. csi_reg_write(mx3_cam, width_field | (height_field << 16), CSI_ACT_FRM_SIZE);
  622. /* ...and position */
  623. ctrl = csi_reg_read(mx3_cam, CSI_OUT_FRM_CTRL) & 0xffff0000;
  624. /* Sensor does the cropping */
  625. csi_reg_write(mx3_cam, ctrl | 0 | (0 << 8), CSI_OUT_FRM_CTRL);
  626. }
  627. static int acquire_dma_channel(struct mx3_camera_dev *mx3_cam)
  628. {
  629. dma_cap_mask_t mask;
  630. struct dma_chan *chan;
  631. struct idmac_channel **ichan = &mx3_cam->idmac_channel[0];
  632. /* We have to use IDMAC_IC_7 for Bayer / generic data */
  633. struct dma_chan_request rq = {.mx3_cam = mx3_cam,
  634. .id = IDMAC_IC_7};
  635. if (*ichan) {
  636. struct videobuf_buffer *vb, *_vb;
  637. dma_release_channel(&(*ichan)->dma_chan);
  638. *ichan = NULL;
  639. mx3_cam->active = NULL;
  640. list_for_each_entry_safe(vb, _vb, &mx3_cam->capture, queue) {
  641. list_del_init(&vb->queue);
  642. vb->state = VIDEOBUF_ERROR;
  643. wake_up(&vb->done);
  644. }
  645. }
  646. dma_cap_zero(mask);
  647. dma_cap_set(DMA_SLAVE, mask);
  648. dma_cap_set(DMA_PRIVATE, mask);
  649. chan = dma_request_channel(mask, chan_filter, &rq);
  650. if (!chan)
  651. return -EBUSY;
  652. *ichan = to_idmac_chan(chan);
  653. (*ichan)->client = mx3_cam;
  654. return 0;
  655. }
  656. /*
  657. * FIXME: learn to use stride != width, then we can keep stride properly aligned
  658. * and support arbitrary (even) widths.
  659. */
  660. static inline void stride_align(__s32 *width)
  661. {
  662. if (((*width + 7) & ~7) < 4096)
  663. *width = (*width + 7) & ~7;
  664. else
  665. *width = *width & ~7;
  666. }
  667. /*
  668. * As long as we don't implement host-side cropping and scaling, we can use
  669. * default g_crop and cropcap from soc_camera.c
  670. */
  671. static int mx3_camera_set_crop(struct soc_camera_device *icd,
  672. struct v4l2_crop *a)
  673. {
  674. struct v4l2_rect *rect = &a->c;
  675. struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
  676. struct mx3_camera_dev *mx3_cam = ici->priv;
  677. struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
  678. struct v4l2_format f = {.type = V4L2_BUF_TYPE_VIDEO_CAPTURE};
  679. struct v4l2_pix_format *pix = &f.fmt.pix;
  680. int ret;
  681. soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096);
  682. soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096);
  683. ret = v4l2_subdev_call(sd, video, s_crop, a);
  684. if (ret < 0)
  685. return ret;
  686. /* The capture device might have changed its output */
  687. ret = v4l2_subdev_call(sd, video, g_fmt, &f);
  688. if (ret < 0)
  689. return ret;
  690. if (pix->width & 7) {
  691. /* Ouch! We can only handle 8-byte aligned width... */
  692. stride_align(&pix->width);
  693. ret = v4l2_subdev_call(sd, video, s_fmt, &f);
  694. if (ret < 0)
  695. return ret;
  696. }
  697. if (pix->width != icd->user_width || pix->height != icd->user_height) {
  698. /*
  699. * We now know pixel formats and can decide upon DMA-channel(s)
  700. * So far only direct camera-to-memory is supported
  701. */
  702. if (channel_change_requested(icd, rect)) {
  703. int ret = acquire_dma_channel(mx3_cam);
  704. if (ret < 0)
  705. return ret;
  706. }
  707. configure_geometry(mx3_cam, pix->width, pix->height);
  708. }
  709. dev_dbg(icd->dev.parent, "Sensor cropped %dx%d\n",
  710. pix->width, pix->height);
  711. icd->user_width = pix->width;
  712. icd->user_height = pix->height;
  713. return ret;
  714. }
  715. static int mx3_camera_set_fmt(struct soc_camera_device *icd,
  716. struct v4l2_format *f)
  717. {
  718. struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
  719. struct mx3_camera_dev *mx3_cam = ici->priv;
  720. struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
  721. const struct soc_camera_format_xlate *xlate;
  722. struct v4l2_pix_format *pix = &f->fmt.pix;
  723. int ret;
  724. xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
  725. if (!xlate) {
  726. dev_warn(icd->dev.parent, "Format %x not found\n",
  727. pix->pixelformat);
  728. return -EINVAL;
  729. }
  730. stride_align(&pix->width);
  731. dev_dbg(icd->dev.parent, "Set format %dx%d\n", pix->width, pix->height);
  732. ret = acquire_dma_channel(mx3_cam);
  733. if (ret < 0)
  734. return ret;
  735. /*
  736. * Might have to perform a complete interface initialisation like in
  737. * ipu_csi_init_interface() in mxc_v4l2_s_param(). Also consider
  738. * mxc_v4l2_s_fmt()
  739. */
  740. configure_geometry(mx3_cam, pix->width, pix->height);
  741. ret = v4l2_subdev_call(sd, video, s_fmt, f);
  742. if (!ret) {
  743. icd->buswidth = xlate->buswidth;
  744. icd->current_fmt = xlate->host_fmt;
  745. }
  746. dev_dbg(icd->dev.parent, "Sensor set %dx%d\n", pix->width, pix->height);
  747. return ret;
  748. }
  749. static int mx3_camera_try_fmt(struct soc_camera_device *icd,
  750. struct v4l2_format *f)
  751. {
  752. struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
  753. const struct soc_camera_format_xlate *xlate;
  754. struct v4l2_pix_format *pix = &f->fmt.pix;
  755. __u32 pixfmt = pix->pixelformat;
  756. enum v4l2_field field;
  757. int ret;
  758. xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
  759. if (pixfmt && !xlate) {
  760. dev_warn(icd->dev.parent, "Format %x not found\n", pixfmt);
  761. return -EINVAL;
  762. }
  763. /* limit to MX3 hardware capabilities */
  764. if (pix->height > 4096)
  765. pix->height = 4096;
  766. if (pix->width > 4096)
  767. pix->width = 4096;
  768. pix->bytesperline = pix->width *
  769. DIV_ROUND_UP(xlate->host_fmt->depth, 8);
  770. pix->sizeimage = pix->height * pix->bytesperline;
  771. /* camera has to see its format, but the user the original one */
  772. pix->pixelformat = xlate->cam_fmt->fourcc;
  773. /* limit to sensor capabilities */
  774. ret = v4l2_subdev_call(sd, video, try_fmt, f);
  775. pix->pixelformat = xlate->host_fmt->fourcc;
  776. field = pix->field;
  777. if (field == V4L2_FIELD_ANY) {
  778. pix->field = V4L2_FIELD_NONE;
  779. } else if (field != V4L2_FIELD_NONE) {
  780. dev_err(icd->dev.parent, "Field type %d unsupported.\n", field);
  781. return -EINVAL;
  782. }
  783. return ret;
  784. }
  785. static int mx3_camera_reqbufs(struct soc_camera_file *icf,
  786. struct v4l2_requestbuffers *p)
  787. {
  788. return 0;
  789. }
  790. static unsigned int mx3_camera_poll(struct file *file, poll_table *pt)
  791. {
  792. struct soc_camera_file *icf = file->private_data;
  793. return videobuf_poll_stream(file, &icf->vb_vidq, pt);
  794. }
  795. static int mx3_camera_querycap(struct soc_camera_host *ici,
  796. struct v4l2_capability *cap)
  797. {
  798. /* cap->name is set by the firendly caller:-> */
  799. strlcpy(cap->card, "i.MX3x Camera", sizeof(cap->card));
  800. cap->version = KERNEL_VERSION(0, 2, 2);
  801. cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
  802. return 0;
  803. }
  804. static int mx3_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
  805. {
  806. struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
  807. struct mx3_camera_dev *mx3_cam = ici->priv;
  808. unsigned long bus_flags, camera_flags, common_flags;
  809. u32 dw, sens_conf;
  810. int ret = test_platform_param(mx3_cam, icd->buswidth, &bus_flags);
  811. const struct soc_camera_format_xlate *xlate;
  812. struct device *dev = icd->dev.parent;
  813. xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
  814. if (!xlate) {
  815. dev_warn(dev, "Format %x not found\n", pixfmt);
  816. return -EINVAL;
  817. }
  818. dev_dbg(dev, "requested bus width %d bit: %d\n",
  819. icd->buswidth, ret);
  820. if (ret < 0)
  821. return ret;
  822. camera_flags = icd->ops->query_bus_param(icd);
  823. common_flags = soc_camera_bus_param_compatible(camera_flags, bus_flags);
  824. dev_dbg(dev, "Flags cam: 0x%lx host: 0x%lx common: 0x%lx\n",
  825. camera_flags, bus_flags, common_flags);
  826. if (!common_flags) {
  827. dev_dbg(dev, "no common flags");
  828. return -EINVAL;
  829. }
  830. /* Make choices, based on platform preferences */
  831. if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) &&
  832. (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) {
  833. if (mx3_cam->platform_flags & MX3_CAMERA_HSP)
  834. common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH;
  835. else
  836. common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW;
  837. }
  838. if ((common_flags & SOCAM_VSYNC_ACTIVE_HIGH) &&
  839. (common_flags & SOCAM_VSYNC_ACTIVE_LOW)) {
  840. if (mx3_cam->platform_flags & MX3_CAMERA_VSP)
  841. common_flags &= ~SOCAM_VSYNC_ACTIVE_HIGH;
  842. else
  843. common_flags &= ~SOCAM_VSYNC_ACTIVE_LOW;
  844. }
  845. if ((common_flags & SOCAM_DATA_ACTIVE_HIGH) &&
  846. (common_flags & SOCAM_DATA_ACTIVE_LOW)) {
  847. if (mx3_cam->platform_flags & MX3_CAMERA_DP)
  848. common_flags &= ~SOCAM_DATA_ACTIVE_HIGH;
  849. else
  850. common_flags &= ~SOCAM_DATA_ACTIVE_LOW;
  851. }
  852. if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) &&
  853. (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) {
  854. if (mx3_cam->platform_flags & MX3_CAMERA_PCP)
  855. common_flags &= ~SOCAM_PCLK_SAMPLE_RISING;
  856. else
  857. common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING;
  858. }
  859. /*
  860. * Make the camera work in widest common mode, we'll take care of
  861. * the rest
  862. */
  863. if (common_flags & SOCAM_DATAWIDTH_15)
  864. common_flags = (common_flags & ~SOCAM_DATAWIDTH_MASK) |
  865. SOCAM_DATAWIDTH_15;
  866. else if (common_flags & SOCAM_DATAWIDTH_10)
  867. common_flags = (common_flags & ~SOCAM_DATAWIDTH_MASK) |
  868. SOCAM_DATAWIDTH_10;
  869. else if (common_flags & SOCAM_DATAWIDTH_8)
  870. common_flags = (common_flags & ~SOCAM_DATAWIDTH_MASK) |
  871. SOCAM_DATAWIDTH_8;
  872. else
  873. common_flags = (common_flags & ~SOCAM_DATAWIDTH_MASK) |
  874. SOCAM_DATAWIDTH_4;
  875. ret = icd->ops->set_bus_param(icd, common_flags);
  876. if (ret < 0) {
  877. dev_dbg(dev, "camera set_bus_param(%lx) returned %d\n",
  878. common_flags, ret);
  879. return ret;
  880. }
  881. /*
  882. * So far only gated clock mode is supported. Add a line
  883. * (3 << CSI_SENS_CONF_SENS_PRTCL_SHIFT) |
  884. * below and select the required mode when supporting other
  885. * synchronisation protocols.
  886. */
  887. sens_conf = csi_reg_read(mx3_cam, CSI_SENS_CONF) &
  888. ~((1 << CSI_SENS_CONF_VSYNC_POL_SHIFT) |
  889. (1 << CSI_SENS_CONF_HSYNC_POL_SHIFT) |
  890. (1 << CSI_SENS_CONF_DATA_POL_SHIFT) |
  891. (1 << CSI_SENS_CONF_PIX_CLK_POL_SHIFT) |
  892. (3 << CSI_SENS_CONF_DATA_FMT_SHIFT) |
  893. (3 << CSI_SENS_CONF_DATA_WIDTH_SHIFT));
  894. /* TODO: Support RGB and YUV formats */
  895. /* This has been set in mx3_camera_activate(), but we clear it above */
  896. sens_conf |= CSI_SENS_CONF_DATA_FMT_BAYER;
  897. if (common_flags & SOCAM_PCLK_SAMPLE_FALLING)
  898. sens_conf |= 1 << CSI_SENS_CONF_PIX_CLK_POL_SHIFT;
  899. if (common_flags & SOCAM_HSYNC_ACTIVE_LOW)
  900. sens_conf |= 1 << CSI_SENS_CONF_HSYNC_POL_SHIFT;
  901. if (common_flags & SOCAM_VSYNC_ACTIVE_LOW)
  902. sens_conf |= 1 << CSI_SENS_CONF_VSYNC_POL_SHIFT;
  903. if (common_flags & SOCAM_DATA_ACTIVE_LOW)
  904. sens_conf |= 1 << CSI_SENS_CONF_DATA_POL_SHIFT;
  905. /* Just do what we're asked to do */
  906. switch (xlate->host_fmt->depth) {
  907. case 4:
  908. dw = 0 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
  909. break;
  910. case 8:
  911. dw = 1 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
  912. break;
  913. case 10:
  914. dw = 2 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
  915. break;
  916. default:
  917. /*
  918. * Actually it can only be 15 now, default is just to silence
  919. * compiler warnings
  920. */
  921. case 15:
  922. dw = 3 << CSI_SENS_CONF_DATA_WIDTH_SHIFT;
  923. }
  924. csi_reg_write(mx3_cam, sens_conf | dw, CSI_SENS_CONF);
  925. dev_dbg(dev, "Set SENS_CONF to %x\n", sens_conf | dw);
  926. return 0;
  927. }
  928. static struct soc_camera_host_ops mx3_soc_camera_host_ops = {
  929. .owner = THIS_MODULE,
  930. .add = mx3_camera_add_device,
  931. .remove = mx3_camera_remove_device,
  932. .set_crop = mx3_camera_set_crop,
  933. .set_fmt = mx3_camera_set_fmt,
  934. .try_fmt = mx3_camera_try_fmt,
  935. .get_formats = mx3_camera_get_formats,
  936. .init_videobuf = mx3_camera_init_videobuf,
  937. .reqbufs = mx3_camera_reqbufs,
  938. .poll = mx3_camera_poll,
  939. .querycap = mx3_camera_querycap,
  940. .set_bus_param = mx3_camera_set_bus_param,
  941. };
  942. static int __devinit mx3_camera_probe(struct platform_device *pdev)
  943. {
  944. struct mx3_camera_dev *mx3_cam;
  945. struct resource *res;
  946. void __iomem *base;
  947. int err = 0;
  948. struct soc_camera_host *soc_host;
  949. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  950. if (!res) {
  951. err = -ENODEV;
  952. goto egetres;
  953. }
  954. mx3_cam = vmalloc(sizeof(*mx3_cam));
  955. if (!mx3_cam) {
  956. dev_err(&pdev->dev, "Could not allocate mx3 camera object\n");
  957. err = -ENOMEM;
  958. goto ealloc;
  959. }
  960. memset(mx3_cam, 0, sizeof(*mx3_cam));
  961. mx3_cam->clk = clk_get(&pdev->dev, NULL);
  962. if (IS_ERR(mx3_cam->clk)) {
  963. err = PTR_ERR(mx3_cam->clk);
  964. goto eclkget;
  965. }
  966. mx3_cam->pdata = pdev->dev.platform_data;
  967. mx3_cam->platform_flags = mx3_cam->pdata->flags;
  968. if (!(mx3_cam->platform_flags & (MX3_CAMERA_DATAWIDTH_4 |
  969. MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10 |
  970. MX3_CAMERA_DATAWIDTH_15))) {
  971. /*
  972. * Platform hasn't set available data widths. This is bad.
  973. * Warn and use a default.
  974. */
  975. dev_warn(&pdev->dev, "WARNING! Platform hasn't set available "
  976. "data widths, using default 8 bit\n");
  977. mx3_cam->platform_flags |= MX3_CAMERA_DATAWIDTH_8;
  978. }
  979. mx3_cam->mclk = mx3_cam->pdata->mclk_10khz * 10000;
  980. if (!mx3_cam->mclk) {
  981. dev_warn(&pdev->dev,
  982. "mclk_10khz == 0! Please, fix your platform data. "
  983. "Using default 20MHz\n");
  984. mx3_cam->mclk = 20000000;
  985. }
  986. /* list of video-buffers */
  987. INIT_LIST_HEAD(&mx3_cam->capture);
  988. spin_lock_init(&mx3_cam->lock);
  989. base = ioremap(res->start, resource_size(res));
  990. if (!base) {
  991. pr_err("Couldn't map %x@%x\n", resource_size(res), res->start);
  992. err = -ENOMEM;
  993. goto eioremap;
  994. }
  995. mx3_cam->base = base;
  996. soc_host = &mx3_cam->soc_host;
  997. soc_host->drv_name = MX3_CAM_DRV_NAME;
  998. soc_host->ops = &mx3_soc_camera_host_ops;
  999. soc_host->priv = mx3_cam;
  1000. soc_host->v4l2_dev.dev = &pdev->dev;
  1001. soc_host->nr = pdev->id;
  1002. err = soc_camera_host_register(soc_host);
  1003. if (err)
  1004. goto ecamhostreg;
  1005. /* IDMAC interface */
  1006. dmaengine_get();
  1007. return 0;
  1008. ecamhostreg:
  1009. iounmap(base);
  1010. eioremap:
  1011. clk_put(mx3_cam->clk);
  1012. eclkget:
  1013. vfree(mx3_cam);
  1014. ealloc:
  1015. egetres:
  1016. return err;
  1017. }
  1018. static int __devexit mx3_camera_remove(struct platform_device *pdev)
  1019. {
  1020. struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
  1021. struct mx3_camera_dev *mx3_cam = container_of(soc_host,
  1022. struct mx3_camera_dev, soc_host);
  1023. clk_put(mx3_cam->clk);
  1024. soc_camera_host_unregister(soc_host);
  1025. iounmap(mx3_cam->base);
  1026. /*
  1027. * The channel has either not been allocated,
  1028. * or should have been released
  1029. */
  1030. if (WARN_ON(mx3_cam->idmac_channel[0]))
  1031. dma_release_channel(&mx3_cam->idmac_channel[0]->dma_chan);
  1032. vfree(mx3_cam);
  1033. dmaengine_put();
  1034. dev_info(&pdev->dev, "i.MX3x Camera driver unloaded\n");
  1035. return 0;
  1036. }
  1037. static struct platform_driver mx3_camera_driver = {
  1038. .driver = {
  1039. .name = MX3_CAM_DRV_NAME,
  1040. },
  1041. .probe = mx3_camera_probe,
  1042. .remove = __devexit_p(mx3_camera_remove),
  1043. };
  1044. static int __init mx3_camera_init(void)
  1045. {
  1046. return platform_driver_register(&mx3_camera_driver);
  1047. }
  1048. static void __exit mx3_camera_exit(void)
  1049. {
  1050. platform_driver_unregister(&mx3_camera_driver);
  1051. }
  1052. module_init(mx3_camera_init);
  1053. module_exit(mx3_camera_exit);
  1054. MODULE_DESCRIPTION("i.MX3x SoC Camera Host driver");
  1055. MODULE_AUTHOR("Guennadi Liakhovetski <lg@denx.de>");
  1056. MODULE_LICENSE("GPL v2");
  1057. MODULE_ALIAS("platform:" MX3_CAM_DRV_NAME);