Kconfig 22 KB

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  1. #
  2. # For a description of the syntax of this configuration file,
  3. # see Documentation/kbuild/kconfig-language.txt.
  4. #
  5. mainmenu "Blackfin Kernel Configuration"
  6. config MMU
  7. bool
  8. default n
  9. config FPU
  10. bool
  11. default n
  12. config RWSEM_GENERIC_SPINLOCK
  13. bool
  14. default y
  15. config RWSEM_XCHGADD_ALGORITHM
  16. bool
  17. default n
  18. config BLACKFIN
  19. bool
  20. default y
  21. select HAVE_IDE
  22. select HAVE_OPROFILE
  23. config ZONE_DMA
  24. bool
  25. default y
  26. config GENERIC_FIND_NEXT_BIT
  27. bool
  28. default y
  29. config GENERIC_HWEIGHT
  30. bool
  31. default y
  32. config GENERIC_HARDIRQS
  33. bool
  34. default y
  35. config GENERIC_IRQ_PROBE
  36. bool
  37. default y
  38. config GENERIC_GPIO
  39. bool
  40. default y
  41. config FORCE_MAX_ZONEORDER
  42. int
  43. default "14"
  44. config GENERIC_CALIBRATE_DELAY
  45. bool
  46. default y
  47. config HARDWARE_PM
  48. def_bool y
  49. depends on OPROFILE
  50. source "init/Kconfig"
  51. source "kernel/Kconfig.preempt"
  52. menu "Blackfin Processor Options"
  53. comment "Processor and Board Settings"
  54. choice
  55. prompt "CPU"
  56. default BF533
  57. config BF522
  58. bool "BF522"
  59. help
  60. BF522 Processor Support.
  61. config BF523
  62. bool "BF523"
  63. help
  64. BF523 Processor Support.
  65. config BF524
  66. bool "BF524"
  67. help
  68. BF524 Processor Support.
  69. config BF525
  70. bool "BF525"
  71. help
  72. BF525 Processor Support.
  73. config BF526
  74. bool "BF526"
  75. help
  76. BF526 Processor Support.
  77. config BF527
  78. bool "BF527"
  79. help
  80. BF527 Processor Support.
  81. config BF531
  82. bool "BF531"
  83. help
  84. BF531 Processor Support.
  85. config BF532
  86. bool "BF532"
  87. help
  88. BF532 Processor Support.
  89. config BF533
  90. bool "BF533"
  91. help
  92. BF533 Processor Support.
  93. config BF534
  94. bool "BF534"
  95. help
  96. BF534 Processor Support.
  97. config BF536
  98. bool "BF536"
  99. help
  100. BF536 Processor Support.
  101. config BF537
  102. bool "BF537"
  103. help
  104. BF537 Processor Support.
  105. config BF542
  106. bool "BF542"
  107. help
  108. BF542 Processor Support.
  109. config BF544
  110. bool "BF544"
  111. help
  112. BF544 Processor Support.
  113. config BF547
  114. bool "BF547"
  115. help
  116. BF547 Processor Support.
  117. config BF548
  118. bool "BF548"
  119. help
  120. BF548 Processor Support.
  121. config BF549
  122. bool "BF549"
  123. help
  124. BF549 Processor Support.
  125. config BF561
  126. bool "BF561"
  127. help
  128. Not Supported Yet - Work in progress - BF561 Processor Support.
  129. endchoice
  130. choice
  131. prompt "Silicon Rev"
  132. default BF_REV_0_1 if BF527
  133. default BF_REV_0_2 if BF537
  134. default BF_REV_0_3 if BF533
  135. default BF_REV_0_0 if BF549
  136. config BF_REV_0_0
  137. bool "0.0"
  138. depends on (BF52x || BF54x)
  139. config BF_REV_0_1
  140. bool "0.1"
  141. depends on (BF52x || BF54x)
  142. config BF_REV_0_2
  143. bool "0.2"
  144. depends on (BF537 || BF536 || BF534)
  145. config BF_REV_0_3
  146. bool "0.3"
  147. depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
  148. config BF_REV_0_4
  149. bool "0.4"
  150. depends on (BF561 || BF533 || BF532 || BF531)
  151. config BF_REV_0_5
  152. bool "0.5"
  153. depends on (BF561 || BF533 || BF532 || BF531)
  154. config BF_REV_ANY
  155. bool "any"
  156. config BF_REV_NONE
  157. bool "none"
  158. endchoice
  159. config BF52x
  160. bool
  161. depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
  162. default y
  163. config BF53x
  164. bool
  165. depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
  166. default y
  167. config BF54x
  168. bool
  169. depends on (BF542 || BF544 || BF547 || BF548 || BF549)
  170. default y
  171. config MEM_GENERIC_BOARD
  172. bool
  173. depends on GENERIC_BOARD
  174. default y
  175. config MEM_MT48LC64M4A2FB_7E
  176. bool
  177. depends on (BFIN533_STAMP)
  178. default y
  179. config MEM_MT48LC16M16A2TG_75
  180. bool
  181. depends on (BFIN533_EZKIT || BFIN561_EZKIT \
  182. || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
  183. || H8606_HVSISTEMAS)
  184. default y
  185. config MEM_MT48LC32M8A2_75
  186. bool
  187. depends on (BFIN537_STAMP || PNAV10)
  188. default y
  189. config MEM_MT48LC8M32B2B5_7
  190. bool
  191. depends on (BFIN561_BLUETECHNIX_CM)
  192. default y
  193. config MEM_MT48LC32M16A2TG_75
  194. bool
  195. depends on (BFIN527_EZKIT || BFIN532_IP0X)
  196. default y
  197. source "arch/blackfin/mach-bf527/Kconfig"
  198. source "arch/blackfin/mach-bf533/Kconfig"
  199. source "arch/blackfin/mach-bf561/Kconfig"
  200. source "arch/blackfin/mach-bf537/Kconfig"
  201. source "arch/blackfin/mach-bf548/Kconfig"
  202. menu "Board customizations"
  203. config CMDLINE_BOOL
  204. bool "Default bootloader kernel arguments"
  205. config CMDLINE
  206. string "Initial kernel command string"
  207. depends on CMDLINE_BOOL
  208. default "console=ttyBF0,57600"
  209. help
  210. If you don't have a boot loader capable of passing a command line string
  211. to the kernel, you may specify one here. As a minimum, you should specify
  212. the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
  213. comment "Clock/PLL Setup"
  214. config CLKIN_HZ
  215. int "Crystal Frequency in Hz"
  216. default "11059200" if BFIN533_STAMP
  217. default "27000000" if BFIN533_EZKIT
  218. default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS)
  219. default "30000000" if BFIN561_EZKIT
  220. default "24576000" if PNAV10
  221. default "10000000" if BFIN532_IP0X
  222. help
  223. The frequency of CLKIN crystal oscillator on the board in Hz.
  224. config BFIN_KERNEL_CLOCK
  225. bool "Re-program Clocks while Kernel boots?"
  226. default n
  227. help
  228. This option decides if kernel clocks are re-programed from the
  229. bootloader settings. If the clocks are not set, the SDRAM settings
  230. are also not changed, and the Bootloader does 100% of the hardware
  231. configuration.
  232. config MEM_ADD_WIDTH
  233. int "Memory Address Width"
  234. depends on BFIN_KERNEL_CLOCK
  235. depends on (!BF54x)
  236. default 9 if BFIN533_EZKIT
  237. default 9 if BFIN561_EZKIT
  238. default 9 if H8606_HVSISTEMAS
  239. default 10 if BFIN527_EZKIT
  240. default 10 if BFIN537_STAMP
  241. default 11 if BFIN533_STAMP
  242. default 10 if PNAV10
  243. default 10 if BFIN532_IP0X
  244. config PLL_BYPASS
  245. bool "Bypass PLL"
  246. depends on BFIN_KERNEL_CLOCK
  247. default n
  248. config CLKIN_HALF
  249. bool "Half Clock In"
  250. depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
  251. default n
  252. help
  253. If this is set the clock will be divided by 2, before it goes to the PLL.
  254. config VCO_MULT
  255. int "VCO Multiplier"
  256. depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
  257. range 1 64
  258. default "22" if BFIN533_EZKIT
  259. default "45" if BFIN533_STAMP
  260. default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM)
  261. default "22" if BFIN533_BLUETECHNIX_CM
  262. default "20" if BFIN537_BLUETECHNIX_CM
  263. default "20" if BFIN561_BLUETECHNIX_CM
  264. default "20" if BFIN561_EZKIT
  265. default "16" if H8606_HVSISTEMAS
  266. help
  267. This controls the frequency of the on-chip PLL. This can be between 1 and 64.
  268. PLL Frequency = (Crystal Frequency) * (this setting)
  269. choice
  270. prompt "Core Clock Divider"
  271. depends on BFIN_KERNEL_CLOCK
  272. default CCLK_DIV_1
  273. help
  274. This sets the frequency of the core. It can be 1, 2, 4 or 8
  275. Core Frequency = (PLL frequency) / (this setting)
  276. config CCLK_DIV_1
  277. bool "1"
  278. config CCLK_DIV_2
  279. bool "2"
  280. config CCLK_DIV_4
  281. bool "4"
  282. config CCLK_DIV_8
  283. bool "8"
  284. endchoice
  285. config SCLK_DIV
  286. int "System Clock Divider"
  287. depends on BFIN_KERNEL_CLOCK
  288. range 1 15
  289. default 5 if BFIN533_EZKIT
  290. default 5 if BFIN533_STAMP
  291. default 4 if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM)
  292. default 5 if BFIN533_BLUETECHNIX_CM
  293. default 4 if BFIN537_BLUETECHNIX_CM
  294. default 4 if BFIN561_BLUETECHNIX_CM
  295. default 5 if BFIN561_EZKIT
  296. default 3 if H8606_HVSISTEMAS
  297. help
  298. This sets the frequency of the system clock (including SDRAM or DDR).
  299. This can be between 1 and 15
  300. System Clock = (PLL frequency) / (this setting)
  301. #
  302. # Max & Min Speeds for various Chips
  303. #
  304. config MAX_VCO_HZ
  305. int
  306. default 600000000 if BF522
  307. default 400000000 if BF523
  308. default 400000000 if BF524
  309. default 600000000 if BF525
  310. default 400000000 if BF526
  311. default 600000000 if BF527
  312. default 400000000 if BF531
  313. default 400000000 if BF532
  314. default 750000000 if BF533
  315. default 500000000 if BF534
  316. default 400000000 if BF536
  317. default 600000000 if BF537
  318. default 533333333 if BF538
  319. default 533333333 if BF539
  320. default 600000000 if BF542
  321. default 533333333 if BF544
  322. default 600000000 if BF547
  323. default 600000000 if BF548
  324. default 533333333 if BF549
  325. default 600000000 if BF561
  326. config MIN_VCO_HZ
  327. int
  328. default 50000000
  329. config MAX_SCLK_HZ
  330. int
  331. default 133333333
  332. config MIN_SCLK_HZ
  333. int
  334. default 27000000
  335. comment "Kernel Timer/Scheduler"
  336. source kernel/Kconfig.hz
  337. config GENERIC_TIME
  338. bool "Generic time"
  339. default y
  340. config GENERIC_CLOCKEVENTS
  341. bool "Generic clock events"
  342. depends on GENERIC_TIME
  343. default y
  344. config CYCLES_CLOCKSOURCE
  345. bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)"
  346. depends on EXPERIMENTAL
  347. depends on GENERIC_CLOCKEVENTS
  348. depends on !BFIN_SCRATCH_REG_CYCLES
  349. default n
  350. help
  351. If you say Y here, you will enable support for using the 'cycles'
  352. registers as a clock source. Doing so means you will be unable to
  353. safely write to the 'cycles' register during runtime. You will
  354. still be able to read it (such as for performance monitoring), but
  355. writing the registers will most likely crash the kernel.
  356. source kernel/time/Kconfig
  357. comment "Memory Setup"
  358. config MEM_SIZE
  359. int "SDRAM Memory Size in MBytes"
  360. default 32 if BFIN533_EZKIT
  361. default 64 if BFIN527_EZKIT
  362. default 64 if BFIN537_STAMP
  363. default 64 if BFIN548_EZKIT
  364. default 64 if BFIN561_EZKIT
  365. default 128 if BFIN533_STAMP
  366. default 64 if PNAV10
  367. default 32 if H8606_HVSISTEMAS
  368. default 64 if BFIN548_BLUETECHNIX_CM
  369. default 64 if BFIN532_IP0X
  370. choice
  371. prompt "DDR SDRAM Chip Type"
  372. depends on (BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM)
  373. default MEM_MT46V32M16_5B
  374. config MEM_MT46V32M16_6T
  375. bool "MT46V32M16_6T"
  376. config MEM_MT46V32M16_5B
  377. bool "MT46V32M16_5B"
  378. endchoice
  379. config ENET_FLASH_PIN
  380. int "PF port/pin used for flash and ethernet sharing"
  381. depends on (BFIN533_STAMP)
  382. default 0
  383. help
  384. PF port/pin used for flash and ethernet sharing to allow other PF
  385. pins to be used on other platforms without having to touch common
  386. code.
  387. For example: PF0 --> 0,PF1 --> 1,PF2 --> 2, etc.
  388. config BOOT_LOAD
  389. hex "Kernel load address for booting"
  390. default "0x1000"
  391. range 0x1000 0x20000000
  392. help
  393. This option allows you to set the load address of the kernel.
  394. This can be useful if you are on a board which has a small amount
  395. of memory or you wish to reserve some memory at the beginning of
  396. the address space.
  397. Note that you need to keep this value above 4k (0x1000) as this
  398. memory region is used to capture NULL pointer references as well
  399. as some core kernel functions.
  400. choice
  401. prompt "Blackfin Exception Scratch Register"
  402. default BFIN_SCRATCH_REG_RETN
  403. help
  404. Select the resource to reserve for the Exception handler:
  405. - RETN: Non-Maskable Interrupt (NMI)
  406. - RETE: Exception Return (JTAG/ICE)
  407. - CYCLES: Performance counter
  408. If you are unsure, please select "RETN".
  409. config BFIN_SCRATCH_REG_RETN
  410. bool "RETN"
  411. help
  412. Use the RETN register in the Blackfin exception handler
  413. as a stack scratch register. This means you cannot
  414. safely use NMI on the Blackfin while running Linux, but
  415. you can debug the system with a JTAG ICE and use the
  416. CYCLES performance registers.
  417. If you are unsure, please select "RETN".
  418. config BFIN_SCRATCH_REG_RETE
  419. bool "RETE"
  420. help
  421. Use the RETE register in the Blackfin exception handler
  422. as a stack scratch register. This means you cannot
  423. safely use a JTAG ICE while debugging a Blackfin board,
  424. but you can safely use the CYCLES performance registers
  425. and the NMI.
  426. If you are unsure, please select "RETN".
  427. config BFIN_SCRATCH_REG_CYCLES
  428. bool "CYCLES"
  429. help
  430. Use the CYCLES register in the Blackfin exception handler
  431. as a stack scratch register. This means you cannot
  432. safely use the CYCLES performance registers on a Blackfin
  433. board at anytime, but you can debug the system with a JTAG
  434. ICE and use the NMI.
  435. If you are unsure, please select "RETN".
  436. endchoice
  437. endmenu
  438. menu "Blackfin Kernel Optimizations"
  439. comment "Memory Optimizations"
  440. config I_ENTRY_L1
  441. bool "Locate interrupt entry code in L1 Memory"
  442. default y
  443. help
  444. If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
  445. into L1 instruction memory. (less latency)
  446. config EXCPT_IRQ_SYSC_L1
  447. bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
  448. default y
  449. help
  450. If enabled, the entire ASM lowlevel exception and interrupt entry code
  451. (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
  452. (less latency)
  453. config DO_IRQ_L1
  454. bool "Locate frequently called do_irq dispatcher function in L1 Memory"
  455. default y
  456. help
  457. If enabled, the frequently called do_irq dispatcher function is linked
  458. into L1 instruction memory. (less latency)
  459. config CORE_TIMER_IRQ_L1
  460. bool "Locate frequently called timer_interrupt() function in L1 Memory"
  461. default y
  462. help
  463. If enabled, the frequently called timer_interrupt() function is linked
  464. into L1 instruction memory. (less latency)
  465. config IDLE_L1
  466. bool "Locate frequently idle function in L1 Memory"
  467. default y
  468. help
  469. If enabled, the frequently called idle function is linked
  470. into L1 instruction memory. (less latency)
  471. config SCHEDULE_L1
  472. bool "Locate kernel schedule function in L1 Memory"
  473. default y
  474. help
  475. If enabled, the frequently called kernel schedule is linked
  476. into L1 instruction memory. (less latency)
  477. config ARITHMETIC_OPS_L1
  478. bool "Locate kernel owned arithmetic functions in L1 Memory"
  479. default y
  480. help
  481. If enabled, arithmetic functions are linked
  482. into L1 instruction memory. (less latency)
  483. config ACCESS_OK_L1
  484. bool "Locate access_ok function in L1 Memory"
  485. default y
  486. help
  487. If enabled, the access_ok function is linked
  488. into L1 instruction memory. (less latency)
  489. config MEMSET_L1
  490. bool "Locate memset function in L1 Memory"
  491. default y
  492. help
  493. If enabled, the memset function is linked
  494. into L1 instruction memory. (less latency)
  495. config MEMCPY_L1
  496. bool "Locate memcpy function in L1 Memory"
  497. default y
  498. help
  499. If enabled, the memcpy function is linked
  500. into L1 instruction memory. (less latency)
  501. config SYS_BFIN_SPINLOCK_L1
  502. bool "Locate sys_bfin_spinlock function in L1 Memory"
  503. default y
  504. help
  505. If enabled, sys_bfin_spinlock function is linked
  506. into L1 instruction memory. (less latency)
  507. config IP_CHECKSUM_L1
  508. bool "Locate IP Checksum function in L1 Memory"
  509. default n
  510. help
  511. If enabled, the IP Checksum function is linked
  512. into L1 instruction memory. (less latency)
  513. config CACHELINE_ALIGNED_L1
  514. bool "Locate cacheline_aligned data to L1 Data Memory"
  515. default y if !BF54x
  516. default n if BF54x
  517. depends on !BF531
  518. help
  519. If enabled, cacheline_anligned data is linked
  520. into L1 data memory. (less latency)
  521. config SYSCALL_TAB_L1
  522. bool "Locate Syscall Table L1 Data Memory"
  523. default n
  524. depends on !BF531
  525. help
  526. If enabled, the Syscall LUT is linked
  527. into L1 data memory. (less latency)
  528. config CPLB_SWITCH_TAB_L1
  529. bool "Locate CPLB Switch Tables L1 Data Memory"
  530. default n
  531. depends on !BF531
  532. help
  533. If enabled, the CPLB Switch Tables are linked
  534. into L1 data memory. (less latency)
  535. endmenu
  536. choice
  537. prompt "Kernel executes from"
  538. help
  539. Choose the memory type that the kernel will be running in.
  540. config RAMKERNEL
  541. bool "RAM"
  542. help
  543. The kernel will be resident in RAM when running.
  544. config ROMKERNEL
  545. bool "ROM"
  546. help
  547. The kernel will be resident in FLASH/ROM when running.
  548. endchoice
  549. source "mm/Kconfig"
  550. config BFIN_GPTIMERS
  551. tristate "Enable Blackfin General Purpose Timers API"
  552. default n
  553. help
  554. Enable support for the General Purpose Timers API. If you
  555. are unsure, say N.
  556. To compile this driver as a module, choose M here: the module
  557. will be called gptimers.ko.
  558. config BFIN_DMA_5XX
  559. bool "Enable DMA Support"
  560. depends on (BF52x || BF53x || BF561 || BF54x)
  561. default y
  562. help
  563. DMA driver for BF5xx.
  564. choice
  565. prompt "Uncached SDRAM region"
  566. default DMA_UNCACHED_1M
  567. depends on BFIN_DMA_5XX
  568. config DMA_UNCACHED_2M
  569. bool "Enable 2M DMA region"
  570. config DMA_UNCACHED_1M
  571. bool "Enable 1M DMA region"
  572. config DMA_UNCACHED_NONE
  573. bool "Disable DMA region"
  574. endchoice
  575. comment "Cache Support"
  576. config BFIN_ICACHE
  577. bool "Enable ICACHE"
  578. config BFIN_DCACHE
  579. bool "Enable DCACHE"
  580. config BFIN_DCACHE_BANKA
  581. bool "Enable only 16k BankA DCACHE - BankB is SRAM"
  582. depends on BFIN_DCACHE && !BF531
  583. default n
  584. config BFIN_ICACHE_LOCK
  585. bool "Enable Instruction Cache Locking"
  586. choice
  587. prompt "Policy"
  588. depends on BFIN_DCACHE
  589. default BFIN_WB
  590. config BFIN_WB
  591. bool "Write back"
  592. help
  593. Write Back Policy:
  594. Cached data will be written back to SDRAM only when needed.
  595. This can give a nice increase in performance, but beware of
  596. broken drivers that do not properly invalidate/flush their
  597. cache.
  598. Write Through Policy:
  599. Cached data will always be written back to SDRAM when the
  600. cache is updated. This is a completely safe setting, but
  601. performance is worse than Write Back.
  602. If you are unsure of the options and you want to be safe,
  603. then go with Write Through.
  604. config BFIN_WT
  605. bool "Write through"
  606. help
  607. Write Back Policy:
  608. Cached data will be written back to SDRAM only when needed.
  609. This can give a nice increase in performance, but beware of
  610. broken drivers that do not properly invalidate/flush their
  611. cache.
  612. Write Through Policy:
  613. Cached data will always be written back to SDRAM when the
  614. cache is updated. This is a completely safe setting, but
  615. performance is worse than Write Back.
  616. If you are unsure of the options and you want to be safe,
  617. then go with Write Through.
  618. endchoice
  619. config L1_MAX_PIECE
  620. int "Set the max L1 SRAM pieces"
  621. default 16
  622. help
  623. Set the max memory pieces for the L1 SRAM allocation algorithm.
  624. Min value is 16. Max value is 1024.
  625. config MPU
  626. bool "Enable the memory protection unit (EXPERIMENTAL)"
  627. default n
  628. help
  629. Use the processor's MPU to protect applications from accessing
  630. memory they do not own. This comes at a performance penalty
  631. and is recommended only for debugging.
  632. comment "Asynchonous Memory Configuration"
  633. menu "EBIU_AMGCTL Global Control"
  634. config C_AMCKEN
  635. bool "Enable CLKOUT"
  636. default y
  637. config C_CDPRIO
  638. bool "DMA has priority over core for ext. accesses"
  639. default n
  640. config C_B0PEN
  641. depends on BF561
  642. bool "Bank 0 16 bit packing enable"
  643. default y
  644. config C_B1PEN
  645. depends on BF561
  646. bool "Bank 1 16 bit packing enable"
  647. default y
  648. config C_B2PEN
  649. depends on BF561
  650. bool "Bank 2 16 bit packing enable"
  651. default y
  652. config C_B3PEN
  653. depends on BF561
  654. bool "Bank 3 16 bit packing enable"
  655. default n
  656. choice
  657. prompt"Enable Asynchonous Memory Banks"
  658. default C_AMBEN_ALL
  659. config C_AMBEN
  660. bool "Disable All Banks"
  661. config C_AMBEN_B0
  662. bool "Enable Bank 0"
  663. config C_AMBEN_B0_B1
  664. bool "Enable Bank 0 & 1"
  665. config C_AMBEN_B0_B1_B2
  666. bool "Enable Bank 0 & 1 & 2"
  667. config C_AMBEN_ALL
  668. bool "Enable All Banks"
  669. endchoice
  670. endmenu
  671. menu "EBIU_AMBCTL Control"
  672. config BANK_0
  673. hex "Bank 0"
  674. default 0x7BB0
  675. config BANK_1
  676. hex "Bank 1"
  677. default 0x7BB0
  678. config BANK_2
  679. hex "Bank 2"
  680. default 0x7BB0
  681. config BANK_3
  682. hex "Bank 3"
  683. default 0x99B3
  684. endmenu
  685. config EBIU_MBSCTLVAL
  686. hex "EBIU Bank Select Control Register"
  687. depends on BF54x
  688. default 0
  689. config EBIU_MODEVAL
  690. hex "Flash Memory Mode Control Register"
  691. depends on BF54x
  692. default 1
  693. config EBIU_FCTLVAL
  694. hex "Flash Memory Bank Control Register"
  695. depends on BF54x
  696. default 6
  697. endmenu
  698. #############################################################################
  699. menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
  700. config PCI
  701. bool "PCI support"
  702. help
  703. Support for PCI bus.
  704. source "drivers/pci/Kconfig"
  705. config HOTPLUG
  706. bool "Support for hot-pluggable device"
  707. help
  708. Say Y here if you want to plug devices into your computer while
  709. the system is running, and be able to use them quickly. In many
  710. cases, the devices can likewise be unplugged at any time too.
  711. One well known example of this is PCMCIA- or PC-cards, credit-card
  712. size devices such as network cards, modems or hard drives which are
  713. plugged into slots found on all modern laptop computers. Another
  714. example, used on modern desktops as well as laptops, is USB.
  715. Enable HOTPLUG and KMOD, and build a modular kernel. Get agent
  716. software (at <http://linux-hotplug.sourceforge.net/>) and install it.
  717. Then your kernel will automatically call out to a user mode "policy
  718. agent" (/sbin/hotplug) to load modules and set up software needed
  719. to use devices as you hotplug them.
  720. source "drivers/pcmcia/Kconfig"
  721. source "drivers/pci/hotplug/Kconfig"
  722. endmenu
  723. menu "Executable file formats"
  724. source "fs/Kconfig.binfmt"
  725. endmenu
  726. menu "Power management options"
  727. source "kernel/power/Kconfig"
  728. config ARCH_SUSPEND_POSSIBLE
  729. def_bool y
  730. depends on !SMP
  731. choice
  732. prompt "Default Power Saving Mode"
  733. depends on PM
  734. default PM_BFIN_SLEEP_DEEPER
  735. config PM_BFIN_SLEEP_DEEPER
  736. bool "Sleep Deeper"
  737. help
  738. Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
  739. power dissipation by disabling the clock to the processor core (CCLK).
  740. Furthermore, Standby sets the internal power supply voltage (VDDINT)
  741. to 0.85 V to provide the greatest power savings, while preserving the
  742. processor state.
  743. The PLL and system clock (SCLK) continue to operate at a very low
  744. frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
  745. the SDRAM is put into Self Refresh Mode. Typically an external event
  746. such as GPIO interrupt or RTC activity wakes up the processor.
  747. Various Peripherals such as UART, SPORT, PPI may not function as
  748. normal during Sleep Deeper, due to the reduced SCLK frequency.
  749. When in the sleep mode, system DMA access to L1 memory is not supported.
  750. config PM_BFIN_SLEEP
  751. bool "Sleep"
  752. help
  753. Sleep Mode (High Power Savings) - The sleep mode reduces power
  754. dissipation by disabling the clock to the processor core (CCLK).
  755. The PLL and system clock (SCLK), however, continue to operate in
  756. this mode. Typically an external event or RTC activity will wake
  757. up the processor. When in the sleep mode,
  758. system DMA access to L1 memory is not supported.
  759. endchoice
  760. config PM_WAKEUP_BY_GPIO
  761. bool "Cause Wakeup Event by GPIO"
  762. config PM_WAKEUP_GPIO_NUMBER
  763. int "Wakeup GPIO number"
  764. range 0 47
  765. depends on PM_WAKEUP_BY_GPIO
  766. default 2 if BFIN537_STAMP
  767. choice
  768. prompt "GPIO Polarity"
  769. depends on PM_WAKEUP_BY_GPIO
  770. default PM_WAKEUP_GPIO_POLAR_H
  771. config PM_WAKEUP_GPIO_POLAR_H
  772. bool "Active High"
  773. config PM_WAKEUP_GPIO_POLAR_L
  774. bool "Active Low"
  775. config PM_WAKEUP_GPIO_POLAR_EDGE_F
  776. bool "Falling EDGE"
  777. config PM_WAKEUP_GPIO_POLAR_EDGE_R
  778. bool "Rising EDGE"
  779. config PM_WAKEUP_GPIO_POLAR_EDGE_B
  780. bool "Both EDGE"
  781. endchoice
  782. endmenu
  783. if (BF537 || BF533 || BF54x)
  784. menu "CPU Frequency scaling"
  785. source "drivers/cpufreq/Kconfig"
  786. config CPU_FREQ
  787. bool
  788. default n
  789. help
  790. If you want to enable this option, you should select the
  791. DPMC driver from Character Devices.
  792. endmenu
  793. endif
  794. source "net/Kconfig"
  795. source "drivers/Kconfig"
  796. source "fs/Kconfig"
  797. source "arch/blackfin/Kconfig.debug"
  798. source "security/Kconfig"
  799. source "crypto/Kconfig"
  800. source "lib/Kconfig"