rtc-pl031.c 13 KB

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  1. /*
  2. * drivers/rtc/rtc-pl031.c
  3. *
  4. * Real Time Clock interface for ARM AMBA PrimeCell 031 RTC
  5. *
  6. * Author: Deepak Saxena <dsaxena@plexity.net>
  7. *
  8. * Copyright 2006 (c) MontaVista Software, Inc.
  9. *
  10. * Author: Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com>
  11. * Copyright 2010 (c) ST-Ericsson AB
  12. *
  13. * This program is free software; you can redistribute it and/or
  14. * modify it under the terms of the GNU General Public License
  15. * as published by the Free Software Foundation; either version
  16. * 2 of the License, or (at your option) any later version.
  17. */
  18. #include <linux/module.h>
  19. #include <linux/rtc.h>
  20. #include <linux/init.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/amba/bus.h>
  23. #include <linux/io.h>
  24. #include <linux/bcd.h>
  25. #include <linux/delay.h>
  26. #include <linux/version.h>
  27. #include <linux/slab.h>
  28. /*
  29. * Register definitions
  30. */
  31. #define RTC_DR 0x00 /* Data read register */
  32. #define RTC_MR 0x04 /* Match register */
  33. #define RTC_LR 0x08 /* Data load register */
  34. #define RTC_CR 0x0c /* Control register */
  35. #define RTC_IMSC 0x10 /* Interrupt mask and set register */
  36. #define RTC_RIS 0x14 /* Raw interrupt status register */
  37. #define RTC_MIS 0x18 /* Masked interrupt status register */
  38. #define RTC_ICR 0x1c /* Interrupt clear register */
  39. /* ST variants have additional timer functionality */
  40. #define RTC_TDR 0x20 /* Timer data read register */
  41. #define RTC_TLR 0x24 /* Timer data load register */
  42. #define RTC_TCR 0x28 /* Timer control register */
  43. #define RTC_YDR 0x30 /* Year data read register */
  44. #define RTC_YMR 0x34 /* Year match register */
  45. #define RTC_YLR 0x38 /* Year data load register */
  46. #define RTC_CR_CWEN (1 << 26) /* Clockwatch enable bit */
  47. #define RTC_TCR_EN (1 << 1) /* Periodic timer enable bit */
  48. /* Common bit definitions for Interrupt status and control registers */
  49. #define RTC_BIT_AI (1 << 0) /* Alarm interrupt bit */
  50. #define RTC_BIT_PI (1 << 1) /* Periodic interrupt bit. ST variants only. */
  51. /* Common bit definations for ST v2 for reading/writing time */
  52. #define RTC_SEC_SHIFT 0
  53. #define RTC_SEC_MASK (0x3F << RTC_SEC_SHIFT) /* Second [0-59] */
  54. #define RTC_MIN_SHIFT 6
  55. #define RTC_MIN_MASK (0x3F << RTC_MIN_SHIFT) /* Minute [0-59] */
  56. #define RTC_HOUR_SHIFT 12
  57. #define RTC_HOUR_MASK (0x1F << RTC_HOUR_SHIFT) /* Hour [0-23] */
  58. #define RTC_WDAY_SHIFT 17
  59. #define RTC_WDAY_MASK (0x7 << RTC_WDAY_SHIFT) /* Day of Week [1-7] 1=Sunday */
  60. #define RTC_MDAY_SHIFT 20
  61. #define RTC_MDAY_MASK (0x1F << RTC_MDAY_SHIFT) /* Day of Month [1-31] */
  62. #define RTC_MON_SHIFT 25
  63. #define RTC_MON_MASK (0xF << RTC_MON_SHIFT) /* Month [1-12] 1=January */
  64. #define RTC_TIMER_FREQ 32768
  65. struct pl031_local {
  66. struct rtc_device *rtc;
  67. void __iomem *base;
  68. u8 hw_designer;
  69. u8 hw_revision:4;
  70. };
  71. static int pl031_alarm_irq_enable(struct device *dev,
  72. unsigned int enabled)
  73. {
  74. struct pl031_local *ldata = dev_get_drvdata(dev);
  75. unsigned long imsc;
  76. /* Clear any pending alarm interrupts. */
  77. writel(RTC_BIT_AI, ldata->base + RTC_ICR);
  78. imsc = readl(ldata->base + RTC_IMSC);
  79. if (enabled == 1)
  80. writel(imsc | RTC_BIT_AI, ldata->base + RTC_IMSC);
  81. else
  82. writel(imsc & ~RTC_BIT_AI, ldata->base + RTC_IMSC);
  83. return 0;
  84. }
  85. /*
  86. * Convert Gregorian date to ST v2 RTC format.
  87. */
  88. static int pl031_stv2_tm_to_time(struct device *dev,
  89. struct rtc_time *tm, unsigned long *st_time,
  90. unsigned long *bcd_year)
  91. {
  92. int year = tm->tm_year + 1900;
  93. int wday = tm->tm_wday;
  94. /* wday masking is not working in hardware so wday must be valid */
  95. if (wday < -1 || wday > 6) {
  96. dev_err(dev, "invalid wday value %d\n", tm->tm_wday);
  97. return -EINVAL;
  98. } else if (wday == -1) {
  99. /* wday is not provided, calculate it here */
  100. unsigned long time;
  101. struct rtc_time calc_tm;
  102. rtc_tm_to_time(tm, &time);
  103. rtc_time_to_tm(time, &calc_tm);
  104. wday = calc_tm.tm_wday;
  105. }
  106. *bcd_year = (bin2bcd(year % 100) | bin2bcd(year / 100) << 8);
  107. *st_time = ((tm->tm_mon + 1) << RTC_MON_SHIFT)
  108. | (tm->tm_mday << RTC_MDAY_SHIFT)
  109. | ((wday + 1) << RTC_WDAY_SHIFT)
  110. | (tm->tm_hour << RTC_HOUR_SHIFT)
  111. | (tm->tm_min << RTC_MIN_SHIFT)
  112. | (tm->tm_sec << RTC_SEC_SHIFT);
  113. return 0;
  114. }
  115. /*
  116. * Convert ST v2 RTC format to Gregorian date.
  117. */
  118. static int pl031_stv2_time_to_tm(unsigned long st_time, unsigned long bcd_year,
  119. struct rtc_time *tm)
  120. {
  121. tm->tm_year = bcd2bin(bcd_year) + (bcd2bin(bcd_year >> 8) * 100);
  122. tm->tm_mon = ((st_time & RTC_MON_MASK) >> RTC_MON_SHIFT) - 1;
  123. tm->tm_mday = ((st_time & RTC_MDAY_MASK) >> RTC_MDAY_SHIFT);
  124. tm->tm_wday = ((st_time & RTC_WDAY_MASK) >> RTC_WDAY_SHIFT) - 1;
  125. tm->tm_hour = ((st_time & RTC_HOUR_MASK) >> RTC_HOUR_SHIFT);
  126. tm->tm_min = ((st_time & RTC_MIN_MASK) >> RTC_MIN_SHIFT);
  127. tm->tm_sec = ((st_time & RTC_SEC_MASK) >> RTC_SEC_SHIFT);
  128. tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year);
  129. tm->tm_year -= 1900;
  130. return 0;
  131. }
  132. static int pl031_stv2_read_time(struct device *dev, struct rtc_time *tm)
  133. {
  134. struct pl031_local *ldata = dev_get_drvdata(dev);
  135. pl031_stv2_time_to_tm(readl(ldata->base + RTC_DR),
  136. readl(ldata->base + RTC_YDR), tm);
  137. return 0;
  138. }
  139. static int pl031_stv2_set_time(struct device *dev, struct rtc_time *tm)
  140. {
  141. unsigned long time;
  142. unsigned long bcd_year;
  143. struct pl031_local *ldata = dev_get_drvdata(dev);
  144. int ret;
  145. ret = pl031_stv2_tm_to_time(dev, tm, &time, &bcd_year);
  146. if (ret == 0) {
  147. writel(bcd_year, ldata->base + RTC_YLR);
  148. writel(time, ldata->base + RTC_LR);
  149. }
  150. return ret;
  151. }
  152. static int pl031_stv2_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
  153. {
  154. struct pl031_local *ldata = dev_get_drvdata(dev);
  155. int ret;
  156. ret = pl031_stv2_time_to_tm(readl(ldata->base + RTC_MR),
  157. readl(ldata->base + RTC_YMR), &alarm->time);
  158. alarm->pending = readl(ldata->base + RTC_RIS) & RTC_BIT_AI;
  159. alarm->enabled = readl(ldata->base + RTC_IMSC) & RTC_BIT_AI;
  160. return ret;
  161. }
  162. static int pl031_stv2_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
  163. {
  164. struct pl031_local *ldata = dev_get_drvdata(dev);
  165. unsigned long time;
  166. unsigned long bcd_year;
  167. int ret;
  168. /* At the moment, we can only deal with non-wildcarded alarm times. */
  169. ret = rtc_valid_tm(&alarm->time);
  170. if (ret == 0) {
  171. ret = pl031_stv2_tm_to_time(dev, &alarm->time,
  172. &time, &bcd_year);
  173. if (ret == 0) {
  174. writel(bcd_year, ldata->base + RTC_YMR);
  175. writel(time, ldata->base + RTC_MR);
  176. pl031_alarm_irq_enable(dev, alarm->enabled);
  177. }
  178. }
  179. return ret;
  180. }
  181. static irqreturn_t pl031_interrupt(int irq, void *dev_id)
  182. {
  183. struct pl031_local *ldata = dev_id;
  184. unsigned long rtcmis;
  185. unsigned long events = 0;
  186. rtcmis = readl(ldata->base + RTC_MIS);
  187. if (rtcmis) {
  188. writel(rtcmis, ldata->base + RTC_ICR);
  189. if (rtcmis & RTC_BIT_AI)
  190. events |= (RTC_AF | RTC_IRQF);
  191. /* Timer interrupt is only available in ST variants */
  192. if ((rtcmis & RTC_BIT_PI) &&
  193. (ldata->hw_designer == AMBA_VENDOR_ST))
  194. events |= (RTC_PF | RTC_IRQF);
  195. rtc_update_irq(ldata->rtc, 1, events);
  196. return IRQ_HANDLED;
  197. }
  198. return IRQ_NONE;
  199. }
  200. static int pl031_read_time(struct device *dev, struct rtc_time *tm)
  201. {
  202. struct pl031_local *ldata = dev_get_drvdata(dev);
  203. rtc_time_to_tm(readl(ldata->base + RTC_DR), tm);
  204. return 0;
  205. }
  206. static int pl031_set_time(struct device *dev, struct rtc_time *tm)
  207. {
  208. unsigned long time;
  209. struct pl031_local *ldata = dev_get_drvdata(dev);
  210. int ret;
  211. ret = rtc_tm_to_time(tm, &time);
  212. if (ret == 0)
  213. writel(time, ldata->base + RTC_LR);
  214. return ret;
  215. }
  216. static int pl031_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
  217. {
  218. struct pl031_local *ldata = dev_get_drvdata(dev);
  219. rtc_time_to_tm(readl(ldata->base + RTC_MR), &alarm->time);
  220. alarm->pending = readl(ldata->base + RTC_RIS) & RTC_BIT_AI;
  221. alarm->enabled = readl(ldata->base + RTC_IMSC) & RTC_BIT_AI;
  222. return 0;
  223. }
  224. static int pl031_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
  225. {
  226. struct pl031_local *ldata = dev_get_drvdata(dev);
  227. unsigned long time;
  228. int ret;
  229. /* At the moment, we can only deal with non-wildcarded alarm times. */
  230. ret = rtc_valid_tm(&alarm->time);
  231. if (ret == 0) {
  232. ret = rtc_tm_to_time(&alarm->time, &time);
  233. if (ret == 0) {
  234. writel(time, ldata->base + RTC_MR);
  235. pl031_alarm_irq_enable(dev, alarm->enabled);
  236. }
  237. }
  238. return ret;
  239. }
  240. /* Periodic interrupt is only available in ST variants. */
  241. static int pl031_irq_set_state(struct device *dev, int enabled)
  242. {
  243. struct pl031_local *ldata = dev_get_drvdata(dev);
  244. if (enabled == 1) {
  245. /* Clear any pending timer interrupt. */
  246. writel(RTC_BIT_PI, ldata->base + RTC_ICR);
  247. writel(readl(ldata->base + RTC_IMSC) | RTC_BIT_PI,
  248. ldata->base + RTC_IMSC);
  249. /* Now start the timer */
  250. writel(readl(ldata->base + RTC_TCR) | RTC_TCR_EN,
  251. ldata->base + RTC_TCR);
  252. } else {
  253. writel(readl(ldata->base + RTC_IMSC) & (~RTC_BIT_PI),
  254. ldata->base + RTC_IMSC);
  255. /* Also stop the timer */
  256. writel(readl(ldata->base + RTC_TCR) & (~RTC_TCR_EN),
  257. ldata->base + RTC_TCR);
  258. }
  259. /* Wait at least 1 RTC32 clock cycle to ensure next access
  260. * to RTC_TCR will succeed.
  261. */
  262. udelay(40);
  263. return 0;
  264. }
  265. static int pl031_irq_set_freq(struct device *dev, int freq)
  266. {
  267. struct pl031_local *ldata = dev_get_drvdata(dev);
  268. /* Cant set timer if it is already enabled */
  269. if (readl(ldata->base + RTC_TCR) & RTC_TCR_EN) {
  270. dev_err(dev, "can't change frequency while timer enabled\n");
  271. return -EINVAL;
  272. }
  273. /* If self start bit in RTC_TCR is set timer will start here,
  274. * but we never set that bit. Instead we start the timer when
  275. * set_state is called with enabled == 1.
  276. */
  277. writel(RTC_TIMER_FREQ / freq, ldata->base + RTC_TLR);
  278. return 0;
  279. }
  280. static int pl031_remove(struct amba_device *adev)
  281. {
  282. struct pl031_local *ldata = dev_get_drvdata(&adev->dev);
  283. amba_set_drvdata(adev, NULL);
  284. free_irq(adev->irq[0], ldata->rtc);
  285. rtc_device_unregister(ldata->rtc);
  286. iounmap(ldata->base);
  287. kfree(ldata);
  288. amba_release_regions(adev);
  289. return 0;
  290. }
  291. static int pl031_probe(struct amba_device *adev, struct amba_id *id)
  292. {
  293. int ret;
  294. struct pl031_local *ldata;
  295. struct rtc_class_ops *ops = id->data;
  296. ret = amba_request_regions(adev, NULL);
  297. if (ret)
  298. goto err_req;
  299. ldata = kzalloc(sizeof(struct pl031_local), GFP_KERNEL);
  300. if (!ldata) {
  301. ret = -ENOMEM;
  302. goto out;
  303. }
  304. ldata->base = ioremap(adev->res.start, resource_size(&adev->res));
  305. if (!ldata->base) {
  306. ret = -ENOMEM;
  307. goto out_no_remap;
  308. }
  309. amba_set_drvdata(adev, ldata);
  310. ldata->hw_designer = amba_manf(adev);
  311. ldata->hw_revision = amba_rev(adev);
  312. dev_dbg(&adev->dev, "designer ID = 0x%02x\n", ldata->hw_designer);
  313. dev_dbg(&adev->dev, "revision = 0x%01x\n", ldata->hw_revision);
  314. /* Enable the clockwatch on ST Variants */
  315. if ((ldata->hw_designer == AMBA_VENDOR_ST) &&
  316. (ldata->hw_revision > 1))
  317. writel(readl(ldata->base + RTC_CR) | RTC_CR_CWEN,
  318. ldata->base + RTC_CR);
  319. ldata->rtc = rtc_device_register("pl031", &adev->dev, ops,
  320. THIS_MODULE);
  321. if (IS_ERR(ldata->rtc)) {
  322. ret = PTR_ERR(ldata->rtc);
  323. goto out_no_rtc;
  324. }
  325. if (request_irq(adev->irq[0], pl031_interrupt,
  326. IRQF_DISABLED | IRQF_SHARED, "rtc-pl031", ldata)) {
  327. ret = -EIO;
  328. goto out_no_irq;
  329. }
  330. return 0;
  331. out_no_irq:
  332. rtc_device_unregister(ldata->rtc);
  333. out_no_rtc:
  334. iounmap(ldata->base);
  335. amba_set_drvdata(adev, NULL);
  336. out_no_remap:
  337. kfree(ldata);
  338. out:
  339. amba_release_regions(adev);
  340. err_req:
  341. return ret;
  342. }
  343. /* Operations for the original ARM version */
  344. static struct rtc_class_ops arm_pl031_ops = {
  345. .read_time = pl031_read_time,
  346. .set_time = pl031_set_time,
  347. .read_alarm = pl031_read_alarm,
  348. .set_alarm = pl031_set_alarm,
  349. .alarm_irq_enable = pl031_alarm_irq_enable,
  350. };
  351. /* The First ST derivative */
  352. static struct rtc_class_ops stv1_pl031_ops = {
  353. .read_time = pl031_read_time,
  354. .set_time = pl031_set_time,
  355. .read_alarm = pl031_read_alarm,
  356. .set_alarm = pl031_set_alarm,
  357. .alarm_irq_enable = pl031_alarm_irq_enable,
  358. .irq_set_state = pl031_irq_set_state,
  359. .irq_set_freq = pl031_irq_set_freq,
  360. };
  361. /* And the second ST derivative */
  362. static struct rtc_class_ops stv2_pl031_ops = {
  363. .read_time = pl031_stv2_read_time,
  364. .set_time = pl031_stv2_set_time,
  365. .read_alarm = pl031_stv2_read_alarm,
  366. .set_alarm = pl031_stv2_set_alarm,
  367. .alarm_irq_enable = pl031_alarm_irq_enable,
  368. .irq_set_state = pl031_irq_set_state,
  369. .irq_set_freq = pl031_irq_set_freq,
  370. };
  371. static struct amba_id pl031_ids[] __initdata = {
  372. {
  373. .id = 0x00041031,
  374. .mask = 0x000fffff,
  375. .data = &arm_pl031_ops,
  376. },
  377. /* ST Micro variants */
  378. {
  379. .id = 0x00180031,
  380. .mask = 0x00ffffff,
  381. .data = &stv1_pl031_ops,
  382. },
  383. {
  384. .id = 0x00280031,
  385. .mask = 0x00ffffff,
  386. .data = &stv2_pl031_ops,
  387. },
  388. {0, 0},
  389. };
  390. static struct amba_driver pl031_driver = {
  391. .drv = {
  392. .name = "rtc-pl031",
  393. },
  394. .id_table = pl031_ids,
  395. .probe = pl031_probe,
  396. .remove = pl031_remove,
  397. };
  398. static int __init pl031_init(void)
  399. {
  400. return amba_driver_register(&pl031_driver);
  401. }
  402. static void __exit pl031_exit(void)
  403. {
  404. amba_driver_unregister(&pl031_driver);
  405. }
  406. module_init(pl031_init);
  407. module_exit(pl031_exit);
  408. MODULE_AUTHOR("Deepak Saxena <dsaxena@plexity.net");
  409. MODULE_DESCRIPTION("ARM AMBA PL031 RTC Driver");
  410. MODULE_LICENSE("GPL");