rtc-ds1307.c 27 KB

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  1. /*
  2. * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
  3. *
  4. * Copyright (C) 2005 James Chapman (ds1337 core)
  5. * Copyright (C) 2006 David Brownell
  6. * Copyright (C) 2009 Matthias Fuchs (rx8025 support)
  7. * Copyright (C) 2012 Bertrand Achard (nvram access fixes)
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/init.h>
  15. #include <linux/slab.h>
  16. #include <linux/i2c.h>
  17. #include <linux/string.h>
  18. #include <linux/rtc.h>
  19. #include <linux/bcd.h>
  20. #include <linux/rtc/ds1307.h>
  21. /*
  22. * We can't determine type by probing, but if we expect pre-Linux code
  23. * to have set the chip up as a clock (turning on the oscillator and
  24. * setting the date and time), Linux can ignore the non-clock features.
  25. * That's a natural job for a factory or repair bench.
  26. */
  27. enum ds_type {
  28. ds_1307,
  29. ds_1337,
  30. ds_1338,
  31. ds_1339,
  32. ds_1340,
  33. ds_1388,
  34. ds_3231,
  35. m41t00,
  36. mcp7941x,
  37. rx_8025,
  38. last_ds_type /* always last */
  39. /* rs5c372 too? different address... */
  40. };
  41. /* RTC registers don't differ much, except for the century flag */
  42. #define DS1307_REG_SECS 0x00 /* 00-59 */
  43. # define DS1307_BIT_CH 0x80
  44. # define DS1340_BIT_nEOSC 0x80
  45. # define MCP7941X_BIT_ST 0x80
  46. #define DS1307_REG_MIN 0x01 /* 00-59 */
  47. #define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
  48. # define DS1307_BIT_12HR 0x40 /* in REG_HOUR */
  49. # define DS1307_BIT_PM 0x20 /* in REG_HOUR */
  50. # define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */
  51. # define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */
  52. #define DS1307_REG_WDAY 0x03 /* 01-07 */
  53. # define MCP7941X_BIT_VBATEN 0x08
  54. #define DS1307_REG_MDAY 0x04 /* 01-31 */
  55. #define DS1307_REG_MONTH 0x05 /* 01-12 */
  56. # define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */
  57. #define DS1307_REG_YEAR 0x06 /* 00-99 */
  58. /*
  59. * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
  60. * start at 7, and they differ a LOT. Only control and status matter for
  61. * basic RTC date and time functionality; be careful using them.
  62. */
  63. #define DS1307_REG_CONTROL 0x07 /* or ds1338 */
  64. # define DS1307_BIT_OUT 0x80
  65. # define DS1338_BIT_OSF 0x20
  66. # define DS1307_BIT_SQWE 0x10
  67. # define DS1307_BIT_RS1 0x02
  68. # define DS1307_BIT_RS0 0x01
  69. #define DS1337_REG_CONTROL 0x0e
  70. # define DS1337_BIT_nEOSC 0x80
  71. # define DS1339_BIT_BBSQI 0x20
  72. # define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */
  73. # define DS1337_BIT_RS2 0x10
  74. # define DS1337_BIT_RS1 0x08
  75. # define DS1337_BIT_INTCN 0x04
  76. # define DS1337_BIT_A2IE 0x02
  77. # define DS1337_BIT_A1IE 0x01
  78. #define DS1340_REG_CONTROL 0x07
  79. # define DS1340_BIT_OUT 0x80
  80. # define DS1340_BIT_FT 0x40
  81. # define DS1340_BIT_CALIB_SIGN 0x20
  82. # define DS1340_M_CALIBRATION 0x1f
  83. #define DS1340_REG_FLAG 0x09
  84. # define DS1340_BIT_OSF 0x80
  85. #define DS1337_REG_STATUS 0x0f
  86. # define DS1337_BIT_OSF 0x80
  87. # define DS1337_BIT_A2I 0x02
  88. # define DS1337_BIT_A1I 0x01
  89. #define DS1339_REG_ALARM1_SECS 0x07
  90. #define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0
  91. #define RX8025_REG_CTRL1 0x0e
  92. # define RX8025_BIT_2412 0x20
  93. #define RX8025_REG_CTRL2 0x0f
  94. # define RX8025_BIT_PON 0x10
  95. # define RX8025_BIT_VDET 0x40
  96. # define RX8025_BIT_XST 0x20
  97. struct ds1307 {
  98. u8 offset; /* register's offset */
  99. u8 regs[11];
  100. u16 nvram_offset;
  101. struct bin_attribute *nvram;
  102. enum ds_type type;
  103. unsigned long flags;
  104. #define HAS_NVRAM 0 /* bit 0 == sysfs file active */
  105. #define HAS_ALARM 1 /* bit 1 == irq claimed */
  106. struct i2c_client *client;
  107. struct rtc_device *rtc;
  108. struct work_struct work;
  109. s32 (*read_block_data)(const struct i2c_client *client, u8 command,
  110. u8 length, u8 *values);
  111. s32 (*write_block_data)(const struct i2c_client *client, u8 command,
  112. u8 length, const u8 *values);
  113. };
  114. struct chip_desc {
  115. unsigned alarm:1;
  116. u16 nvram_offset;
  117. u16 nvram_size;
  118. u16 trickle_charger_reg;
  119. };
  120. static const struct chip_desc chips[last_ds_type] = {
  121. [ds_1307] = {
  122. .nvram_offset = 8,
  123. .nvram_size = 56,
  124. },
  125. [ds_1337] = {
  126. .alarm = 1,
  127. },
  128. [ds_1338] = {
  129. .nvram_offset = 8,
  130. .nvram_size = 56,
  131. },
  132. [ds_1339] = {
  133. .alarm = 1,
  134. .trickle_charger_reg = 0x10,
  135. },
  136. [ds_1340] = {
  137. .trickle_charger_reg = 0x08,
  138. },
  139. [ds_1388] = {
  140. .trickle_charger_reg = 0x0a,
  141. },
  142. [ds_3231] = {
  143. .alarm = 1,
  144. },
  145. [mcp7941x] = {
  146. /* this is battery backed SRAM */
  147. .nvram_offset = 0x20,
  148. .nvram_size = 0x40,
  149. },
  150. };
  151. static const struct i2c_device_id ds1307_id[] = {
  152. { "ds1307", ds_1307 },
  153. { "ds1337", ds_1337 },
  154. { "ds1338", ds_1338 },
  155. { "ds1339", ds_1339 },
  156. { "ds1388", ds_1388 },
  157. { "ds1340", ds_1340 },
  158. { "ds3231", ds_3231 },
  159. { "m41t00", m41t00 },
  160. { "mcp7941x", mcp7941x },
  161. { "pt7c4338", ds_1307 },
  162. { "rx8025", rx_8025 },
  163. { }
  164. };
  165. MODULE_DEVICE_TABLE(i2c, ds1307_id);
  166. /*----------------------------------------------------------------------*/
  167. #define BLOCK_DATA_MAX_TRIES 10
  168. static s32 ds1307_read_block_data_once(const struct i2c_client *client,
  169. u8 command, u8 length, u8 *values)
  170. {
  171. s32 i, data;
  172. for (i = 0; i < length; i++) {
  173. data = i2c_smbus_read_byte_data(client, command + i);
  174. if (data < 0)
  175. return data;
  176. values[i] = data;
  177. }
  178. return i;
  179. }
  180. static s32 ds1307_read_block_data(const struct i2c_client *client, u8 command,
  181. u8 length, u8 *values)
  182. {
  183. u8 oldvalues[255];
  184. s32 ret;
  185. int tries = 0;
  186. dev_dbg(&client->dev, "ds1307_read_block_data (length=%d)\n", length);
  187. ret = ds1307_read_block_data_once(client, command, length, values);
  188. if (ret < 0)
  189. return ret;
  190. do {
  191. if (++tries > BLOCK_DATA_MAX_TRIES) {
  192. dev_err(&client->dev,
  193. "ds1307_read_block_data failed\n");
  194. return -EIO;
  195. }
  196. memcpy(oldvalues, values, length);
  197. ret = ds1307_read_block_data_once(client, command, length,
  198. values);
  199. if (ret < 0)
  200. return ret;
  201. } while (memcmp(oldvalues, values, length));
  202. return length;
  203. }
  204. static s32 ds1307_write_block_data(const struct i2c_client *client, u8 command,
  205. u8 length, const u8 *values)
  206. {
  207. u8 currvalues[255];
  208. int tries = 0;
  209. dev_dbg(&client->dev, "ds1307_write_block_data (length=%d)\n", length);
  210. do {
  211. s32 i, ret;
  212. if (++tries > BLOCK_DATA_MAX_TRIES) {
  213. dev_err(&client->dev,
  214. "ds1307_write_block_data failed\n");
  215. return -EIO;
  216. }
  217. for (i = 0; i < length; i++) {
  218. ret = i2c_smbus_write_byte_data(client, command + i,
  219. values[i]);
  220. if (ret < 0)
  221. return ret;
  222. }
  223. ret = ds1307_read_block_data_once(client, command, length,
  224. currvalues);
  225. if (ret < 0)
  226. return ret;
  227. } while (memcmp(currvalues, values, length));
  228. return length;
  229. }
  230. /*----------------------------------------------------------------------*/
  231. /* These RTC devices are not designed to be connected to a SMbus adapter.
  232. SMbus limits block operations length to 32 bytes, whereas it's not
  233. limited on I2C buses. As a result, accesses may exceed 32 bytes;
  234. in that case, split them into smaller blocks */
  235. static s32 ds1307_native_smbus_write_block_data(const struct i2c_client *client,
  236. u8 command, u8 length, const u8 *values)
  237. {
  238. u8 suboffset = 0;
  239. if (length <= I2C_SMBUS_BLOCK_MAX)
  240. return i2c_smbus_write_i2c_block_data(client,
  241. command, length, values);
  242. while (suboffset < length) {
  243. s32 retval = i2c_smbus_write_i2c_block_data(client,
  244. command + suboffset,
  245. min(I2C_SMBUS_BLOCK_MAX, length - suboffset),
  246. values + suboffset);
  247. if (retval < 0)
  248. return retval;
  249. suboffset += I2C_SMBUS_BLOCK_MAX;
  250. }
  251. return length;
  252. }
  253. static s32 ds1307_native_smbus_read_block_data(const struct i2c_client *client,
  254. u8 command, u8 length, u8 *values)
  255. {
  256. u8 suboffset = 0;
  257. if (length <= I2C_SMBUS_BLOCK_MAX)
  258. return i2c_smbus_read_i2c_block_data(client,
  259. command, length, values);
  260. while (suboffset < length) {
  261. s32 retval = i2c_smbus_read_i2c_block_data(client,
  262. command + suboffset,
  263. min(I2C_SMBUS_BLOCK_MAX, length - suboffset),
  264. values + suboffset);
  265. if (retval < 0)
  266. return retval;
  267. suboffset += I2C_SMBUS_BLOCK_MAX;
  268. }
  269. return length;
  270. }
  271. /*----------------------------------------------------------------------*/
  272. /*
  273. * The IRQ logic includes a "real" handler running in IRQ context just
  274. * long enough to schedule this workqueue entry. We need a task context
  275. * to talk to the RTC, since I2C I/O calls require that; and disable the
  276. * IRQ until we clear its status on the chip, so that this handler can
  277. * work with any type of triggering (not just falling edge).
  278. *
  279. * The ds1337 and ds1339 both have two alarms, but we only use the first
  280. * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
  281. * signal; ds1339 chips have only one alarm signal.
  282. */
  283. static void ds1307_work(struct work_struct *work)
  284. {
  285. struct ds1307 *ds1307;
  286. struct i2c_client *client;
  287. struct mutex *lock;
  288. int stat, control;
  289. ds1307 = container_of(work, struct ds1307, work);
  290. client = ds1307->client;
  291. lock = &ds1307->rtc->ops_lock;
  292. mutex_lock(lock);
  293. stat = i2c_smbus_read_byte_data(client, DS1337_REG_STATUS);
  294. if (stat < 0)
  295. goto out;
  296. if (stat & DS1337_BIT_A1I) {
  297. stat &= ~DS1337_BIT_A1I;
  298. i2c_smbus_write_byte_data(client, DS1337_REG_STATUS, stat);
  299. control = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL);
  300. if (control < 0)
  301. goto out;
  302. control &= ~DS1337_BIT_A1IE;
  303. i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, control);
  304. rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
  305. }
  306. out:
  307. if (test_bit(HAS_ALARM, &ds1307->flags))
  308. enable_irq(client->irq);
  309. mutex_unlock(lock);
  310. }
  311. static irqreturn_t ds1307_irq(int irq, void *dev_id)
  312. {
  313. struct i2c_client *client = dev_id;
  314. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  315. disable_irq_nosync(irq);
  316. schedule_work(&ds1307->work);
  317. return IRQ_HANDLED;
  318. }
  319. /*----------------------------------------------------------------------*/
  320. static int ds1307_get_time(struct device *dev, struct rtc_time *t)
  321. {
  322. struct ds1307 *ds1307 = dev_get_drvdata(dev);
  323. int tmp;
  324. /* read the RTC date and time registers all at once */
  325. tmp = ds1307->read_block_data(ds1307->client,
  326. ds1307->offset, 7, ds1307->regs);
  327. if (tmp != 7) {
  328. dev_err(dev, "%s error %d\n", "read", tmp);
  329. return -EIO;
  330. }
  331. dev_dbg(dev, "%s: %7ph\n", "read", ds1307->regs);
  332. t->tm_sec = bcd2bin(ds1307->regs[DS1307_REG_SECS] & 0x7f);
  333. t->tm_min = bcd2bin(ds1307->regs[DS1307_REG_MIN] & 0x7f);
  334. tmp = ds1307->regs[DS1307_REG_HOUR] & 0x3f;
  335. t->tm_hour = bcd2bin(tmp);
  336. t->tm_wday = bcd2bin(ds1307->regs[DS1307_REG_WDAY] & 0x07) - 1;
  337. t->tm_mday = bcd2bin(ds1307->regs[DS1307_REG_MDAY] & 0x3f);
  338. tmp = ds1307->regs[DS1307_REG_MONTH] & 0x1f;
  339. t->tm_mon = bcd2bin(tmp) - 1;
  340. /* assume 20YY not 19YY, and ignore DS1337_BIT_CENTURY */
  341. t->tm_year = bcd2bin(ds1307->regs[DS1307_REG_YEAR]) + 100;
  342. dev_dbg(dev, "%s secs=%d, mins=%d, "
  343. "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
  344. "read", t->tm_sec, t->tm_min,
  345. t->tm_hour, t->tm_mday,
  346. t->tm_mon, t->tm_year, t->tm_wday);
  347. /* initial clock setting can be undefined */
  348. return rtc_valid_tm(t);
  349. }
  350. static int ds1307_set_time(struct device *dev, struct rtc_time *t)
  351. {
  352. struct ds1307 *ds1307 = dev_get_drvdata(dev);
  353. int result;
  354. int tmp;
  355. u8 *buf = ds1307->regs;
  356. dev_dbg(dev, "%s secs=%d, mins=%d, "
  357. "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
  358. "write", t->tm_sec, t->tm_min,
  359. t->tm_hour, t->tm_mday,
  360. t->tm_mon, t->tm_year, t->tm_wday);
  361. buf[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
  362. buf[DS1307_REG_MIN] = bin2bcd(t->tm_min);
  363. buf[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
  364. buf[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
  365. buf[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
  366. buf[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
  367. /* assume 20YY not 19YY */
  368. tmp = t->tm_year - 100;
  369. buf[DS1307_REG_YEAR] = bin2bcd(tmp);
  370. switch (ds1307->type) {
  371. case ds_1337:
  372. case ds_1339:
  373. case ds_3231:
  374. buf[DS1307_REG_MONTH] |= DS1337_BIT_CENTURY;
  375. break;
  376. case ds_1340:
  377. buf[DS1307_REG_HOUR] |= DS1340_BIT_CENTURY_EN
  378. | DS1340_BIT_CENTURY;
  379. break;
  380. case mcp7941x:
  381. /*
  382. * these bits were cleared when preparing the date/time
  383. * values and need to be set again before writing the
  384. * buffer out to the device.
  385. */
  386. buf[DS1307_REG_SECS] |= MCP7941X_BIT_ST;
  387. buf[DS1307_REG_WDAY] |= MCP7941X_BIT_VBATEN;
  388. break;
  389. default:
  390. break;
  391. }
  392. dev_dbg(dev, "%s: %7ph\n", "write", buf);
  393. result = ds1307->write_block_data(ds1307->client,
  394. ds1307->offset, 7, buf);
  395. if (result < 0) {
  396. dev_err(dev, "%s error %d\n", "write", result);
  397. return result;
  398. }
  399. return 0;
  400. }
  401. static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
  402. {
  403. struct i2c_client *client = to_i2c_client(dev);
  404. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  405. int ret;
  406. if (!test_bit(HAS_ALARM, &ds1307->flags))
  407. return -EINVAL;
  408. /* read all ALARM1, ALARM2, and status registers at once */
  409. ret = ds1307->read_block_data(client,
  410. DS1339_REG_ALARM1_SECS, 9, ds1307->regs);
  411. if (ret != 9) {
  412. dev_err(dev, "%s error %d\n", "alarm read", ret);
  413. return -EIO;
  414. }
  415. dev_dbg(dev, "%s: %02x %02x %02x %02x, %02x %02x %02x, %02x %02x\n",
  416. "alarm read",
  417. ds1307->regs[0], ds1307->regs[1],
  418. ds1307->regs[2], ds1307->regs[3],
  419. ds1307->regs[4], ds1307->regs[5],
  420. ds1307->regs[6], ds1307->regs[7],
  421. ds1307->regs[8]);
  422. /*
  423. * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
  424. * and that all four fields are checked matches
  425. */
  426. t->time.tm_sec = bcd2bin(ds1307->regs[0] & 0x7f);
  427. t->time.tm_min = bcd2bin(ds1307->regs[1] & 0x7f);
  428. t->time.tm_hour = bcd2bin(ds1307->regs[2] & 0x3f);
  429. t->time.tm_mday = bcd2bin(ds1307->regs[3] & 0x3f);
  430. t->time.tm_mon = -1;
  431. t->time.tm_year = -1;
  432. t->time.tm_wday = -1;
  433. t->time.tm_yday = -1;
  434. t->time.tm_isdst = -1;
  435. /* ... and status */
  436. t->enabled = !!(ds1307->regs[7] & DS1337_BIT_A1IE);
  437. t->pending = !!(ds1307->regs[8] & DS1337_BIT_A1I);
  438. dev_dbg(dev, "%s secs=%d, mins=%d, "
  439. "hours=%d, mday=%d, enabled=%d, pending=%d\n",
  440. "alarm read", t->time.tm_sec, t->time.tm_min,
  441. t->time.tm_hour, t->time.tm_mday,
  442. t->enabled, t->pending);
  443. return 0;
  444. }
  445. static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
  446. {
  447. struct i2c_client *client = to_i2c_client(dev);
  448. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  449. unsigned char *buf = ds1307->regs;
  450. u8 control, status;
  451. int ret;
  452. if (!test_bit(HAS_ALARM, &ds1307->flags))
  453. return -EINVAL;
  454. dev_dbg(dev, "%s secs=%d, mins=%d, "
  455. "hours=%d, mday=%d, enabled=%d, pending=%d\n",
  456. "alarm set", t->time.tm_sec, t->time.tm_min,
  457. t->time.tm_hour, t->time.tm_mday,
  458. t->enabled, t->pending);
  459. /* read current status of both alarms and the chip */
  460. ret = ds1307->read_block_data(client,
  461. DS1339_REG_ALARM1_SECS, 9, buf);
  462. if (ret != 9) {
  463. dev_err(dev, "%s error %d\n", "alarm write", ret);
  464. return -EIO;
  465. }
  466. control = ds1307->regs[7];
  467. status = ds1307->regs[8];
  468. dev_dbg(dev, "%s: %02x %02x %02x %02x, %02x %02x %02x, %02x %02x\n",
  469. "alarm set (old status)",
  470. ds1307->regs[0], ds1307->regs[1],
  471. ds1307->regs[2], ds1307->regs[3],
  472. ds1307->regs[4], ds1307->regs[5],
  473. ds1307->regs[6], control, status);
  474. /* set ALARM1, using 24 hour and day-of-month modes */
  475. buf[0] = bin2bcd(t->time.tm_sec);
  476. buf[1] = bin2bcd(t->time.tm_min);
  477. buf[2] = bin2bcd(t->time.tm_hour);
  478. buf[3] = bin2bcd(t->time.tm_mday);
  479. /* set ALARM2 to non-garbage */
  480. buf[4] = 0;
  481. buf[5] = 0;
  482. buf[6] = 0;
  483. /* optionally enable ALARM1 */
  484. buf[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
  485. if (t->enabled) {
  486. dev_dbg(dev, "alarm IRQ armed\n");
  487. buf[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */
  488. }
  489. buf[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
  490. ret = ds1307->write_block_data(client,
  491. DS1339_REG_ALARM1_SECS, 9, buf);
  492. if (ret < 0) {
  493. dev_err(dev, "can't set alarm time\n");
  494. return ret;
  495. }
  496. return 0;
  497. }
  498. static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
  499. {
  500. struct i2c_client *client = to_i2c_client(dev);
  501. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  502. int ret;
  503. if (!test_bit(HAS_ALARM, &ds1307->flags))
  504. return -ENOTTY;
  505. ret = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL);
  506. if (ret < 0)
  507. return ret;
  508. if (enabled)
  509. ret |= DS1337_BIT_A1IE;
  510. else
  511. ret &= ~DS1337_BIT_A1IE;
  512. ret = i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, ret);
  513. if (ret < 0)
  514. return ret;
  515. return 0;
  516. }
  517. static const struct rtc_class_ops ds13xx_rtc_ops = {
  518. .read_time = ds1307_get_time,
  519. .set_time = ds1307_set_time,
  520. .read_alarm = ds1337_read_alarm,
  521. .set_alarm = ds1337_set_alarm,
  522. .alarm_irq_enable = ds1307_alarm_irq_enable,
  523. };
  524. /*----------------------------------------------------------------------*/
  525. static ssize_t
  526. ds1307_nvram_read(struct file *filp, struct kobject *kobj,
  527. struct bin_attribute *attr,
  528. char *buf, loff_t off, size_t count)
  529. {
  530. struct i2c_client *client;
  531. struct ds1307 *ds1307;
  532. int result;
  533. client = kobj_to_i2c_client(kobj);
  534. ds1307 = i2c_get_clientdata(client);
  535. if (unlikely(off >= ds1307->nvram->size))
  536. return 0;
  537. if ((off + count) > ds1307->nvram->size)
  538. count = ds1307->nvram->size - off;
  539. if (unlikely(!count))
  540. return count;
  541. result = ds1307->read_block_data(client, ds1307->nvram_offset + off,
  542. count, buf);
  543. if (result < 0)
  544. dev_err(&client->dev, "%s error %d\n", "nvram read", result);
  545. return result;
  546. }
  547. static ssize_t
  548. ds1307_nvram_write(struct file *filp, struct kobject *kobj,
  549. struct bin_attribute *attr,
  550. char *buf, loff_t off, size_t count)
  551. {
  552. struct i2c_client *client;
  553. struct ds1307 *ds1307;
  554. int result;
  555. client = kobj_to_i2c_client(kobj);
  556. ds1307 = i2c_get_clientdata(client);
  557. if (unlikely(off >= ds1307->nvram->size))
  558. return -EFBIG;
  559. if ((off + count) > ds1307->nvram->size)
  560. count = ds1307->nvram->size - off;
  561. if (unlikely(!count))
  562. return count;
  563. result = ds1307->write_block_data(client, ds1307->nvram_offset + off,
  564. count, buf);
  565. if (result < 0) {
  566. dev_err(&client->dev, "%s error %d\n", "nvram write", result);
  567. return result;
  568. }
  569. return count;
  570. }
  571. /*----------------------------------------------------------------------*/
  572. static int ds1307_probe(struct i2c_client *client,
  573. const struct i2c_device_id *id)
  574. {
  575. struct ds1307 *ds1307;
  576. int err = -ENODEV;
  577. int tmp;
  578. const struct chip_desc *chip = &chips[id->driver_data];
  579. struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
  580. bool want_irq = false;
  581. unsigned char *buf;
  582. struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev);
  583. static const int bbsqi_bitpos[] = {
  584. [ds_1337] = 0,
  585. [ds_1339] = DS1339_BIT_BBSQI,
  586. [ds_3231] = DS3231_BIT_BBSQW,
  587. };
  588. if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)
  589. && !i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK))
  590. return -EIO;
  591. ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL);
  592. if (!ds1307)
  593. return -ENOMEM;
  594. i2c_set_clientdata(client, ds1307);
  595. ds1307->client = client;
  596. ds1307->type = id->driver_data;
  597. if (pdata && pdata->trickle_charger_setup && chip->trickle_charger_reg)
  598. i2c_smbus_write_byte_data(client, chip->trickle_charger_reg,
  599. DS13XX_TRICKLE_CHARGER_MAGIC | pdata->trickle_charger_setup);
  600. buf = ds1307->regs;
  601. if (i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK)) {
  602. ds1307->read_block_data = ds1307_native_smbus_read_block_data;
  603. ds1307->write_block_data = ds1307_native_smbus_write_block_data;
  604. } else {
  605. ds1307->read_block_data = ds1307_read_block_data;
  606. ds1307->write_block_data = ds1307_write_block_data;
  607. }
  608. switch (ds1307->type) {
  609. case ds_1337:
  610. case ds_1339:
  611. case ds_3231:
  612. /* get registers that the "rtc" read below won't read... */
  613. tmp = ds1307->read_block_data(ds1307->client,
  614. DS1337_REG_CONTROL, 2, buf);
  615. if (tmp != 2) {
  616. dev_dbg(&client->dev, "read error %d\n", tmp);
  617. err = -EIO;
  618. goto exit;
  619. }
  620. /* oscillator off? turn it on, so clock can tick. */
  621. if (ds1307->regs[0] & DS1337_BIT_nEOSC)
  622. ds1307->regs[0] &= ~DS1337_BIT_nEOSC;
  623. /*
  624. * Using IRQ? Disable the square wave and both alarms.
  625. * For some variants, be sure alarms can trigger when we're
  626. * running on Vbackup (BBSQI/BBSQW)
  627. */
  628. if (ds1307->client->irq > 0 && chip->alarm) {
  629. INIT_WORK(&ds1307->work, ds1307_work);
  630. ds1307->regs[0] |= DS1337_BIT_INTCN
  631. | bbsqi_bitpos[ds1307->type];
  632. ds1307->regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
  633. want_irq = true;
  634. }
  635. i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL,
  636. ds1307->regs[0]);
  637. /* oscillator fault? clear flag, and warn */
  638. if (ds1307->regs[1] & DS1337_BIT_OSF) {
  639. i2c_smbus_write_byte_data(client, DS1337_REG_STATUS,
  640. ds1307->regs[1] & ~DS1337_BIT_OSF);
  641. dev_warn(&client->dev, "SET TIME!\n");
  642. }
  643. break;
  644. case rx_8025:
  645. tmp = i2c_smbus_read_i2c_block_data(ds1307->client,
  646. RX8025_REG_CTRL1 << 4 | 0x08, 2, buf);
  647. if (tmp != 2) {
  648. dev_dbg(&client->dev, "read error %d\n", tmp);
  649. err = -EIO;
  650. goto exit;
  651. }
  652. /* oscillator off? turn it on, so clock can tick. */
  653. if (!(ds1307->regs[1] & RX8025_BIT_XST)) {
  654. ds1307->regs[1] |= RX8025_BIT_XST;
  655. i2c_smbus_write_byte_data(client,
  656. RX8025_REG_CTRL2 << 4 | 0x08,
  657. ds1307->regs[1]);
  658. dev_warn(&client->dev,
  659. "oscillator stop detected - SET TIME!\n");
  660. }
  661. if (ds1307->regs[1] & RX8025_BIT_PON) {
  662. ds1307->regs[1] &= ~RX8025_BIT_PON;
  663. i2c_smbus_write_byte_data(client,
  664. RX8025_REG_CTRL2 << 4 | 0x08,
  665. ds1307->regs[1]);
  666. dev_warn(&client->dev, "power-on detected\n");
  667. }
  668. if (ds1307->regs[1] & RX8025_BIT_VDET) {
  669. ds1307->regs[1] &= ~RX8025_BIT_VDET;
  670. i2c_smbus_write_byte_data(client,
  671. RX8025_REG_CTRL2 << 4 | 0x08,
  672. ds1307->regs[1]);
  673. dev_warn(&client->dev, "voltage drop detected\n");
  674. }
  675. /* make sure we are running in 24hour mode */
  676. if (!(ds1307->regs[0] & RX8025_BIT_2412)) {
  677. u8 hour;
  678. /* switch to 24 hour mode */
  679. i2c_smbus_write_byte_data(client,
  680. RX8025_REG_CTRL1 << 4 | 0x08,
  681. ds1307->regs[0] |
  682. RX8025_BIT_2412);
  683. tmp = i2c_smbus_read_i2c_block_data(ds1307->client,
  684. RX8025_REG_CTRL1 << 4 | 0x08, 2, buf);
  685. if (tmp != 2) {
  686. dev_dbg(&client->dev, "read error %d\n", tmp);
  687. err = -EIO;
  688. goto exit;
  689. }
  690. /* correct hour */
  691. hour = bcd2bin(ds1307->regs[DS1307_REG_HOUR]);
  692. if (hour == 12)
  693. hour = 0;
  694. if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
  695. hour += 12;
  696. i2c_smbus_write_byte_data(client,
  697. DS1307_REG_HOUR << 4 | 0x08,
  698. hour);
  699. }
  700. break;
  701. case ds_1388:
  702. ds1307->offset = 1; /* Seconds starts at 1 */
  703. break;
  704. default:
  705. break;
  706. }
  707. read_rtc:
  708. /* read RTC registers */
  709. tmp = ds1307->read_block_data(ds1307->client, ds1307->offset, 8, buf);
  710. if (tmp != 8) {
  711. dev_dbg(&client->dev, "read error %d\n", tmp);
  712. err = -EIO;
  713. goto exit;
  714. }
  715. /*
  716. * minimal sanity checking; some chips (like DS1340) don't
  717. * specify the extra bits as must-be-zero, but there are
  718. * still a few values that are clearly out-of-range.
  719. */
  720. tmp = ds1307->regs[DS1307_REG_SECS];
  721. switch (ds1307->type) {
  722. case ds_1307:
  723. case m41t00:
  724. /* clock halted? turn it on, so clock can tick. */
  725. if (tmp & DS1307_BIT_CH) {
  726. i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
  727. dev_warn(&client->dev, "SET TIME!\n");
  728. goto read_rtc;
  729. }
  730. break;
  731. case ds_1338:
  732. /* clock halted? turn it on, so clock can tick. */
  733. if (tmp & DS1307_BIT_CH)
  734. i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
  735. /* oscillator fault? clear flag, and warn */
  736. if (ds1307->regs[DS1307_REG_CONTROL] & DS1338_BIT_OSF) {
  737. i2c_smbus_write_byte_data(client, DS1307_REG_CONTROL,
  738. ds1307->regs[DS1307_REG_CONTROL]
  739. & ~DS1338_BIT_OSF);
  740. dev_warn(&client->dev, "SET TIME!\n");
  741. goto read_rtc;
  742. }
  743. break;
  744. case ds_1340:
  745. /* clock halted? turn it on, so clock can tick. */
  746. if (tmp & DS1340_BIT_nEOSC)
  747. i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
  748. tmp = i2c_smbus_read_byte_data(client, DS1340_REG_FLAG);
  749. if (tmp < 0) {
  750. dev_dbg(&client->dev, "read error %d\n", tmp);
  751. err = -EIO;
  752. goto exit;
  753. }
  754. /* oscillator fault? clear flag, and warn */
  755. if (tmp & DS1340_BIT_OSF) {
  756. i2c_smbus_write_byte_data(client, DS1340_REG_FLAG, 0);
  757. dev_warn(&client->dev, "SET TIME!\n");
  758. }
  759. break;
  760. case mcp7941x:
  761. /* make sure that the backup battery is enabled */
  762. if (!(ds1307->regs[DS1307_REG_WDAY] & MCP7941X_BIT_VBATEN)) {
  763. i2c_smbus_write_byte_data(client, DS1307_REG_WDAY,
  764. ds1307->regs[DS1307_REG_WDAY]
  765. | MCP7941X_BIT_VBATEN);
  766. }
  767. /* clock halted? turn it on, so clock can tick. */
  768. if (!(tmp & MCP7941X_BIT_ST)) {
  769. i2c_smbus_write_byte_data(client, DS1307_REG_SECS,
  770. MCP7941X_BIT_ST);
  771. dev_warn(&client->dev, "SET TIME!\n");
  772. goto read_rtc;
  773. }
  774. break;
  775. default:
  776. break;
  777. }
  778. tmp = ds1307->regs[DS1307_REG_HOUR];
  779. switch (ds1307->type) {
  780. case ds_1340:
  781. case m41t00:
  782. /*
  783. * NOTE: ignores century bits; fix before deploying
  784. * systems that will run through year 2100.
  785. */
  786. break;
  787. case rx_8025:
  788. break;
  789. default:
  790. if (!(tmp & DS1307_BIT_12HR))
  791. break;
  792. /*
  793. * Be sure we're in 24 hour mode. Multi-master systems
  794. * take note...
  795. */
  796. tmp = bcd2bin(tmp & 0x1f);
  797. if (tmp == 12)
  798. tmp = 0;
  799. if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
  800. tmp += 12;
  801. i2c_smbus_write_byte_data(client,
  802. ds1307->offset + DS1307_REG_HOUR,
  803. bin2bcd(tmp));
  804. }
  805. ds1307->rtc = devm_rtc_device_register(&client->dev, client->name,
  806. &ds13xx_rtc_ops, THIS_MODULE);
  807. if (IS_ERR(ds1307->rtc)) {
  808. err = PTR_ERR(ds1307->rtc);
  809. dev_err(&client->dev,
  810. "unable to register the class device\n");
  811. goto exit;
  812. }
  813. if (want_irq) {
  814. err = request_irq(client->irq, ds1307_irq, IRQF_SHARED,
  815. ds1307->rtc->name, client);
  816. if (err) {
  817. dev_err(&client->dev,
  818. "unable to request IRQ!\n");
  819. goto exit;
  820. }
  821. device_set_wakeup_capable(&client->dev, 1);
  822. set_bit(HAS_ALARM, &ds1307->flags);
  823. dev_dbg(&client->dev, "got IRQ %d\n", client->irq);
  824. }
  825. if (chip->nvram_size) {
  826. ds1307->nvram = devm_kzalloc(&client->dev,
  827. sizeof(struct bin_attribute),
  828. GFP_KERNEL);
  829. if (!ds1307->nvram) {
  830. err = -ENOMEM;
  831. goto err_irq;
  832. }
  833. ds1307->nvram->attr.name = "nvram";
  834. ds1307->nvram->attr.mode = S_IRUGO | S_IWUSR;
  835. sysfs_bin_attr_init(ds1307->nvram);
  836. ds1307->nvram->read = ds1307_nvram_read;
  837. ds1307->nvram->write = ds1307_nvram_write;
  838. ds1307->nvram->size = chip->nvram_size;
  839. ds1307->nvram_offset = chip->nvram_offset;
  840. err = sysfs_create_bin_file(&client->dev.kobj, ds1307->nvram);
  841. if (err)
  842. goto err_irq;
  843. set_bit(HAS_NVRAM, &ds1307->flags);
  844. dev_info(&client->dev, "%zu bytes nvram\n", ds1307->nvram->size);
  845. }
  846. return 0;
  847. err_irq:
  848. free_irq(client->irq, client);
  849. exit:
  850. return err;
  851. }
  852. static int ds1307_remove(struct i2c_client *client)
  853. {
  854. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  855. if (test_and_clear_bit(HAS_ALARM, &ds1307->flags)) {
  856. free_irq(client->irq, client);
  857. cancel_work_sync(&ds1307->work);
  858. }
  859. if (test_and_clear_bit(HAS_NVRAM, &ds1307->flags))
  860. sysfs_remove_bin_file(&client->dev.kobj, ds1307->nvram);
  861. return 0;
  862. }
  863. static struct i2c_driver ds1307_driver = {
  864. .driver = {
  865. .name = "rtc-ds1307",
  866. .owner = THIS_MODULE,
  867. },
  868. .probe = ds1307_probe,
  869. .remove = ds1307_remove,
  870. .id_table = ds1307_id,
  871. };
  872. module_i2c_driver(ds1307_driver);
  873. MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
  874. MODULE_LICENSE("GPL");