devices.c 20 KB

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  1. #include <linux/module.h>
  2. #include <linux/kernel.h>
  3. #include <linux/init.h>
  4. #include <linux/platform_device.h>
  5. #include <linux/dma-mapping.h>
  6. #include <mach/udc.h>
  7. #include <mach/pxafb.h>
  8. #include <mach/mmc.h>
  9. #include <mach/irda.h>
  10. #include <mach/ohci.h>
  11. #include <mach/pxa27x_keypad.h>
  12. #include <mach/pxa2xx_spi.h>
  13. #include <mach/camera.h>
  14. #include <mach/audio.h>
  15. #include <plat/i2c.h>
  16. #include <plat/pxa3xx_nand.h>
  17. #include "devices.h"
  18. #include "generic.h"
  19. void __init pxa_register_device(struct platform_device *dev, void *data)
  20. {
  21. int ret;
  22. dev->dev.platform_data = data;
  23. ret = platform_device_register(dev);
  24. if (ret)
  25. dev_err(&dev->dev, "unable to register device: %d\n", ret);
  26. }
  27. static struct resource pxamci_resources[] = {
  28. [0] = {
  29. .start = 0x41100000,
  30. .end = 0x41100fff,
  31. .flags = IORESOURCE_MEM,
  32. },
  33. [1] = {
  34. .start = IRQ_MMC,
  35. .end = IRQ_MMC,
  36. .flags = IORESOURCE_IRQ,
  37. },
  38. [2] = {
  39. .start = 21,
  40. .end = 21,
  41. .flags = IORESOURCE_DMA,
  42. },
  43. [3] = {
  44. .start = 22,
  45. .end = 22,
  46. .flags = IORESOURCE_DMA,
  47. },
  48. };
  49. static u64 pxamci_dmamask = 0xffffffffUL;
  50. struct platform_device pxa_device_mci = {
  51. .name = "pxa2xx-mci",
  52. .id = 0,
  53. .dev = {
  54. .dma_mask = &pxamci_dmamask,
  55. .coherent_dma_mask = 0xffffffff,
  56. },
  57. .num_resources = ARRAY_SIZE(pxamci_resources),
  58. .resource = pxamci_resources,
  59. };
  60. void __init pxa_set_mci_info(struct pxamci_platform_data *info)
  61. {
  62. pxa_register_device(&pxa_device_mci, info);
  63. }
  64. static struct pxa2xx_udc_mach_info pxa_udc_info = {
  65. .gpio_pullup = -1,
  66. .gpio_vbus = -1,
  67. };
  68. void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
  69. {
  70. memcpy(&pxa_udc_info, info, sizeof *info);
  71. }
  72. static struct resource pxa2xx_udc_resources[] = {
  73. [0] = {
  74. .start = 0x40600000,
  75. .end = 0x4060ffff,
  76. .flags = IORESOURCE_MEM,
  77. },
  78. [1] = {
  79. .start = IRQ_USB,
  80. .end = IRQ_USB,
  81. .flags = IORESOURCE_IRQ,
  82. },
  83. };
  84. static u64 udc_dma_mask = ~(u32)0;
  85. struct platform_device pxa25x_device_udc = {
  86. .name = "pxa25x-udc",
  87. .id = -1,
  88. .resource = pxa2xx_udc_resources,
  89. .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
  90. .dev = {
  91. .platform_data = &pxa_udc_info,
  92. .dma_mask = &udc_dma_mask,
  93. }
  94. };
  95. struct platform_device pxa27x_device_udc = {
  96. .name = "pxa27x-udc",
  97. .id = -1,
  98. .resource = pxa2xx_udc_resources,
  99. .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
  100. .dev = {
  101. .platform_data = &pxa_udc_info,
  102. .dma_mask = &udc_dma_mask,
  103. }
  104. };
  105. static struct resource pxafb_resources[] = {
  106. [0] = {
  107. .start = 0x44000000,
  108. .end = 0x4400ffff,
  109. .flags = IORESOURCE_MEM,
  110. },
  111. [1] = {
  112. .start = IRQ_LCD,
  113. .end = IRQ_LCD,
  114. .flags = IORESOURCE_IRQ,
  115. },
  116. };
  117. static u64 fb_dma_mask = ~(u64)0;
  118. struct platform_device pxa_device_fb = {
  119. .name = "pxa2xx-fb",
  120. .id = -1,
  121. .dev = {
  122. .dma_mask = &fb_dma_mask,
  123. .coherent_dma_mask = 0xffffffff,
  124. },
  125. .num_resources = ARRAY_SIZE(pxafb_resources),
  126. .resource = pxafb_resources,
  127. };
  128. void __init set_pxa_fb_info(struct pxafb_mach_info *info)
  129. {
  130. pxa_register_device(&pxa_device_fb, info);
  131. }
  132. void __init set_pxa_fb_parent(struct device *parent_dev)
  133. {
  134. pxa_device_fb.dev.parent = parent_dev;
  135. }
  136. static struct resource pxa_resource_ffuart[] = {
  137. {
  138. .start = 0x40100000,
  139. .end = 0x40100023,
  140. .flags = IORESOURCE_MEM,
  141. }, {
  142. .start = IRQ_FFUART,
  143. .end = IRQ_FFUART,
  144. .flags = IORESOURCE_IRQ,
  145. }
  146. };
  147. struct platform_device pxa_device_ffuart = {
  148. .name = "pxa2xx-uart",
  149. .id = 0,
  150. .resource = pxa_resource_ffuart,
  151. .num_resources = ARRAY_SIZE(pxa_resource_ffuart),
  152. };
  153. void __init pxa_set_ffuart_info(void *info)
  154. {
  155. pxa_register_device(&pxa_device_ffuart, info);
  156. }
  157. static struct resource pxa_resource_btuart[] = {
  158. {
  159. .start = 0x40200000,
  160. .end = 0x40200023,
  161. .flags = IORESOURCE_MEM,
  162. }, {
  163. .start = IRQ_BTUART,
  164. .end = IRQ_BTUART,
  165. .flags = IORESOURCE_IRQ,
  166. }
  167. };
  168. struct platform_device pxa_device_btuart = {
  169. .name = "pxa2xx-uart",
  170. .id = 1,
  171. .resource = pxa_resource_btuart,
  172. .num_resources = ARRAY_SIZE(pxa_resource_btuart),
  173. };
  174. void __init pxa_set_btuart_info(void *info)
  175. {
  176. pxa_register_device(&pxa_device_btuart, info);
  177. }
  178. static struct resource pxa_resource_stuart[] = {
  179. {
  180. .start = 0x40700000,
  181. .end = 0x40700023,
  182. .flags = IORESOURCE_MEM,
  183. }, {
  184. .start = IRQ_STUART,
  185. .end = IRQ_STUART,
  186. .flags = IORESOURCE_IRQ,
  187. }
  188. };
  189. struct platform_device pxa_device_stuart = {
  190. .name = "pxa2xx-uart",
  191. .id = 2,
  192. .resource = pxa_resource_stuart,
  193. .num_resources = ARRAY_SIZE(pxa_resource_stuart),
  194. };
  195. void __init pxa_set_stuart_info(void *info)
  196. {
  197. pxa_register_device(&pxa_device_stuart, info);
  198. }
  199. static struct resource pxa_resource_hwuart[] = {
  200. {
  201. .start = 0x41600000,
  202. .end = 0x4160002F,
  203. .flags = IORESOURCE_MEM,
  204. }, {
  205. .start = IRQ_HWUART,
  206. .end = IRQ_HWUART,
  207. .flags = IORESOURCE_IRQ,
  208. }
  209. };
  210. struct platform_device pxa_device_hwuart = {
  211. .name = "pxa2xx-uart",
  212. .id = 3,
  213. .resource = pxa_resource_hwuart,
  214. .num_resources = ARRAY_SIZE(pxa_resource_hwuart),
  215. };
  216. void __init pxa_set_hwuart_info(void *info)
  217. {
  218. if (cpu_is_pxa255())
  219. pxa_register_device(&pxa_device_hwuart, info);
  220. else
  221. pr_info("UART: Ignoring attempt to register HWUART on non-PXA255 hardware");
  222. }
  223. static struct resource pxai2c_resources[] = {
  224. {
  225. .start = 0x40301680,
  226. .end = 0x403016a3,
  227. .flags = IORESOURCE_MEM,
  228. }, {
  229. .start = IRQ_I2C,
  230. .end = IRQ_I2C,
  231. .flags = IORESOURCE_IRQ,
  232. },
  233. };
  234. struct platform_device pxa_device_i2c = {
  235. .name = "pxa2xx-i2c",
  236. .id = 0,
  237. .resource = pxai2c_resources,
  238. .num_resources = ARRAY_SIZE(pxai2c_resources),
  239. };
  240. void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
  241. {
  242. pxa_register_device(&pxa_device_i2c, info);
  243. }
  244. #ifdef CONFIG_PXA27x
  245. static struct resource pxa27x_resources_i2c_power[] = {
  246. {
  247. .start = 0x40f00180,
  248. .end = 0x40f001a3,
  249. .flags = IORESOURCE_MEM,
  250. }, {
  251. .start = IRQ_PWRI2C,
  252. .end = IRQ_PWRI2C,
  253. .flags = IORESOURCE_IRQ,
  254. },
  255. };
  256. struct platform_device pxa27x_device_i2c_power = {
  257. .name = "pxa2xx-i2c",
  258. .id = 1,
  259. .resource = pxa27x_resources_i2c_power,
  260. .num_resources = ARRAY_SIZE(pxa27x_resources_i2c_power),
  261. };
  262. #endif
  263. #ifdef CONFIG_PXA3xx
  264. static struct resource pxa3xx_resources_i2c_power[] = {
  265. {
  266. .start = 0x40f500c0,
  267. .end = 0x40f500d3,
  268. .flags = IORESOURCE_MEM,
  269. }, {
  270. .start = IRQ_PWRI2C,
  271. .end = IRQ_PWRI2C,
  272. .flags = IORESOURCE_IRQ,
  273. },
  274. };
  275. struct platform_device pxa3xx_device_i2c_power = {
  276. .name = "pxa3xx-pwri2c",
  277. .id = 1,
  278. .resource = pxa3xx_resources_i2c_power,
  279. .num_resources = ARRAY_SIZE(pxa3xx_resources_i2c_power),
  280. };
  281. #endif
  282. static struct resource pxai2s_resources[] = {
  283. {
  284. .start = 0x40400000,
  285. .end = 0x40400083,
  286. .flags = IORESOURCE_MEM,
  287. }, {
  288. .start = IRQ_I2S,
  289. .end = IRQ_I2S,
  290. .flags = IORESOURCE_IRQ,
  291. },
  292. };
  293. struct platform_device pxa_device_i2s = {
  294. .name = "pxa2xx-i2s",
  295. .id = -1,
  296. .resource = pxai2s_resources,
  297. .num_resources = ARRAY_SIZE(pxai2s_resources),
  298. };
  299. static u64 pxaficp_dmamask = ~(u32)0;
  300. struct platform_device pxa_device_ficp = {
  301. .name = "pxa2xx-ir",
  302. .id = -1,
  303. .dev = {
  304. .dma_mask = &pxaficp_dmamask,
  305. .coherent_dma_mask = 0xffffffff,
  306. },
  307. };
  308. void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
  309. {
  310. pxa_register_device(&pxa_device_ficp, info);
  311. }
  312. static struct resource pxa_rtc_resources[] = {
  313. [0] = {
  314. .start = 0x40900000,
  315. .end = 0x40900000 + 0x3b,
  316. .flags = IORESOURCE_MEM,
  317. },
  318. [1] = {
  319. .start = IRQ_RTC1Hz,
  320. .end = IRQ_RTC1Hz,
  321. .flags = IORESOURCE_IRQ,
  322. },
  323. [2] = {
  324. .start = IRQ_RTCAlrm,
  325. .end = IRQ_RTCAlrm,
  326. .flags = IORESOURCE_IRQ,
  327. },
  328. };
  329. struct platform_device sa1100_device_rtc = {
  330. .name = "sa1100-rtc",
  331. .id = -1,
  332. };
  333. struct platform_device pxa_device_rtc = {
  334. .name = "pxa-rtc",
  335. .id = -1,
  336. .num_resources = ARRAY_SIZE(pxa_rtc_resources),
  337. .resource = pxa_rtc_resources,
  338. };
  339. static struct resource pxa_ac97_resources[] = {
  340. [0] = {
  341. .start = 0x40500000,
  342. .end = 0x40500000 + 0xfff,
  343. .flags = IORESOURCE_MEM,
  344. },
  345. [1] = {
  346. .start = IRQ_AC97,
  347. .end = IRQ_AC97,
  348. .flags = IORESOURCE_IRQ,
  349. },
  350. };
  351. static u64 pxa_ac97_dmamask = 0xffffffffUL;
  352. struct platform_device pxa_device_ac97 = {
  353. .name = "pxa2xx-ac97",
  354. .id = -1,
  355. .dev = {
  356. .dma_mask = &pxa_ac97_dmamask,
  357. .coherent_dma_mask = 0xffffffff,
  358. },
  359. .num_resources = ARRAY_SIZE(pxa_ac97_resources),
  360. .resource = pxa_ac97_resources,
  361. };
  362. void __init pxa_set_ac97_info(pxa2xx_audio_ops_t *ops)
  363. {
  364. pxa_register_device(&pxa_device_ac97, ops);
  365. }
  366. #ifdef CONFIG_PXA25x
  367. static struct resource pxa25x_resource_pwm0[] = {
  368. [0] = {
  369. .start = 0x40b00000,
  370. .end = 0x40b0000f,
  371. .flags = IORESOURCE_MEM,
  372. },
  373. };
  374. struct platform_device pxa25x_device_pwm0 = {
  375. .name = "pxa25x-pwm",
  376. .id = 0,
  377. .resource = pxa25x_resource_pwm0,
  378. .num_resources = ARRAY_SIZE(pxa25x_resource_pwm0),
  379. };
  380. static struct resource pxa25x_resource_pwm1[] = {
  381. [0] = {
  382. .start = 0x40c00000,
  383. .end = 0x40c0000f,
  384. .flags = IORESOURCE_MEM,
  385. },
  386. };
  387. struct platform_device pxa25x_device_pwm1 = {
  388. .name = "pxa25x-pwm",
  389. .id = 1,
  390. .resource = pxa25x_resource_pwm1,
  391. .num_resources = ARRAY_SIZE(pxa25x_resource_pwm1),
  392. };
  393. static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
  394. static struct resource pxa25x_resource_ssp[] = {
  395. [0] = {
  396. .start = 0x41000000,
  397. .end = 0x4100001f,
  398. .flags = IORESOURCE_MEM,
  399. },
  400. [1] = {
  401. .start = IRQ_SSP,
  402. .end = IRQ_SSP,
  403. .flags = IORESOURCE_IRQ,
  404. },
  405. [2] = {
  406. /* DRCMR for RX */
  407. .start = 13,
  408. .end = 13,
  409. .flags = IORESOURCE_DMA,
  410. },
  411. [3] = {
  412. /* DRCMR for TX */
  413. .start = 14,
  414. .end = 14,
  415. .flags = IORESOURCE_DMA,
  416. },
  417. };
  418. struct platform_device pxa25x_device_ssp = {
  419. .name = "pxa25x-ssp",
  420. .id = 0,
  421. .dev = {
  422. .dma_mask = &pxa25x_ssp_dma_mask,
  423. .coherent_dma_mask = DMA_BIT_MASK(32),
  424. },
  425. .resource = pxa25x_resource_ssp,
  426. .num_resources = ARRAY_SIZE(pxa25x_resource_ssp),
  427. };
  428. static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
  429. static struct resource pxa25x_resource_nssp[] = {
  430. [0] = {
  431. .start = 0x41400000,
  432. .end = 0x4140002f,
  433. .flags = IORESOURCE_MEM,
  434. },
  435. [1] = {
  436. .start = IRQ_NSSP,
  437. .end = IRQ_NSSP,
  438. .flags = IORESOURCE_IRQ,
  439. },
  440. [2] = {
  441. /* DRCMR for RX */
  442. .start = 15,
  443. .end = 15,
  444. .flags = IORESOURCE_DMA,
  445. },
  446. [3] = {
  447. /* DRCMR for TX */
  448. .start = 16,
  449. .end = 16,
  450. .flags = IORESOURCE_DMA,
  451. },
  452. };
  453. struct platform_device pxa25x_device_nssp = {
  454. .name = "pxa25x-nssp",
  455. .id = 1,
  456. .dev = {
  457. .dma_mask = &pxa25x_nssp_dma_mask,
  458. .coherent_dma_mask = DMA_BIT_MASK(32),
  459. },
  460. .resource = pxa25x_resource_nssp,
  461. .num_resources = ARRAY_SIZE(pxa25x_resource_nssp),
  462. };
  463. static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
  464. static struct resource pxa25x_resource_assp[] = {
  465. [0] = {
  466. .start = 0x41500000,
  467. .end = 0x4150002f,
  468. .flags = IORESOURCE_MEM,
  469. },
  470. [1] = {
  471. .start = IRQ_ASSP,
  472. .end = IRQ_ASSP,
  473. .flags = IORESOURCE_IRQ,
  474. },
  475. [2] = {
  476. /* DRCMR for RX */
  477. .start = 23,
  478. .end = 23,
  479. .flags = IORESOURCE_DMA,
  480. },
  481. [3] = {
  482. /* DRCMR for TX */
  483. .start = 24,
  484. .end = 24,
  485. .flags = IORESOURCE_DMA,
  486. },
  487. };
  488. struct platform_device pxa25x_device_assp = {
  489. /* ASSP is basically equivalent to NSSP */
  490. .name = "pxa25x-nssp",
  491. .id = 2,
  492. .dev = {
  493. .dma_mask = &pxa25x_assp_dma_mask,
  494. .coherent_dma_mask = DMA_BIT_MASK(32),
  495. },
  496. .resource = pxa25x_resource_assp,
  497. .num_resources = ARRAY_SIZE(pxa25x_resource_assp),
  498. };
  499. #endif /* CONFIG_PXA25x */
  500. #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
  501. static struct resource pxa27x_resource_keypad[] = {
  502. [0] = {
  503. .start = 0x41500000,
  504. .end = 0x4150004c,
  505. .flags = IORESOURCE_MEM,
  506. },
  507. [1] = {
  508. .start = IRQ_KEYPAD,
  509. .end = IRQ_KEYPAD,
  510. .flags = IORESOURCE_IRQ,
  511. },
  512. };
  513. struct platform_device pxa27x_device_keypad = {
  514. .name = "pxa27x-keypad",
  515. .id = -1,
  516. .resource = pxa27x_resource_keypad,
  517. .num_resources = ARRAY_SIZE(pxa27x_resource_keypad),
  518. };
  519. void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
  520. {
  521. pxa_register_device(&pxa27x_device_keypad, info);
  522. }
  523. static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
  524. static struct resource pxa27x_resource_ohci[] = {
  525. [0] = {
  526. .start = 0x4C000000,
  527. .end = 0x4C00ff6f,
  528. .flags = IORESOURCE_MEM,
  529. },
  530. [1] = {
  531. .start = IRQ_USBH1,
  532. .end = IRQ_USBH1,
  533. .flags = IORESOURCE_IRQ,
  534. },
  535. };
  536. struct platform_device pxa27x_device_ohci = {
  537. .name = "pxa27x-ohci",
  538. .id = -1,
  539. .dev = {
  540. .dma_mask = &pxa27x_ohci_dma_mask,
  541. .coherent_dma_mask = DMA_BIT_MASK(32),
  542. },
  543. .num_resources = ARRAY_SIZE(pxa27x_resource_ohci),
  544. .resource = pxa27x_resource_ohci,
  545. };
  546. void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
  547. {
  548. pxa_register_device(&pxa27x_device_ohci, info);
  549. }
  550. static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
  551. static struct resource pxa27x_resource_ssp1[] = {
  552. [0] = {
  553. .start = 0x41000000,
  554. .end = 0x4100003f,
  555. .flags = IORESOURCE_MEM,
  556. },
  557. [1] = {
  558. .start = IRQ_SSP,
  559. .end = IRQ_SSP,
  560. .flags = IORESOURCE_IRQ,
  561. },
  562. [2] = {
  563. /* DRCMR for RX */
  564. .start = 13,
  565. .end = 13,
  566. .flags = IORESOURCE_DMA,
  567. },
  568. [3] = {
  569. /* DRCMR for TX */
  570. .start = 14,
  571. .end = 14,
  572. .flags = IORESOURCE_DMA,
  573. },
  574. };
  575. struct platform_device pxa27x_device_ssp1 = {
  576. .name = "pxa27x-ssp",
  577. .id = 0,
  578. .dev = {
  579. .dma_mask = &pxa27x_ssp1_dma_mask,
  580. .coherent_dma_mask = DMA_BIT_MASK(32),
  581. },
  582. .resource = pxa27x_resource_ssp1,
  583. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
  584. };
  585. static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
  586. static struct resource pxa27x_resource_ssp2[] = {
  587. [0] = {
  588. .start = 0x41700000,
  589. .end = 0x4170003f,
  590. .flags = IORESOURCE_MEM,
  591. },
  592. [1] = {
  593. .start = IRQ_SSP2,
  594. .end = IRQ_SSP2,
  595. .flags = IORESOURCE_IRQ,
  596. },
  597. [2] = {
  598. /* DRCMR for RX */
  599. .start = 15,
  600. .end = 15,
  601. .flags = IORESOURCE_DMA,
  602. },
  603. [3] = {
  604. /* DRCMR for TX */
  605. .start = 16,
  606. .end = 16,
  607. .flags = IORESOURCE_DMA,
  608. },
  609. };
  610. struct platform_device pxa27x_device_ssp2 = {
  611. .name = "pxa27x-ssp",
  612. .id = 1,
  613. .dev = {
  614. .dma_mask = &pxa27x_ssp2_dma_mask,
  615. .coherent_dma_mask = DMA_BIT_MASK(32),
  616. },
  617. .resource = pxa27x_resource_ssp2,
  618. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
  619. };
  620. static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
  621. static struct resource pxa27x_resource_ssp3[] = {
  622. [0] = {
  623. .start = 0x41900000,
  624. .end = 0x4190003f,
  625. .flags = IORESOURCE_MEM,
  626. },
  627. [1] = {
  628. .start = IRQ_SSP3,
  629. .end = IRQ_SSP3,
  630. .flags = IORESOURCE_IRQ,
  631. },
  632. [2] = {
  633. /* DRCMR for RX */
  634. .start = 66,
  635. .end = 66,
  636. .flags = IORESOURCE_DMA,
  637. },
  638. [3] = {
  639. /* DRCMR for TX */
  640. .start = 67,
  641. .end = 67,
  642. .flags = IORESOURCE_DMA,
  643. },
  644. };
  645. struct platform_device pxa27x_device_ssp3 = {
  646. .name = "pxa27x-ssp",
  647. .id = 2,
  648. .dev = {
  649. .dma_mask = &pxa27x_ssp3_dma_mask,
  650. .coherent_dma_mask = DMA_BIT_MASK(32),
  651. },
  652. .resource = pxa27x_resource_ssp3,
  653. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
  654. };
  655. static struct resource pxa27x_resource_pwm0[] = {
  656. [0] = {
  657. .start = 0x40b00000,
  658. .end = 0x40b0001f,
  659. .flags = IORESOURCE_MEM,
  660. },
  661. };
  662. struct platform_device pxa27x_device_pwm0 = {
  663. .name = "pxa27x-pwm",
  664. .id = 0,
  665. .resource = pxa27x_resource_pwm0,
  666. .num_resources = ARRAY_SIZE(pxa27x_resource_pwm0),
  667. };
  668. static struct resource pxa27x_resource_pwm1[] = {
  669. [0] = {
  670. .start = 0x40c00000,
  671. .end = 0x40c0001f,
  672. .flags = IORESOURCE_MEM,
  673. },
  674. };
  675. struct platform_device pxa27x_device_pwm1 = {
  676. .name = "pxa27x-pwm",
  677. .id = 1,
  678. .resource = pxa27x_resource_pwm1,
  679. .num_resources = ARRAY_SIZE(pxa27x_resource_pwm1),
  680. };
  681. static struct resource pxa27x_resource_camera[] = {
  682. [0] = {
  683. .start = 0x50000000,
  684. .end = 0x50000fff,
  685. .flags = IORESOURCE_MEM,
  686. },
  687. [1] = {
  688. .start = IRQ_CAMERA,
  689. .end = IRQ_CAMERA,
  690. .flags = IORESOURCE_IRQ,
  691. },
  692. };
  693. static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
  694. static struct platform_device pxa27x_device_camera = {
  695. .name = "pxa27x-camera",
  696. .id = 0, /* This is used to put cameras on this interface */
  697. .dev = {
  698. .dma_mask = &pxa27x_dma_mask_camera,
  699. .coherent_dma_mask = 0xffffffff,
  700. },
  701. .num_resources = ARRAY_SIZE(pxa27x_resource_camera),
  702. .resource = pxa27x_resource_camera,
  703. };
  704. void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
  705. {
  706. pxa_register_device(&pxa27x_device_camera, info);
  707. }
  708. #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
  709. #ifdef CONFIG_PXA3xx
  710. static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
  711. static struct resource pxa3xx_resource_ssp4[] = {
  712. [0] = {
  713. .start = 0x41a00000,
  714. .end = 0x41a0003f,
  715. .flags = IORESOURCE_MEM,
  716. },
  717. [1] = {
  718. .start = IRQ_SSP4,
  719. .end = IRQ_SSP4,
  720. .flags = IORESOURCE_IRQ,
  721. },
  722. [2] = {
  723. /* DRCMR for RX */
  724. .start = 2,
  725. .end = 2,
  726. .flags = IORESOURCE_DMA,
  727. },
  728. [3] = {
  729. /* DRCMR for TX */
  730. .start = 3,
  731. .end = 3,
  732. .flags = IORESOURCE_DMA,
  733. },
  734. };
  735. struct platform_device pxa3xx_device_ssp4 = {
  736. /* PXA3xx SSP is basically equivalent to PXA27x */
  737. .name = "pxa27x-ssp",
  738. .id = 3,
  739. .dev = {
  740. .dma_mask = &pxa3xx_ssp4_dma_mask,
  741. .coherent_dma_mask = DMA_BIT_MASK(32),
  742. },
  743. .resource = pxa3xx_resource_ssp4,
  744. .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4),
  745. };
  746. static struct resource pxa3xx_resources_mci2[] = {
  747. [0] = {
  748. .start = 0x42000000,
  749. .end = 0x42000fff,
  750. .flags = IORESOURCE_MEM,
  751. },
  752. [1] = {
  753. .start = IRQ_MMC2,
  754. .end = IRQ_MMC2,
  755. .flags = IORESOURCE_IRQ,
  756. },
  757. [2] = {
  758. .start = 93,
  759. .end = 93,
  760. .flags = IORESOURCE_DMA,
  761. },
  762. [3] = {
  763. .start = 94,
  764. .end = 94,
  765. .flags = IORESOURCE_DMA,
  766. },
  767. };
  768. struct platform_device pxa3xx_device_mci2 = {
  769. .name = "pxa2xx-mci",
  770. .id = 1,
  771. .dev = {
  772. .dma_mask = &pxamci_dmamask,
  773. .coherent_dma_mask = 0xffffffff,
  774. },
  775. .num_resources = ARRAY_SIZE(pxa3xx_resources_mci2),
  776. .resource = pxa3xx_resources_mci2,
  777. };
  778. void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info)
  779. {
  780. pxa_register_device(&pxa3xx_device_mci2, info);
  781. }
  782. static struct resource pxa3xx_resources_mci3[] = {
  783. [0] = {
  784. .start = 0x42500000,
  785. .end = 0x42500fff,
  786. .flags = IORESOURCE_MEM,
  787. },
  788. [1] = {
  789. .start = IRQ_MMC3,
  790. .end = IRQ_MMC3,
  791. .flags = IORESOURCE_IRQ,
  792. },
  793. [2] = {
  794. .start = 100,
  795. .end = 100,
  796. .flags = IORESOURCE_DMA,
  797. },
  798. [3] = {
  799. .start = 101,
  800. .end = 101,
  801. .flags = IORESOURCE_DMA,
  802. },
  803. };
  804. struct platform_device pxa3xx_device_mci3 = {
  805. .name = "pxa2xx-mci",
  806. .id = 2,
  807. .dev = {
  808. .dma_mask = &pxamci_dmamask,
  809. .coherent_dma_mask = 0xffffffff,
  810. },
  811. .num_resources = ARRAY_SIZE(pxa3xx_resources_mci3),
  812. .resource = pxa3xx_resources_mci3,
  813. };
  814. void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
  815. {
  816. pxa_register_device(&pxa3xx_device_mci3, info);
  817. }
  818. static struct resource pxa3xx_resources_nand[] = {
  819. [0] = {
  820. .start = 0x43100000,
  821. .end = 0x43100053,
  822. .flags = IORESOURCE_MEM,
  823. },
  824. [1] = {
  825. .start = IRQ_NAND,
  826. .end = IRQ_NAND,
  827. .flags = IORESOURCE_IRQ,
  828. },
  829. [2] = {
  830. /* DRCMR for Data DMA */
  831. .start = 97,
  832. .end = 97,
  833. .flags = IORESOURCE_DMA,
  834. },
  835. [3] = {
  836. /* DRCMR for Command DMA */
  837. .start = 99,
  838. .end = 99,
  839. .flags = IORESOURCE_DMA,
  840. },
  841. };
  842. static u64 pxa3xx_nand_dma_mask = DMA_BIT_MASK(32);
  843. struct platform_device pxa3xx_device_nand = {
  844. .name = "pxa3xx-nand",
  845. .id = -1,
  846. .dev = {
  847. .dma_mask = &pxa3xx_nand_dma_mask,
  848. .coherent_dma_mask = DMA_BIT_MASK(32),
  849. },
  850. .num_resources = ARRAY_SIZE(pxa3xx_resources_nand),
  851. .resource = pxa3xx_resources_nand,
  852. };
  853. void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info)
  854. {
  855. pxa_register_device(&pxa3xx_device_nand, info);
  856. }
  857. static struct resource pxa3xx_resources_gcu[] = {
  858. {
  859. .start = 0x54000000,
  860. .end = 0x54000fff,
  861. .flags = IORESOURCE_MEM,
  862. },
  863. {
  864. .start = IRQ_GCU,
  865. .end = IRQ_GCU,
  866. .flags = IORESOURCE_IRQ,
  867. },
  868. };
  869. static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32);
  870. struct platform_device pxa3xx_device_gcu = {
  871. .name = "pxa3xx-gcu",
  872. .id = -1,
  873. .num_resources = ARRAY_SIZE(pxa3xx_resources_gcu),
  874. .resource = pxa3xx_resources_gcu,
  875. .dev = {
  876. .dma_mask = &pxa3xx_gcu_dmamask,
  877. .coherent_dma_mask = 0xffffffff,
  878. },
  879. };
  880. #endif /* CONFIG_PXA3xx */
  881. /* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1.
  882. * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */
  883. void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info)
  884. {
  885. struct platform_device *pd;
  886. pd = platform_device_alloc("pxa2xx-spi", id);
  887. if (pd == NULL) {
  888. printk(KERN_ERR "pxa2xx-spi: failed to allocate device id %d\n",
  889. id);
  890. return;
  891. }
  892. pd->dev.platform_data = info;
  893. platform_device_add(pd);
  894. }