ql4_mbx.c 59 KB

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  1. /*
  2. * QLogic iSCSI HBA Driver
  3. * Copyright (c) 2003-2012 QLogic Corporation
  4. *
  5. * See LICENSE.qla4xxx for copyright and licensing details.
  6. */
  7. #include "ql4_def.h"
  8. #include "ql4_glbl.h"
  9. #include "ql4_dbg.h"
  10. #include "ql4_inline.h"
  11. #include "ql4_version.h"
  12. void qla4xxx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd,
  13. int in_count)
  14. {
  15. int i;
  16. /* Load all mailbox registers, except mailbox 0. */
  17. for (i = 1; i < in_count; i++)
  18. writel(mbx_cmd[i], &ha->reg->mailbox[i]);
  19. /* Wakeup firmware */
  20. writel(mbx_cmd[0], &ha->reg->mailbox[0]);
  21. readl(&ha->reg->mailbox[0]);
  22. writel(set_rmask(CSR_INTR_RISC), &ha->reg->ctrl_status);
  23. readl(&ha->reg->ctrl_status);
  24. }
  25. void qla4xxx_process_mbox_intr(struct scsi_qla_host *ha, int out_count)
  26. {
  27. int intr_status;
  28. intr_status = readl(&ha->reg->ctrl_status);
  29. if (intr_status & INTR_PENDING) {
  30. /*
  31. * Service the interrupt.
  32. * The ISR will save the mailbox status registers
  33. * to a temporary storage location in the adapter structure.
  34. */
  35. ha->mbox_status_count = out_count;
  36. ha->isp_ops->interrupt_service_routine(ha, intr_status);
  37. }
  38. }
  39. /**
  40. * qla4xxx_is_intr_poll_mode – Are we allowed to poll for interrupts?
  41. * @ha: Pointer to host adapter structure.
  42. * @ret: 1=polling mode, 0=non-polling mode
  43. **/
  44. static int qla4xxx_is_intr_poll_mode(struct scsi_qla_host *ha)
  45. {
  46. int rval = 1;
  47. if (is_qla8032(ha)) {
  48. if (test_bit(AF_IRQ_ATTACHED, &ha->flags) &&
  49. test_bit(AF_83XX_MBOX_INTR_ON, &ha->flags))
  50. rval = 0;
  51. } else {
  52. if (test_bit(AF_IRQ_ATTACHED, &ha->flags) &&
  53. test_bit(AF_INTERRUPTS_ON, &ha->flags) &&
  54. test_bit(AF_ONLINE, &ha->flags) &&
  55. !test_bit(AF_HA_REMOVAL, &ha->flags))
  56. rval = 0;
  57. }
  58. return rval;
  59. }
  60. /**
  61. * qla4xxx_mailbox_command - issues mailbox commands
  62. * @ha: Pointer to host adapter structure.
  63. * @inCount: number of mailbox registers to load.
  64. * @outCount: number of mailbox registers to return.
  65. * @mbx_cmd: data pointer for mailbox in registers.
  66. * @mbx_sts: data pointer for mailbox out registers.
  67. *
  68. * This routine issue mailbox commands and waits for completion.
  69. * If outCount is 0, this routine completes successfully WITHOUT waiting
  70. * for the mailbox command to complete.
  71. **/
  72. int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount,
  73. uint8_t outCount, uint32_t *mbx_cmd,
  74. uint32_t *mbx_sts)
  75. {
  76. int status = QLA_ERROR;
  77. uint8_t i;
  78. u_long wait_count;
  79. unsigned long flags = 0;
  80. uint32_t dev_state;
  81. /* Make sure that pointers are valid */
  82. if (!mbx_cmd || !mbx_sts) {
  83. DEBUG2(printk("scsi%ld: %s: Invalid mbx_cmd or mbx_sts "
  84. "pointer\n", ha->host_no, __func__));
  85. return status;
  86. }
  87. if (is_qla40XX(ha)) {
  88. if (test_bit(AF_HA_REMOVAL, &ha->flags)) {
  89. DEBUG2(ql4_printk(KERN_WARNING, ha, "scsi%ld: %s: "
  90. "prematurely completing mbx cmd as "
  91. "adapter removal detected\n",
  92. ha->host_no, __func__));
  93. return status;
  94. }
  95. }
  96. if ((is_aer_supported(ha)) &&
  97. (test_bit(AF_PCI_CHANNEL_IO_PERM_FAILURE, &ha->flags))) {
  98. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: Perm failure on EEH, "
  99. "timeout MBX Exiting.\n", ha->host_no, __func__));
  100. return status;
  101. }
  102. /* Mailbox code active */
  103. wait_count = MBOX_TOV * 100;
  104. while (wait_count--) {
  105. mutex_lock(&ha->mbox_sem);
  106. if (!test_bit(AF_MBOX_COMMAND, &ha->flags)) {
  107. set_bit(AF_MBOX_COMMAND, &ha->flags);
  108. mutex_unlock(&ha->mbox_sem);
  109. break;
  110. }
  111. mutex_unlock(&ha->mbox_sem);
  112. if (!wait_count) {
  113. DEBUG2(printk("scsi%ld: %s: mbox_sem failed\n",
  114. ha->host_no, __func__));
  115. return status;
  116. }
  117. msleep(10);
  118. }
  119. if (is_qla80XX(ha)) {
  120. if (test_bit(AF_FW_RECOVERY, &ha->flags)) {
  121. DEBUG2(ql4_printk(KERN_WARNING, ha,
  122. "scsi%ld: %s: prematurely completing mbx cmd as firmware recovery detected\n",
  123. ha->host_no, __func__));
  124. goto mbox_exit;
  125. }
  126. /* Do not send any mbx cmd if h/w is in failed state*/
  127. ha->isp_ops->idc_lock(ha);
  128. dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE);
  129. ha->isp_ops->idc_unlock(ha);
  130. if (dev_state == QLA8XXX_DEV_FAILED) {
  131. ql4_printk(KERN_WARNING, ha,
  132. "scsi%ld: %s: H/W is in failed state, do not send any mailbox commands\n",
  133. ha->host_no, __func__);
  134. goto mbox_exit;
  135. }
  136. }
  137. spin_lock_irqsave(&ha->hardware_lock, flags);
  138. ha->mbox_status_count = outCount;
  139. for (i = 0; i < outCount; i++)
  140. ha->mbox_status[i] = 0;
  141. /* Queue the mailbox command to the firmware */
  142. ha->isp_ops->queue_mailbox_command(ha, mbx_cmd, inCount);
  143. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  144. /* Wait for completion */
  145. /*
  146. * If we don't want status, don't wait for the mailbox command to
  147. * complete. For example, MBOX_CMD_RESET_FW doesn't return status,
  148. * you must poll the inbound Interrupt Mask for completion.
  149. */
  150. if (outCount == 0) {
  151. status = QLA_SUCCESS;
  152. goto mbox_exit;
  153. }
  154. /*
  155. * Wait for completion: Poll or completion queue
  156. */
  157. if (qla4xxx_is_intr_poll_mode(ha)) {
  158. /* Poll for command to complete */
  159. wait_count = jiffies + MBOX_TOV * HZ;
  160. while (test_bit(AF_MBOX_COMMAND_DONE, &ha->flags) == 0) {
  161. if (time_after_eq(jiffies, wait_count))
  162. break;
  163. /*
  164. * Service the interrupt.
  165. * The ISR will save the mailbox status registers
  166. * to a temporary storage location in the adapter
  167. * structure.
  168. */
  169. spin_lock_irqsave(&ha->hardware_lock, flags);
  170. ha->isp_ops->process_mailbox_interrupt(ha, outCount);
  171. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  172. msleep(10);
  173. }
  174. } else {
  175. /* Do not poll for completion. Use completion queue */
  176. set_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
  177. wait_for_completion_timeout(&ha->mbx_intr_comp, MBOX_TOV * HZ);
  178. clear_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
  179. }
  180. /* Check for mailbox timeout. */
  181. if (!test_bit(AF_MBOX_COMMAND_DONE, &ha->flags)) {
  182. if (is_qla80XX(ha) &&
  183. test_bit(AF_FW_RECOVERY, &ha->flags)) {
  184. DEBUG2(ql4_printk(KERN_INFO, ha,
  185. "scsi%ld: %s: prematurely completing mbx cmd as "
  186. "firmware recovery detected\n",
  187. ha->host_no, __func__));
  188. goto mbox_exit;
  189. }
  190. DEBUG2(printk("scsi%ld: Mailbox Cmd 0x%08X timed out ...,"
  191. " Scheduling Adapter Reset\n", ha->host_no,
  192. mbx_cmd[0]));
  193. ha->mailbox_timeout_count++;
  194. mbx_sts[0] = (-1);
  195. set_bit(DPC_RESET_HA, &ha->dpc_flags);
  196. if (is_qla8022(ha)) {
  197. ql4_printk(KERN_INFO, ha,
  198. "disabling pause transmit on port 0 & 1.\n");
  199. qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98,
  200. CRB_NIU_XG_PAUSE_CTL_P0 |
  201. CRB_NIU_XG_PAUSE_CTL_P1);
  202. } else if (is_qla8032(ha)) {
  203. ql4_printk(KERN_INFO, ha, " %s: disabling pause transmit on port 0 & 1.\n",
  204. __func__);
  205. qla4_83xx_disable_pause(ha);
  206. }
  207. goto mbox_exit;
  208. }
  209. /*
  210. * Copy the mailbox out registers to the caller's mailbox in/out
  211. * structure.
  212. */
  213. spin_lock_irqsave(&ha->hardware_lock, flags);
  214. for (i = 0; i < outCount; i++)
  215. mbx_sts[i] = ha->mbox_status[i];
  216. /* Set return status and error flags (if applicable). */
  217. switch (ha->mbox_status[0]) {
  218. case MBOX_STS_COMMAND_COMPLETE:
  219. status = QLA_SUCCESS;
  220. break;
  221. case MBOX_STS_INTERMEDIATE_COMPLETION:
  222. status = QLA_SUCCESS;
  223. break;
  224. case MBOX_STS_BUSY:
  225. DEBUG2( printk("scsi%ld: %s: Cmd = %08X, ISP BUSY\n",
  226. ha->host_no, __func__, mbx_cmd[0]));
  227. ha->mailbox_timeout_count++;
  228. break;
  229. default:
  230. DEBUG2(printk("scsi%ld: %s: **** FAILED, cmd = %08X, "
  231. "sts = %08X ****\n", ha->host_no, __func__,
  232. mbx_cmd[0], mbx_sts[0]));
  233. break;
  234. }
  235. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  236. mbox_exit:
  237. mutex_lock(&ha->mbox_sem);
  238. clear_bit(AF_MBOX_COMMAND, &ha->flags);
  239. mutex_unlock(&ha->mbox_sem);
  240. clear_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
  241. return status;
  242. }
  243. /**
  244. * qla4xxx_get_minidump_template - Get the firmware template
  245. * @ha: Pointer to host adapter structure.
  246. * @phys_addr: dma address for template
  247. *
  248. * Obtain the minidump template from firmware during initialization
  249. * as it may not be available when minidump is desired.
  250. **/
  251. int qla4xxx_get_minidump_template(struct scsi_qla_host *ha,
  252. dma_addr_t phys_addr)
  253. {
  254. uint32_t mbox_cmd[MBOX_REG_COUNT];
  255. uint32_t mbox_sts[MBOX_REG_COUNT];
  256. int status;
  257. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  258. memset(&mbox_sts, 0, sizeof(mbox_sts));
  259. mbox_cmd[0] = MBOX_CMD_MINIDUMP;
  260. mbox_cmd[1] = MINIDUMP_GET_TMPLT_SUBCOMMAND;
  261. mbox_cmd[2] = LSDW(phys_addr);
  262. mbox_cmd[3] = MSDW(phys_addr);
  263. mbox_cmd[4] = ha->fw_dump_tmplt_size;
  264. mbox_cmd[5] = 0;
  265. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0],
  266. &mbox_sts[0]);
  267. if (status != QLA_SUCCESS) {
  268. DEBUG2(ql4_printk(KERN_INFO, ha,
  269. "scsi%ld: %s: Cmd = %08X, mbx[0] = 0x%04x, mbx[1] = 0x%04x\n",
  270. ha->host_no, __func__, mbox_cmd[0],
  271. mbox_sts[0], mbox_sts[1]));
  272. }
  273. return status;
  274. }
  275. /**
  276. * qla4xxx_req_template_size - Get minidump template size from firmware.
  277. * @ha: Pointer to host adapter structure.
  278. **/
  279. int qla4xxx_req_template_size(struct scsi_qla_host *ha)
  280. {
  281. uint32_t mbox_cmd[MBOX_REG_COUNT];
  282. uint32_t mbox_sts[MBOX_REG_COUNT];
  283. int status;
  284. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  285. memset(&mbox_sts, 0, sizeof(mbox_sts));
  286. mbox_cmd[0] = MBOX_CMD_MINIDUMP;
  287. mbox_cmd[1] = MINIDUMP_GET_SIZE_SUBCOMMAND;
  288. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 8, &mbox_cmd[0],
  289. &mbox_sts[0]);
  290. if (status == QLA_SUCCESS) {
  291. ha->fw_dump_tmplt_size = mbox_sts[1];
  292. DEBUG2(ql4_printk(KERN_INFO, ha,
  293. "%s: sts[0]=0x%04x, template size=0x%04x, size_cm_02=0x%04x, size_cm_04=0x%04x, size_cm_08=0x%04x, size_cm_10=0x%04x, size_cm_FF=0x%04x, version=0x%04x\n",
  294. __func__, mbox_sts[0], mbox_sts[1],
  295. mbox_sts[2], mbox_sts[3], mbox_sts[4],
  296. mbox_sts[5], mbox_sts[6], mbox_sts[7]));
  297. if (ha->fw_dump_tmplt_size == 0)
  298. status = QLA_ERROR;
  299. } else {
  300. ql4_printk(KERN_WARNING, ha,
  301. "%s: Error sts[0]=0x%04x, mbx[1]=0x%04x\n",
  302. __func__, mbox_sts[0], mbox_sts[1]);
  303. status = QLA_ERROR;
  304. }
  305. return status;
  306. }
  307. void qla4xxx_mailbox_premature_completion(struct scsi_qla_host *ha)
  308. {
  309. set_bit(AF_FW_RECOVERY, &ha->flags);
  310. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: set FW RECOVERY!\n",
  311. ha->host_no, __func__);
  312. if (test_bit(AF_MBOX_COMMAND, &ha->flags)) {
  313. if (test_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags)) {
  314. complete(&ha->mbx_intr_comp);
  315. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
  316. "recovery, doing premature completion of "
  317. "mbx cmd\n", ha->host_no, __func__);
  318. } else {
  319. set_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
  320. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
  321. "recovery, doing premature completion of "
  322. "polling mbx cmd\n", ha->host_no, __func__);
  323. }
  324. }
  325. }
  326. static uint8_t
  327. qla4xxx_set_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  328. uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
  329. {
  330. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  331. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  332. if (is_qla8022(ha))
  333. qla4_82xx_wr_32(ha, ha->nx_db_wr_ptr, 0);
  334. mbox_cmd[0] = MBOX_CMD_INITIALIZE_FIRMWARE;
  335. mbox_cmd[1] = 0;
  336. mbox_cmd[2] = LSDW(init_fw_cb_dma);
  337. mbox_cmd[3] = MSDW(init_fw_cb_dma);
  338. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  339. mbox_cmd[5] = (IFCB_VER_MAX << 8) | IFCB_VER_MIN;
  340. if (qla4xxx_mailbox_command(ha, 6, 6, mbox_cmd, mbox_sts) !=
  341. QLA_SUCCESS) {
  342. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
  343. "MBOX_CMD_INITIALIZE_FIRMWARE"
  344. " failed w/ status %04X\n",
  345. ha->host_no, __func__, mbox_sts[0]));
  346. return QLA_ERROR;
  347. }
  348. return QLA_SUCCESS;
  349. }
  350. uint8_t
  351. qla4xxx_get_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  352. uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
  353. {
  354. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  355. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  356. mbox_cmd[0] = MBOX_CMD_GET_INIT_FW_CTRL_BLOCK;
  357. mbox_cmd[2] = LSDW(init_fw_cb_dma);
  358. mbox_cmd[3] = MSDW(init_fw_cb_dma);
  359. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  360. if (qla4xxx_mailbox_command(ha, 5, 5, mbox_cmd, mbox_sts) !=
  361. QLA_SUCCESS) {
  362. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
  363. "MBOX_CMD_GET_INIT_FW_CTRL_BLOCK"
  364. " failed w/ status %04X\n",
  365. ha->host_no, __func__, mbox_sts[0]));
  366. return QLA_ERROR;
  367. }
  368. return QLA_SUCCESS;
  369. }
  370. static void
  371. qla4xxx_update_local_ip(struct scsi_qla_host *ha,
  372. struct addr_ctrl_blk *init_fw_cb)
  373. {
  374. ha->ip_config.tcp_options = le16_to_cpu(init_fw_cb->ipv4_tcp_opts);
  375. ha->ip_config.ipv4_options = le16_to_cpu(init_fw_cb->ipv4_ip_opts);
  376. ha->ip_config.ipv4_addr_state =
  377. le16_to_cpu(init_fw_cb->ipv4_addr_state);
  378. ha->ip_config.eth_mtu_size =
  379. le16_to_cpu(init_fw_cb->eth_mtu_size);
  380. ha->ip_config.ipv4_port = le16_to_cpu(init_fw_cb->ipv4_port);
  381. if (ha->acb_version == ACB_SUPPORTED) {
  382. ha->ip_config.ipv6_options = le16_to_cpu(init_fw_cb->ipv6_opts);
  383. ha->ip_config.ipv6_addl_options =
  384. le16_to_cpu(init_fw_cb->ipv6_addtl_opts);
  385. }
  386. /* Save IPv4 Address Info */
  387. memcpy(ha->ip_config.ip_address, init_fw_cb->ipv4_addr,
  388. min(sizeof(ha->ip_config.ip_address),
  389. sizeof(init_fw_cb->ipv4_addr)));
  390. memcpy(ha->ip_config.subnet_mask, init_fw_cb->ipv4_subnet,
  391. min(sizeof(ha->ip_config.subnet_mask),
  392. sizeof(init_fw_cb->ipv4_subnet)));
  393. memcpy(ha->ip_config.gateway, init_fw_cb->ipv4_gw_addr,
  394. min(sizeof(ha->ip_config.gateway),
  395. sizeof(init_fw_cb->ipv4_gw_addr)));
  396. ha->ip_config.ipv4_vlan_tag = be16_to_cpu(init_fw_cb->ipv4_vlan_tag);
  397. if (is_ipv6_enabled(ha)) {
  398. /* Save IPv6 Address */
  399. ha->ip_config.ipv6_link_local_state =
  400. le16_to_cpu(init_fw_cb->ipv6_lnk_lcl_addr_state);
  401. ha->ip_config.ipv6_addr0_state =
  402. le16_to_cpu(init_fw_cb->ipv6_addr0_state);
  403. ha->ip_config.ipv6_addr1_state =
  404. le16_to_cpu(init_fw_cb->ipv6_addr1_state);
  405. ha->ip_config.ipv6_default_router_state =
  406. le16_to_cpu(init_fw_cb->ipv6_dflt_rtr_state);
  407. ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[0] = 0xFE;
  408. ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[1] = 0x80;
  409. memcpy(&ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[8],
  410. init_fw_cb->ipv6_if_id,
  411. min(sizeof(ha->ip_config.ipv6_link_local_addr)/2,
  412. sizeof(init_fw_cb->ipv6_if_id)));
  413. memcpy(&ha->ip_config.ipv6_addr0, init_fw_cb->ipv6_addr0,
  414. min(sizeof(ha->ip_config.ipv6_addr0),
  415. sizeof(init_fw_cb->ipv6_addr0)));
  416. memcpy(&ha->ip_config.ipv6_addr1, init_fw_cb->ipv6_addr1,
  417. min(sizeof(ha->ip_config.ipv6_addr1),
  418. sizeof(init_fw_cb->ipv6_addr1)));
  419. memcpy(&ha->ip_config.ipv6_default_router_addr,
  420. init_fw_cb->ipv6_dflt_rtr_addr,
  421. min(sizeof(ha->ip_config.ipv6_default_router_addr),
  422. sizeof(init_fw_cb->ipv6_dflt_rtr_addr)));
  423. ha->ip_config.ipv6_vlan_tag =
  424. be16_to_cpu(init_fw_cb->ipv6_vlan_tag);
  425. ha->ip_config.ipv6_port = le16_to_cpu(init_fw_cb->ipv6_port);
  426. }
  427. }
  428. uint8_t
  429. qla4xxx_update_local_ifcb(struct scsi_qla_host *ha,
  430. uint32_t *mbox_cmd,
  431. uint32_t *mbox_sts,
  432. struct addr_ctrl_blk *init_fw_cb,
  433. dma_addr_t init_fw_cb_dma)
  434. {
  435. if (qla4xxx_get_ifcb(ha, mbox_cmd, mbox_sts, init_fw_cb_dma)
  436. != QLA_SUCCESS) {
  437. DEBUG2(printk(KERN_WARNING
  438. "scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
  439. ha->host_no, __func__));
  440. return QLA_ERROR;
  441. }
  442. DEBUG2(qla4xxx_dump_buffer(init_fw_cb, sizeof(struct addr_ctrl_blk)));
  443. /* Save some info in adapter structure. */
  444. ha->acb_version = init_fw_cb->acb_version;
  445. ha->firmware_options = le16_to_cpu(init_fw_cb->fw_options);
  446. ha->heartbeat_interval = init_fw_cb->hb_interval;
  447. memcpy(ha->name_string, init_fw_cb->iscsi_name,
  448. min(sizeof(ha->name_string),
  449. sizeof(init_fw_cb->iscsi_name)));
  450. ha->def_timeout = le16_to_cpu(init_fw_cb->def_timeout);
  451. /*memcpy(ha->alias, init_fw_cb->Alias,
  452. min(sizeof(ha->alias), sizeof(init_fw_cb->Alias)));*/
  453. qla4xxx_update_local_ip(ha, init_fw_cb);
  454. return QLA_SUCCESS;
  455. }
  456. /**
  457. * qla4xxx_initialize_fw_cb - initializes firmware control block.
  458. * @ha: Pointer to host adapter structure.
  459. **/
  460. int qla4xxx_initialize_fw_cb(struct scsi_qla_host * ha)
  461. {
  462. struct addr_ctrl_blk *init_fw_cb;
  463. dma_addr_t init_fw_cb_dma;
  464. uint32_t mbox_cmd[MBOX_REG_COUNT];
  465. uint32_t mbox_sts[MBOX_REG_COUNT];
  466. int status = QLA_ERROR;
  467. init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
  468. sizeof(struct addr_ctrl_blk),
  469. &init_fw_cb_dma, GFP_KERNEL);
  470. if (init_fw_cb == NULL) {
  471. DEBUG2(printk("scsi%ld: %s: Unable to alloc init_cb\n",
  472. ha->host_no, __func__));
  473. goto exit_init_fw_cb_no_free;
  474. }
  475. memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk));
  476. /* Get Initialize Firmware Control Block. */
  477. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  478. memset(&mbox_sts, 0, sizeof(mbox_sts));
  479. if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
  480. QLA_SUCCESS) {
  481. dma_free_coherent(&ha->pdev->dev,
  482. sizeof(struct addr_ctrl_blk),
  483. init_fw_cb, init_fw_cb_dma);
  484. goto exit_init_fw_cb;
  485. }
  486. /* Initialize request and response queues. */
  487. qla4xxx_init_rings(ha);
  488. /* Fill in the request and response queue information. */
  489. init_fw_cb->rqq_consumer_idx = cpu_to_le16(ha->request_out);
  490. init_fw_cb->compq_producer_idx = cpu_to_le16(ha->response_in);
  491. init_fw_cb->rqq_len = __constant_cpu_to_le16(REQUEST_QUEUE_DEPTH);
  492. init_fw_cb->compq_len = __constant_cpu_to_le16(RESPONSE_QUEUE_DEPTH);
  493. init_fw_cb->rqq_addr_lo = cpu_to_le32(LSDW(ha->request_dma));
  494. init_fw_cb->rqq_addr_hi = cpu_to_le32(MSDW(ha->request_dma));
  495. init_fw_cb->compq_addr_lo = cpu_to_le32(LSDW(ha->response_dma));
  496. init_fw_cb->compq_addr_hi = cpu_to_le32(MSDW(ha->response_dma));
  497. init_fw_cb->shdwreg_addr_lo = cpu_to_le32(LSDW(ha->shadow_regs_dma));
  498. init_fw_cb->shdwreg_addr_hi = cpu_to_le32(MSDW(ha->shadow_regs_dma));
  499. /* Set up required options. */
  500. init_fw_cb->fw_options |=
  501. __constant_cpu_to_le16(FWOPT_SESSION_MODE |
  502. FWOPT_INITIATOR_MODE);
  503. if (is_qla80XX(ha))
  504. init_fw_cb->fw_options |=
  505. __constant_cpu_to_le16(FWOPT_ENABLE_CRBDB);
  506. init_fw_cb->fw_options &= __constant_cpu_to_le16(~FWOPT_TARGET_MODE);
  507. init_fw_cb->add_fw_options = 0;
  508. init_fw_cb->add_fw_options |=
  509. __constant_cpu_to_le16(ADFWOPT_SERIALIZE_TASK_MGMT);
  510. init_fw_cb->add_fw_options |=
  511. __constant_cpu_to_le16(ADFWOPT_AUTOCONN_DISABLE);
  512. if (qla4xxx_set_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma)
  513. != QLA_SUCCESS) {
  514. DEBUG2(printk(KERN_WARNING
  515. "scsi%ld: %s: Failed to set init_fw_ctrl_blk\n",
  516. ha->host_no, __func__));
  517. goto exit_init_fw_cb;
  518. }
  519. if (qla4xxx_update_local_ifcb(ha, &mbox_cmd[0], &mbox_sts[0],
  520. init_fw_cb, init_fw_cb_dma) != QLA_SUCCESS) {
  521. DEBUG2(printk("scsi%ld: %s: Failed to update local ifcb\n",
  522. ha->host_no, __func__));
  523. goto exit_init_fw_cb;
  524. }
  525. status = QLA_SUCCESS;
  526. exit_init_fw_cb:
  527. dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
  528. init_fw_cb, init_fw_cb_dma);
  529. exit_init_fw_cb_no_free:
  530. return status;
  531. }
  532. /**
  533. * qla4xxx_get_dhcp_ip_address - gets HBA ip address via DHCP
  534. * @ha: Pointer to host adapter structure.
  535. **/
  536. int qla4xxx_get_dhcp_ip_address(struct scsi_qla_host * ha)
  537. {
  538. struct addr_ctrl_blk *init_fw_cb;
  539. dma_addr_t init_fw_cb_dma;
  540. uint32_t mbox_cmd[MBOX_REG_COUNT];
  541. uint32_t mbox_sts[MBOX_REG_COUNT];
  542. init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
  543. sizeof(struct addr_ctrl_blk),
  544. &init_fw_cb_dma, GFP_KERNEL);
  545. if (init_fw_cb == NULL) {
  546. printk("scsi%ld: %s: Unable to alloc init_cb\n", ha->host_no,
  547. __func__);
  548. return QLA_ERROR;
  549. }
  550. /* Get Initialize Firmware Control Block. */
  551. memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk));
  552. if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
  553. QLA_SUCCESS) {
  554. DEBUG2(printk("scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
  555. ha->host_no, __func__));
  556. dma_free_coherent(&ha->pdev->dev,
  557. sizeof(struct addr_ctrl_blk),
  558. init_fw_cb, init_fw_cb_dma);
  559. return QLA_ERROR;
  560. }
  561. /* Save IP Address. */
  562. qla4xxx_update_local_ip(ha, init_fw_cb);
  563. dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
  564. init_fw_cb, init_fw_cb_dma);
  565. return QLA_SUCCESS;
  566. }
  567. /**
  568. * qla4xxx_get_firmware_state - gets firmware state of HBA
  569. * @ha: Pointer to host adapter structure.
  570. **/
  571. int qla4xxx_get_firmware_state(struct scsi_qla_host * ha)
  572. {
  573. uint32_t mbox_cmd[MBOX_REG_COUNT];
  574. uint32_t mbox_sts[MBOX_REG_COUNT];
  575. /* Get firmware version */
  576. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  577. memset(&mbox_sts, 0, sizeof(mbox_sts));
  578. mbox_cmd[0] = MBOX_CMD_GET_FW_STATE;
  579. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 4, &mbox_cmd[0], &mbox_sts[0]) !=
  580. QLA_SUCCESS) {
  581. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATE failed w/ "
  582. "status %04X\n", ha->host_no, __func__,
  583. mbox_sts[0]));
  584. return QLA_ERROR;
  585. }
  586. ha->firmware_state = mbox_sts[1];
  587. ha->board_id = mbox_sts[2];
  588. ha->addl_fw_state = mbox_sts[3];
  589. DEBUG2(printk("scsi%ld: %s firmware_state=0x%x\n",
  590. ha->host_no, __func__, ha->firmware_state);)
  591. return QLA_SUCCESS;
  592. }
  593. /**
  594. * qla4xxx_get_firmware_status - retrieves firmware status
  595. * @ha: Pointer to host adapter structure.
  596. **/
  597. int qla4xxx_get_firmware_status(struct scsi_qla_host * ha)
  598. {
  599. uint32_t mbox_cmd[MBOX_REG_COUNT];
  600. uint32_t mbox_sts[MBOX_REG_COUNT];
  601. /* Get firmware version */
  602. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  603. memset(&mbox_sts, 0, sizeof(mbox_sts));
  604. mbox_cmd[0] = MBOX_CMD_GET_FW_STATUS;
  605. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0], &mbox_sts[0]) !=
  606. QLA_SUCCESS) {
  607. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATUS failed w/ "
  608. "status %04X\n", ha->host_no, __func__,
  609. mbox_sts[0]));
  610. return QLA_ERROR;
  611. }
  612. ql4_printk(KERN_INFO, ha, "%ld firmware IOCBs available (%d).\n",
  613. ha->host_no, mbox_sts[2]);
  614. return QLA_SUCCESS;
  615. }
  616. /**
  617. * qla4xxx_get_fwddb_entry - retrieves firmware ddb entry
  618. * @ha: Pointer to host adapter structure.
  619. * @fw_ddb_index: Firmware's device database index
  620. * @fw_ddb_entry: Pointer to firmware's device database entry structure
  621. * @num_valid_ddb_entries: Pointer to number of valid ddb entries
  622. * @next_ddb_index: Pointer to next valid device database index
  623. * @fw_ddb_device_state: Pointer to device state
  624. **/
  625. int qla4xxx_get_fwddb_entry(struct scsi_qla_host *ha,
  626. uint16_t fw_ddb_index,
  627. struct dev_db_entry *fw_ddb_entry,
  628. dma_addr_t fw_ddb_entry_dma,
  629. uint32_t *num_valid_ddb_entries,
  630. uint32_t *next_ddb_index,
  631. uint32_t *fw_ddb_device_state,
  632. uint32_t *conn_err_detail,
  633. uint16_t *tcp_source_port_num,
  634. uint16_t *connection_id)
  635. {
  636. int status = QLA_ERROR;
  637. uint16_t options;
  638. uint32_t mbox_cmd[MBOX_REG_COUNT];
  639. uint32_t mbox_sts[MBOX_REG_COUNT];
  640. /* Make sure the device index is valid */
  641. if (fw_ddb_index >= MAX_DDB_ENTRIES) {
  642. DEBUG2(printk("scsi%ld: %s: ddb [%d] out of range.\n",
  643. ha->host_no, __func__, fw_ddb_index));
  644. goto exit_get_fwddb;
  645. }
  646. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  647. memset(&mbox_sts, 0, sizeof(mbox_sts));
  648. if (fw_ddb_entry)
  649. memset(fw_ddb_entry, 0, sizeof(struct dev_db_entry));
  650. mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY;
  651. mbox_cmd[1] = (uint32_t) fw_ddb_index;
  652. mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
  653. mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
  654. mbox_cmd[4] = sizeof(struct dev_db_entry);
  655. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 7, &mbox_cmd[0], &mbox_sts[0]) ==
  656. QLA_ERROR) {
  657. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_DATABASE_ENTRY failed"
  658. " with status 0x%04X\n", ha->host_no, __func__,
  659. mbox_sts[0]));
  660. goto exit_get_fwddb;
  661. }
  662. if (fw_ddb_index != mbox_sts[1]) {
  663. DEBUG2(printk("scsi%ld: %s: ddb mismatch [%d] != [%d].\n",
  664. ha->host_no, __func__, fw_ddb_index,
  665. mbox_sts[1]));
  666. goto exit_get_fwddb;
  667. }
  668. if (fw_ddb_entry) {
  669. options = le16_to_cpu(fw_ddb_entry->options);
  670. if (options & DDB_OPT_IPV6_DEVICE) {
  671. ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
  672. "Next %d State %04x ConnErr %08x %pI6 "
  673. ":%04d \"%s\"\n", __func__, fw_ddb_index,
  674. mbox_sts[0], mbox_sts[2], mbox_sts[3],
  675. mbox_sts[4], mbox_sts[5],
  676. fw_ddb_entry->ip_addr,
  677. le16_to_cpu(fw_ddb_entry->port),
  678. fw_ddb_entry->iscsi_name);
  679. } else {
  680. ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
  681. "Next %d State %04x ConnErr %08x %pI4 "
  682. ":%04d \"%s\"\n", __func__, fw_ddb_index,
  683. mbox_sts[0], mbox_sts[2], mbox_sts[3],
  684. mbox_sts[4], mbox_sts[5],
  685. fw_ddb_entry->ip_addr,
  686. le16_to_cpu(fw_ddb_entry->port),
  687. fw_ddb_entry->iscsi_name);
  688. }
  689. }
  690. if (num_valid_ddb_entries)
  691. *num_valid_ddb_entries = mbox_sts[2];
  692. if (next_ddb_index)
  693. *next_ddb_index = mbox_sts[3];
  694. if (fw_ddb_device_state)
  695. *fw_ddb_device_state = mbox_sts[4];
  696. /*
  697. * RA: This mailbox has been changed to pass connection error and
  698. * details. Its true for ISP4010 as per Version E - Not sure when it
  699. * was changed. Get the time2wait from the fw_dd_entry field :
  700. * default_time2wait which we call it as minTime2Wait DEV_DB_ENTRY
  701. * struct.
  702. */
  703. if (conn_err_detail)
  704. *conn_err_detail = mbox_sts[5];
  705. if (tcp_source_port_num)
  706. *tcp_source_port_num = (uint16_t) (mbox_sts[6] >> 16);
  707. if (connection_id)
  708. *connection_id = (uint16_t) mbox_sts[6] & 0x00FF;
  709. status = QLA_SUCCESS;
  710. exit_get_fwddb:
  711. return status;
  712. }
  713. int qla4xxx_conn_open(struct scsi_qla_host *ha, uint16_t fw_ddb_index)
  714. {
  715. uint32_t mbox_cmd[MBOX_REG_COUNT];
  716. uint32_t mbox_sts[MBOX_REG_COUNT];
  717. int status;
  718. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  719. memset(&mbox_sts, 0, sizeof(mbox_sts));
  720. mbox_cmd[0] = MBOX_CMD_CONN_OPEN;
  721. mbox_cmd[1] = fw_ddb_index;
  722. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0],
  723. &mbox_sts[0]);
  724. DEBUG2(ql4_printk(KERN_INFO, ha,
  725. "%s: status = %d mbx0 = 0x%x mbx1 = 0x%x\n",
  726. __func__, status, mbox_sts[0], mbox_sts[1]));
  727. return status;
  728. }
  729. /**
  730. * qla4xxx_set_fwddb_entry - sets a ddb entry.
  731. * @ha: Pointer to host adapter structure.
  732. * @fw_ddb_index: Firmware's device database index
  733. * @fw_ddb_entry_dma: dma address of ddb entry
  734. * @mbx_sts: mailbox 0 to be returned or NULL
  735. *
  736. * This routine initializes or updates the adapter's device database
  737. * entry for the specified device.
  738. **/
  739. int qla4xxx_set_ddb_entry(struct scsi_qla_host * ha, uint16_t fw_ddb_index,
  740. dma_addr_t fw_ddb_entry_dma, uint32_t *mbx_sts)
  741. {
  742. uint32_t mbox_cmd[MBOX_REG_COUNT];
  743. uint32_t mbox_sts[MBOX_REG_COUNT];
  744. int status;
  745. /* Do not wait for completion. The firmware will send us an
  746. * ASTS_DATABASE_CHANGED (0x8014) to notify us of the login status.
  747. */
  748. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  749. memset(&mbox_sts, 0, sizeof(mbox_sts));
  750. mbox_cmd[0] = MBOX_CMD_SET_DATABASE_ENTRY;
  751. mbox_cmd[1] = (uint32_t) fw_ddb_index;
  752. mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
  753. mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
  754. mbox_cmd[4] = sizeof(struct dev_db_entry);
  755. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
  756. &mbox_sts[0]);
  757. if (mbx_sts)
  758. *mbx_sts = mbox_sts[0];
  759. DEBUG2(printk("scsi%ld: %s: status=%d mbx0=0x%x mbx4=0x%x\n",
  760. ha->host_no, __func__, status, mbox_sts[0], mbox_sts[4]);)
  761. return status;
  762. }
  763. int qla4xxx_session_logout_ddb(struct scsi_qla_host *ha,
  764. struct ddb_entry *ddb_entry, int options)
  765. {
  766. int status;
  767. uint32_t mbox_cmd[MBOX_REG_COUNT];
  768. uint32_t mbox_sts[MBOX_REG_COUNT];
  769. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  770. memset(&mbox_sts, 0, sizeof(mbox_sts));
  771. mbox_cmd[0] = MBOX_CMD_CONN_CLOSE_SESS_LOGOUT;
  772. mbox_cmd[1] = ddb_entry->fw_ddb_index;
  773. mbox_cmd[3] = options;
  774. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0],
  775. &mbox_sts[0]);
  776. if (status != QLA_SUCCESS) {
  777. DEBUG2(ql4_printk(KERN_INFO, ha,
  778. "%s: MBOX_CMD_CONN_CLOSE_SESS_LOGOUT "
  779. "failed sts %04X %04X", __func__,
  780. mbox_sts[0], mbox_sts[1]));
  781. }
  782. return status;
  783. }
  784. /**
  785. * qla4xxx_get_crash_record - retrieves crash record.
  786. * @ha: Pointer to host adapter structure.
  787. *
  788. * This routine retrieves a crash record from the QLA4010 after an 8002h aen.
  789. **/
  790. void qla4xxx_get_crash_record(struct scsi_qla_host * ha)
  791. {
  792. uint32_t mbox_cmd[MBOX_REG_COUNT];
  793. uint32_t mbox_sts[MBOX_REG_COUNT];
  794. struct crash_record *crash_record = NULL;
  795. dma_addr_t crash_record_dma = 0;
  796. uint32_t crash_record_size = 0;
  797. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  798. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  799. /* Get size of crash record. */
  800. mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
  801. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  802. QLA_SUCCESS) {
  803. DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve size!\n",
  804. ha->host_no, __func__));
  805. goto exit_get_crash_record;
  806. }
  807. crash_record_size = mbox_sts[4];
  808. if (crash_record_size == 0) {
  809. DEBUG2(printk("scsi%ld: %s: ERROR: Crash record size is 0!\n",
  810. ha->host_no, __func__));
  811. goto exit_get_crash_record;
  812. }
  813. /* Alloc Memory for Crash Record. */
  814. crash_record = dma_alloc_coherent(&ha->pdev->dev, crash_record_size,
  815. &crash_record_dma, GFP_KERNEL);
  816. if (crash_record == NULL)
  817. goto exit_get_crash_record;
  818. /* Get Crash Record. */
  819. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  820. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  821. mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
  822. mbox_cmd[2] = LSDW(crash_record_dma);
  823. mbox_cmd[3] = MSDW(crash_record_dma);
  824. mbox_cmd[4] = crash_record_size;
  825. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  826. QLA_SUCCESS)
  827. goto exit_get_crash_record;
  828. /* Dump Crash Record. */
  829. exit_get_crash_record:
  830. if (crash_record)
  831. dma_free_coherent(&ha->pdev->dev, crash_record_size,
  832. crash_record, crash_record_dma);
  833. }
  834. /**
  835. * qla4xxx_get_conn_event_log - retrieves connection event log
  836. * @ha: Pointer to host adapter structure.
  837. **/
  838. void qla4xxx_get_conn_event_log(struct scsi_qla_host * ha)
  839. {
  840. uint32_t mbox_cmd[MBOX_REG_COUNT];
  841. uint32_t mbox_sts[MBOX_REG_COUNT];
  842. struct conn_event_log_entry *event_log = NULL;
  843. dma_addr_t event_log_dma = 0;
  844. uint32_t event_log_size = 0;
  845. uint32_t num_valid_entries;
  846. uint32_t oldest_entry = 0;
  847. uint32_t max_event_log_entries;
  848. uint8_t i;
  849. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  850. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  851. /* Get size of crash record. */
  852. mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
  853. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  854. QLA_SUCCESS)
  855. goto exit_get_event_log;
  856. event_log_size = mbox_sts[4];
  857. if (event_log_size == 0)
  858. goto exit_get_event_log;
  859. /* Alloc Memory for Crash Record. */
  860. event_log = dma_alloc_coherent(&ha->pdev->dev, event_log_size,
  861. &event_log_dma, GFP_KERNEL);
  862. if (event_log == NULL)
  863. goto exit_get_event_log;
  864. /* Get Crash Record. */
  865. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  866. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  867. mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
  868. mbox_cmd[2] = LSDW(event_log_dma);
  869. mbox_cmd[3] = MSDW(event_log_dma);
  870. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  871. QLA_SUCCESS) {
  872. DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve event "
  873. "log!\n", ha->host_no, __func__));
  874. goto exit_get_event_log;
  875. }
  876. /* Dump Event Log. */
  877. num_valid_entries = mbox_sts[1];
  878. max_event_log_entries = event_log_size /
  879. sizeof(struct conn_event_log_entry);
  880. if (num_valid_entries > max_event_log_entries)
  881. oldest_entry = num_valid_entries % max_event_log_entries;
  882. DEBUG3(printk("scsi%ld: Connection Event Log Dump (%d entries):\n",
  883. ha->host_no, num_valid_entries));
  884. if (ql4xextended_error_logging == 3) {
  885. if (oldest_entry == 0) {
  886. /* Circular Buffer has not wrapped around */
  887. for (i=0; i < num_valid_entries; i++) {
  888. qla4xxx_dump_buffer((uint8_t *)event_log+
  889. (i*sizeof(*event_log)),
  890. sizeof(*event_log));
  891. }
  892. }
  893. else {
  894. /* Circular Buffer has wrapped around -
  895. * display accordingly*/
  896. for (i=oldest_entry; i < max_event_log_entries; i++) {
  897. qla4xxx_dump_buffer((uint8_t *)event_log+
  898. (i*sizeof(*event_log)),
  899. sizeof(*event_log));
  900. }
  901. for (i=0; i < oldest_entry; i++) {
  902. qla4xxx_dump_buffer((uint8_t *)event_log+
  903. (i*sizeof(*event_log)),
  904. sizeof(*event_log));
  905. }
  906. }
  907. }
  908. exit_get_event_log:
  909. if (event_log)
  910. dma_free_coherent(&ha->pdev->dev, event_log_size, event_log,
  911. event_log_dma);
  912. }
  913. /**
  914. * qla4xxx_abort_task - issues Abort Task
  915. * @ha: Pointer to host adapter structure.
  916. * @srb: Pointer to srb entry
  917. *
  918. * This routine performs a LUN RESET on the specified target/lun.
  919. * The caller must ensure that the ddb_entry and lun_entry pointers
  920. * are valid before calling this routine.
  921. **/
  922. int qla4xxx_abort_task(struct scsi_qla_host *ha, struct srb *srb)
  923. {
  924. uint32_t mbox_cmd[MBOX_REG_COUNT];
  925. uint32_t mbox_sts[MBOX_REG_COUNT];
  926. struct scsi_cmnd *cmd = srb->cmd;
  927. int status = QLA_SUCCESS;
  928. unsigned long flags = 0;
  929. uint32_t index;
  930. /*
  931. * Send abort task command to ISP, so that the ISP will return
  932. * request with ABORT status
  933. */
  934. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  935. memset(&mbox_sts, 0, sizeof(mbox_sts));
  936. spin_lock_irqsave(&ha->hardware_lock, flags);
  937. index = (unsigned long)(unsigned char *)cmd->host_scribble;
  938. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  939. /* Firmware already posted completion on response queue */
  940. if (index == MAX_SRBS)
  941. return status;
  942. mbox_cmd[0] = MBOX_CMD_ABORT_TASK;
  943. mbox_cmd[1] = srb->ddb->fw_ddb_index;
  944. mbox_cmd[2] = index;
  945. /* Immediate Command Enable */
  946. mbox_cmd[5] = 0x01;
  947. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
  948. &mbox_sts[0]);
  949. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE) {
  950. status = QLA_ERROR;
  951. DEBUG2(printk(KERN_WARNING "scsi%ld:%d:%d: abort task FAILED: "
  952. "mbx0=%04X, mb1=%04X, mb2=%04X, mb3=%04X, mb4=%04X\n",
  953. ha->host_no, cmd->device->id, cmd->device->lun, mbox_sts[0],
  954. mbox_sts[1], mbox_sts[2], mbox_sts[3], mbox_sts[4]));
  955. }
  956. return status;
  957. }
  958. /**
  959. * qla4xxx_reset_lun - issues LUN Reset
  960. * @ha: Pointer to host adapter structure.
  961. * @ddb_entry: Pointer to device database entry
  962. * @lun: lun number
  963. *
  964. * This routine performs a LUN RESET on the specified target/lun.
  965. * The caller must ensure that the ddb_entry and lun_entry pointers
  966. * are valid before calling this routine.
  967. **/
  968. int qla4xxx_reset_lun(struct scsi_qla_host * ha, struct ddb_entry * ddb_entry,
  969. int lun)
  970. {
  971. uint32_t mbox_cmd[MBOX_REG_COUNT];
  972. uint32_t mbox_sts[MBOX_REG_COUNT];
  973. int status = QLA_SUCCESS;
  974. DEBUG2(printk("scsi%ld:%d:%d: lun reset issued\n", ha->host_no,
  975. ddb_entry->fw_ddb_index, lun));
  976. /*
  977. * Send lun reset command to ISP, so that the ISP will return all
  978. * outstanding requests with RESET status
  979. */
  980. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  981. memset(&mbox_sts, 0, sizeof(mbox_sts));
  982. mbox_cmd[0] = MBOX_CMD_LUN_RESET;
  983. mbox_cmd[1] = ddb_entry->fw_ddb_index;
  984. mbox_cmd[2] = lun << 8;
  985. mbox_cmd[5] = 0x01; /* Immediate Command Enable */
  986. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]);
  987. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
  988. mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
  989. status = QLA_ERROR;
  990. return status;
  991. }
  992. /**
  993. * qla4xxx_reset_target - issues target Reset
  994. * @ha: Pointer to host adapter structure.
  995. * @db_entry: Pointer to device database entry
  996. * @un_entry: Pointer to lun entry structure
  997. *
  998. * This routine performs a TARGET RESET on the specified target.
  999. * The caller must ensure that the ddb_entry pointers
  1000. * are valid before calling this routine.
  1001. **/
  1002. int qla4xxx_reset_target(struct scsi_qla_host *ha,
  1003. struct ddb_entry *ddb_entry)
  1004. {
  1005. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1006. uint32_t mbox_sts[MBOX_REG_COUNT];
  1007. int status = QLA_SUCCESS;
  1008. DEBUG2(printk("scsi%ld:%d: target reset issued\n", ha->host_no,
  1009. ddb_entry->fw_ddb_index));
  1010. /*
  1011. * Send target reset command to ISP, so that the ISP will return all
  1012. * outstanding requests with RESET status
  1013. */
  1014. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1015. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1016. mbox_cmd[0] = MBOX_CMD_TARGET_WARM_RESET;
  1017. mbox_cmd[1] = ddb_entry->fw_ddb_index;
  1018. mbox_cmd[5] = 0x01; /* Immediate Command Enable */
  1019. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
  1020. &mbox_sts[0]);
  1021. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
  1022. mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
  1023. status = QLA_ERROR;
  1024. return status;
  1025. }
  1026. int qla4xxx_get_flash(struct scsi_qla_host * ha, dma_addr_t dma_addr,
  1027. uint32_t offset, uint32_t len)
  1028. {
  1029. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1030. uint32_t mbox_sts[MBOX_REG_COUNT];
  1031. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1032. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1033. mbox_cmd[0] = MBOX_CMD_READ_FLASH;
  1034. mbox_cmd[1] = LSDW(dma_addr);
  1035. mbox_cmd[2] = MSDW(dma_addr);
  1036. mbox_cmd[3] = offset;
  1037. mbox_cmd[4] = len;
  1038. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0], &mbox_sts[0]) !=
  1039. QLA_SUCCESS) {
  1040. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_READ_FLASH, failed w/ "
  1041. "status %04X %04X, offset %08x, len %08x\n", ha->host_no,
  1042. __func__, mbox_sts[0], mbox_sts[1], offset, len));
  1043. return QLA_ERROR;
  1044. }
  1045. return QLA_SUCCESS;
  1046. }
  1047. /**
  1048. * qla4xxx_about_firmware - gets FW, iscsi draft and boot loader version
  1049. * @ha: Pointer to host adapter structure.
  1050. *
  1051. * Retrieves the FW version, iSCSI draft version & bootloader version of HBA.
  1052. * Mailboxes 2 & 3 may hold an address for data. Make sure that we write 0 to
  1053. * those mailboxes, if unused.
  1054. **/
  1055. int qla4xxx_about_firmware(struct scsi_qla_host *ha)
  1056. {
  1057. struct about_fw_info *about_fw = NULL;
  1058. dma_addr_t about_fw_dma;
  1059. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1060. uint32_t mbox_sts[MBOX_REG_COUNT];
  1061. int status = QLA_ERROR;
  1062. about_fw = dma_alloc_coherent(&ha->pdev->dev,
  1063. sizeof(struct about_fw_info),
  1064. &about_fw_dma, GFP_KERNEL);
  1065. if (!about_fw) {
  1066. DEBUG2(ql4_printk(KERN_ERR, ha, "%s: Unable to alloc memory "
  1067. "for about_fw\n", __func__));
  1068. return status;
  1069. }
  1070. memset(about_fw, 0, sizeof(struct about_fw_info));
  1071. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1072. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1073. mbox_cmd[0] = MBOX_CMD_ABOUT_FW;
  1074. mbox_cmd[2] = LSDW(about_fw_dma);
  1075. mbox_cmd[3] = MSDW(about_fw_dma);
  1076. mbox_cmd[4] = sizeof(struct about_fw_info);
  1077. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT,
  1078. &mbox_cmd[0], &mbox_sts[0]);
  1079. if (status != QLA_SUCCESS) {
  1080. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_ABOUT_FW "
  1081. "failed w/ status %04X\n", __func__,
  1082. mbox_sts[0]));
  1083. goto exit_about_fw;
  1084. }
  1085. /* Save version information. */
  1086. ha->firmware_version[0] = le16_to_cpu(about_fw->fw_major);
  1087. ha->firmware_version[1] = le16_to_cpu(about_fw->fw_minor);
  1088. ha->patch_number = le16_to_cpu(about_fw->fw_patch);
  1089. ha->build_number = le16_to_cpu(about_fw->fw_build);
  1090. ha->iscsi_major = le16_to_cpu(about_fw->iscsi_major);
  1091. ha->iscsi_minor = le16_to_cpu(about_fw->iscsi_minor);
  1092. ha->bootload_major = le16_to_cpu(about_fw->bootload_major);
  1093. ha->bootload_minor = le16_to_cpu(about_fw->bootload_minor);
  1094. ha->bootload_patch = le16_to_cpu(about_fw->bootload_patch);
  1095. ha->bootload_build = le16_to_cpu(about_fw->bootload_build);
  1096. status = QLA_SUCCESS;
  1097. exit_about_fw:
  1098. dma_free_coherent(&ha->pdev->dev, sizeof(struct about_fw_info),
  1099. about_fw, about_fw_dma);
  1100. return status;
  1101. }
  1102. static int qla4xxx_get_default_ddb(struct scsi_qla_host *ha, uint32_t options,
  1103. dma_addr_t dma_addr)
  1104. {
  1105. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1106. uint32_t mbox_sts[MBOX_REG_COUNT];
  1107. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1108. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1109. mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS;
  1110. mbox_cmd[1] = options;
  1111. mbox_cmd[2] = LSDW(dma_addr);
  1112. mbox_cmd[3] = MSDW(dma_addr);
  1113. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]) !=
  1114. QLA_SUCCESS) {
  1115. DEBUG2(printk("scsi%ld: %s: failed status %04X\n",
  1116. ha->host_no, __func__, mbox_sts[0]));
  1117. return QLA_ERROR;
  1118. }
  1119. return QLA_SUCCESS;
  1120. }
  1121. int qla4xxx_req_ddb_entry(struct scsi_qla_host *ha, uint32_t ddb_index,
  1122. uint32_t *mbx_sts)
  1123. {
  1124. int status;
  1125. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1126. uint32_t mbox_sts[MBOX_REG_COUNT];
  1127. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1128. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1129. mbox_cmd[0] = MBOX_CMD_REQUEST_DATABASE_ENTRY;
  1130. mbox_cmd[1] = ddb_index;
  1131. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
  1132. &mbox_sts[0]);
  1133. if (status != QLA_SUCCESS) {
  1134. DEBUG2(ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n",
  1135. __func__, mbox_sts[0]));
  1136. }
  1137. *mbx_sts = mbox_sts[0];
  1138. return status;
  1139. }
  1140. int qla4xxx_clear_ddb_entry(struct scsi_qla_host *ha, uint32_t ddb_index)
  1141. {
  1142. int status;
  1143. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1144. uint32_t mbox_sts[MBOX_REG_COUNT];
  1145. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1146. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1147. mbox_cmd[0] = MBOX_CMD_CLEAR_DATABASE_ENTRY;
  1148. mbox_cmd[1] = ddb_index;
  1149. status = qla4xxx_mailbox_command(ha, 2, 1, &mbox_cmd[0],
  1150. &mbox_sts[0]);
  1151. if (status != QLA_SUCCESS) {
  1152. DEBUG2(ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n",
  1153. __func__, mbox_sts[0]));
  1154. }
  1155. return status;
  1156. }
  1157. int qla4xxx_set_flash(struct scsi_qla_host *ha, dma_addr_t dma_addr,
  1158. uint32_t offset, uint32_t length, uint32_t options)
  1159. {
  1160. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1161. uint32_t mbox_sts[MBOX_REG_COUNT];
  1162. int status = QLA_SUCCESS;
  1163. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1164. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1165. mbox_cmd[0] = MBOX_CMD_WRITE_FLASH;
  1166. mbox_cmd[1] = LSDW(dma_addr);
  1167. mbox_cmd[2] = MSDW(dma_addr);
  1168. mbox_cmd[3] = offset;
  1169. mbox_cmd[4] = length;
  1170. mbox_cmd[5] = options;
  1171. status = qla4xxx_mailbox_command(ha, 6, 2, &mbox_cmd[0], &mbox_sts[0]);
  1172. if (status != QLA_SUCCESS) {
  1173. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_WRITE_FLASH "
  1174. "failed w/ status %04X, mbx1 %04X\n",
  1175. __func__, mbox_sts[0], mbox_sts[1]));
  1176. }
  1177. return status;
  1178. }
  1179. int qla4xxx_bootdb_by_index(struct scsi_qla_host *ha,
  1180. struct dev_db_entry *fw_ddb_entry,
  1181. dma_addr_t fw_ddb_entry_dma, uint16_t ddb_index)
  1182. {
  1183. uint32_t dev_db_start_offset = FLASH_OFFSET_DB_INFO;
  1184. uint32_t dev_db_end_offset;
  1185. int status = QLA_ERROR;
  1186. memset(fw_ddb_entry, 0, sizeof(*fw_ddb_entry));
  1187. dev_db_start_offset += (ddb_index * sizeof(*fw_ddb_entry));
  1188. dev_db_end_offset = FLASH_OFFSET_DB_END;
  1189. if (dev_db_start_offset > dev_db_end_offset) {
  1190. DEBUG2(ql4_printk(KERN_ERR, ha,
  1191. "%s:Invalid DDB index %d", __func__,
  1192. ddb_index));
  1193. goto exit_bootdb_failed;
  1194. }
  1195. if (qla4xxx_get_flash(ha, fw_ddb_entry_dma, dev_db_start_offset,
  1196. sizeof(*fw_ddb_entry)) != QLA_SUCCESS) {
  1197. ql4_printk(KERN_ERR, ha, "scsi%ld: %s: Get Flash"
  1198. "failed\n", ha->host_no, __func__);
  1199. goto exit_bootdb_failed;
  1200. }
  1201. if (fw_ddb_entry->cookie == DDB_VALID_COOKIE)
  1202. status = QLA_SUCCESS;
  1203. exit_bootdb_failed:
  1204. return status;
  1205. }
  1206. int qla4xxx_get_chap(struct scsi_qla_host *ha, char *username, char *password,
  1207. uint16_t idx)
  1208. {
  1209. int ret = 0;
  1210. int rval = QLA_ERROR;
  1211. uint32_t offset = 0, chap_size;
  1212. struct ql4_chap_table *chap_table;
  1213. dma_addr_t chap_dma;
  1214. chap_table = dma_pool_alloc(ha->chap_dma_pool, GFP_KERNEL, &chap_dma);
  1215. if (chap_table == NULL) {
  1216. ret = -ENOMEM;
  1217. goto exit_get_chap;
  1218. }
  1219. chap_size = sizeof(struct ql4_chap_table);
  1220. memset(chap_table, 0, chap_size);
  1221. if (is_qla40XX(ha))
  1222. offset = FLASH_CHAP_OFFSET | (idx * chap_size);
  1223. else {
  1224. offset = FLASH_RAW_ACCESS_ADDR + (ha->hw.flt_region_chap << 2);
  1225. /* flt_chap_size is CHAP table size for both ports
  1226. * so divide it by 2 to calculate the offset for second port
  1227. */
  1228. if (ha->port_num == 1)
  1229. offset += (ha->hw.flt_chap_size / 2);
  1230. offset += (idx * chap_size);
  1231. }
  1232. rval = qla4xxx_get_flash(ha, chap_dma, offset, chap_size);
  1233. if (rval != QLA_SUCCESS) {
  1234. ret = -EINVAL;
  1235. goto exit_get_chap;
  1236. }
  1237. DEBUG2(ql4_printk(KERN_INFO, ha, "Chap Cookie: x%x\n",
  1238. __le16_to_cpu(chap_table->cookie)));
  1239. if (__le16_to_cpu(chap_table->cookie) != CHAP_VALID_COOKIE) {
  1240. ql4_printk(KERN_ERR, ha, "No valid chap entry found\n");
  1241. goto exit_get_chap;
  1242. }
  1243. strncpy(password, chap_table->secret, QL4_CHAP_MAX_SECRET_LEN);
  1244. strncpy(username, chap_table->name, QL4_CHAP_MAX_NAME_LEN);
  1245. chap_table->cookie = __constant_cpu_to_le16(CHAP_VALID_COOKIE);
  1246. exit_get_chap:
  1247. dma_pool_free(ha->chap_dma_pool, chap_table, chap_dma);
  1248. return ret;
  1249. }
  1250. static int qla4xxx_set_chap(struct scsi_qla_host *ha, char *username,
  1251. char *password, uint16_t idx, int bidi)
  1252. {
  1253. int ret = 0;
  1254. int rval = QLA_ERROR;
  1255. uint32_t offset = 0;
  1256. struct ql4_chap_table *chap_table;
  1257. dma_addr_t chap_dma;
  1258. chap_table = dma_pool_alloc(ha->chap_dma_pool, GFP_KERNEL, &chap_dma);
  1259. if (chap_table == NULL) {
  1260. ret = -ENOMEM;
  1261. goto exit_set_chap;
  1262. }
  1263. memset(chap_table, 0, sizeof(struct ql4_chap_table));
  1264. if (bidi)
  1265. chap_table->flags |= BIT_6; /* peer */
  1266. else
  1267. chap_table->flags |= BIT_7; /* local */
  1268. chap_table->secret_len = strlen(password);
  1269. strncpy(chap_table->secret, password, MAX_CHAP_SECRET_LEN);
  1270. strncpy(chap_table->name, username, MAX_CHAP_NAME_LEN);
  1271. chap_table->cookie = __constant_cpu_to_le16(CHAP_VALID_COOKIE);
  1272. offset = FLASH_CHAP_OFFSET | (idx * sizeof(struct ql4_chap_table));
  1273. rval = qla4xxx_set_flash(ha, chap_dma, offset,
  1274. sizeof(struct ql4_chap_table),
  1275. FLASH_OPT_RMW_COMMIT);
  1276. if (rval == QLA_SUCCESS && ha->chap_list) {
  1277. /* Update ha chap_list cache */
  1278. memcpy((struct ql4_chap_table *)ha->chap_list + idx,
  1279. chap_table, sizeof(struct ql4_chap_table));
  1280. }
  1281. dma_pool_free(ha->chap_dma_pool, chap_table, chap_dma);
  1282. if (rval != QLA_SUCCESS)
  1283. ret = -EINVAL;
  1284. exit_set_chap:
  1285. return ret;
  1286. }
  1287. /**
  1288. * qla4xxx_get_chap_index - Get chap index given username and secret
  1289. * @ha: pointer to adapter structure
  1290. * @username: CHAP username to be searched
  1291. * @password: CHAP password to be searched
  1292. * @bidi: Is this a BIDI CHAP
  1293. * @chap_index: CHAP index to be returned
  1294. *
  1295. * Match the username and password in the chap_list, return the index if a
  1296. * match is found. If a match is not found then add the entry in FLASH and
  1297. * return the index at which entry is written in the FLASH.
  1298. **/
  1299. int qla4xxx_get_chap_index(struct scsi_qla_host *ha, char *username,
  1300. char *password, int bidi, uint16_t *chap_index)
  1301. {
  1302. int i, rval;
  1303. int free_index = -1;
  1304. int found_index = 0;
  1305. int max_chap_entries = 0;
  1306. struct ql4_chap_table *chap_table;
  1307. if (is_qla8022(ha))
  1308. max_chap_entries = (ha->hw.flt_chap_size / 2) /
  1309. sizeof(struct ql4_chap_table);
  1310. else
  1311. max_chap_entries = MAX_CHAP_ENTRIES_40XX;
  1312. if (!ha->chap_list) {
  1313. ql4_printk(KERN_ERR, ha, "Do not have CHAP table cache\n");
  1314. return QLA_ERROR;
  1315. }
  1316. if (!username || !password) {
  1317. ql4_printk(KERN_ERR, ha, "Do not have username and psw\n");
  1318. return QLA_ERROR;
  1319. }
  1320. mutex_lock(&ha->chap_sem);
  1321. for (i = 0; i < max_chap_entries; i++) {
  1322. chap_table = (struct ql4_chap_table *)ha->chap_list + i;
  1323. if (chap_table->cookie !=
  1324. __constant_cpu_to_le16(CHAP_VALID_COOKIE)) {
  1325. if (i > MAX_RESRV_CHAP_IDX && free_index == -1)
  1326. free_index = i;
  1327. continue;
  1328. }
  1329. if (bidi) {
  1330. if (chap_table->flags & BIT_7)
  1331. continue;
  1332. } else {
  1333. if (chap_table->flags & BIT_6)
  1334. continue;
  1335. }
  1336. if (!strncmp(chap_table->secret, password,
  1337. MAX_CHAP_SECRET_LEN) &&
  1338. !strncmp(chap_table->name, username,
  1339. MAX_CHAP_NAME_LEN)) {
  1340. *chap_index = i;
  1341. found_index = 1;
  1342. break;
  1343. }
  1344. }
  1345. /* If chap entry is not present and a free index is available then
  1346. * write the entry in flash
  1347. */
  1348. if (!found_index && free_index != -1) {
  1349. rval = qla4xxx_set_chap(ha, username, password,
  1350. free_index, bidi);
  1351. if (!rval) {
  1352. *chap_index = free_index;
  1353. found_index = 1;
  1354. }
  1355. }
  1356. mutex_unlock(&ha->chap_sem);
  1357. if (found_index)
  1358. return QLA_SUCCESS;
  1359. return QLA_ERROR;
  1360. }
  1361. int qla4xxx_conn_close_sess_logout(struct scsi_qla_host *ha,
  1362. uint16_t fw_ddb_index,
  1363. uint16_t connection_id,
  1364. uint16_t option)
  1365. {
  1366. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1367. uint32_t mbox_sts[MBOX_REG_COUNT];
  1368. int status = QLA_SUCCESS;
  1369. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1370. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1371. mbox_cmd[0] = MBOX_CMD_CONN_CLOSE_SESS_LOGOUT;
  1372. mbox_cmd[1] = fw_ddb_index;
  1373. mbox_cmd[2] = connection_id;
  1374. mbox_cmd[3] = option;
  1375. status = qla4xxx_mailbox_command(ha, 4, 2, &mbox_cmd[0], &mbox_sts[0]);
  1376. if (status != QLA_SUCCESS) {
  1377. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_CONN_CLOSE "
  1378. "option %04x failed w/ status %04X %04X\n",
  1379. __func__, option, mbox_sts[0], mbox_sts[1]));
  1380. }
  1381. return status;
  1382. }
  1383. int qla4xxx_disable_acb(struct scsi_qla_host *ha)
  1384. {
  1385. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1386. uint32_t mbox_sts[MBOX_REG_COUNT];
  1387. int status = QLA_SUCCESS;
  1388. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1389. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1390. mbox_cmd[0] = MBOX_CMD_DISABLE_ACB;
  1391. status = qla4xxx_mailbox_command(ha, 8, 5, &mbox_cmd[0], &mbox_sts[0]);
  1392. if (status != QLA_SUCCESS) {
  1393. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_DISABLE_ACB "
  1394. "failed w/ status %04X %04X %04X", __func__,
  1395. mbox_sts[0], mbox_sts[1], mbox_sts[2]));
  1396. }
  1397. return status;
  1398. }
  1399. int qla4xxx_get_acb(struct scsi_qla_host *ha, dma_addr_t acb_dma,
  1400. uint32_t acb_type, uint32_t len)
  1401. {
  1402. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1403. uint32_t mbox_sts[MBOX_REG_COUNT];
  1404. int status = QLA_SUCCESS;
  1405. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1406. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1407. mbox_cmd[0] = MBOX_CMD_GET_ACB;
  1408. mbox_cmd[1] = acb_type;
  1409. mbox_cmd[2] = LSDW(acb_dma);
  1410. mbox_cmd[3] = MSDW(acb_dma);
  1411. mbox_cmd[4] = len;
  1412. status = qla4xxx_mailbox_command(ha, 5, 5, &mbox_cmd[0], &mbox_sts[0]);
  1413. if (status != QLA_SUCCESS) {
  1414. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_GET_ACB "
  1415. "failed w/ status %04X\n", __func__,
  1416. mbox_sts[0]));
  1417. }
  1418. return status;
  1419. }
  1420. int qla4xxx_set_acb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  1421. uint32_t *mbox_sts, dma_addr_t acb_dma)
  1422. {
  1423. int status = QLA_SUCCESS;
  1424. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  1425. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  1426. mbox_cmd[0] = MBOX_CMD_SET_ACB;
  1427. mbox_cmd[1] = 0; /* Primary ACB */
  1428. mbox_cmd[2] = LSDW(acb_dma);
  1429. mbox_cmd[3] = MSDW(acb_dma);
  1430. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  1431. status = qla4xxx_mailbox_command(ha, 5, 5, &mbox_cmd[0], &mbox_sts[0]);
  1432. if (status != QLA_SUCCESS) {
  1433. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_SET_ACB "
  1434. "failed w/ status %04X\n", __func__,
  1435. mbox_sts[0]));
  1436. }
  1437. return status;
  1438. }
  1439. int qla4xxx_set_param_ddbentry(struct scsi_qla_host *ha,
  1440. struct ddb_entry *ddb_entry,
  1441. struct iscsi_cls_conn *cls_conn,
  1442. uint32_t *mbx_sts)
  1443. {
  1444. struct dev_db_entry *fw_ddb_entry;
  1445. struct iscsi_conn *conn;
  1446. struct iscsi_session *sess;
  1447. struct qla_conn *qla_conn;
  1448. struct sockaddr *dst_addr;
  1449. dma_addr_t fw_ddb_entry_dma;
  1450. int status = QLA_SUCCESS;
  1451. int rval = 0;
  1452. struct sockaddr_in *addr;
  1453. struct sockaddr_in6 *addr6;
  1454. char *ip;
  1455. uint16_t iscsi_opts = 0;
  1456. uint32_t options = 0;
  1457. uint16_t idx, *ptid;
  1458. fw_ddb_entry = dma_alloc_coherent(&ha->pdev->dev, sizeof(*fw_ddb_entry),
  1459. &fw_ddb_entry_dma, GFP_KERNEL);
  1460. if (!fw_ddb_entry) {
  1461. DEBUG2(ql4_printk(KERN_ERR, ha,
  1462. "%s: Unable to allocate dma buffer.\n",
  1463. __func__));
  1464. rval = -ENOMEM;
  1465. goto exit_set_param_no_free;
  1466. }
  1467. conn = cls_conn->dd_data;
  1468. qla_conn = conn->dd_data;
  1469. sess = conn->session;
  1470. dst_addr = (struct sockaddr *)&qla_conn->qla_ep->dst_addr;
  1471. if (dst_addr->sa_family == AF_INET6)
  1472. options |= IPV6_DEFAULT_DDB_ENTRY;
  1473. status = qla4xxx_get_default_ddb(ha, options, fw_ddb_entry_dma);
  1474. if (status == QLA_ERROR) {
  1475. rval = -EINVAL;
  1476. goto exit_set_param;
  1477. }
  1478. ptid = (uint16_t *)&fw_ddb_entry->isid[1];
  1479. *ptid = cpu_to_le16((uint16_t)ddb_entry->sess->target_id);
  1480. DEBUG2(ql4_printk(KERN_INFO, ha, "ISID [%02x%02x%02x%02x%02x%02x]\n",
  1481. fw_ddb_entry->isid[5], fw_ddb_entry->isid[4],
  1482. fw_ddb_entry->isid[3], fw_ddb_entry->isid[2],
  1483. fw_ddb_entry->isid[1], fw_ddb_entry->isid[0]));
  1484. iscsi_opts = le16_to_cpu(fw_ddb_entry->iscsi_options);
  1485. memset(fw_ddb_entry->iscsi_alias, 0, sizeof(fw_ddb_entry->iscsi_alias));
  1486. memset(fw_ddb_entry->iscsi_name, 0, sizeof(fw_ddb_entry->iscsi_name));
  1487. if (sess->targetname != NULL) {
  1488. memcpy(fw_ddb_entry->iscsi_name, sess->targetname,
  1489. min(strlen(sess->targetname),
  1490. sizeof(fw_ddb_entry->iscsi_name)));
  1491. }
  1492. memset(fw_ddb_entry->ip_addr, 0, sizeof(fw_ddb_entry->ip_addr));
  1493. memset(fw_ddb_entry->tgt_addr, 0, sizeof(fw_ddb_entry->tgt_addr));
  1494. fw_ddb_entry->options = DDB_OPT_TARGET | DDB_OPT_AUTO_SENDTGTS_DISABLE;
  1495. if (dst_addr->sa_family == AF_INET) {
  1496. addr = (struct sockaddr_in *)dst_addr;
  1497. ip = (char *)&addr->sin_addr;
  1498. memcpy(fw_ddb_entry->ip_addr, ip, IP_ADDR_LEN);
  1499. fw_ddb_entry->port = cpu_to_le16(ntohs(addr->sin_port));
  1500. DEBUG2(ql4_printk(KERN_INFO, ha,
  1501. "%s: Destination Address [%pI4]: index [%d]\n",
  1502. __func__, fw_ddb_entry->ip_addr,
  1503. ddb_entry->fw_ddb_index));
  1504. } else if (dst_addr->sa_family == AF_INET6) {
  1505. addr6 = (struct sockaddr_in6 *)dst_addr;
  1506. ip = (char *)&addr6->sin6_addr;
  1507. memcpy(fw_ddb_entry->ip_addr, ip, IPv6_ADDR_LEN);
  1508. fw_ddb_entry->port = cpu_to_le16(ntohs(addr6->sin6_port));
  1509. fw_ddb_entry->options |= DDB_OPT_IPV6_DEVICE;
  1510. DEBUG2(ql4_printk(KERN_INFO, ha,
  1511. "%s: Destination Address [%pI6]: index [%d]\n",
  1512. __func__, fw_ddb_entry->ip_addr,
  1513. ddb_entry->fw_ddb_index));
  1514. } else {
  1515. ql4_printk(KERN_ERR, ha,
  1516. "%s: Failed to get IP Address\n",
  1517. __func__);
  1518. rval = -EINVAL;
  1519. goto exit_set_param;
  1520. }
  1521. /* CHAP */
  1522. if (sess->username != NULL && sess->password != NULL) {
  1523. if (strlen(sess->username) && strlen(sess->password)) {
  1524. iscsi_opts |= BIT_7;
  1525. rval = qla4xxx_get_chap_index(ha, sess->username,
  1526. sess->password,
  1527. LOCAL_CHAP, &idx);
  1528. if (rval)
  1529. goto exit_set_param;
  1530. fw_ddb_entry->chap_tbl_idx = cpu_to_le16(idx);
  1531. }
  1532. }
  1533. if (sess->username_in != NULL && sess->password_in != NULL) {
  1534. /* Check if BIDI CHAP */
  1535. if (strlen(sess->username_in) && strlen(sess->password_in)) {
  1536. iscsi_opts |= BIT_4;
  1537. rval = qla4xxx_get_chap_index(ha, sess->username_in,
  1538. sess->password_in,
  1539. BIDI_CHAP, &idx);
  1540. if (rval)
  1541. goto exit_set_param;
  1542. }
  1543. }
  1544. if (sess->initial_r2t_en)
  1545. iscsi_opts |= BIT_10;
  1546. if (sess->imm_data_en)
  1547. iscsi_opts |= BIT_11;
  1548. fw_ddb_entry->iscsi_options = cpu_to_le16(iscsi_opts);
  1549. if (conn->max_recv_dlength)
  1550. fw_ddb_entry->iscsi_max_rcv_data_seg_len =
  1551. __constant_cpu_to_le16((conn->max_recv_dlength / BYTE_UNITS));
  1552. if (sess->max_r2t)
  1553. fw_ddb_entry->iscsi_max_outsnd_r2t = cpu_to_le16(sess->max_r2t);
  1554. if (sess->first_burst)
  1555. fw_ddb_entry->iscsi_first_burst_len =
  1556. __constant_cpu_to_le16((sess->first_burst / BYTE_UNITS));
  1557. if (sess->max_burst)
  1558. fw_ddb_entry->iscsi_max_burst_len =
  1559. __constant_cpu_to_le16((sess->max_burst / BYTE_UNITS));
  1560. if (sess->time2wait)
  1561. fw_ddb_entry->iscsi_def_time2wait =
  1562. cpu_to_le16(sess->time2wait);
  1563. if (sess->time2retain)
  1564. fw_ddb_entry->iscsi_def_time2retain =
  1565. cpu_to_le16(sess->time2retain);
  1566. status = qla4xxx_set_ddb_entry(ha, ddb_entry->fw_ddb_index,
  1567. fw_ddb_entry_dma, mbx_sts);
  1568. if (status != QLA_SUCCESS)
  1569. rval = -EINVAL;
  1570. exit_set_param:
  1571. dma_free_coherent(&ha->pdev->dev, sizeof(*fw_ddb_entry),
  1572. fw_ddb_entry, fw_ddb_entry_dma);
  1573. exit_set_param_no_free:
  1574. return rval;
  1575. }
  1576. int qla4xxx_get_mgmt_data(struct scsi_qla_host *ha, uint16_t fw_ddb_index,
  1577. uint16_t stats_size, dma_addr_t stats_dma)
  1578. {
  1579. int status = QLA_SUCCESS;
  1580. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1581. uint32_t mbox_sts[MBOX_REG_COUNT];
  1582. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  1583. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  1584. mbox_cmd[0] = MBOX_CMD_GET_MANAGEMENT_DATA;
  1585. mbox_cmd[1] = fw_ddb_index;
  1586. mbox_cmd[2] = LSDW(stats_dma);
  1587. mbox_cmd[3] = MSDW(stats_dma);
  1588. mbox_cmd[4] = stats_size;
  1589. status = qla4xxx_mailbox_command(ha, 5, 1, &mbox_cmd[0], &mbox_sts[0]);
  1590. if (status != QLA_SUCCESS) {
  1591. DEBUG2(ql4_printk(KERN_WARNING, ha,
  1592. "%s: MBOX_CMD_GET_MANAGEMENT_DATA "
  1593. "failed w/ status %04X\n", __func__,
  1594. mbox_sts[0]));
  1595. }
  1596. return status;
  1597. }
  1598. int qla4xxx_get_ip_state(struct scsi_qla_host *ha, uint32_t acb_idx,
  1599. uint32_t ip_idx, uint32_t *sts)
  1600. {
  1601. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1602. uint32_t mbox_sts[MBOX_REG_COUNT];
  1603. int status = QLA_SUCCESS;
  1604. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1605. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1606. mbox_cmd[0] = MBOX_CMD_GET_IP_ADDR_STATE;
  1607. mbox_cmd[1] = acb_idx;
  1608. mbox_cmd[2] = ip_idx;
  1609. status = qla4xxx_mailbox_command(ha, 3, 8, &mbox_cmd[0], &mbox_sts[0]);
  1610. if (status != QLA_SUCCESS) {
  1611. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: "
  1612. "MBOX_CMD_GET_IP_ADDR_STATE failed w/ "
  1613. "status %04X\n", __func__, mbox_sts[0]));
  1614. }
  1615. memcpy(sts, mbox_sts, sizeof(mbox_sts));
  1616. return status;
  1617. }
  1618. int qla4xxx_get_nvram(struct scsi_qla_host *ha, dma_addr_t nvram_dma,
  1619. uint32_t offset, uint32_t size)
  1620. {
  1621. int status = QLA_SUCCESS;
  1622. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1623. uint32_t mbox_sts[MBOX_REG_COUNT];
  1624. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1625. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1626. mbox_cmd[0] = MBOX_CMD_GET_NVRAM;
  1627. mbox_cmd[1] = LSDW(nvram_dma);
  1628. mbox_cmd[2] = MSDW(nvram_dma);
  1629. mbox_cmd[3] = offset;
  1630. mbox_cmd[4] = size;
  1631. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
  1632. &mbox_sts[0]);
  1633. if (status != QLA_SUCCESS) {
  1634. DEBUG2(ql4_printk(KERN_ERR, ha, "scsi%ld: %s: failed "
  1635. "status %04X\n", ha->host_no, __func__,
  1636. mbox_sts[0]));
  1637. }
  1638. return status;
  1639. }
  1640. int qla4xxx_set_nvram(struct scsi_qla_host *ha, dma_addr_t nvram_dma,
  1641. uint32_t offset, uint32_t size)
  1642. {
  1643. int status = QLA_SUCCESS;
  1644. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1645. uint32_t mbox_sts[MBOX_REG_COUNT];
  1646. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1647. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1648. mbox_cmd[0] = MBOX_CMD_SET_NVRAM;
  1649. mbox_cmd[1] = LSDW(nvram_dma);
  1650. mbox_cmd[2] = MSDW(nvram_dma);
  1651. mbox_cmd[3] = offset;
  1652. mbox_cmd[4] = size;
  1653. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
  1654. &mbox_sts[0]);
  1655. if (status != QLA_SUCCESS) {
  1656. DEBUG2(ql4_printk(KERN_ERR, ha, "scsi%ld: %s: failed "
  1657. "status %04X\n", ha->host_no, __func__,
  1658. mbox_sts[0]));
  1659. }
  1660. return status;
  1661. }
  1662. int qla4xxx_restore_factory_defaults(struct scsi_qla_host *ha,
  1663. uint32_t region, uint32_t field0,
  1664. uint32_t field1)
  1665. {
  1666. int status = QLA_SUCCESS;
  1667. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1668. uint32_t mbox_sts[MBOX_REG_COUNT];
  1669. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1670. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1671. mbox_cmd[0] = MBOX_CMD_RESTORE_FACTORY_DEFAULTS;
  1672. mbox_cmd[3] = region;
  1673. mbox_cmd[4] = field0;
  1674. mbox_cmd[5] = field1;
  1675. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0],
  1676. &mbox_sts[0]);
  1677. if (status != QLA_SUCCESS) {
  1678. DEBUG2(ql4_printk(KERN_ERR, ha, "scsi%ld: %s: failed "
  1679. "status %04X\n", ha->host_no, __func__,
  1680. mbox_sts[0]));
  1681. }
  1682. return status;
  1683. }
  1684. /**
  1685. * qla4_8xxx_set_param - set driver version in firmware.
  1686. * @ha: Pointer to host adapter structure.
  1687. * @param: Parameter to set i.e driver version
  1688. **/
  1689. int qla4_8xxx_set_param(struct scsi_qla_host *ha, int param)
  1690. {
  1691. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1692. uint32_t mbox_sts[MBOX_REG_COUNT];
  1693. uint32_t status;
  1694. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1695. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1696. mbox_cmd[0] = MBOX_CMD_SET_PARAM;
  1697. if (param == SET_DRVR_VERSION) {
  1698. mbox_cmd[1] = SET_DRVR_VERSION;
  1699. strncpy((char *)&mbox_cmd[2], QLA4XXX_DRIVER_VERSION,
  1700. MAX_DRVR_VER_LEN);
  1701. } else {
  1702. ql4_printk(KERN_ERR, ha, "%s: invalid parameter 0x%x\n",
  1703. __func__, param);
  1704. status = QLA_ERROR;
  1705. goto exit_set_param;
  1706. }
  1707. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, mbox_cmd,
  1708. mbox_sts);
  1709. if (status == QLA_ERROR)
  1710. ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n",
  1711. __func__, mbox_sts[0]);
  1712. exit_set_param:
  1713. return status;
  1714. }
  1715. /**
  1716. * qla4_83xx_post_idc_ack - post IDC ACK
  1717. * @ha: Pointer to host adapter structure.
  1718. *
  1719. * Posts IDC ACK for IDC Request Notification AEN.
  1720. **/
  1721. int qla4_83xx_post_idc_ack(struct scsi_qla_host *ha)
  1722. {
  1723. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1724. uint32_t mbox_sts[MBOX_REG_COUNT];
  1725. int status;
  1726. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1727. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1728. mbox_cmd[0] = MBOX_CMD_IDC_ACK;
  1729. mbox_cmd[1] = ha->idc_info.request_desc;
  1730. mbox_cmd[2] = ha->idc_info.info1;
  1731. mbox_cmd[3] = ha->idc_info.info2;
  1732. mbox_cmd[4] = ha->idc_info.info3;
  1733. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT,
  1734. mbox_cmd, mbox_sts);
  1735. if (status == QLA_ERROR)
  1736. ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n", __func__,
  1737. mbox_sts[0]);
  1738. else
  1739. DEBUG2(ql4_printk(KERN_INFO, ha, "%s: IDC ACK posted\n",
  1740. __func__));
  1741. return status;
  1742. }