pasemi_mac.c 36 KB

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  1. /*
  2. * Copyright (C) 2006-2007 PA Semi, Inc
  3. *
  4. * Driver for the PA Semi PWRficient onchip 1G/10G Ethernet MACs
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. */
  19. #include <linux/init.h>
  20. #include <linux/module.h>
  21. #include <linux/pci.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/dmaengine.h>
  24. #include <linux/delay.h>
  25. #include <linux/netdevice.h>
  26. #include <linux/etherdevice.h>
  27. #include <asm/dma-mapping.h>
  28. #include <linux/in.h>
  29. #include <linux/skbuff.h>
  30. #include <linux/ip.h>
  31. #include <linux/tcp.h>
  32. #include <net/checksum.h>
  33. #include <asm/irq.h>
  34. #include <asm/firmware.h>
  35. #include <asm/pasemi_dma.h>
  36. #include "pasemi_mac.h"
  37. /* We have our own align, since ppc64 in general has it at 0 because
  38. * of design flaws in some of the server bridge chips. However, for
  39. * PWRficient doing the unaligned copies is more expensive than doing
  40. * unaligned DMA, so make sure the data is aligned instead.
  41. */
  42. #define LOCAL_SKB_ALIGN 2
  43. /* TODO list
  44. *
  45. * - Multicast support
  46. * - Large MTU support
  47. * - SW LRO
  48. * - Multiqueue RX/TX
  49. */
  50. /* Must be a power of two */
  51. #define RX_RING_SIZE 1024
  52. #define TX_RING_SIZE 4096
  53. #define DEFAULT_MSG_ENABLE \
  54. (NETIF_MSG_DRV | \
  55. NETIF_MSG_PROBE | \
  56. NETIF_MSG_LINK | \
  57. NETIF_MSG_TIMER | \
  58. NETIF_MSG_IFDOWN | \
  59. NETIF_MSG_IFUP | \
  60. NETIF_MSG_RX_ERR | \
  61. NETIF_MSG_TX_ERR)
  62. #define TX_DESC(tx, num) ((tx)->chan.ring_virt[(num) & (TX_RING_SIZE-1)])
  63. #define TX_DESC_INFO(tx, num) ((tx)->ring_info[(num) & (TX_RING_SIZE-1)])
  64. #define RX_DESC(rx, num) ((rx)->chan.ring_virt[(num) & (RX_RING_SIZE-1)])
  65. #define RX_DESC_INFO(rx, num) ((rx)->ring_info[(num) & (RX_RING_SIZE-1)])
  66. #define RX_BUFF(rx, num) ((rx)->buffers[(num) & (RX_RING_SIZE-1)])
  67. #define RING_USED(ring) (((ring)->next_to_fill - (ring)->next_to_clean) \
  68. & ((ring)->size - 1))
  69. #define RING_AVAIL(ring) ((ring->size) - RING_USED(ring))
  70. #define BUF_SIZE 1646 /* 1500 MTU + ETH_HLEN + VLAN_HLEN + 2 64B cachelines */
  71. MODULE_LICENSE("GPL");
  72. MODULE_AUTHOR ("Olof Johansson <olof@lixom.net>");
  73. MODULE_DESCRIPTION("PA Semi PWRficient Ethernet driver");
  74. static int debug = -1; /* -1 == use DEFAULT_MSG_ENABLE as value */
  75. module_param(debug, int, 0);
  76. MODULE_PARM_DESC(debug, "PA Semi MAC bitmapped debugging message enable value");
  77. static int translation_enabled(void)
  78. {
  79. #if defined(CONFIG_PPC_PASEMI_IOMMU_DMA_FORCE)
  80. return 1;
  81. #else
  82. return firmware_has_feature(FW_FEATURE_LPAR);
  83. #endif
  84. }
  85. static void write_iob_reg(unsigned int reg, unsigned int val)
  86. {
  87. pasemi_write_iob_reg(reg, val);
  88. }
  89. static unsigned int read_mac_reg(const struct pasemi_mac *mac, unsigned int reg)
  90. {
  91. return pasemi_read_mac_reg(mac->dma_if, reg);
  92. }
  93. static void write_mac_reg(const struct pasemi_mac *mac, unsigned int reg,
  94. unsigned int val)
  95. {
  96. pasemi_write_mac_reg(mac->dma_if, reg, val);
  97. }
  98. static unsigned int read_dma_reg(unsigned int reg)
  99. {
  100. return pasemi_read_dma_reg(reg);
  101. }
  102. static void write_dma_reg(unsigned int reg, unsigned int val)
  103. {
  104. pasemi_write_dma_reg(reg, val);
  105. }
  106. static struct pasemi_mac_rxring *rx_ring(const struct pasemi_mac *mac)
  107. {
  108. return mac->rx;
  109. }
  110. static struct pasemi_mac_txring *tx_ring(const struct pasemi_mac *mac)
  111. {
  112. return mac->tx;
  113. }
  114. static inline void prefetch_skb(const struct sk_buff *skb)
  115. {
  116. const void *d = skb;
  117. prefetch(d);
  118. prefetch(d+64);
  119. prefetch(d+128);
  120. prefetch(d+192);
  121. }
  122. static int mac_to_intf(struct pasemi_mac *mac)
  123. {
  124. struct pci_dev *pdev = mac->pdev;
  125. u32 tmp;
  126. int nintf, off, i, j;
  127. int devfn = pdev->devfn;
  128. tmp = read_dma_reg(PAS_DMA_CAP_IFI);
  129. nintf = (tmp & PAS_DMA_CAP_IFI_NIN_M) >> PAS_DMA_CAP_IFI_NIN_S;
  130. off = (tmp & PAS_DMA_CAP_IFI_IOFF_M) >> PAS_DMA_CAP_IFI_IOFF_S;
  131. /* IOFF contains the offset to the registers containing the
  132. * DMA interface-to-MAC-pci-id mappings, and NIN contains number
  133. * of total interfaces. Each register contains 4 devfns.
  134. * Just do a linear search until we find the devfn of the MAC
  135. * we're trying to look up.
  136. */
  137. for (i = 0; i < (nintf+3)/4; i++) {
  138. tmp = read_dma_reg(off+4*i);
  139. for (j = 0; j < 4; j++) {
  140. if (((tmp >> (8*j)) & 0xff) == devfn)
  141. return i*4 + j;
  142. }
  143. }
  144. return -1;
  145. }
  146. static int pasemi_get_mac_addr(struct pasemi_mac *mac)
  147. {
  148. struct pci_dev *pdev = mac->pdev;
  149. struct device_node *dn = pci_device_to_OF_node(pdev);
  150. int len;
  151. const u8 *maddr;
  152. u8 addr[6];
  153. if (!dn) {
  154. dev_dbg(&pdev->dev,
  155. "No device node for mac, not configuring\n");
  156. return -ENOENT;
  157. }
  158. maddr = of_get_property(dn, "local-mac-address", &len);
  159. if (maddr && len == 6) {
  160. memcpy(mac->mac_addr, maddr, 6);
  161. return 0;
  162. }
  163. /* Some old versions of firmware mistakenly uses mac-address
  164. * (and as a string) instead of a byte array in local-mac-address.
  165. */
  166. if (maddr == NULL)
  167. maddr = of_get_property(dn, "mac-address", NULL);
  168. if (maddr == NULL) {
  169. dev_warn(&pdev->dev,
  170. "no mac address in device tree, not configuring\n");
  171. return -ENOENT;
  172. }
  173. if (sscanf(maddr, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &addr[0],
  174. &addr[1], &addr[2], &addr[3], &addr[4], &addr[5]) != 6) {
  175. dev_warn(&pdev->dev,
  176. "can't parse mac address, not configuring\n");
  177. return -EINVAL;
  178. }
  179. memcpy(mac->mac_addr, addr, 6);
  180. return 0;
  181. }
  182. static int pasemi_mac_unmap_tx_skb(struct pasemi_mac *mac,
  183. struct sk_buff *skb,
  184. const dma_addr_t *dmas)
  185. {
  186. int f;
  187. int nfrags = skb_shinfo(skb)->nr_frags;
  188. struct pci_dev *pdev = mac->dma_pdev;
  189. pci_unmap_single(pdev, dmas[0], skb_headlen(skb), PCI_DMA_TODEVICE);
  190. for (f = 0; f < nfrags; f++) {
  191. skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
  192. pci_unmap_page(pdev, dmas[f+1], frag->size, PCI_DMA_TODEVICE);
  193. }
  194. dev_kfree_skb_irq(skb);
  195. /* Freed descriptor slot + main SKB ptr + nfrags additional ptrs,
  196. * aligned up to a power of 2
  197. */
  198. return (nfrags + 3) & ~1;
  199. }
  200. static int pasemi_mac_setup_rx_resources(const struct net_device *dev)
  201. {
  202. struct pasemi_mac_rxring *ring;
  203. struct pasemi_mac *mac = netdev_priv(dev);
  204. int chno;
  205. unsigned int cfg;
  206. ring = pasemi_dma_alloc_chan(RXCHAN, sizeof(struct pasemi_mac_rxring),
  207. offsetof(struct pasemi_mac_rxring, chan));
  208. if (!ring) {
  209. dev_err(&mac->pdev->dev, "Can't allocate RX channel\n");
  210. goto out_chan;
  211. }
  212. chno = ring->chan.chno;
  213. spin_lock_init(&ring->lock);
  214. ring->size = RX_RING_SIZE;
  215. ring->ring_info = kzalloc(sizeof(struct pasemi_mac_buffer) *
  216. RX_RING_SIZE, GFP_KERNEL);
  217. if (!ring->ring_info)
  218. goto out_ring_info;
  219. /* Allocate descriptors */
  220. if (pasemi_dma_alloc_ring(&ring->chan, RX_RING_SIZE))
  221. goto out_ring_desc;
  222. ring->buffers = dma_alloc_coherent(&mac->dma_pdev->dev,
  223. RX_RING_SIZE * sizeof(u64),
  224. &ring->buf_dma, GFP_KERNEL);
  225. if (!ring->buffers)
  226. goto out_ring_desc;
  227. memset(ring->buffers, 0, RX_RING_SIZE * sizeof(u64));
  228. write_dma_reg(PAS_DMA_RXCHAN_BASEL(chno),
  229. PAS_DMA_RXCHAN_BASEL_BRBL(ring->chan.ring_dma));
  230. write_dma_reg(PAS_DMA_RXCHAN_BASEU(chno),
  231. PAS_DMA_RXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32) |
  232. PAS_DMA_RXCHAN_BASEU_SIZ(RX_RING_SIZE >> 3));
  233. cfg = PAS_DMA_RXCHAN_CFG_HBU(2);
  234. if (translation_enabled())
  235. cfg |= PAS_DMA_RXCHAN_CFG_CTR;
  236. write_dma_reg(PAS_DMA_RXCHAN_CFG(chno), cfg);
  237. write_dma_reg(PAS_DMA_RXINT_BASEL(mac->dma_if),
  238. PAS_DMA_RXINT_BASEL_BRBL(ring->buf_dma));
  239. write_dma_reg(PAS_DMA_RXINT_BASEU(mac->dma_if),
  240. PAS_DMA_RXINT_BASEU_BRBH(ring->buf_dma >> 32) |
  241. PAS_DMA_RXINT_BASEU_SIZ(RX_RING_SIZE >> 3));
  242. cfg = PAS_DMA_RXINT_CFG_DHL(2) | PAS_DMA_RXINT_CFG_L2 |
  243. PAS_DMA_RXINT_CFG_LW | PAS_DMA_RXINT_CFG_RBP |
  244. PAS_DMA_RXINT_CFG_HEN;
  245. if (translation_enabled())
  246. cfg |= PAS_DMA_RXINT_CFG_ITRR | PAS_DMA_RXINT_CFG_ITR;
  247. write_dma_reg(PAS_DMA_RXINT_CFG(mac->dma_if), cfg);
  248. ring->next_to_fill = 0;
  249. ring->next_to_clean = 0;
  250. ring->mac = mac;
  251. mac->rx = ring;
  252. return 0;
  253. out_ring_desc:
  254. kfree(ring->ring_info);
  255. out_ring_info:
  256. pasemi_dma_free_chan(&ring->chan);
  257. out_chan:
  258. return -ENOMEM;
  259. }
  260. static struct pasemi_mac_txring *
  261. pasemi_mac_setup_tx_resources(const struct net_device *dev)
  262. {
  263. struct pasemi_mac *mac = netdev_priv(dev);
  264. u32 val;
  265. struct pasemi_mac_txring *ring;
  266. unsigned int cfg;
  267. int chno;
  268. ring = pasemi_dma_alloc_chan(TXCHAN, sizeof(struct pasemi_mac_txring),
  269. offsetof(struct pasemi_mac_txring, chan));
  270. if (!ring) {
  271. dev_err(&mac->pdev->dev, "Can't allocate TX channel\n");
  272. goto out_chan;
  273. }
  274. chno = ring->chan.chno;
  275. spin_lock_init(&ring->lock);
  276. ring->size = TX_RING_SIZE;
  277. ring->ring_info = kzalloc(sizeof(struct pasemi_mac_buffer) *
  278. TX_RING_SIZE, GFP_KERNEL);
  279. if (!ring->ring_info)
  280. goto out_ring_info;
  281. /* Allocate descriptors */
  282. if (pasemi_dma_alloc_ring(&ring->chan, TX_RING_SIZE))
  283. goto out_ring_desc;
  284. write_dma_reg(PAS_DMA_TXCHAN_BASEL(chno),
  285. PAS_DMA_TXCHAN_BASEL_BRBL(ring->chan.ring_dma));
  286. val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32);
  287. val |= PAS_DMA_TXCHAN_BASEU_SIZ(TX_RING_SIZE >> 3);
  288. write_dma_reg(PAS_DMA_TXCHAN_BASEU(chno), val);
  289. cfg = PAS_DMA_TXCHAN_CFG_TY_IFACE |
  290. PAS_DMA_TXCHAN_CFG_TATTR(mac->dma_if) |
  291. PAS_DMA_TXCHAN_CFG_UP |
  292. PAS_DMA_TXCHAN_CFG_WT(2);
  293. if (translation_enabled())
  294. cfg |= PAS_DMA_TXCHAN_CFG_TRD | PAS_DMA_TXCHAN_CFG_TRR;
  295. write_dma_reg(PAS_DMA_TXCHAN_CFG(chno), cfg);
  296. ring->next_to_fill = 0;
  297. ring->next_to_clean = 0;
  298. ring->mac = mac;
  299. return ring;
  300. out_ring_desc:
  301. kfree(ring->ring_info);
  302. out_ring_info:
  303. pasemi_dma_free_chan(&ring->chan);
  304. out_chan:
  305. return NULL;
  306. }
  307. static void pasemi_mac_free_tx_resources(struct pasemi_mac *mac)
  308. {
  309. struct pasemi_mac_txring *txring = tx_ring(mac);
  310. unsigned int i, j;
  311. struct pasemi_mac_buffer *info;
  312. dma_addr_t dmas[MAX_SKB_FRAGS+1];
  313. int freed;
  314. int start, limit;
  315. start = txring->next_to_clean;
  316. limit = txring->next_to_fill;
  317. /* Compensate for when fill has wrapped and clean has not */
  318. if (start > limit)
  319. limit += TX_RING_SIZE;
  320. for (i = start; i < limit; i += freed) {
  321. info = &txring->ring_info[(i+1) & (TX_RING_SIZE-1)];
  322. if (info->dma && info->skb) {
  323. for (j = 0; j <= skb_shinfo(info->skb)->nr_frags; j++)
  324. dmas[j] = txring->ring_info[(i+1+j) &
  325. (TX_RING_SIZE-1)].dma;
  326. freed = pasemi_mac_unmap_tx_skb(mac, info->skb, dmas);
  327. } else
  328. freed = 2;
  329. }
  330. kfree(txring->ring_info);
  331. pasemi_dma_free_chan(&txring->chan);
  332. }
  333. static void pasemi_mac_free_rx_resources(struct pasemi_mac *mac)
  334. {
  335. struct pasemi_mac_rxring *rx = rx_ring(mac);
  336. unsigned int i;
  337. struct pasemi_mac_buffer *info;
  338. for (i = 0; i < RX_RING_SIZE; i++) {
  339. info = &RX_DESC_INFO(rx, i);
  340. if (info->skb && info->dma) {
  341. pci_unmap_single(mac->dma_pdev,
  342. info->dma,
  343. info->skb->len,
  344. PCI_DMA_FROMDEVICE);
  345. dev_kfree_skb_any(info->skb);
  346. }
  347. info->dma = 0;
  348. info->skb = NULL;
  349. }
  350. for (i = 0; i < RX_RING_SIZE; i++)
  351. RX_DESC(rx, i) = 0;
  352. dma_free_coherent(&mac->dma_pdev->dev, RX_RING_SIZE * sizeof(u64),
  353. rx_ring(mac)->buffers, rx_ring(mac)->buf_dma);
  354. kfree(rx_ring(mac)->ring_info);
  355. pasemi_dma_free_chan(&rx_ring(mac)->chan);
  356. mac->rx = NULL;
  357. }
  358. static void pasemi_mac_replenish_rx_ring(const struct net_device *dev,
  359. const int limit)
  360. {
  361. const struct pasemi_mac *mac = netdev_priv(dev);
  362. struct pasemi_mac_rxring *rx = rx_ring(mac);
  363. int fill, count;
  364. if (limit <= 0)
  365. return;
  366. fill = rx_ring(mac)->next_to_fill;
  367. for (count = 0; count < limit; count++) {
  368. struct pasemi_mac_buffer *info = &RX_DESC_INFO(rx, fill);
  369. u64 *buff = &RX_BUFF(rx, fill);
  370. struct sk_buff *skb;
  371. dma_addr_t dma;
  372. /* Entry in use? */
  373. WARN_ON(*buff);
  374. /* skb might still be in there for recycle on short receives */
  375. if (info->skb)
  376. skb = info->skb;
  377. else {
  378. skb = dev_alloc_skb(BUF_SIZE);
  379. skb_reserve(skb, LOCAL_SKB_ALIGN);
  380. }
  381. if (unlikely(!skb))
  382. break;
  383. dma = pci_map_single(mac->dma_pdev, skb->data,
  384. BUF_SIZE - LOCAL_SKB_ALIGN,
  385. PCI_DMA_FROMDEVICE);
  386. if (unlikely(dma_mapping_error(dma))) {
  387. dev_kfree_skb_irq(info->skb);
  388. break;
  389. }
  390. info->skb = skb;
  391. info->dma = dma;
  392. *buff = XCT_RXB_LEN(BUF_SIZE) | XCT_RXB_ADDR(dma);
  393. fill++;
  394. }
  395. wmb();
  396. write_dma_reg(PAS_DMA_RXINT_INCR(mac->dma_if), count);
  397. rx_ring(mac)->next_to_fill = (rx_ring(mac)->next_to_fill + count) &
  398. (RX_RING_SIZE - 1);
  399. }
  400. static void pasemi_mac_restart_rx_intr(const struct pasemi_mac *mac)
  401. {
  402. unsigned int reg, pcnt;
  403. /* Re-enable packet count interrupts: finally
  404. * ack the packet count interrupt we got in rx_intr.
  405. */
  406. pcnt = *rx_ring(mac)->chan.status & PAS_STATUS_PCNT_M;
  407. reg = PAS_IOB_DMA_RXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_RXCH_RESET_PINTC;
  408. write_iob_reg(PAS_IOB_DMA_RXCH_RESET(mac->rx->chan.chno), reg);
  409. }
  410. static void pasemi_mac_restart_tx_intr(const struct pasemi_mac *mac)
  411. {
  412. unsigned int reg, pcnt;
  413. /* Re-enable packet count interrupts */
  414. pcnt = *tx_ring(mac)->chan.status & PAS_STATUS_PCNT_M;
  415. reg = PAS_IOB_DMA_TXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_TXCH_RESET_PINTC;
  416. write_iob_reg(PAS_IOB_DMA_TXCH_RESET(tx_ring(mac)->chan.chno), reg);
  417. }
  418. static inline void pasemi_mac_rx_error(const struct pasemi_mac *mac,
  419. const u64 macrx)
  420. {
  421. unsigned int rcmdsta, ccmdsta;
  422. struct pasemi_dmachan *chan = &rx_ring(mac)->chan;
  423. if (!netif_msg_rx_err(mac))
  424. return;
  425. rcmdsta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if));
  426. ccmdsta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(chan->chno));
  427. printk(KERN_ERR "pasemi_mac: rx error. macrx %016lx, rx status %lx\n",
  428. macrx, *chan->status);
  429. printk(KERN_ERR "pasemi_mac: rcmdsta %08x ccmdsta %08x\n",
  430. rcmdsta, ccmdsta);
  431. }
  432. static inline void pasemi_mac_tx_error(const struct pasemi_mac *mac,
  433. const u64 mactx)
  434. {
  435. unsigned int cmdsta;
  436. struct pasemi_dmachan *chan = &tx_ring(mac)->chan;
  437. if (!netif_msg_tx_err(mac))
  438. return;
  439. cmdsta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(chan->chno));
  440. printk(KERN_ERR "pasemi_mac: tx error. mactx 0x%016lx, "\
  441. "tx status 0x%016lx\n", mactx, *chan->status);
  442. printk(KERN_ERR "pasemi_mac: tcmdsta 0x%08x\n", cmdsta);
  443. }
  444. static int pasemi_mac_clean_rx(struct pasemi_mac_rxring *rx,
  445. const int limit)
  446. {
  447. const struct pasemi_dmachan *chan = &rx->chan;
  448. struct pasemi_mac *mac = rx->mac;
  449. struct pci_dev *pdev = mac->dma_pdev;
  450. unsigned int n;
  451. int count, buf_index, tot_bytes, packets;
  452. struct pasemi_mac_buffer *info;
  453. struct sk_buff *skb;
  454. unsigned int len;
  455. u64 macrx, eval;
  456. dma_addr_t dma;
  457. tot_bytes = 0;
  458. packets = 0;
  459. spin_lock(&rx->lock);
  460. n = rx->next_to_clean;
  461. prefetch(&RX_DESC(rx, n));
  462. for (count = 0; count < limit; count++) {
  463. macrx = RX_DESC(rx, n);
  464. prefetch(&RX_DESC(rx, n+4));
  465. if ((macrx & XCT_MACRX_E) ||
  466. (*chan->status & PAS_STATUS_ERROR))
  467. pasemi_mac_rx_error(mac, macrx);
  468. if (!(macrx & XCT_MACRX_O))
  469. break;
  470. info = NULL;
  471. BUG_ON(!(macrx & XCT_MACRX_RR_8BRES));
  472. eval = (RX_DESC(rx, n+1) & XCT_RXRES_8B_EVAL_M) >>
  473. XCT_RXRES_8B_EVAL_S;
  474. buf_index = eval-1;
  475. dma = (RX_DESC(rx, n+2) & XCT_PTR_ADDR_M);
  476. info = &RX_DESC_INFO(rx, buf_index);
  477. skb = info->skb;
  478. prefetch_skb(skb);
  479. len = (macrx & XCT_MACRX_LLEN_M) >> XCT_MACRX_LLEN_S;
  480. pci_unmap_single(pdev, dma, BUF_SIZE-LOCAL_SKB_ALIGN,
  481. PCI_DMA_FROMDEVICE);
  482. if (macrx & XCT_MACRX_CRC) {
  483. /* CRC error flagged */
  484. mac->netdev->stats.rx_errors++;
  485. mac->netdev->stats.rx_crc_errors++;
  486. /* No need to free skb, it'll be reused */
  487. goto next;
  488. }
  489. if (len < 256) {
  490. struct sk_buff *new_skb;
  491. new_skb = netdev_alloc_skb(mac->netdev,
  492. len + LOCAL_SKB_ALIGN);
  493. if (new_skb) {
  494. skb_reserve(new_skb, LOCAL_SKB_ALIGN);
  495. memcpy(new_skb->data, skb->data, len);
  496. /* save the skb in buffer_info as good */
  497. skb = new_skb;
  498. }
  499. /* else just continue with the old one */
  500. } else
  501. info->skb = NULL;
  502. info->dma = 0;
  503. if (likely((macrx & XCT_MACRX_HTY_M) == XCT_MACRX_HTY_IPV4_OK)) {
  504. skb->ip_summed = CHECKSUM_UNNECESSARY;
  505. skb->csum = (macrx & XCT_MACRX_CSUM_M) >>
  506. XCT_MACRX_CSUM_S;
  507. } else
  508. skb->ip_summed = CHECKSUM_NONE;
  509. packets++;
  510. tot_bytes += len;
  511. /* Don't include CRC */
  512. skb_put(skb, len-4);
  513. skb->protocol = eth_type_trans(skb, mac->netdev);
  514. netif_receive_skb(skb);
  515. next:
  516. RX_DESC(rx, n) = 0;
  517. RX_DESC(rx, n+1) = 0;
  518. /* Need to zero it out since hardware doesn't, since the
  519. * replenish loop uses it to tell when it's done.
  520. */
  521. RX_BUFF(rx, buf_index) = 0;
  522. n += 4;
  523. }
  524. if (n > RX_RING_SIZE) {
  525. /* Errata 5971 workaround: L2 target of headers */
  526. write_iob_reg(PAS_IOB_COM_PKTHDRCNT, 0);
  527. n &= (RX_RING_SIZE-1);
  528. }
  529. rx_ring(mac)->next_to_clean = n;
  530. /* Increase is in number of 16-byte entries, and since each descriptor
  531. * with an 8BRES takes up 3x8 bytes (padded to 4x8), increase with
  532. * count*2.
  533. */
  534. write_dma_reg(PAS_DMA_RXCHAN_INCR(mac->rx->chan.chno), count << 1);
  535. pasemi_mac_replenish_rx_ring(mac->netdev, count);
  536. mac->netdev->stats.rx_bytes += tot_bytes;
  537. mac->netdev->stats.rx_packets += packets;
  538. spin_unlock(&rx_ring(mac)->lock);
  539. return count;
  540. }
  541. /* Can't make this too large or we blow the kernel stack limits */
  542. #define TX_CLEAN_BATCHSIZE (128/MAX_SKB_FRAGS)
  543. static int pasemi_mac_clean_tx(struct pasemi_mac_txring *txring)
  544. {
  545. struct pasemi_dmachan *chan = &txring->chan;
  546. struct pasemi_mac *mac = txring->mac;
  547. int i, j;
  548. unsigned int start, descr_count, buf_count, batch_limit;
  549. unsigned int ring_limit;
  550. unsigned int total_count;
  551. unsigned long flags;
  552. struct sk_buff *skbs[TX_CLEAN_BATCHSIZE];
  553. dma_addr_t dmas[TX_CLEAN_BATCHSIZE][MAX_SKB_FRAGS+1];
  554. total_count = 0;
  555. batch_limit = TX_CLEAN_BATCHSIZE;
  556. restart:
  557. spin_lock_irqsave(&txring->lock, flags);
  558. start = txring->next_to_clean;
  559. ring_limit = txring->next_to_fill;
  560. /* Compensate for when fill has wrapped but clean has not */
  561. if (start > ring_limit)
  562. ring_limit += TX_RING_SIZE;
  563. buf_count = 0;
  564. descr_count = 0;
  565. for (i = start;
  566. descr_count < batch_limit && i < ring_limit;
  567. i += buf_count) {
  568. u64 mactx = TX_DESC(txring, i);
  569. struct sk_buff *skb;
  570. if ((mactx & XCT_MACTX_E) ||
  571. (*chan->status & PAS_STATUS_ERROR))
  572. pasemi_mac_tx_error(mac, mactx);
  573. if (unlikely(mactx & XCT_MACTX_O))
  574. /* Not yet transmitted */
  575. break;
  576. skb = TX_DESC_INFO(txring, i+1).skb;
  577. skbs[descr_count] = skb;
  578. buf_count = 2 + skb_shinfo(skb)->nr_frags;
  579. for (j = 0; j <= skb_shinfo(skb)->nr_frags; j++)
  580. dmas[descr_count][j] = TX_DESC_INFO(txring, i+1+j).dma;
  581. TX_DESC(txring, i) = 0;
  582. TX_DESC(txring, i+1) = 0;
  583. /* Since we always fill with an even number of entries, make
  584. * sure we skip any unused one at the end as well.
  585. */
  586. if (buf_count & 1)
  587. buf_count++;
  588. descr_count++;
  589. }
  590. txring->next_to_clean = i & (TX_RING_SIZE-1);
  591. spin_unlock_irqrestore(&txring->lock, flags);
  592. netif_wake_queue(mac->netdev);
  593. for (i = 0; i < descr_count; i++)
  594. pasemi_mac_unmap_tx_skb(mac, skbs[i], dmas[i]);
  595. total_count += descr_count;
  596. /* If the batch was full, try to clean more */
  597. if (descr_count == batch_limit)
  598. goto restart;
  599. return total_count;
  600. }
  601. static irqreturn_t pasemi_mac_rx_intr(int irq, void *data)
  602. {
  603. const struct pasemi_mac_rxring *rxring = data;
  604. struct pasemi_mac *mac = rxring->mac;
  605. struct net_device *dev = mac->netdev;
  606. const struct pasemi_dmachan *chan = &rxring->chan;
  607. unsigned int reg;
  608. if (!(*chan->status & PAS_STATUS_CAUSE_M))
  609. return IRQ_NONE;
  610. /* Don't reset packet count so it won't fire again but clear
  611. * all others.
  612. */
  613. reg = 0;
  614. if (*chan->status & PAS_STATUS_SOFT)
  615. reg |= PAS_IOB_DMA_RXCH_RESET_SINTC;
  616. if (*chan->status & PAS_STATUS_ERROR)
  617. reg |= PAS_IOB_DMA_RXCH_RESET_DINTC;
  618. if (*chan->status & PAS_STATUS_TIMER)
  619. reg |= PAS_IOB_DMA_RXCH_RESET_TINTC;
  620. netif_rx_schedule(dev, &mac->napi);
  621. write_iob_reg(PAS_IOB_DMA_RXCH_RESET(chan->chno), reg);
  622. return IRQ_HANDLED;
  623. }
  624. static irqreturn_t pasemi_mac_tx_intr(int irq, void *data)
  625. {
  626. struct pasemi_mac_txring *txring = data;
  627. const struct pasemi_dmachan *chan = &txring->chan;
  628. unsigned int reg, pcnt;
  629. if (!(*chan->status & PAS_STATUS_CAUSE_M))
  630. return IRQ_NONE;
  631. pasemi_mac_clean_tx(txring);
  632. pcnt = *chan->status & PAS_STATUS_PCNT_M;
  633. reg = PAS_IOB_DMA_TXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_TXCH_RESET_PINTC;
  634. if (*chan->status & PAS_STATUS_SOFT)
  635. reg |= PAS_IOB_DMA_TXCH_RESET_SINTC;
  636. if (*chan->status & PAS_STATUS_ERROR)
  637. reg |= PAS_IOB_DMA_TXCH_RESET_DINTC;
  638. write_iob_reg(PAS_IOB_DMA_TXCH_RESET(chan->chno), reg);
  639. return IRQ_HANDLED;
  640. }
  641. static void pasemi_adjust_link(struct net_device *dev)
  642. {
  643. struct pasemi_mac *mac = netdev_priv(dev);
  644. int msg;
  645. unsigned int flags;
  646. unsigned int new_flags;
  647. if (!mac->phydev->link) {
  648. /* If no link, MAC speed settings don't matter. Just report
  649. * link down and return.
  650. */
  651. if (mac->link && netif_msg_link(mac))
  652. printk(KERN_INFO "%s: Link is down.\n", dev->name);
  653. netif_carrier_off(dev);
  654. mac->link = 0;
  655. return;
  656. } else
  657. netif_carrier_on(dev);
  658. flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG);
  659. new_flags = flags & ~(PAS_MAC_CFG_PCFG_HD | PAS_MAC_CFG_PCFG_SPD_M |
  660. PAS_MAC_CFG_PCFG_TSR_M);
  661. if (!mac->phydev->duplex)
  662. new_flags |= PAS_MAC_CFG_PCFG_HD;
  663. switch (mac->phydev->speed) {
  664. case 1000:
  665. new_flags |= PAS_MAC_CFG_PCFG_SPD_1G |
  666. PAS_MAC_CFG_PCFG_TSR_1G;
  667. break;
  668. case 100:
  669. new_flags |= PAS_MAC_CFG_PCFG_SPD_100M |
  670. PAS_MAC_CFG_PCFG_TSR_100M;
  671. break;
  672. case 10:
  673. new_flags |= PAS_MAC_CFG_PCFG_SPD_10M |
  674. PAS_MAC_CFG_PCFG_TSR_10M;
  675. break;
  676. default:
  677. printk("Unsupported speed %d\n", mac->phydev->speed);
  678. }
  679. /* Print on link or speed/duplex change */
  680. msg = mac->link != mac->phydev->link || flags != new_flags;
  681. mac->duplex = mac->phydev->duplex;
  682. mac->speed = mac->phydev->speed;
  683. mac->link = mac->phydev->link;
  684. if (new_flags != flags)
  685. write_mac_reg(mac, PAS_MAC_CFG_PCFG, new_flags);
  686. if (msg && netif_msg_link(mac))
  687. printk(KERN_INFO "%s: Link is up at %d Mbps, %s duplex.\n",
  688. dev->name, mac->speed, mac->duplex ? "full" : "half");
  689. }
  690. static int pasemi_mac_phy_init(struct net_device *dev)
  691. {
  692. struct pasemi_mac *mac = netdev_priv(dev);
  693. struct device_node *dn, *phy_dn;
  694. struct phy_device *phydev;
  695. unsigned int phy_id;
  696. const phandle *ph;
  697. const unsigned int *prop;
  698. struct resource r;
  699. int ret;
  700. dn = pci_device_to_OF_node(mac->pdev);
  701. ph = of_get_property(dn, "phy-handle", NULL);
  702. if (!ph)
  703. return -ENODEV;
  704. phy_dn = of_find_node_by_phandle(*ph);
  705. prop = of_get_property(phy_dn, "reg", NULL);
  706. ret = of_address_to_resource(phy_dn->parent, 0, &r);
  707. if (ret)
  708. goto err;
  709. phy_id = *prop;
  710. snprintf(mac->phy_id, BUS_ID_SIZE, PHY_ID_FMT, (int)r.start, phy_id);
  711. of_node_put(phy_dn);
  712. mac->link = 0;
  713. mac->speed = 0;
  714. mac->duplex = -1;
  715. phydev = phy_connect(dev, mac->phy_id, &pasemi_adjust_link, 0, PHY_INTERFACE_MODE_SGMII);
  716. if (IS_ERR(phydev)) {
  717. printk(KERN_ERR "%s: Could not attach to phy\n", dev->name);
  718. return PTR_ERR(phydev);
  719. }
  720. mac->phydev = phydev;
  721. return 0;
  722. err:
  723. of_node_put(phy_dn);
  724. return -ENODEV;
  725. }
  726. static int pasemi_mac_open(struct net_device *dev)
  727. {
  728. struct pasemi_mac *mac = netdev_priv(dev);
  729. unsigned int flags;
  730. int ret;
  731. /* enable rx section */
  732. write_dma_reg(PAS_DMA_COM_RXCMD, PAS_DMA_COM_RXCMD_EN);
  733. /* enable tx section */
  734. write_dma_reg(PAS_DMA_COM_TXCMD, PAS_DMA_COM_TXCMD_EN);
  735. flags = PAS_MAC_CFG_TXP_FCE | PAS_MAC_CFG_TXP_FPC(3) |
  736. PAS_MAC_CFG_TXP_SL(3) | PAS_MAC_CFG_TXP_COB(0xf) |
  737. PAS_MAC_CFG_TXP_TIFT(8) | PAS_MAC_CFG_TXP_TIFG(12);
  738. write_mac_reg(mac, PAS_MAC_CFG_TXP, flags);
  739. /* 0xffffff is max value, about 16ms */
  740. write_iob_reg(PAS_IOB_DMA_COM_TIMEOUTCFG,
  741. PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(0xffffff));
  742. ret = pasemi_mac_setup_rx_resources(dev);
  743. if (ret)
  744. goto out_rx_resources;
  745. mac->tx = pasemi_mac_setup_tx_resources(dev);
  746. if (!mac->tx)
  747. goto out_tx_ring;
  748. write_iob_reg(PAS_IOB_DMA_RXCH_CFG(mac->rx->chan.chno),
  749. PAS_IOB_DMA_RXCH_CFG_CNTTH(0));
  750. write_iob_reg(PAS_IOB_DMA_TXCH_CFG(mac->tx->chan.chno),
  751. PAS_IOB_DMA_TXCH_CFG_CNTTH(128));
  752. write_mac_reg(mac, PAS_MAC_IPC_CHNL,
  753. PAS_MAC_IPC_CHNL_DCHNO(mac->rx->chan.chno) |
  754. PAS_MAC_IPC_CHNL_BCH(mac->rx->chan.chno));
  755. /* enable rx if */
  756. write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
  757. PAS_DMA_RXINT_RCMDSTA_EN |
  758. PAS_DMA_RXINT_RCMDSTA_DROPS_M |
  759. PAS_DMA_RXINT_RCMDSTA_BP |
  760. PAS_DMA_RXINT_RCMDSTA_OO |
  761. PAS_DMA_RXINT_RCMDSTA_BT);
  762. /* enable rx channel */
  763. pasemi_dma_start_chan(&rx_ring(mac)->chan, PAS_DMA_RXCHAN_CCMDSTA_DU |
  764. PAS_DMA_RXCHAN_CCMDSTA_OD |
  765. PAS_DMA_RXCHAN_CCMDSTA_FD |
  766. PAS_DMA_RXCHAN_CCMDSTA_DT);
  767. /* enable tx channel */
  768. pasemi_dma_start_chan(&tx_ring(mac)->chan, PAS_DMA_TXCHAN_TCMDSTA_SZ |
  769. PAS_DMA_TXCHAN_TCMDSTA_DB |
  770. PAS_DMA_TXCHAN_TCMDSTA_DE |
  771. PAS_DMA_TXCHAN_TCMDSTA_DA);
  772. pasemi_mac_replenish_rx_ring(dev, RX_RING_SIZE);
  773. write_dma_reg(PAS_DMA_RXCHAN_INCR(rx_ring(mac)->chan.chno),
  774. RX_RING_SIZE>>1);
  775. /* Clear out any residual packet count state from firmware */
  776. pasemi_mac_restart_rx_intr(mac);
  777. pasemi_mac_restart_tx_intr(mac);
  778. flags = PAS_MAC_CFG_PCFG_S1 | PAS_MAC_CFG_PCFG_PE |
  779. PAS_MAC_CFG_PCFG_PR | PAS_MAC_CFG_PCFG_CE;
  780. if (mac->type == MAC_TYPE_GMAC)
  781. flags |= PAS_MAC_CFG_PCFG_TSR_1G | PAS_MAC_CFG_PCFG_SPD_1G;
  782. else
  783. flags |= PAS_MAC_CFG_PCFG_TSR_10G | PAS_MAC_CFG_PCFG_SPD_10G;
  784. /* Enable interface in MAC */
  785. write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags);
  786. ret = pasemi_mac_phy_init(dev);
  787. /* Some configs don't have PHYs (XAUI etc), so don't complain about
  788. * failed init due to -ENODEV.
  789. */
  790. if (ret && ret != -ENODEV)
  791. dev_warn(&mac->pdev->dev, "phy init failed: %d\n", ret);
  792. netif_start_queue(dev);
  793. napi_enable(&mac->napi);
  794. snprintf(mac->tx_irq_name, sizeof(mac->tx_irq_name), "%s tx",
  795. dev->name);
  796. ret = request_irq(mac->tx->chan.irq, &pasemi_mac_tx_intr, IRQF_DISABLED,
  797. mac->tx_irq_name, mac->tx);
  798. if (ret) {
  799. dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n",
  800. mac->tx->chan.irq, ret);
  801. goto out_tx_int;
  802. }
  803. snprintf(mac->rx_irq_name, sizeof(mac->rx_irq_name), "%s rx",
  804. dev->name);
  805. ret = request_irq(mac->rx->chan.irq, &pasemi_mac_rx_intr, IRQF_DISABLED,
  806. mac->rx_irq_name, mac->rx);
  807. if (ret) {
  808. dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n",
  809. mac->rx->chan.irq, ret);
  810. goto out_rx_int;
  811. }
  812. if (mac->phydev)
  813. phy_start(mac->phydev);
  814. return 0;
  815. out_rx_int:
  816. free_irq(mac->tx->chan.irq, mac->tx);
  817. out_tx_int:
  818. napi_disable(&mac->napi);
  819. netif_stop_queue(dev);
  820. out_tx_ring:
  821. if (mac->tx)
  822. pasemi_mac_free_tx_resources(mac);
  823. pasemi_mac_free_rx_resources(mac);
  824. out_rx_resources:
  825. return ret;
  826. }
  827. #define MAX_RETRIES 5000
  828. static int pasemi_mac_close(struct net_device *dev)
  829. {
  830. struct pasemi_mac *mac = netdev_priv(dev);
  831. unsigned int sta;
  832. int retries;
  833. int rxch, txch;
  834. rxch = rx_ring(mac)->chan.chno;
  835. txch = tx_ring(mac)->chan.chno;
  836. if (mac->phydev) {
  837. phy_stop(mac->phydev);
  838. phy_disconnect(mac->phydev);
  839. }
  840. netif_stop_queue(dev);
  841. napi_disable(&mac->napi);
  842. sta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if));
  843. if (sta & (PAS_DMA_RXINT_RCMDSTA_BP |
  844. PAS_DMA_RXINT_RCMDSTA_OO |
  845. PAS_DMA_RXINT_RCMDSTA_BT))
  846. printk(KERN_DEBUG "pasemi_mac: rcmdsta error: 0x%08x\n", sta);
  847. sta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch));
  848. if (sta & (PAS_DMA_RXCHAN_CCMDSTA_DU |
  849. PAS_DMA_RXCHAN_CCMDSTA_OD |
  850. PAS_DMA_RXCHAN_CCMDSTA_FD |
  851. PAS_DMA_RXCHAN_CCMDSTA_DT))
  852. printk(KERN_DEBUG "pasemi_mac: ccmdsta error: 0x%08x\n", sta);
  853. sta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch));
  854. if (sta & (PAS_DMA_TXCHAN_TCMDSTA_SZ | PAS_DMA_TXCHAN_TCMDSTA_DB |
  855. PAS_DMA_TXCHAN_TCMDSTA_DE | PAS_DMA_TXCHAN_TCMDSTA_DA))
  856. printk(KERN_DEBUG "pasemi_mac: tcmdsta error: 0x%08x\n", sta);
  857. /* Clean out any pending buffers */
  858. pasemi_mac_clean_tx(tx_ring(mac));
  859. pasemi_mac_clean_rx(rx_ring(mac), RX_RING_SIZE);
  860. /* Disable interface */
  861. write_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch),
  862. PAS_DMA_TXCHAN_TCMDSTA_ST);
  863. write_dma_reg( PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
  864. PAS_DMA_RXINT_RCMDSTA_ST);
  865. write_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch),
  866. PAS_DMA_RXCHAN_CCMDSTA_ST);
  867. for (retries = 0; retries < MAX_RETRIES; retries++) {
  868. sta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(rxch));
  869. if (!(sta & PAS_DMA_TXCHAN_TCMDSTA_ACT))
  870. break;
  871. cond_resched();
  872. }
  873. if (sta & PAS_DMA_TXCHAN_TCMDSTA_ACT)
  874. dev_err(&mac->dma_pdev->dev, "Failed to stop tx channel\n");
  875. for (retries = 0; retries < MAX_RETRIES; retries++) {
  876. sta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch));
  877. if (!(sta & PAS_DMA_RXCHAN_CCMDSTA_ACT))
  878. break;
  879. cond_resched();
  880. }
  881. if (sta & PAS_DMA_RXCHAN_CCMDSTA_ACT)
  882. dev_err(&mac->dma_pdev->dev, "Failed to stop rx channel\n");
  883. for (retries = 0; retries < MAX_RETRIES; retries++) {
  884. sta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if));
  885. if (!(sta & PAS_DMA_RXINT_RCMDSTA_ACT))
  886. break;
  887. cond_resched();
  888. }
  889. if (sta & PAS_DMA_RXINT_RCMDSTA_ACT)
  890. dev_err(&mac->dma_pdev->dev, "Failed to stop rx interface\n");
  891. /* Then, disable the channel. This must be done separately from
  892. * stopping, since you can't disable when active.
  893. */
  894. write_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch), 0);
  895. write_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch), 0);
  896. write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if), 0);
  897. free_irq(mac->tx->chan.irq, mac->tx);
  898. free_irq(mac->rx->chan.irq, mac->rx);
  899. /* Free resources */
  900. pasemi_mac_free_rx_resources(mac);
  901. pasemi_mac_free_tx_resources(mac);
  902. return 0;
  903. }
  904. static int pasemi_mac_start_tx(struct sk_buff *skb, struct net_device *dev)
  905. {
  906. struct pasemi_mac *mac = netdev_priv(dev);
  907. struct pasemi_mac_txring *txring;
  908. u64 dflags, mactx;
  909. dma_addr_t map[MAX_SKB_FRAGS+1];
  910. unsigned int map_size[MAX_SKB_FRAGS+1];
  911. unsigned long flags;
  912. int i, nfrags;
  913. int fill;
  914. dflags = XCT_MACTX_O | XCT_MACTX_ST | XCT_MACTX_CRC_PAD;
  915. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  916. const unsigned char *nh = skb_network_header(skb);
  917. switch (ip_hdr(skb)->protocol) {
  918. case IPPROTO_TCP:
  919. dflags |= XCT_MACTX_CSUM_TCP;
  920. dflags |= XCT_MACTX_IPH(skb_network_header_len(skb) >> 2);
  921. dflags |= XCT_MACTX_IPO(nh - skb->data);
  922. break;
  923. case IPPROTO_UDP:
  924. dflags |= XCT_MACTX_CSUM_UDP;
  925. dflags |= XCT_MACTX_IPH(skb_network_header_len(skb) >> 2);
  926. dflags |= XCT_MACTX_IPO(nh - skb->data);
  927. break;
  928. }
  929. }
  930. nfrags = skb_shinfo(skb)->nr_frags;
  931. map[0] = pci_map_single(mac->dma_pdev, skb->data, skb_headlen(skb),
  932. PCI_DMA_TODEVICE);
  933. map_size[0] = skb_headlen(skb);
  934. if (dma_mapping_error(map[0]))
  935. goto out_err_nolock;
  936. for (i = 0; i < nfrags; i++) {
  937. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  938. map[i+1] = pci_map_page(mac->dma_pdev, frag->page,
  939. frag->page_offset, frag->size,
  940. PCI_DMA_TODEVICE);
  941. map_size[i+1] = frag->size;
  942. if (dma_mapping_error(map[i+1])) {
  943. nfrags = i;
  944. goto out_err_nolock;
  945. }
  946. }
  947. mactx = dflags | XCT_MACTX_LLEN(skb->len);
  948. txring = tx_ring(mac);
  949. spin_lock_irqsave(&txring->lock, flags);
  950. fill = txring->next_to_fill;
  951. /* Avoid stepping on the same cache line that the DMA controller
  952. * is currently about to send, so leave at least 8 words available.
  953. * Total free space needed is mactx + fragments + 8
  954. */
  955. if (RING_AVAIL(txring) < nfrags + 10) {
  956. /* no room -- stop the queue and wait for tx intr */
  957. netif_stop_queue(dev);
  958. goto out_err;
  959. }
  960. TX_DESC(txring, fill) = mactx;
  961. fill++;
  962. TX_DESC_INFO(txring, fill).skb = skb;
  963. for (i = 0; i <= nfrags; i++) {
  964. TX_DESC(txring, fill+i) =
  965. XCT_PTR_LEN(map_size[i]) | XCT_PTR_ADDR(map[i]);
  966. TX_DESC_INFO(txring, fill+i).dma = map[i];
  967. }
  968. /* We have to add an even number of 8-byte entries to the ring
  969. * even if the last one is unused. That means always an odd number
  970. * of pointers + one mactx descriptor.
  971. */
  972. if (nfrags & 1)
  973. nfrags++;
  974. txring->next_to_fill = (fill + nfrags + 1) & (TX_RING_SIZE-1);
  975. dev->stats.tx_packets++;
  976. dev->stats.tx_bytes += skb->len;
  977. spin_unlock_irqrestore(&txring->lock, flags);
  978. write_dma_reg(PAS_DMA_TXCHAN_INCR(txring->chan.chno), (nfrags+2) >> 1);
  979. return NETDEV_TX_OK;
  980. out_err:
  981. spin_unlock_irqrestore(&txring->lock, flags);
  982. out_err_nolock:
  983. while (nfrags--)
  984. pci_unmap_single(mac->dma_pdev, map[nfrags], map_size[nfrags],
  985. PCI_DMA_TODEVICE);
  986. return NETDEV_TX_BUSY;
  987. }
  988. static void pasemi_mac_set_rx_mode(struct net_device *dev)
  989. {
  990. const struct pasemi_mac *mac = netdev_priv(dev);
  991. unsigned int flags;
  992. flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG);
  993. /* Set promiscuous */
  994. if (dev->flags & IFF_PROMISC)
  995. flags |= PAS_MAC_CFG_PCFG_PR;
  996. else
  997. flags &= ~PAS_MAC_CFG_PCFG_PR;
  998. write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags);
  999. }
  1000. static int pasemi_mac_poll(struct napi_struct *napi, int budget)
  1001. {
  1002. struct pasemi_mac *mac = container_of(napi, struct pasemi_mac, napi);
  1003. struct net_device *dev = mac->netdev;
  1004. int pkts;
  1005. pasemi_mac_clean_tx(tx_ring(mac));
  1006. pkts = pasemi_mac_clean_rx(rx_ring(mac), budget);
  1007. if (pkts < budget) {
  1008. /* all done, no more packets present */
  1009. netif_rx_complete(dev, napi);
  1010. pasemi_mac_restart_rx_intr(mac);
  1011. }
  1012. return pkts;
  1013. }
  1014. static int __devinit
  1015. pasemi_mac_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  1016. {
  1017. struct net_device *dev;
  1018. struct pasemi_mac *mac;
  1019. int err;
  1020. DECLARE_MAC_BUF(mac_buf);
  1021. err = pci_enable_device(pdev);
  1022. if (err)
  1023. return err;
  1024. dev = alloc_etherdev(sizeof(struct pasemi_mac));
  1025. if (dev == NULL) {
  1026. dev_err(&pdev->dev,
  1027. "pasemi_mac: Could not allocate ethernet device.\n");
  1028. err = -ENOMEM;
  1029. goto out_disable_device;
  1030. }
  1031. pci_set_drvdata(pdev, dev);
  1032. SET_NETDEV_DEV(dev, &pdev->dev);
  1033. mac = netdev_priv(dev);
  1034. mac->pdev = pdev;
  1035. mac->netdev = dev;
  1036. netif_napi_add(dev, &mac->napi, pasemi_mac_poll, 64);
  1037. dev->features = NETIF_F_IP_CSUM | NETIF_F_LLTX | NETIF_F_SG |
  1038. NETIF_F_HIGHDMA;
  1039. mac->dma_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa007, NULL);
  1040. if (!mac->dma_pdev) {
  1041. dev_err(&mac->pdev->dev, "Can't find DMA Controller\n");
  1042. err = -ENODEV;
  1043. goto out;
  1044. }
  1045. mac->iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL);
  1046. if (!mac->iob_pdev) {
  1047. dev_err(&mac->pdev->dev, "Can't find I/O Bridge\n");
  1048. err = -ENODEV;
  1049. goto out;
  1050. }
  1051. /* get mac addr from device tree */
  1052. if (pasemi_get_mac_addr(mac) || !is_valid_ether_addr(mac->mac_addr)) {
  1053. err = -ENODEV;
  1054. goto out;
  1055. }
  1056. memcpy(dev->dev_addr, mac->mac_addr, sizeof(mac->mac_addr));
  1057. mac->dma_if = mac_to_intf(mac);
  1058. if (mac->dma_if < 0) {
  1059. dev_err(&mac->pdev->dev, "Can't map DMA interface\n");
  1060. err = -ENODEV;
  1061. goto out;
  1062. }
  1063. switch (pdev->device) {
  1064. case 0xa005:
  1065. mac->type = MAC_TYPE_GMAC;
  1066. break;
  1067. case 0xa006:
  1068. mac->type = MAC_TYPE_XAUI;
  1069. break;
  1070. default:
  1071. err = -ENODEV;
  1072. goto out;
  1073. }
  1074. dev->open = pasemi_mac_open;
  1075. dev->stop = pasemi_mac_close;
  1076. dev->hard_start_xmit = pasemi_mac_start_tx;
  1077. dev->set_multicast_list = pasemi_mac_set_rx_mode;
  1078. if (err)
  1079. goto out;
  1080. mac->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
  1081. /* Enable most messages by default */
  1082. mac->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
  1083. err = register_netdev(dev);
  1084. if (err) {
  1085. dev_err(&mac->pdev->dev, "register_netdev failed with error %d\n",
  1086. err);
  1087. goto out;
  1088. } else if netif_msg_probe(mac)
  1089. printk(KERN_INFO "%s: PA Semi %s: intf %d, hw addr %s\n",
  1090. dev->name, mac->type == MAC_TYPE_GMAC ? "GMAC" : "XAUI",
  1091. mac->dma_if, print_mac(mac_buf, dev->dev_addr));
  1092. return err;
  1093. out:
  1094. if (mac->iob_pdev)
  1095. pci_dev_put(mac->iob_pdev);
  1096. if (mac->dma_pdev)
  1097. pci_dev_put(mac->dma_pdev);
  1098. free_netdev(dev);
  1099. out_disable_device:
  1100. pci_disable_device(pdev);
  1101. return err;
  1102. }
  1103. static void __devexit pasemi_mac_remove(struct pci_dev *pdev)
  1104. {
  1105. struct net_device *netdev = pci_get_drvdata(pdev);
  1106. struct pasemi_mac *mac;
  1107. if (!netdev)
  1108. return;
  1109. mac = netdev_priv(netdev);
  1110. unregister_netdev(netdev);
  1111. pci_disable_device(pdev);
  1112. pci_dev_put(mac->dma_pdev);
  1113. pci_dev_put(mac->iob_pdev);
  1114. pasemi_dma_free_chan(&mac->tx->chan);
  1115. pasemi_dma_free_chan(&mac->rx->chan);
  1116. pci_set_drvdata(pdev, NULL);
  1117. free_netdev(netdev);
  1118. }
  1119. static struct pci_device_id pasemi_mac_pci_tbl[] = {
  1120. { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa005) },
  1121. { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa006) },
  1122. { },
  1123. };
  1124. MODULE_DEVICE_TABLE(pci, pasemi_mac_pci_tbl);
  1125. static struct pci_driver pasemi_mac_driver = {
  1126. .name = "pasemi_mac",
  1127. .id_table = pasemi_mac_pci_tbl,
  1128. .probe = pasemi_mac_probe,
  1129. .remove = __devexit_p(pasemi_mac_remove),
  1130. };
  1131. static void __exit pasemi_mac_cleanup_module(void)
  1132. {
  1133. pci_unregister_driver(&pasemi_mac_driver);
  1134. }
  1135. int pasemi_mac_init_module(void)
  1136. {
  1137. int err;
  1138. err = pasemi_dma_init();
  1139. if (err)
  1140. return err;
  1141. return pci_register_driver(&pasemi_mac_driver);
  1142. }
  1143. module_init(pasemi_mac_init_module);
  1144. module_exit(pasemi_mac_cleanup_module);