iwl4965-base.c 269 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891289228932894289528962897289828992900290129022903290429052906290729082909291029112912291329142915291629172918291929202921292229232924292529262927292829292930293129322933293429352936293729382939294029412942294329442945294629472948294929502951295229532954295529562957295829592960296129622963296429652966296729682969297029712972297329742975297629772978297929802981298229832984298529862987298829892990299129922993299429952996299729982999300030013002300330043005300630073008300930103011301230133014301530163017301830193020302130223023302430253026302730283029303030313032303330343035303630373038303930403041304230433044304530463047304830493050305130523053305430553056305730583059306030613062306330643065306630673068306930703071307230733074307530763077307830793080308130823083308430853086308730883089309030913092309330943095309630973098309931003101310231033104310531063107310831093110311131123113311431153116311731183119312031213122312331243125312631273128312931303131313231333134313531363137313831393140314131423143314431453146314731483149315031513152315331543155315631573158315931603161316231633164316531663167316831693170317131723173317431753176317731783179318031813182318331843185318631873188318931903191319231933194319531963197319831993200320132023203320432053206320732083209321032113212321332143215321632173218321932203221322232233224322532263227322832293230323132323233323432353236323732383239324032413242324332443245324632473248324932503251325232533254325532563257325832593260326132623263326432653266326732683269327032713272327332743275327632773278327932803281328232833284328532863287328832893290329132923293329432953296329732983299330033013302330333043305330633073308330933103311331233133314331533163317331833193320332133223323332433253326332733283329333033313332333333343335333633373338333933403341334233433344334533463347334833493350335133523353335433553356335733583359336033613362336333643365336633673368336933703371337233733374337533763377337833793380338133823383338433853386338733883389339033913392339333943395339633973398339934003401340234033404340534063407340834093410341134123413341434153416341734183419342034213422342334243425342634273428342934303431343234333434343534363437343834393440344134423443344434453446344734483449345034513452345334543455345634573458345934603461346234633464346534663467346834693470347134723473347434753476347734783479348034813482348334843485348634873488348934903491349234933494349534963497349834993500350135023503350435053506350735083509351035113512351335143515351635173518351935203521352235233524352535263527352835293530353135323533353435353536353735383539354035413542354335443545354635473548354935503551355235533554355535563557355835593560356135623563356435653566356735683569357035713572357335743575357635773578357935803581358235833584358535863587358835893590359135923593359435953596359735983599360036013602360336043605360636073608360936103611361236133614361536163617361836193620362136223623362436253626362736283629363036313632363336343635363636373638363936403641364236433644364536463647364836493650365136523653365436553656365736583659366036613662366336643665366636673668366936703671367236733674367536763677367836793680368136823683368436853686368736883689369036913692369336943695369636973698369937003701370237033704370537063707370837093710371137123713371437153716371737183719372037213722372337243725372637273728372937303731373237333734373537363737373837393740374137423743374437453746374737483749375037513752375337543755375637573758375937603761376237633764376537663767376837693770377137723773377437753776377737783779378037813782378337843785378637873788378937903791379237933794379537963797379837993800380138023803380438053806380738083809381038113812381338143815381638173818381938203821382238233824382538263827382838293830383138323833383438353836383738383839384038413842384338443845384638473848384938503851385238533854385538563857385838593860386138623863386438653866386738683869387038713872387338743875387638773878387938803881388238833884388538863887388838893890389138923893389438953896389738983899390039013902390339043905390639073908390939103911391239133914391539163917391839193920392139223923392439253926392739283929393039313932393339343935393639373938393939403941394239433944394539463947394839493950395139523953395439553956395739583959396039613962396339643965396639673968396939703971397239733974397539763977397839793980398139823983398439853986398739883989399039913992399339943995399639973998399940004001400240034004400540064007400840094010401140124013401440154016401740184019402040214022402340244025402640274028402940304031403240334034403540364037403840394040404140424043404440454046404740484049405040514052405340544055405640574058405940604061406240634064406540664067406840694070407140724073407440754076407740784079408040814082408340844085408640874088408940904091409240934094409540964097409840994100410141024103410441054106410741084109411041114112411341144115411641174118411941204121412241234124412541264127412841294130413141324133413441354136413741384139414041414142414341444145414641474148414941504151415241534154415541564157415841594160416141624163416441654166416741684169417041714172417341744175417641774178417941804181418241834184418541864187418841894190419141924193419441954196419741984199420042014202420342044205420642074208420942104211421242134214421542164217421842194220422142224223422442254226422742284229423042314232423342344235423642374238423942404241424242434244424542464247424842494250425142524253425442554256425742584259426042614262426342644265426642674268426942704271427242734274427542764277427842794280428142824283428442854286428742884289429042914292429342944295429642974298429943004301430243034304430543064307430843094310431143124313431443154316431743184319432043214322432343244325432643274328432943304331433243334334433543364337433843394340434143424343434443454346434743484349435043514352435343544355435643574358435943604361436243634364436543664367436843694370437143724373437443754376437743784379438043814382438343844385438643874388438943904391439243934394439543964397439843994400440144024403440444054406440744084409441044114412441344144415441644174418441944204421442244234424442544264427442844294430443144324433443444354436443744384439444044414442444344444445444644474448444944504451445244534454445544564457445844594460446144624463446444654466446744684469447044714472447344744475447644774478447944804481448244834484448544864487448844894490449144924493449444954496449744984499450045014502450345044505450645074508450945104511451245134514451545164517451845194520452145224523452445254526452745284529453045314532453345344535453645374538453945404541454245434544454545464547454845494550455145524553455445554556455745584559456045614562456345644565456645674568456945704571457245734574457545764577457845794580458145824583458445854586458745884589459045914592459345944595459645974598459946004601460246034604460546064607460846094610461146124613461446154616461746184619462046214622462346244625462646274628462946304631463246334634463546364637463846394640464146424643464446454646464746484649465046514652465346544655465646574658465946604661466246634664466546664667466846694670467146724673467446754676467746784679468046814682468346844685468646874688468946904691469246934694469546964697469846994700470147024703470447054706470747084709471047114712471347144715471647174718471947204721472247234724472547264727472847294730473147324733473447354736473747384739474047414742474347444745474647474748474947504751475247534754475547564757475847594760476147624763476447654766476747684769477047714772477347744775477647774778477947804781478247834784478547864787478847894790479147924793479447954796479747984799480048014802480348044805480648074808480948104811481248134814481548164817481848194820482148224823482448254826482748284829483048314832483348344835483648374838483948404841484248434844484548464847484848494850485148524853485448554856485748584859486048614862486348644865486648674868486948704871487248734874487548764877487848794880488148824883488448854886488748884889489048914892489348944895489648974898489949004901490249034904490549064907490849094910491149124913491449154916491749184919492049214922492349244925492649274928492949304931493249334934493549364937493849394940494149424943494449454946494749484949495049514952495349544955495649574958495949604961496249634964496549664967496849694970497149724973497449754976497749784979498049814982498349844985498649874988498949904991499249934994499549964997499849995000500150025003500450055006500750085009501050115012501350145015501650175018501950205021502250235024502550265027502850295030503150325033503450355036503750385039504050415042504350445045504650475048504950505051505250535054505550565057505850595060506150625063506450655066506750685069507050715072507350745075507650775078507950805081508250835084508550865087508850895090509150925093509450955096509750985099510051015102510351045105510651075108510951105111511251135114511551165117511851195120512151225123512451255126512751285129513051315132513351345135513651375138513951405141514251435144514551465147514851495150515151525153515451555156515751585159516051615162516351645165516651675168516951705171517251735174517551765177517851795180518151825183518451855186518751885189519051915192519351945195519651975198519952005201520252035204520552065207520852095210521152125213521452155216521752185219522052215222522352245225522652275228522952305231523252335234523552365237523852395240524152425243524452455246524752485249525052515252525352545255525652575258525952605261526252635264526552665267526852695270527152725273527452755276527752785279528052815282528352845285528652875288528952905291529252935294529552965297529852995300530153025303530453055306530753085309531053115312531353145315531653175318531953205321532253235324532553265327532853295330533153325333533453355336533753385339534053415342534353445345534653475348534953505351535253535354535553565357535853595360536153625363536453655366536753685369537053715372537353745375537653775378537953805381538253835384538553865387538853895390539153925393539453955396539753985399540054015402540354045405540654075408540954105411541254135414541554165417541854195420542154225423542454255426542754285429543054315432543354345435543654375438543954405441544254435444544554465447544854495450545154525453545454555456545754585459546054615462546354645465546654675468546954705471547254735474547554765477547854795480548154825483548454855486548754885489549054915492549354945495549654975498549955005501550255035504550555065507550855095510551155125513551455155516551755185519552055215522552355245525552655275528552955305531553255335534553555365537553855395540554155425543554455455546554755485549555055515552555355545555555655575558555955605561556255635564556555665567556855695570557155725573557455755576557755785579558055815582558355845585558655875588558955905591559255935594559555965597559855995600560156025603560456055606560756085609561056115612561356145615561656175618561956205621562256235624562556265627562856295630563156325633563456355636563756385639564056415642564356445645564656475648564956505651565256535654565556565657565856595660566156625663566456655666566756685669567056715672567356745675567656775678567956805681568256835684568556865687568856895690569156925693569456955696569756985699570057015702570357045705570657075708570957105711571257135714571557165717571857195720572157225723572457255726572757285729573057315732573357345735573657375738573957405741574257435744574557465747574857495750575157525753575457555756575757585759576057615762576357645765576657675768576957705771577257735774577557765777577857795780578157825783578457855786578757885789579057915792579357945795579657975798579958005801580258035804580558065807580858095810581158125813581458155816581758185819582058215822582358245825582658275828582958305831583258335834583558365837583858395840584158425843584458455846584758485849585058515852585358545855585658575858585958605861586258635864586558665867586858695870587158725873587458755876587758785879588058815882588358845885588658875888588958905891589258935894589558965897589858995900590159025903590459055906590759085909591059115912591359145915591659175918591959205921592259235924592559265927592859295930593159325933593459355936593759385939594059415942594359445945594659475948594959505951595259535954595559565957595859595960596159625963596459655966596759685969597059715972597359745975597659775978597959805981598259835984598559865987598859895990599159925993599459955996599759985999600060016002600360046005600660076008600960106011601260136014601560166017601860196020602160226023602460256026602760286029603060316032603360346035603660376038603960406041604260436044604560466047604860496050605160526053605460556056605760586059606060616062606360646065606660676068606960706071607260736074607560766077607860796080608160826083608460856086608760886089609060916092609360946095609660976098609961006101610261036104610561066107610861096110611161126113611461156116611761186119612061216122612361246125612661276128612961306131613261336134613561366137613861396140614161426143614461456146614761486149615061516152615361546155615661576158615961606161616261636164616561666167616861696170617161726173617461756176617761786179618061816182618361846185618661876188618961906191619261936194619561966197619861996200620162026203620462056206620762086209621062116212621362146215621662176218621962206221622262236224622562266227622862296230623162326233623462356236623762386239624062416242624362446245624662476248624962506251625262536254625562566257625862596260626162626263626462656266626762686269627062716272627362746275627662776278627962806281628262836284628562866287628862896290629162926293629462956296629762986299630063016302630363046305630663076308630963106311631263136314631563166317631863196320632163226323632463256326632763286329633063316332633363346335633663376338633963406341634263436344634563466347634863496350635163526353635463556356635763586359636063616362636363646365636663676368636963706371637263736374637563766377637863796380638163826383638463856386638763886389639063916392639363946395639663976398639964006401640264036404640564066407640864096410641164126413641464156416641764186419642064216422642364246425642664276428642964306431643264336434643564366437643864396440644164426443644464456446644764486449645064516452645364546455645664576458645964606461646264636464646564666467646864696470647164726473647464756476647764786479648064816482648364846485648664876488648964906491649264936494649564966497649864996500650165026503650465056506650765086509651065116512651365146515651665176518651965206521652265236524652565266527652865296530653165326533653465356536653765386539654065416542654365446545654665476548654965506551655265536554655565566557655865596560656165626563656465656566656765686569657065716572657365746575657665776578657965806581658265836584658565866587658865896590659165926593659465956596659765986599660066016602660366046605660666076608660966106611661266136614661566166617661866196620662166226623662466256626662766286629663066316632663366346635663666376638663966406641664266436644664566466647664866496650665166526653665466556656665766586659666066616662666366646665666666676668666966706671667266736674667566766677667866796680668166826683668466856686668766886689669066916692669366946695669666976698669967006701670267036704670567066707670867096710671167126713671467156716671767186719672067216722672367246725672667276728672967306731673267336734673567366737673867396740674167426743674467456746674767486749675067516752675367546755675667576758675967606761676267636764676567666767676867696770677167726773677467756776677767786779678067816782678367846785678667876788678967906791679267936794679567966797679867996800680168026803680468056806680768086809681068116812681368146815681668176818681968206821682268236824682568266827682868296830683168326833683468356836683768386839684068416842684368446845684668476848684968506851685268536854685568566857685868596860686168626863686468656866686768686869687068716872687368746875687668776878687968806881688268836884688568866887688868896890689168926893689468956896689768986899690069016902690369046905690669076908690969106911691269136914691569166917691869196920692169226923692469256926692769286929693069316932693369346935693669376938693969406941694269436944694569466947694869496950695169526953695469556956695769586959696069616962696369646965696669676968696969706971697269736974697569766977697869796980698169826983698469856986698769886989699069916992699369946995699669976998699970007001700270037004700570067007700870097010701170127013701470157016701770187019702070217022702370247025702670277028702970307031703270337034703570367037703870397040704170427043704470457046704770487049705070517052705370547055705670577058705970607061706270637064706570667067706870697070707170727073707470757076707770787079708070817082708370847085708670877088708970907091709270937094709570967097709870997100710171027103710471057106710771087109711071117112711371147115711671177118711971207121712271237124712571267127712871297130713171327133713471357136713771387139714071417142714371447145714671477148714971507151715271537154715571567157715871597160716171627163716471657166716771687169717071717172717371747175717671777178717971807181718271837184718571867187718871897190719171927193719471957196719771987199720072017202720372047205720672077208720972107211721272137214721572167217721872197220722172227223722472257226722772287229723072317232723372347235723672377238723972407241724272437244724572467247724872497250725172527253725472557256725772587259726072617262726372647265726672677268726972707271727272737274727572767277727872797280728172827283728472857286728772887289729072917292729372947295729672977298729973007301730273037304730573067307730873097310731173127313731473157316731773187319732073217322732373247325732673277328732973307331733273337334733573367337733873397340734173427343734473457346734773487349735073517352735373547355735673577358735973607361736273637364736573667367736873697370737173727373737473757376737773787379738073817382738373847385738673877388738973907391739273937394739573967397739873997400740174027403740474057406740774087409741074117412741374147415741674177418741974207421742274237424742574267427742874297430743174327433743474357436743774387439744074417442744374447445744674477448744974507451745274537454745574567457745874597460746174627463746474657466746774687469747074717472747374747475747674777478747974807481748274837484748574867487748874897490749174927493749474957496749774987499750075017502750375047505750675077508750975107511751275137514751575167517751875197520752175227523752475257526752775287529753075317532753375347535753675377538753975407541754275437544754575467547754875497550755175527553755475557556755775587559756075617562756375647565756675677568756975707571757275737574757575767577757875797580758175827583758475857586758775887589759075917592759375947595759675977598759976007601760276037604760576067607760876097610761176127613761476157616761776187619762076217622762376247625762676277628762976307631763276337634763576367637763876397640764176427643764476457646764776487649765076517652765376547655765676577658765976607661766276637664766576667667766876697670767176727673767476757676767776787679768076817682768376847685768676877688768976907691769276937694769576967697769876997700770177027703770477057706770777087709771077117712771377147715771677177718771977207721772277237724772577267727772877297730773177327733773477357736773777387739774077417742774377447745774677477748774977507751775277537754775577567757775877597760776177627763776477657766776777687769777077717772777377747775777677777778777977807781778277837784778577867787778877897790779177927793779477957796779777987799780078017802780378047805780678077808780978107811781278137814781578167817781878197820782178227823782478257826782778287829783078317832783378347835783678377838783978407841784278437844784578467847784878497850785178527853785478557856785778587859786078617862786378647865786678677868786978707871787278737874787578767877787878797880788178827883788478857886788778887889789078917892789378947895789678977898789979007901790279037904790579067907790879097910791179127913791479157916791779187919792079217922792379247925792679277928792979307931793279337934793579367937793879397940794179427943794479457946794779487949795079517952795379547955795679577958795979607961796279637964796579667967796879697970797179727973797479757976797779787979798079817982798379847985798679877988798979907991799279937994799579967997799879998000800180028003800480058006800780088009801080118012801380148015801680178018801980208021802280238024802580268027802880298030803180328033803480358036803780388039804080418042804380448045804680478048804980508051805280538054805580568057805880598060806180628063806480658066806780688069807080718072807380748075807680778078807980808081808280838084808580868087808880898090809180928093809480958096809780988099810081018102810381048105810681078108810981108111811281138114811581168117811881198120812181228123812481258126812781288129813081318132813381348135813681378138813981408141814281438144814581468147814881498150815181528153815481558156815781588159816081618162816381648165816681678168816981708171817281738174817581768177817881798180818181828183818481858186818781888189819081918192819381948195819681978198819982008201820282038204820582068207820882098210821182128213821482158216821782188219822082218222822382248225822682278228822982308231823282338234823582368237823882398240824182428243824482458246824782488249825082518252825382548255825682578258825982608261826282638264826582668267826882698270827182728273827482758276827782788279828082818282828382848285828682878288828982908291829282938294829582968297829882998300830183028303830483058306830783088309831083118312831383148315831683178318831983208321832283238324832583268327832883298330833183328333833483358336833783388339834083418342834383448345834683478348834983508351835283538354835583568357835883598360836183628363836483658366836783688369837083718372837383748375837683778378837983808381838283838384838583868387838883898390839183928393839483958396839783988399840084018402840384048405840684078408840984108411841284138414841584168417841884198420842184228423842484258426842784288429843084318432843384348435843684378438843984408441844284438444844584468447844884498450845184528453845484558456845784588459846084618462846384648465846684678468846984708471847284738474847584768477847884798480848184828483848484858486848784888489849084918492849384948495849684978498849985008501850285038504850585068507850885098510851185128513851485158516851785188519852085218522852385248525852685278528852985308531853285338534853585368537853885398540854185428543854485458546854785488549855085518552855385548555855685578558855985608561856285638564856585668567856885698570857185728573857485758576857785788579858085818582858385848585858685878588858985908591859285938594859585968597859885998600860186028603860486058606860786088609861086118612861386148615861686178618861986208621862286238624862586268627862886298630863186328633863486358636863786388639864086418642864386448645864686478648864986508651865286538654865586568657865886598660866186628663866486658666866786688669867086718672867386748675867686778678867986808681868286838684868586868687868886898690869186928693869486958696869786988699870087018702870387048705870687078708870987108711871287138714871587168717871887198720872187228723872487258726872787288729873087318732873387348735873687378738873987408741874287438744874587468747874887498750875187528753875487558756875787588759876087618762876387648765876687678768876987708771877287738774877587768777877887798780878187828783878487858786878787888789879087918792879387948795879687978798879988008801880288038804880588068807880888098810881188128813881488158816881788188819882088218822882388248825882688278828882988308831883288338834883588368837883888398840884188428843884488458846884788488849885088518852885388548855885688578858885988608861886288638864886588668867886888698870887188728873887488758876887788788879888088818882888388848885888688878888888988908891889288938894889588968897889888998900890189028903890489058906890789088909891089118912891389148915891689178918891989208921892289238924892589268927892889298930893189328933893489358936893789388939894089418942894389448945894689478948894989508951895289538954895589568957895889598960896189628963896489658966896789688969897089718972897389748975897689778978897989808981898289838984898589868987898889898990899189928993899489958996899789988999900090019002900390049005900690079008900990109011901290139014901590169017901890199020902190229023902490259026902790289029903090319032903390349035903690379038903990409041904290439044904590469047904890499050905190529053905490559056905790589059906090619062906390649065906690679068906990709071907290739074907590769077907890799080908190829083908490859086908790889089909090919092909390949095909690979098909991009101910291039104910591069107910891099110911191129113911491159116911791189119912091219122912391249125912691279128912991309131913291339134913591369137913891399140914191429143914491459146914791489149915091519152915391549155915691579158915991609161916291639164916591669167916891699170917191729173917491759176917791789179918091819182918391849185918691879188918991909191919291939194919591969197919891999200920192029203920492059206920792089209921092119212921392149215921692179218921992209221922292239224922592269227922892299230923192329233923492359236923792389239924092419242924392449245924692479248924992509251925292539254925592569257925892599260926192629263926492659266926792689269927092719272927392749275927692779278927992809281928292839284928592869287928892899290929192929293929492959296929792989299930093019302930393049305930693079308930993109311931293139314931593169317931893199320932193229323932493259326932793289329933093319332933393349335933693379338933993409341934293439344934593469347934893499350935193529353935493559356935793589359936093619362936393649365936693679368936993709371937293739374937593769377937893799380938193829383938493859386938793889389939093919392939393949395939693979398939994009401940294039404940594069407940894099410941194129413941494159416941794189419942094219422942394249425942694279428942994309431943294339434943594369437943894399440944194429443944494459446944794489449945094519452945394549455945694579458945994609461946294639464946594669467946894699470947194729473947494759476947794789479948094819482948394849485948694879488948994909491949294939494949594969497949894999500950195029503950495059506950795089509951095119512951395149515951695179518951995209521952295239524952595269527952895299530953195329533953495359536953795389539954095419542954395449545954695479548954995509551955295539554955595569557955895599560956195629563956495659566956795689569957095719572957395749575957695779578957995809581958295839584958595869587958895899590959195929593
  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2007 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * James P. Ketrenos <ipw2100-admin@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/version.h>
  32. #include <linux/init.h>
  33. #include <linux/pci.h>
  34. #include <linux/dma-mapping.h>
  35. #include <linux/delay.h>
  36. #include <linux/skbuff.h>
  37. #include <linux/netdevice.h>
  38. #include <linux/wireless.h>
  39. #include <linux/firmware.h>
  40. #include <linux/etherdevice.h>
  41. #include <linux/if_arp.h>
  42. #include <net/ieee80211_radiotap.h>
  43. #include <net/mac80211.h>
  44. #include <asm/div64.h>
  45. #include "iwl-4965.h"
  46. #include "iwl-helpers.h"
  47. #ifdef CONFIG_IWL4965_DEBUG
  48. u32 iwl4965_debug_level;
  49. #endif
  50. static int iwl4965_tx_queue_update_write_ptr(struct iwl4965_priv *priv,
  51. struct iwl4965_tx_queue *txq);
  52. /******************************************************************************
  53. *
  54. * module boiler plate
  55. *
  56. ******************************************************************************/
  57. /* module parameters */
  58. static int iwl4965_param_disable_hw_scan; /* def: 0 = use 4965's h/w scan */
  59. static int iwl4965_param_debug; /* def: 0 = minimal debug log messages */
  60. static int iwl4965_param_disable; /* def: enable radio */
  61. static int iwl4965_param_antenna; /* def: 0 = both antennas (use diversity) */
  62. int iwl4965_param_hwcrypto; /* def: using software encryption */
  63. static int iwl4965_param_qos_enable = 1; /* def: 1 = use quality of service */
  64. int iwl4965_param_queues_num = IWL_MAX_NUM_QUEUES; /* def: 16 Tx queues */
  65. /*
  66. * module name, copyright, version, etc.
  67. * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk
  68. */
  69. #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link 4965AGN driver for Linux"
  70. #ifdef CONFIG_IWL4965_DEBUG
  71. #define VD "d"
  72. #else
  73. #define VD
  74. #endif
  75. #ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT
  76. #define VS "s"
  77. #else
  78. #define VS
  79. #endif
  80. #define IWLWIFI_VERSION "1.1.19k" VD VS
  81. #define DRV_COPYRIGHT "Copyright(c) 2003-2007 Intel Corporation"
  82. #define DRV_VERSION IWLWIFI_VERSION
  83. /* Change firmware file name, using "-" and incrementing number,
  84. * *only* when uCode interface or architecture changes so that it
  85. * is not compatible with earlier drivers.
  86. * This number will also appear in << 8 position of 1st dword of uCode file */
  87. #define IWL4965_UCODE_API "-1"
  88. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  89. MODULE_VERSION(DRV_VERSION);
  90. MODULE_AUTHOR(DRV_COPYRIGHT);
  91. MODULE_LICENSE("GPL");
  92. __le16 *ieee80211_get_qos_ctrl(struct ieee80211_hdr *hdr)
  93. {
  94. u16 fc = le16_to_cpu(hdr->frame_control);
  95. int hdr_len = ieee80211_get_hdrlen(fc);
  96. if ((fc & 0x00cc) == (IEEE80211_STYPE_QOS_DATA | IEEE80211_FTYPE_DATA))
  97. return (__le16 *) ((u8 *) hdr + hdr_len - QOS_CONTROL_LEN);
  98. return NULL;
  99. }
  100. static const struct ieee80211_hw_mode *iwl4965_get_hw_mode(
  101. struct iwl4965_priv *priv, int mode)
  102. {
  103. int i;
  104. for (i = 0; i < 3; i++)
  105. if (priv->modes[i].mode == mode)
  106. return &priv->modes[i];
  107. return NULL;
  108. }
  109. static int iwl4965_is_empty_essid(const char *essid, int essid_len)
  110. {
  111. /* Single white space is for Linksys APs */
  112. if (essid_len == 1 && essid[0] == ' ')
  113. return 1;
  114. /* Otherwise, if the entire essid is 0, we assume it is hidden */
  115. while (essid_len) {
  116. essid_len--;
  117. if (essid[essid_len] != '\0')
  118. return 0;
  119. }
  120. return 1;
  121. }
  122. static const char *iwl4965_escape_essid(const char *essid, u8 essid_len)
  123. {
  124. static char escaped[IW_ESSID_MAX_SIZE * 2 + 1];
  125. const char *s = essid;
  126. char *d = escaped;
  127. if (iwl4965_is_empty_essid(essid, essid_len)) {
  128. memcpy(escaped, "<hidden>", sizeof("<hidden>"));
  129. return escaped;
  130. }
  131. essid_len = min(essid_len, (u8) IW_ESSID_MAX_SIZE);
  132. while (essid_len--) {
  133. if (*s == '\0') {
  134. *d++ = '\\';
  135. *d++ = '0';
  136. s++;
  137. } else
  138. *d++ = *s++;
  139. }
  140. *d = '\0';
  141. return escaped;
  142. }
  143. static void iwl4965_print_hex_dump(int level, void *p, u32 len)
  144. {
  145. #ifdef CONFIG_IWL4965_DEBUG
  146. if (!(iwl4965_debug_level & level))
  147. return;
  148. print_hex_dump(KERN_DEBUG, "iwl data: ", DUMP_PREFIX_OFFSET, 16, 1,
  149. p, len, 1);
  150. #endif
  151. }
  152. /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
  153. * DMA services
  154. *
  155. * Theory of operation
  156. *
  157. * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
  158. * of buffer descriptors, each of which points to one or more data buffers for
  159. * the device to read from or fill. Driver and device exchange status of each
  160. * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
  161. * entries in each circular buffer, to protect against confusing empty and full
  162. * queue states.
  163. *
  164. * The device reads or writes the data in the queues via the device's several
  165. * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
  166. *
  167. * For Tx queue, there are low mark and high mark limits. If, after queuing
  168. * the packet for Tx, free space become < low mark, Tx queue stopped. When
  169. * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
  170. * Tx queue resumed.
  171. *
  172. * The 4965 operates with up to 17 queues: One receive queue, one transmit
  173. * queue (#4) for sending commands to the device firmware, and 15 other
  174. * Tx queues that may be mapped to prioritized Tx DMA/FIFO channels.
  175. *
  176. * See more detailed info in iwl-4965-hw.h.
  177. ***************************************************/
  178. static int iwl4965_queue_space(const struct iwl4965_queue *q)
  179. {
  180. int s = q->read_ptr - q->write_ptr;
  181. if (q->read_ptr > q->write_ptr)
  182. s -= q->n_bd;
  183. if (s <= 0)
  184. s += q->n_window;
  185. /* keep some reserve to not confuse empty and full situations */
  186. s -= 2;
  187. if (s < 0)
  188. s = 0;
  189. return s;
  190. }
  191. /**
  192. * iwl4965_queue_inc_wrap - increment queue index, wrap back to beginning
  193. * @index -- current index
  194. * @n_bd -- total number of entries in queue (must be power of 2)
  195. */
  196. static inline int iwl4965_queue_inc_wrap(int index, int n_bd)
  197. {
  198. return ++index & (n_bd - 1);
  199. }
  200. /**
  201. * iwl4965_queue_dec_wrap - decrement queue index, wrap back to end
  202. * @index -- current index
  203. * @n_bd -- total number of entries in queue (must be power of 2)
  204. */
  205. static inline int iwl4965_queue_dec_wrap(int index, int n_bd)
  206. {
  207. return --index & (n_bd - 1);
  208. }
  209. static inline int x2_queue_used(const struct iwl4965_queue *q, int i)
  210. {
  211. return q->write_ptr > q->read_ptr ?
  212. (i >= q->read_ptr && i < q->write_ptr) :
  213. !(i < q->read_ptr && i >= q->write_ptr);
  214. }
  215. static inline u8 get_cmd_index(struct iwl4965_queue *q, u32 index, int is_huge)
  216. {
  217. /* This is for scan command, the big buffer at end of command array */
  218. if (is_huge)
  219. return q->n_window; /* must be power of 2 */
  220. /* Otherwise, use normal size buffers */
  221. return index & (q->n_window - 1);
  222. }
  223. /**
  224. * iwl4965_queue_init - Initialize queue's high/low-water and read/write indexes
  225. */
  226. static int iwl4965_queue_init(struct iwl4965_priv *priv, struct iwl4965_queue *q,
  227. int count, int slots_num, u32 id)
  228. {
  229. q->n_bd = count;
  230. q->n_window = slots_num;
  231. q->id = id;
  232. /* count must be power-of-two size, otherwise iwl4965_queue_inc_wrap
  233. * and iwl4965_queue_dec_wrap are broken. */
  234. BUG_ON(!is_power_of_2(count));
  235. /* slots_num must be power-of-two size, otherwise
  236. * get_cmd_index is broken. */
  237. BUG_ON(!is_power_of_2(slots_num));
  238. q->low_mark = q->n_window / 4;
  239. if (q->low_mark < 4)
  240. q->low_mark = 4;
  241. q->high_mark = q->n_window / 8;
  242. if (q->high_mark < 2)
  243. q->high_mark = 2;
  244. q->write_ptr = q->read_ptr = 0;
  245. return 0;
  246. }
  247. /**
  248. * iwl4965_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
  249. */
  250. static int iwl4965_tx_queue_alloc(struct iwl4965_priv *priv,
  251. struct iwl4965_tx_queue *txq, u32 id)
  252. {
  253. struct pci_dev *dev = priv->pci_dev;
  254. /* Driver private data, only for Tx (not command) queues,
  255. * not shared with device. */
  256. if (id != IWL_CMD_QUEUE_NUM) {
  257. txq->txb = kmalloc(sizeof(txq->txb[0]) *
  258. TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
  259. if (!txq->txb) {
  260. IWL_ERROR("kmalloc for auxiliary BD "
  261. "structures failed\n");
  262. goto error;
  263. }
  264. } else
  265. txq->txb = NULL;
  266. /* Circular buffer of transmit frame descriptors (TFDs),
  267. * shared with device */
  268. txq->bd = pci_alloc_consistent(dev,
  269. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
  270. &txq->q.dma_addr);
  271. if (!txq->bd) {
  272. IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
  273. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
  274. goto error;
  275. }
  276. txq->q.id = id;
  277. return 0;
  278. error:
  279. if (txq->txb) {
  280. kfree(txq->txb);
  281. txq->txb = NULL;
  282. }
  283. return -ENOMEM;
  284. }
  285. /**
  286. * iwl4965_tx_queue_init - Allocate and initialize one tx/cmd queue
  287. */
  288. int iwl4965_tx_queue_init(struct iwl4965_priv *priv,
  289. struct iwl4965_tx_queue *txq, int slots_num, u32 txq_id)
  290. {
  291. struct pci_dev *dev = priv->pci_dev;
  292. int len;
  293. int rc = 0;
  294. /*
  295. * Alloc buffer array for commands (Tx or other types of commands).
  296. * For the command queue (#4), allocate command space + one big
  297. * command for scan, since scan command is very huge; the system will
  298. * not have two scans at the same time, so only one is needed.
  299. * For data Tx queues (all other queues), no super-size command
  300. * space is needed.
  301. */
  302. len = sizeof(struct iwl4965_cmd) * slots_num;
  303. if (txq_id == IWL_CMD_QUEUE_NUM)
  304. len += IWL_MAX_SCAN_SIZE;
  305. txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
  306. if (!txq->cmd)
  307. return -ENOMEM;
  308. /* Alloc driver data array and TFD circular buffer */
  309. rc = iwl4965_tx_queue_alloc(priv, txq, txq_id);
  310. if (rc) {
  311. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  312. return -ENOMEM;
  313. }
  314. txq->need_update = 0;
  315. /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
  316. * iwl4965_queue_inc_wrap and iwl4965_queue_dec_wrap are broken. */
  317. BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
  318. /* Initialize queue's high/low-water marks, and head/tail indexes */
  319. iwl4965_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
  320. /* Tell device where to find queue */
  321. iwl4965_hw_tx_queue_init(priv, txq);
  322. return 0;
  323. }
  324. /**
  325. * iwl4965_tx_queue_free - Deallocate DMA queue.
  326. * @txq: Transmit queue to deallocate.
  327. *
  328. * Empty queue by removing and destroying all BD's.
  329. * Free all buffers.
  330. * 0-fill, but do not free "txq" descriptor structure.
  331. */
  332. void iwl4965_tx_queue_free(struct iwl4965_priv *priv, struct iwl4965_tx_queue *txq)
  333. {
  334. struct iwl4965_queue *q = &txq->q;
  335. struct pci_dev *dev = priv->pci_dev;
  336. int len;
  337. if (q->n_bd == 0)
  338. return;
  339. /* first, empty all BD's */
  340. for (; q->write_ptr != q->read_ptr;
  341. q->read_ptr = iwl4965_queue_inc_wrap(q->read_ptr, q->n_bd))
  342. iwl4965_hw_txq_free_tfd(priv, txq);
  343. len = sizeof(struct iwl4965_cmd) * q->n_window;
  344. if (q->id == IWL_CMD_QUEUE_NUM)
  345. len += IWL_MAX_SCAN_SIZE;
  346. /* De-alloc array of command/tx buffers */
  347. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  348. /* De-alloc circular buffer of TFDs */
  349. if (txq->q.n_bd)
  350. pci_free_consistent(dev, sizeof(struct iwl4965_tfd_frame) *
  351. txq->q.n_bd, txq->bd, txq->q.dma_addr);
  352. /* De-alloc array of per-TFD driver data */
  353. if (txq->txb) {
  354. kfree(txq->txb);
  355. txq->txb = NULL;
  356. }
  357. /* 0-fill queue descriptor structure */
  358. memset(txq, 0, sizeof(*txq));
  359. }
  360. const u8 iwl4965_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
  361. /*************** STATION TABLE MANAGEMENT ****
  362. * mac80211 should be examined to determine if sta_info is duplicating
  363. * the functionality provided here
  364. */
  365. /**************************************************************/
  366. #if 0 /* temporary disable till we add real remove station */
  367. /**
  368. * iwl4965_remove_station - Remove driver's knowledge of station.
  369. *
  370. * NOTE: This does not remove station from device's station table.
  371. */
  372. static u8 iwl4965_remove_station(struct iwl4965_priv *priv, const u8 *addr, int is_ap)
  373. {
  374. int index = IWL_INVALID_STATION;
  375. int i;
  376. unsigned long flags;
  377. spin_lock_irqsave(&priv->sta_lock, flags);
  378. if (is_ap)
  379. index = IWL_AP_ID;
  380. else if (is_broadcast_ether_addr(addr))
  381. index = priv->hw_setting.bcast_sta_id;
  382. else
  383. for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
  384. if (priv->stations[i].used &&
  385. !compare_ether_addr(priv->stations[i].sta.sta.addr,
  386. addr)) {
  387. index = i;
  388. break;
  389. }
  390. if (unlikely(index == IWL_INVALID_STATION))
  391. goto out;
  392. if (priv->stations[index].used) {
  393. priv->stations[index].used = 0;
  394. priv->num_stations--;
  395. }
  396. BUG_ON(priv->num_stations < 0);
  397. out:
  398. spin_unlock_irqrestore(&priv->sta_lock, flags);
  399. return 0;
  400. }
  401. #endif
  402. /**
  403. * iwl4965_clear_stations_table - Clear the driver's station table
  404. *
  405. * NOTE: This does not clear or otherwise alter the device's station table.
  406. */
  407. static void iwl4965_clear_stations_table(struct iwl4965_priv *priv)
  408. {
  409. unsigned long flags;
  410. spin_lock_irqsave(&priv->sta_lock, flags);
  411. priv->num_stations = 0;
  412. memset(priv->stations, 0, sizeof(priv->stations));
  413. spin_unlock_irqrestore(&priv->sta_lock, flags);
  414. }
  415. /**
  416. * iwl4965_add_station_flags - Add station to tables in driver and device
  417. */
  418. u8 iwl4965_add_station_flags(struct iwl4965_priv *priv, const u8 *addr, int is_ap, u8 flags)
  419. {
  420. int i;
  421. int index = IWL_INVALID_STATION;
  422. struct iwl4965_station_entry *station;
  423. unsigned long flags_spin;
  424. DECLARE_MAC_BUF(mac);
  425. spin_lock_irqsave(&priv->sta_lock, flags_spin);
  426. if (is_ap)
  427. index = IWL_AP_ID;
  428. else if (is_broadcast_ether_addr(addr))
  429. index = priv->hw_setting.bcast_sta_id;
  430. else
  431. for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) {
  432. if (!compare_ether_addr(priv->stations[i].sta.sta.addr,
  433. addr)) {
  434. index = i;
  435. break;
  436. }
  437. if (!priv->stations[i].used &&
  438. index == IWL_INVALID_STATION)
  439. index = i;
  440. }
  441. /* These two conditions have the same outcome, but keep them separate
  442. since they have different meanings */
  443. if (unlikely(index == IWL_INVALID_STATION)) {
  444. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  445. return index;
  446. }
  447. if (priv->stations[index].used &&
  448. !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) {
  449. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  450. return index;
  451. }
  452. IWL_DEBUG_ASSOC("Add STA ID %d: %s\n", index, print_mac(mac, addr));
  453. station = &priv->stations[index];
  454. station->used = 1;
  455. priv->num_stations++;
  456. /* Set up the REPLY_ADD_STA command to send to device */
  457. memset(&station->sta, 0, sizeof(struct iwl4965_addsta_cmd));
  458. memcpy(station->sta.sta.addr, addr, ETH_ALEN);
  459. station->sta.mode = 0;
  460. station->sta.sta.sta_id = index;
  461. station->sta.station_flags = 0;
  462. #ifdef CONFIG_IWL4965_HT
  463. /* BCAST station and IBSS stations do not work in HT mode */
  464. if (index != priv->hw_setting.bcast_sta_id &&
  465. priv->iw_mode != IEEE80211_IF_TYPE_IBSS)
  466. iwl4965_set_ht_add_station(priv, index);
  467. #endif /*CONFIG_IWL4965_HT*/
  468. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  469. /* Add station to device's station table */
  470. iwl4965_send_add_station(priv, &station->sta, flags);
  471. return index;
  472. }
  473. /*************** DRIVER STATUS FUNCTIONS *****/
  474. static inline int iwl4965_is_ready(struct iwl4965_priv *priv)
  475. {
  476. /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
  477. * set but EXIT_PENDING is not */
  478. return test_bit(STATUS_READY, &priv->status) &&
  479. test_bit(STATUS_GEO_CONFIGURED, &priv->status) &&
  480. !test_bit(STATUS_EXIT_PENDING, &priv->status);
  481. }
  482. static inline int iwl4965_is_alive(struct iwl4965_priv *priv)
  483. {
  484. return test_bit(STATUS_ALIVE, &priv->status);
  485. }
  486. static inline int iwl4965_is_init(struct iwl4965_priv *priv)
  487. {
  488. return test_bit(STATUS_INIT, &priv->status);
  489. }
  490. static inline int iwl4965_is_rfkill(struct iwl4965_priv *priv)
  491. {
  492. return test_bit(STATUS_RF_KILL_HW, &priv->status) ||
  493. test_bit(STATUS_RF_KILL_SW, &priv->status);
  494. }
  495. static inline int iwl4965_is_ready_rf(struct iwl4965_priv *priv)
  496. {
  497. if (iwl4965_is_rfkill(priv))
  498. return 0;
  499. return iwl4965_is_ready(priv);
  500. }
  501. /*************** HOST COMMAND QUEUE FUNCTIONS *****/
  502. #define IWL_CMD(x) case x : return #x
  503. static const char *get_cmd_string(u8 cmd)
  504. {
  505. switch (cmd) {
  506. IWL_CMD(REPLY_ALIVE);
  507. IWL_CMD(REPLY_ERROR);
  508. IWL_CMD(REPLY_RXON);
  509. IWL_CMD(REPLY_RXON_ASSOC);
  510. IWL_CMD(REPLY_QOS_PARAM);
  511. IWL_CMD(REPLY_RXON_TIMING);
  512. IWL_CMD(REPLY_ADD_STA);
  513. IWL_CMD(REPLY_REMOVE_STA);
  514. IWL_CMD(REPLY_REMOVE_ALL_STA);
  515. IWL_CMD(REPLY_TX);
  516. IWL_CMD(REPLY_RATE_SCALE);
  517. IWL_CMD(REPLY_LEDS_CMD);
  518. IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
  519. IWL_CMD(RADAR_NOTIFICATION);
  520. IWL_CMD(REPLY_QUIET_CMD);
  521. IWL_CMD(REPLY_CHANNEL_SWITCH);
  522. IWL_CMD(CHANNEL_SWITCH_NOTIFICATION);
  523. IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD);
  524. IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION);
  525. IWL_CMD(POWER_TABLE_CMD);
  526. IWL_CMD(PM_SLEEP_NOTIFICATION);
  527. IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC);
  528. IWL_CMD(REPLY_SCAN_CMD);
  529. IWL_CMD(REPLY_SCAN_ABORT_CMD);
  530. IWL_CMD(SCAN_START_NOTIFICATION);
  531. IWL_CMD(SCAN_RESULTS_NOTIFICATION);
  532. IWL_CMD(SCAN_COMPLETE_NOTIFICATION);
  533. IWL_CMD(BEACON_NOTIFICATION);
  534. IWL_CMD(REPLY_TX_BEACON);
  535. IWL_CMD(WHO_IS_AWAKE_NOTIFICATION);
  536. IWL_CMD(QUIET_NOTIFICATION);
  537. IWL_CMD(REPLY_TX_PWR_TABLE_CMD);
  538. IWL_CMD(MEASURE_ABORT_NOTIFICATION);
  539. IWL_CMD(REPLY_BT_CONFIG);
  540. IWL_CMD(REPLY_STATISTICS_CMD);
  541. IWL_CMD(STATISTICS_NOTIFICATION);
  542. IWL_CMD(REPLY_CARD_STATE_CMD);
  543. IWL_CMD(CARD_STATE_NOTIFICATION);
  544. IWL_CMD(MISSED_BEACONS_NOTIFICATION);
  545. IWL_CMD(REPLY_CT_KILL_CONFIG_CMD);
  546. IWL_CMD(SENSITIVITY_CMD);
  547. IWL_CMD(REPLY_PHY_CALIBRATION_CMD);
  548. IWL_CMD(REPLY_RX_PHY_CMD);
  549. IWL_CMD(REPLY_RX_MPDU_CMD);
  550. IWL_CMD(REPLY_4965_RX);
  551. IWL_CMD(REPLY_COMPRESSED_BA);
  552. default:
  553. return "UNKNOWN";
  554. }
  555. }
  556. #define HOST_COMPLETE_TIMEOUT (HZ / 2)
  557. /**
  558. * iwl4965_enqueue_hcmd - enqueue a uCode command
  559. * @priv: device private data point
  560. * @cmd: a point to the ucode command structure
  561. *
  562. * The function returns < 0 values to indicate the operation is
  563. * failed. On success, it turns the index (> 0) of command in the
  564. * command queue.
  565. */
  566. static int iwl4965_enqueue_hcmd(struct iwl4965_priv *priv, struct iwl4965_host_cmd *cmd)
  567. {
  568. struct iwl4965_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
  569. struct iwl4965_queue *q = &txq->q;
  570. struct iwl4965_tfd_frame *tfd;
  571. u32 *control_flags;
  572. struct iwl4965_cmd *out_cmd;
  573. u32 idx;
  574. u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
  575. dma_addr_t phys_addr;
  576. int ret;
  577. unsigned long flags;
  578. /* If any of the command structures end up being larger than
  579. * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
  580. * we will need to increase the size of the TFD entries */
  581. BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
  582. !(cmd->meta.flags & CMD_SIZE_HUGE));
  583. if (iwl4965_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
  584. IWL_ERROR("No space for Tx\n");
  585. return -ENOSPC;
  586. }
  587. spin_lock_irqsave(&priv->hcmd_lock, flags);
  588. tfd = &txq->bd[q->write_ptr];
  589. memset(tfd, 0, sizeof(*tfd));
  590. control_flags = (u32 *) tfd;
  591. idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
  592. out_cmd = &txq->cmd[idx];
  593. out_cmd->hdr.cmd = cmd->id;
  594. memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
  595. memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
  596. /* At this point, the out_cmd now has all of the incoming cmd
  597. * information */
  598. out_cmd->hdr.flags = 0;
  599. out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
  600. INDEX_TO_SEQ(q->write_ptr));
  601. if (out_cmd->meta.flags & CMD_SIZE_HUGE)
  602. out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME);
  603. phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
  604. offsetof(struct iwl4965_cmd, hdr);
  605. iwl4965_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
  606. IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
  607. "%d bytes at %d[%d]:%d\n",
  608. get_cmd_string(out_cmd->hdr.cmd),
  609. out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
  610. fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
  611. txq->need_update = 1;
  612. /* Set up entry in queue's byte count circular buffer */
  613. ret = iwl4965_tx_queue_update_wr_ptr(priv, txq, 0);
  614. /* Increment and update queue's write index */
  615. q->write_ptr = iwl4965_queue_inc_wrap(q->write_ptr, q->n_bd);
  616. iwl4965_tx_queue_update_write_ptr(priv, txq);
  617. spin_unlock_irqrestore(&priv->hcmd_lock, flags);
  618. return ret ? ret : idx;
  619. }
  620. static int iwl4965_send_cmd_async(struct iwl4965_priv *priv, struct iwl4965_host_cmd *cmd)
  621. {
  622. int ret;
  623. BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
  624. /* An asynchronous command can not expect an SKB to be set. */
  625. BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
  626. /* An asynchronous command MUST have a callback. */
  627. BUG_ON(!cmd->meta.u.callback);
  628. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  629. return -EBUSY;
  630. ret = iwl4965_enqueue_hcmd(priv, cmd);
  631. if (ret < 0) {
  632. IWL_ERROR("Error sending %s: iwl4965_enqueue_hcmd failed: %d\n",
  633. get_cmd_string(cmd->id), ret);
  634. return ret;
  635. }
  636. return 0;
  637. }
  638. static int iwl4965_send_cmd_sync(struct iwl4965_priv *priv, struct iwl4965_host_cmd *cmd)
  639. {
  640. int cmd_idx;
  641. int ret;
  642. static atomic_t entry = ATOMIC_INIT(0); /* reentrance protection */
  643. BUG_ON(cmd->meta.flags & CMD_ASYNC);
  644. /* A synchronous command can not have a callback set. */
  645. BUG_ON(cmd->meta.u.callback != NULL);
  646. if (atomic_xchg(&entry, 1)) {
  647. IWL_ERROR("Error sending %s: Already sending a host command\n",
  648. get_cmd_string(cmd->id));
  649. return -EBUSY;
  650. }
  651. set_bit(STATUS_HCMD_ACTIVE, &priv->status);
  652. if (cmd->meta.flags & CMD_WANT_SKB)
  653. cmd->meta.source = &cmd->meta;
  654. cmd_idx = iwl4965_enqueue_hcmd(priv, cmd);
  655. if (cmd_idx < 0) {
  656. ret = cmd_idx;
  657. IWL_ERROR("Error sending %s: iwl4965_enqueue_hcmd failed: %d\n",
  658. get_cmd_string(cmd->id), ret);
  659. goto out;
  660. }
  661. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  662. !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
  663. HOST_COMPLETE_TIMEOUT);
  664. if (!ret) {
  665. if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
  666. IWL_ERROR("Error sending %s: time out after %dms.\n",
  667. get_cmd_string(cmd->id),
  668. jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
  669. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  670. ret = -ETIMEDOUT;
  671. goto cancel;
  672. }
  673. }
  674. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  675. IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
  676. get_cmd_string(cmd->id));
  677. ret = -ECANCELED;
  678. goto fail;
  679. }
  680. if (test_bit(STATUS_FW_ERROR, &priv->status)) {
  681. IWL_DEBUG_INFO("Command %s failed: FW Error\n",
  682. get_cmd_string(cmd->id));
  683. ret = -EIO;
  684. goto fail;
  685. }
  686. if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
  687. IWL_ERROR("Error: Response NULL in '%s'\n",
  688. get_cmd_string(cmd->id));
  689. ret = -EIO;
  690. goto out;
  691. }
  692. ret = 0;
  693. goto out;
  694. cancel:
  695. if (cmd->meta.flags & CMD_WANT_SKB) {
  696. struct iwl4965_cmd *qcmd;
  697. /* Cancel the CMD_WANT_SKB flag for the cmd in the
  698. * TX cmd queue. Otherwise in case the cmd comes
  699. * in later, it will possibly set an invalid
  700. * address (cmd->meta.source). */
  701. qcmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
  702. qcmd->meta.flags &= ~CMD_WANT_SKB;
  703. }
  704. fail:
  705. if (cmd->meta.u.skb) {
  706. dev_kfree_skb_any(cmd->meta.u.skb);
  707. cmd->meta.u.skb = NULL;
  708. }
  709. out:
  710. atomic_set(&entry, 0);
  711. return ret;
  712. }
  713. int iwl4965_send_cmd(struct iwl4965_priv *priv, struct iwl4965_host_cmd *cmd)
  714. {
  715. if (cmd->meta.flags & CMD_ASYNC)
  716. return iwl4965_send_cmd_async(priv, cmd);
  717. return iwl4965_send_cmd_sync(priv, cmd);
  718. }
  719. int iwl4965_send_cmd_pdu(struct iwl4965_priv *priv, u8 id, u16 len, const void *data)
  720. {
  721. struct iwl4965_host_cmd cmd = {
  722. .id = id,
  723. .len = len,
  724. .data = data,
  725. };
  726. return iwl4965_send_cmd_sync(priv, &cmd);
  727. }
  728. static int __must_check iwl4965_send_cmd_u32(struct iwl4965_priv *priv, u8 id, u32 val)
  729. {
  730. struct iwl4965_host_cmd cmd = {
  731. .id = id,
  732. .len = sizeof(val),
  733. .data = &val,
  734. };
  735. return iwl4965_send_cmd_sync(priv, &cmd);
  736. }
  737. int iwl4965_send_statistics_request(struct iwl4965_priv *priv)
  738. {
  739. return iwl4965_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
  740. }
  741. /**
  742. * iwl4965_rxon_add_station - add station into station table.
  743. *
  744. * there is only one AP station with id= IWL_AP_ID
  745. * NOTE: mutex must be held before calling this fnction
  746. */
  747. static int iwl4965_rxon_add_station(struct iwl4965_priv *priv,
  748. const u8 *addr, int is_ap)
  749. {
  750. u8 sta_id;
  751. /* Add station to device's station table */
  752. sta_id = iwl4965_add_station_flags(priv, addr, is_ap, 0);
  753. /* Set up default rate scaling table in device's station table */
  754. iwl4965_add_station(priv, addr, is_ap);
  755. return sta_id;
  756. }
  757. /**
  758. * iwl4965_set_rxon_channel - Set the phymode and channel values in staging RXON
  759. * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
  760. * @channel: Any channel valid for the requested phymode
  761. * In addition to setting the staging RXON, priv->phymode is also set.
  762. *
  763. * NOTE: Does not commit to the hardware; it sets appropriate bit fields
  764. * in the staging RXON flag structure based on the phymode
  765. */
  766. static int iwl4965_set_rxon_channel(struct iwl4965_priv *priv, u8 phymode,
  767. u16 channel)
  768. {
  769. if (!iwl4965_get_channel_info(priv, phymode, channel)) {
  770. IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
  771. channel, phymode);
  772. return -EINVAL;
  773. }
  774. if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
  775. (priv->phymode == phymode))
  776. return 0;
  777. priv->staging_rxon.channel = cpu_to_le16(channel);
  778. if (phymode == MODE_IEEE80211A)
  779. priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
  780. else
  781. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  782. priv->phymode = phymode;
  783. IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, phymode);
  784. return 0;
  785. }
  786. /**
  787. * iwl4965_check_rxon_cmd - validate RXON structure is valid
  788. *
  789. * NOTE: This is really only useful during development and can eventually
  790. * be #ifdef'd out once the driver is stable and folks aren't actively
  791. * making changes
  792. */
  793. static int iwl4965_check_rxon_cmd(struct iwl4965_rxon_cmd *rxon)
  794. {
  795. int error = 0;
  796. int counter = 1;
  797. if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
  798. error |= le32_to_cpu(rxon->flags &
  799. (RXON_FLG_TGJ_NARROW_BAND_MSK |
  800. RXON_FLG_RADAR_DETECT_MSK));
  801. if (error)
  802. IWL_WARNING("check 24G fields %d | %d\n",
  803. counter++, error);
  804. } else {
  805. error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
  806. 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
  807. if (error)
  808. IWL_WARNING("check 52 fields %d | %d\n",
  809. counter++, error);
  810. error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
  811. if (error)
  812. IWL_WARNING("check 52 CCK %d | %d\n",
  813. counter++, error);
  814. }
  815. error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
  816. if (error)
  817. IWL_WARNING("check mac addr %d | %d\n", counter++, error);
  818. /* make sure basic rates 6Mbps and 1Mbps are supported */
  819. error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
  820. ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
  821. if (error)
  822. IWL_WARNING("check basic rate %d | %d\n", counter++, error);
  823. error |= (le16_to_cpu(rxon->assoc_id) > 2007);
  824. if (error)
  825. IWL_WARNING("check assoc id %d | %d\n", counter++, error);
  826. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
  827. == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
  828. if (error)
  829. IWL_WARNING("check CCK and short slot %d | %d\n",
  830. counter++, error);
  831. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
  832. == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
  833. if (error)
  834. IWL_WARNING("check CCK & auto detect %d | %d\n",
  835. counter++, error);
  836. error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
  837. RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
  838. if (error)
  839. IWL_WARNING("check TGG and auto detect %d | %d\n",
  840. counter++, error);
  841. if (error)
  842. IWL_WARNING("Tuning to channel %d\n",
  843. le16_to_cpu(rxon->channel));
  844. if (error) {
  845. IWL_ERROR("Not a valid iwl4965_rxon_assoc_cmd field values\n");
  846. return -1;
  847. }
  848. return 0;
  849. }
  850. /**
  851. * iwl4965_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
  852. * @priv: staging_rxon is compared to active_rxon
  853. *
  854. * If the RXON structure is changing enough to require a new tune,
  855. * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
  856. * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
  857. */
  858. static int iwl4965_full_rxon_required(struct iwl4965_priv *priv)
  859. {
  860. /* These items are only settable from the full RXON command */
  861. if (!(priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) ||
  862. compare_ether_addr(priv->staging_rxon.bssid_addr,
  863. priv->active_rxon.bssid_addr) ||
  864. compare_ether_addr(priv->staging_rxon.node_addr,
  865. priv->active_rxon.node_addr) ||
  866. compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
  867. priv->active_rxon.wlap_bssid_addr) ||
  868. (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
  869. (priv->staging_rxon.channel != priv->active_rxon.channel) ||
  870. (priv->staging_rxon.air_propagation !=
  871. priv->active_rxon.air_propagation) ||
  872. (priv->staging_rxon.ofdm_ht_single_stream_basic_rates !=
  873. priv->active_rxon.ofdm_ht_single_stream_basic_rates) ||
  874. (priv->staging_rxon.ofdm_ht_dual_stream_basic_rates !=
  875. priv->active_rxon.ofdm_ht_dual_stream_basic_rates) ||
  876. (priv->staging_rxon.rx_chain != priv->active_rxon.rx_chain) ||
  877. (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
  878. return 1;
  879. /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
  880. * be updated with the RXON_ASSOC command -- however only some
  881. * flag transitions are allowed using RXON_ASSOC */
  882. /* Check if we are not switching bands */
  883. if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
  884. (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
  885. return 1;
  886. /* Check if we are switching association toggle */
  887. if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
  888. (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
  889. return 1;
  890. return 0;
  891. }
  892. static int iwl4965_send_rxon_assoc(struct iwl4965_priv *priv)
  893. {
  894. int rc = 0;
  895. struct iwl4965_rx_packet *res = NULL;
  896. struct iwl4965_rxon_assoc_cmd rxon_assoc;
  897. struct iwl4965_host_cmd cmd = {
  898. .id = REPLY_RXON_ASSOC,
  899. .len = sizeof(rxon_assoc),
  900. .meta.flags = CMD_WANT_SKB,
  901. .data = &rxon_assoc,
  902. };
  903. const struct iwl4965_rxon_cmd *rxon1 = &priv->staging_rxon;
  904. const struct iwl4965_rxon_cmd *rxon2 = &priv->active_rxon;
  905. if ((rxon1->flags == rxon2->flags) &&
  906. (rxon1->filter_flags == rxon2->filter_flags) &&
  907. (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
  908. (rxon1->ofdm_ht_single_stream_basic_rates ==
  909. rxon2->ofdm_ht_single_stream_basic_rates) &&
  910. (rxon1->ofdm_ht_dual_stream_basic_rates ==
  911. rxon2->ofdm_ht_dual_stream_basic_rates) &&
  912. (rxon1->rx_chain == rxon2->rx_chain) &&
  913. (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
  914. IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
  915. return 0;
  916. }
  917. rxon_assoc.flags = priv->staging_rxon.flags;
  918. rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
  919. rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
  920. rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
  921. rxon_assoc.reserved = 0;
  922. rxon_assoc.ofdm_ht_single_stream_basic_rates =
  923. priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
  924. rxon_assoc.ofdm_ht_dual_stream_basic_rates =
  925. priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
  926. rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
  927. rc = iwl4965_send_cmd_sync(priv, &cmd);
  928. if (rc)
  929. return rc;
  930. res = (struct iwl4965_rx_packet *)cmd.meta.u.skb->data;
  931. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  932. IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n");
  933. rc = -EIO;
  934. }
  935. priv->alloc_rxb_skb--;
  936. dev_kfree_skb_any(cmd.meta.u.skb);
  937. return rc;
  938. }
  939. /**
  940. * iwl4965_commit_rxon - commit staging_rxon to hardware
  941. *
  942. * The RXON command in staging_rxon is committed to the hardware and
  943. * the active_rxon structure is updated with the new data. This
  944. * function correctly transitions out of the RXON_ASSOC_MSK state if
  945. * a HW tune is required based on the RXON structure changes.
  946. */
  947. static int iwl4965_commit_rxon(struct iwl4965_priv *priv)
  948. {
  949. /* cast away the const for active_rxon in this function */
  950. struct iwl4965_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  951. DECLARE_MAC_BUF(mac);
  952. int rc = 0;
  953. if (!iwl4965_is_alive(priv))
  954. return -1;
  955. /* always get timestamp with Rx frame */
  956. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  957. rc = iwl4965_check_rxon_cmd(&priv->staging_rxon);
  958. if (rc) {
  959. IWL_ERROR("Invalid RXON configuration. Not committing.\n");
  960. return -EINVAL;
  961. }
  962. /* If we don't need to send a full RXON, we can use
  963. * iwl4965_rxon_assoc_cmd which is used to reconfigure filter
  964. * and other flags for the current radio configuration. */
  965. if (!iwl4965_full_rxon_required(priv)) {
  966. rc = iwl4965_send_rxon_assoc(priv);
  967. if (rc) {
  968. IWL_ERROR("Error setting RXON_ASSOC "
  969. "configuration (%d).\n", rc);
  970. return rc;
  971. }
  972. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  973. return 0;
  974. }
  975. /* station table will be cleared */
  976. priv->assoc_station_added = 0;
  977. #ifdef CONFIG_IWL4965_SENSITIVITY
  978. priv->sensitivity_data.state = IWL_SENS_CALIB_NEED_REINIT;
  979. if (!priv->error_recovering)
  980. priv->start_calib = 0;
  981. iwl4965_init_sensitivity(priv, CMD_ASYNC, 1);
  982. #endif /* CONFIG_IWL4965_SENSITIVITY */
  983. /* If we are currently associated and the new config requires
  984. * an RXON_ASSOC and the new config wants the associated mask enabled,
  985. * we must clear the associated from the active configuration
  986. * before we apply the new config */
  987. if (iwl4965_is_associated(priv) &&
  988. (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
  989. IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
  990. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  991. rc = iwl4965_send_cmd_pdu(priv, REPLY_RXON,
  992. sizeof(struct iwl4965_rxon_cmd),
  993. &priv->active_rxon);
  994. /* If the mask clearing failed then we set
  995. * active_rxon back to what it was previously */
  996. if (rc) {
  997. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  998. IWL_ERROR("Error clearing ASSOC_MSK on current "
  999. "configuration (%d).\n", rc);
  1000. return rc;
  1001. }
  1002. }
  1003. IWL_DEBUG_INFO("Sending RXON\n"
  1004. "* with%s RXON_FILTER_ASSOC_MSK\n"
  1005. "* channel = %d\n"
  1006. "* bssid = %s\n",
  1007. ((priv->staging_rxon.filter_flags &
  1008. RXON_FILTER_ASSOC_MSK) ? "" : "out"),
  1009. le16_to_cpu(priv->staging_rxon.channel),
  1010. print_mac(mac, priv->staging_rxon.bssid_addr));
  1011. /* Apply the new configuration */
  1012. rc = iwl4965_send_cmd_pdu(priv, REPLY_RXON,
  1013. sizeof(struct iwl4965_rxon_cmd), &priv->staging_rxon);
  1014. if (rc) {
  1015. IWL_ERROR("Error setting new configuration (%d).\n", rc);
  1016. return rc;
  1017. }
  1018. iwl4965_clear_stations_table(priv);
  1019. #ifdef CONFIG_IWL4965_SENSITIVITY
  1020. if (!priv->error_recovering)
  1021. priv->start_calib = 0;
  1022. priv->sensitivity_data.state = IWL_SENS_CALIB_NEED_REINIT;
  1023. iwl4965_init_sensitivity(priv, CMD_ASYNC, 1);
  1024. #endif /* CONFIG_IWL4965_SENSITIVITY */
  1025. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  1026. /* If we issue a new RXON command which required a tune then we must
  1027. * send a new TXPOWER command or we won't be able to Tx any frames */
  1028. rc = iwl4965_hw_reg_send_txpower(priv);
  1029. if (rc) {
  1030. IWL_ERROR("Error setting Tx power (%d).\n", rc);
  1031. return rc;
  1032. }
  1033. /* Add the broadcast address so we can send broadcast frames */
  1034. if (iwl4965_rxon_add_station(priv, iwl4965_broadcast_addr, 0) ==
  1035. IWL_INVALID_STATION) {
  1036. IWL_ERROR("Error adding BROADCAST address for transmit.\n");
  1037. return -EIO;
  1038. }
  1039. /* If we have set the ASSOC_MSK and we are in BSS mode then
  1040. * add the IWL_AP_ID to the station rate table */
  1041. if (iwl4965_is_associated(priv) &&
  1042. (priv->iw_mode == IEEE80211_IF_TYPE_STA)) {
  1043. if (iwl4965_rxon_add_station(priv, priv->active_rxon.bssid_addr, 1)
  1044. == IWL_INVALID_STATION) {
  1045. IWL_ERROR("Error adding AP address for transmit.\n");
  1046. return -EIO;
  1047. }
  1048. priv->assoc_station_added = 1;
  1049. }
  1050. return 0;
  1051. }
  1052. static int iwl4965_send_bt_config(struct iwl4965_priv *priv)
  1053. {
  1054. struct iwl4965_bt_cmd bt_cmd = {
  1055. .flags = 3,
  1056. .lead_time = 0xAA,
  1057. .max_kill = 1,
  1058. .kill_ack_mask = 0,
  1059. .kill_cts_mask = 0,
  1060. };
  1061. return iwl4965_send_cmd_pdu(priv, REPLY_BT_CONFIG,
  1062. sizeof(struct iwl4965_bt_cmd), &bt_cmd);
  1063. }
  1064. static int iwl4965_send_scan_abort(struct iwl4965_priv *priv)
  1065. {
  1066. int rc = 0;
  1067. struct iwl4965_rx_packet *res;
  1068. struct iwl4965_host_cmd cmd = {
  1069. .id = REPLY_SCAN_ABORT_CMD,
  1070. .meta.flags = CMD_WANT_SKB,
  1071. };
  1072. /* If there isn't a scan actively going on in the hardware
  1073. * then we are in between scan bands and not actually
  1074. * actively scanning, so don't send the abort command */
  1075. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  1076. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  1077. return 0;
  1078. }
  1079. rc = iwl4965_send_cmd_sync(priv, &cmd);
  1080. if (rc) {
  1081. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  1082. return rc;
  1083. }
  1084. res = (struct iwl4965_rx_packet *)cmd.meta.u.skb->data;
  1085. if (res->u.status != CAN_ABORT_STATUS) {
  1086. /* The scan abort will return 1 for success or
  1087. * 2 for "failure". A failure condition can be
  1088. * due to simply not being in an active scan which
  1089. * can occur if we send the scan abort before we
  1090. * the microcode has notified us that a scan is
  1091. * completed. */
  1092. IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
  1093. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  1094. clear_bit(STATUS_SCAN_HW, &priv->status);
  1095. }
  1096. dev_kfree_skb_any(cmd.meta.u.skb);
  1097. return rc;
  1098. }
  1099. static int iwl4965_card_state_sync_callback(struct iwl4965_priv *priv,
  1100. struct iwl4965_cmd *cmd,
  1101. struct sk_buff *skb)
  1102. {
  1103. return 1;
  1104. }
  1105. /*
  1106. * CARD_STATE_CMD
  1107. *
  1108. * Use: Sets the device's internal card state to enable, disable, or halt
  1109. *
  1110. * When in the 'enable' state the card operates as normal.
  1111. * When in the 'disable' state, the card enters into a low power mode.
  1112. * When in the 'halt' state, the card is shut down and must be fully
  1113. * restarted to come back on.
  1114. */
  1115. static int iwl4965_send_card_state(struct iwl4965_priv *priv, u32 flags, u8 meta_flag)
  1116. {
  1117. struct iwl4965_host_cmd cmd = {
  1118. .id = REPLY_CARD_STATE_CMD,
  1119. .len = sizeof(u32),
  1120. .data = &flags,
  1121. .meta.flags = meta_flag,
  1122. };
  1123. if (meta_flag & CMD_ASYNC)
  1124. cmd.meta.u.callback = iwl4965_card_state_sync_callback;
  1125. return iwl4965_send_cmd(priv, &cmd);
  1126. }
  1127. static int iwl4965_add_sta_sync_callback(struct iwl4965_priv *priv,
  1128. struct iwl4965_cmd *cmd, struct sk_buff *skb)
  1129. {
  1130. struct iwl4965_rx_packet *res = NULL;
  1131. if (!skb) {
  1132. IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n");
  1133. return 1;
  1134. }
  1135. res = (struct iwl4965_rx_packet *)skb->data;
  1136. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  1137. IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
  1138. res->hdr.flags);
  1139. return 1;
  1140. }
  1141. switch (res->u.add_sta.status) {
  1142. case ADD_STA_SUCCESS_MSK:
  1143. break;
  1144. default:
  1145. break;
  1146. }
  1147. /* We didn't cache the SKB; let the caller free it */
  1148. return 1;
  1149. }
  1150. int iwl4965_send_add_station(struct iwl4965_priv *priv,
  1151. struct iwl4965_addsta_cmd *sta, u8 flags)
  1152. {
  1153. struct iwl4965_rx_packet *res = NULL;
  1154. int rc = 0;
  1155. struct iwl4965_host_cmd cmd = {
  1156. .id = REPLY_ADD_STA,
  1157. .len = sizeof(struct iwl4965_addsta_cmd),
  1158. .meta.flags = flags,
  1159. .data = sta,
  1160. };
  1161. if (flags & CMD_ASYNC)
  1162. cmd.meta.u.callback = iwl4965_add_sta_sync_callback;
  1163. else
  1164. cmd.meta.flags |= CMD_WANT_SKB;
  1165. rc = iwl4965_send_cmd(priv, &cmd);
  1166. if (rc || (flags & CMD_ASYNC))
  1167. return rc;
  1168. res = (struct iwl4965_rx_packet *)cmd.meta.u.skb->data;
  1169. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  1170. IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
  1171. res->hdr.flags);
  1172. rc = -EIO;
  1173. }
  1174. if (rc == 0) {
  1175. switch (res->u.add_sta.status) {
  1176. case ADD_STA_SUCCESS_MSK:
  1177. IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
  1178. break;
  1179. default:
  1180. rc = -EIO;
  1181. IWL_WARNING("REPLY_ADD_STA failed\n");
  1182. break;
  1183. }
  1184. }
  1185. priv->alloc_rxb_skb--;
  1186. dev_kfree_skb_any(cmd.meta.u.skb);
  1187. return rc;
  1188. }
  1189. static int iwl4965_update_sta_key_info(struct iwl4965_priv *priv,
  1190. struct ieee80211_key_conf *keyconf,
  1191. u8 sta_id)
  1192. {
  1193. unsigned long flags;
  1194. __le16 key_flags = 0;
  1195. switch (keyconf->alg) {
  1196. case ALG_CCMP:
  1197. key_flags |= STA_KEY_FLG_CCMP;
  1198. key_flags |= cpu_to_le16(
  1199. keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
  1200. key_flags &= ~STA_KEY_FLG_INVALID;
  1201. break;
  1202. case ALG_TKIP:
  1203. case ALG_WEP:
  1204. default:
  1205. return -EINVAL;
  1206. }
  1207. spin_lock_irqsave(&priv->sta_lock, flags);
  1208. priv->stations[sta_id].keyinfo.alg = keyconf->alg;
  1209. priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
  1210. memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
  1211. keyconf->keylen);
  1212. memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
  1213. keyconf->keylen);
  1214. priv->stations[sta_id].sta.key.key_flags = key_flags;
  1215. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1216. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1217. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1218. IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
  1219. iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, 0);
  1220. return 0;
  1221. }
  1222. static int iwl4965_clear_sta_key_info(struct iwl4965_priv *priv, u8 sta_id)
  1223. {
  1224. unsigned long flags;
  1225. spin_lock_irqsave(&priv->sta_lock, flags);
  1226. memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl4965_hw_key));
  1227. memset(&priv->stations[sta_id].sta.key, 0, sizeof(struct iwl4965_keyinfo));
  1228. priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
  1229. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1230. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1231. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1232. IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
  1233. iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, 0);
  1234. return 0;
  1235. }
  1236. static void iwl4965_clear_free_frames(struct iwl4965_priv *priv)
  1237. {
  1238. struct list_head *element;
  1239. IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
  1240. priv->frames_count);
  1241. while (!list_empty(&priv->free_frames)) {
  1242. element = priv->free_frames.next;
  1243. list_del(element);
  1244. kfree(list_entry(element, struct iwl4965_frame, list));
  1245. priv->frames_count--;
  1246. }
  1247. if (priv->frames_count) {
  1248. IWL_WARNING("%d frames still in use. Did we lose one?\n",
  1249. priv->frames_count);
  1250. priv->frames_count = 0;
  1251. }
  1252. }
  1253. static struct iwl4965_frame *iwl4965_get_free_frame(struct iwl4965_priv *priv)
  1254. {
  1255. struct iwl4965_frame *frame;
  1256. struct list_head *element;
  1257. if (list_empty(&priv->free_frames)) {
  1258. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  1259. if (!frame) {
  1260. IWL_ERROR("Could not allocate frame!\n");
  1261. return NULL;
  1262. }
  1263. priv->frames_count++;
  1264. return frame;
  1265. }
  1266. element = priv->free_frames.next;
  1267. list_del(element);
  1268. return list_entry(element, struct iwl4965_frame, list);
  1269. }
  1270. static void iwl4965_free_frame(struct iwl4965_priv *priv, struct iwl4965_frame *frame)
  1271. {
  1272. memset(frame, 0, sizeof(*frame));
  1273. list_add(&frame->list, &priv->free_frames);
  1274. }
  1275. unsigned int iwl4965_fill_beacon_frame(struct iwl4965_priv *priv,
  1276. struct ieee80211_hdr *hdr,
  1277. const u8 *dest, int left)
  1278. {
  1279. if (!iwl4965_is_associated(priv) || !priv->ibss_beacon ||
  1280. ((priv->iw_mode != IEEE80211_IF_TYPE_IBSS) &&
  1281. (priv->iw_mode != IEEE80211_IF_TYPE_AP)))
  1282. return 0;
  1283. if (priv->ibss_beacon->len > left)
  1284. return 0;
  1285. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  1286. return priv->ibss_beacon->len;
  1287. }
  1288. int iwl4965_rate_index_from_plcp(int plcp)
  1289. {
  1290. int i = 0;
  1291. /* 4965 HT rate format */
  1292. if (plcp & RATE_MCS_HT_MSK) {
  1293. i = (plcp & 0xff);
  1294. if (i >= IWL_RATE_MIMO_6M_PLCP)
  1295. i = i - IWL_RATE_MIMO_6M_PLCP;
  1296. i += IWL_FIRST_OFDM_RATE;
  1297. /* skip 9M not supported in ht*/
  1298. if (i >= IWL_RATE_9M_INDEX)
  1299. i += 1;
  1300. if ((i >= IWL_FIRST_OFDM_RATE) &&
  1301. (i <= IWL_LAST_OFDM_RATE))
  1302. return i;
  1303. /* 4965 legacy rate format, search for match in table */
  1304. } else {
  1305. for (i = 0; i < ARRAY_SIZE(iwl4965_rates); i++)
  1306. if (iwl4965_rates[i].plcp == (plcp &0xFF))
  1307. return i;
  1308. }
  1309. return -1;
  1310. }
  1311. static u8 iwl4965_rate_get_lowest_plcp(int rate_mask)
  1312. {
  1313. u8 i;
  1314. for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
  1315. i = iwl4965_rates[i].next_ieee) {
  1316. if (rate_mask & (1 << i))
  1317. return iwl4965_rates[i].plcp;
  1318. }
  1319. return IWL_RATE_INVALID;
  1320. }
  1321. static int iwl4965_send_beacon_cmd(struct iwl4965_priv *priv)
  1322. {
  1323. struct iwl4965_frame *frame;
  1324. unsigned int frame_size;
  1325. int rc;
  1326. u8 rate;
  1327. frame = iwl4965_get_free_frame(priv);
  1328. if (!frame) {
  1329. IWL_ERROR("Could not obtain free frame buffer for beacon "
  1330. "command.\n");
  1331. return -ENOMEM;
  1332. }
  1333. if (!(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)) {
  1334. rate = iwl4965_rate_get_lowest_plcp(priv->active_rate_basic &
  1335. 0xFF0);
  1336. if (rate == IWL_INVALID_RATE)
  1337. rate = IWL_RATE_6M_PLCP;
  1338. } else {
  1339. rate = iwl4965_rate_get_lowest_plcp(priv->active_rate_basic & 0xF);
  1340. if (rate == IWL_INVALID_RATE)
  1341. rate = IWL_RATE_1M_PLCP;
  1342. }
  1343. frame_size = iwl4965_hw_get_beacon_cmd(priv, frame, rate);
  1344. rc = iwl4965_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  1345. &frame->u.cmd[0]);
  1346. iwl4965_free_frame(priv, frame);
  1347. return rc;
  1348. }
  1349. /******************************************************************************
  1350. *
  1351. * EEPROM related functions
  1352. *
  1353. ******************************************************************************/
  1354. static void get_eeprom_mac(struct iwl4965_priv *priv, u8 *mac)
  1355. {
  1356. memcpy(mac, priv->eeprom.mac_address, 6);
  1357. }
  1358. /**
  1359. * iwl4965_eeprom_init - read EEPROM contents
  1360. *
  1361. * Load the EEPROM contents from adapter into priv->eeprom
  1362. *
  1363. * NOTE: This routine uses the non-debug IO access functions.
  1364. */
  1365. int iwl4965_eeprom_init(struct iwl4965_priv *priv)
  1366. {
  1367. u16 *e = (u16 *)&priv->eeprom;
  1368. u32 gp = iwl4965_read32(priv, CSR_EEPROM_GP);
  1369. u32 r;
  1370. int sz = sizeof(priv->eeprom);
  1371. int rc;
  1372. int i;
  1373. u16 addr;
  1374. /* The EEPROM structure has several padding buffers within it
  1375. * and when adding new EEPROM maps is subject to programmer errors
  1376. * which may be very difficult to identify without explicitly
  1377. * checking the resulting size of the eeprom map. */
  1378. BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE);
  1379. if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
  1380. IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x", gp);
  1381. return -ENOENT;
  1382. }
  1383. /* Make sure driver (instead of uCode) is allowed to read EEPROM */
  1384. rc = iwl4965_eeprom_acquire_semaphore(priv);
  1385. if (rc < 0) {
  1386. IWL_ERROR("Failed to acquire EEPROM semaphore.\n");
  1387. return -ENOENT;
  1388. }
  1389. /* eeprom is an array of 16bit values */
  1390. for (addr = 0; addr < sz; addr += sizeof(u16)) {
  1391. _iwl4965_write32(priv, CSR_EEPROM_REG, addr << 1);
  1392. _iwl4965_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
  1393. for (i = 0; i < IWL_EEPROM_ACCESS_TIMEOUT;
  1394. i += IWL_EEPROM_ACCESS_DELAY) {
  1395. r = _iwl4965_read_direct32(priv, CSR_EEPROM_REG);
  1396. if (r & CSR_EEPROM_REG_READ_VALID_MSK)
  1397. break;
  1398. udelay(IWL_EEPROM_ACCESS_DELAY);
  1399. }
  1400. if (!(r & CSR_EEPROM_REG_READ_VALID_MSK)) {
  1401. IWL_ERROR("Time out reading EEPROM[%d]", addr);
  1402. rc = -ETIMEDOUT;
  1403. goto done;
  1404. }
  1405. e[addr / 2] = le16_to_cpu(r >> 16);
  1406. }
  1407. rc = 0;
  1408. done:
  1409. iwl4965_eeprom_release_semaphore(priv);
  1410. return rc;
  1411. }
  1412. /******************************************************************************
  1413. *
  1414. * Misc. internal state and helper functions
  1415. *
  1416. ******************************************************************************/
  1417. #ifdef CONFIG_IWL4965_DEBUG
  1418. /**
  1419. * iwl4965_report_frame - dump frame to syslog during debug sessions
  1420. *
  1421. * You may hack this function to show different aspects of received frames,
  1422. * including selective frame dumps.
  1423. * group100 parameter selects whether to show 1 out of 100 good frames.
  1424. *
  1425. * TODO: This was originally written for 3945, need to audit for
  1426. * proper operation with 4965.
  1427. */
  1428. void iwl4965_report_frame(struct iwl4965_priv *priv,
  1429. struct iwl4965_rx_packet *pkt,
  1430. struct ieee80211_hdr *header, int group100)
  1431. {
  1432. u32 to_us;
  1433. u32 print_summary = 0;
  1434. u32 print_dump = 0; /* set to 1 to dump all frames' contents */
  1435. u32 hundred = 0;
  1436. u32 dataframe = 0;
  1437. u16 fc;
  1438. u16 seq_ctl;
  1439. u16 channel;
  1440. u16 phy_flags;
  1441. int rate_sym;
  1442. u16 length;
  1443. u16 status;
  1444. u16 bcn_tmr;
  1445. u32 tsf_low;
  1446. u64 tsf;
  1447. u8 rssi;
  1448. u8 agc;
  1449. u16 sig_avg;
  1450. u16 noise_diff;
  1451. struct iwl4965_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
  1452. struct iwl4965_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
  1453. struct iwl4965_rx_frame_end *rx_end = IWL_RX_END(pkt);
  1454. u8 *data = IWL_RX_DATA(pkt);
  1455. /* MAC header */
  1456. fc = le16_to_cpu(header->frame_control);
  1457. seq_ctl = le16_to_cpu(header->seq_ctrl);
  1458. /* metadata */
  1459. channel = le16_to_cpu(rx_hdr->channel);
  1460. phy_flags = le16_to_cpu(rx_hdr->phy_flags);
  1461. rate_sym = rx_hdr->rate;
  1462. length = le16_to_cpu(rx_hdr->len);
  1463. /* end-of-frame status and timestamp */
  1464. status = le32_to_cpu(rx_end->status);
  1465. bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
  1466. tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
  1467. tsf = le64_to_cpu(rx_end->timestamp);
  1468. /* signal statistics */
  1469. rssi = rx_stats->rssi;
  1470. agc = rx_stats->agc;
  1471. sig_avg = le16_to_cpu(rx_stats->sig_avg);
  1472. noise_diff = le16_to_cpu(rx_stats->noise_diff);
  1473. to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
  1474. /* if data frame is to us and all is good,
  1475. * (optionally) print summary for only 1 out of every 100 */
  1476. if (to_us && (fc & ~IEEE80211_FCTL_PROTECTED) ==
  1477. (IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
  1478. dataframe = 1;
  1479. if (!group100)
  1480. print_summary = 1; /* print each frame */
  1481. else if (priv->framecnt_to_us < 100) {
  1482. priv->framecnt_to_us++;
  1483. print_summary = 0;
  1484. } else {
  1485. priv->framecnt_to_us = 0;
  1486. print_summary = 1;
  1487. hundred = 1;
  1488. }
  1489. } else {
  1490. /* print summary for all other frames */
  1491. print_summary = 1;
  1492. }
  1493. if (print_summary) {
  1494. char *title;
  1495. u32 rate;
  1496. if (hundred)
  1497. title = "100Frames";
  1498. else if (fc & IEEE80211_FCTL_RETRY)
  1499. title = "Retry";
  1500. else if (ieee80211_is_assoc_response(fc))
  1501. title = "AscRsp";
  1502. else if (ieee80211_is_reassoc_response(fc))
  1503. title = "RasRsp";
  1504. else if (ieee80211_is_probe_response(fc)) {
  1505. title = "PrbRsp";
  1506. print_dump = 1; /* dump frame contents */
  1507. } else if (ieee80211_is_beacon(fc)) {
  1508. title = "Beacon";
  1509. print_dump = 1; /* dump frame contents */
  1510. } else if (ieee80211_is_atim(fc))
  1511. title = "ATIM";
  1512. else if (ieee80211_is_auth(fc))
  1513. title = "Auth";
  1514. else if (ieee80211_is_deauth(fc))
  1515. title = "DeAuth";
  1516. else if (ieee80211_is_disassoc(fc))
  1517. title = "DisAssoc";
  1518. else
  1519. title = "Frame";
  1520. rate = iwl4965_rate_index_from_plcp(rate_sym);
  1521. if (rate == -1)
  1522. rate = 0;
  1523. else
  1524. rate = iwl4965_rates[rate].ieee / 2;
  1525. /* print frame summary.
  1526. * MAC addresses show just the last byte (for brevity),
  1527. * but you can hack it to show more, if you'd like to. */
  1528. if (dataframe)
  1529. IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
  1530. "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
  1531. title, fc, header->addr1[5],
  1532. length, rssi, channel, rate);
  1533. else {
  1534. /* src/dst addresses assume managed mode */
  1535. IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
  1536. "src=0x%02x, rssi=%u, tim=%lu usec, "
  1537. "phy=0x%02x, chnl=%d\n",
  1538. title, fc, header->addr1[5],
  1539. header->addr3[5], rssi,
  1540. tsf_low - priv->scan_start_tsf,
  1541. phy_flags, channel);
  1542. }
  1543. }
  1544. if (print_dump)
  1545. iwl4965_print_hex_dump(IWL_DL_RX, data, length);
  1546. }
  1547. #endif
  1548. static void iwl4965_unset_hw_setting(struct iwl4965_priv *priv)
  1549. {
  1550. if (priv->hw_setting.shared_virt)
  1551. pci_free_consistent(priv->pci_dev,
  1552. sizeof(struct iwl4965_shared),
  1553. priv->hw_setting.shared_virt,
  1554. priv->hw_setting.shared_phys);
  1555. }
  1556. /**
  1557. * iwl4965_supported_rate_to_ie - fill in the supported rate in IE field
  1558. *
  1559. * return : set the bit for each supported rate insert in ie
  1560. */
  1561. static u16 iwl4965_supported_rate_to_ie(u8 *ie, u16 supported_rate,
  1562. u16 basic_rate, int *left)
  1563. {
  1564. u16 ret_rates = 0, bit;
  1565. int i;
  1566. u8 *cnt = ie;
  1567. u8 *rates = ie + 1;
  1568. for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
  1569. if (bit & supported_rate) {
  1570. ret_rates |= bit;
  1571. rates[*cnt] = iwl4965_rates[i].ieee |
  1572. ((bit & basic_rate) ? 0x80 : 0x00);
  1573. (*cnt)++;
  1574. (*left)--;
  1575. if ((*left <= 0) ||
  1576. (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
  1577. break;
  1578. }
  1579. }
  1580. return ret_rates;
  1581. }
  1582. #ifdef CONFIG_IWL4965_HT
  1583. void static iwl4965_set_ht_capab(struct ieee80211_hw *hw,
  1584. struct ieee80211_ht_capability *ht_cap,
  1585. u8 use_wide_chan);
  1586. #endif
  1587. /**
  1588. * iwl4965_fill_probe_req - fill in all required fields and IE for probe request
  1589. */
  1590. static u16 iwl4965_fill_probe_req(struct iwl4965_priv *priv,
  1591. struct ieee80211_mgmt *frame,
  1592. int left, int is_direct)
  1593. {
  1594. int len = 0;
  1595. u8 *pos = NULL;
  1596. u16 active_rates, ret_rates, cck_rates, active_rate_basic;
  1597. /* Make sure there is enough space for the probe request,
  1598. * two mandatory IEs and the data */
  1599. left -= 24;
  1600. if (left < 0)
  1601. return 0;
  1602. len += 24;
  1603. frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
  1604. memcpy(frame->da, iwl4965_broadcast_addr, ETH_ALEN);
  1605. memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
  1606. memcpy(frame->bssid, iwl4965_broadcast_addr, ETH_ALEN);
  1607. frame->seq_ctrl = 0;
  1608. /* fill in our indirect SSID IE */
  1609. /* ...next IE... */
  1610. left -= 2;
  1611. if (left < 0)
  1612. return 0;
  1613. len += 2;
  1614. pos = &(frame->u.probe_req.variable[0]);
  1615. *pos++ = WLAN_EID_SSID;
  1616. *pos++ = 0;
  1617. /* fill in our direct SSID IE... */
  1618. if (is_direct) {
  1619. /* ...next IE... */
  1620. left -= 2 + priv->essid_len;
  1621. if (left < 0)
  1622. return 0;
  1623. /* ... fill it in... */
  1624. *pos++ = WLAN_EID_SSID;
  1625. *pos++ = priv->essid_len;
  1626. memcpy(pos, priv->essid, priv->essid_len);
  1627. pos += priv->essid_len;
  1628. len += 2 + priv->essid_len;
  1629. }
  1630. /* fill in supported rate */
  1631. /* ...next IE... */
  1632. left -= 2;
  1633. if (left < 0)
  1634. return 0;
  1635. /* ... fill it in... */
  1636. *pos++ = WLAN_EID_SUPP_RATES;
  1637. *pos = 0;
  1638. /* exclude 60M rate */
  1639. active_rates = priv->rates_mask;
  1640. active_rates &= ~IWL_RATE_60M_MASK;
  1641. active_rate_basic = active_rates & IWL_BASIC_RATES_MASK;
  1642. cck_rates = IWL_CCK_RATES_MASK & active_rates;
  1643. ret_rates = iwl4965_supported_rate_to_ie(pos, cck_rates,
  1644. active_rate_basic, &left);
  1645. active_rates &= ~ret_rates;
  1646. ret_rates = iwl4965_supported_rate_to_ie(pos, active_rates,
  1647. active_rate_basic, &left);
  1648. active_rates &= ~ret_rates;
  1649. len += 2 + *pos;
  1650. pos += (*pos) + 1;
  1651. if (active_rates == 0)
  1652. goto fill_end;
  1653. /* fill in supported extended rate */
  1654. /* ...next IE... */
  1655. left -= 2;
  1656. if (left < 0)
  1657. return 0;
  1658. /* ... fill it in... */
  1659. *pos++ = WLAN_EID_EXT_SUPP_RATES;
  1660. *pos = 0;
  1661. iwl4965_supported_rate_to_ie(pos, active_rates,
  1662. active_rate_basic, &left);
  1663. if (*pos > 0)
  1664. len += 2 + *pos;
  1665. #ifdef CONFIG_IWL4965_HT
  1666. if (is_direct && priv->is_ht_enabled) {
  1667. u8 use_wide_chan = 1;
  1668. if (priv->channel_width != IWL_CHANNEL_WIDTH_40MHZ)
  1669. use_wide_chan = 0;
  1670. pos += (*pos) + 1;
  1671. *pos++ = WLAN_EID_HT_CAPABILITY;
  1672. *pos++ = sizeof(struct ieee80211_ht_capability);
  1673. iwl4965_set_ht_capab(NULL, (struct ieee80211_ht_capability *)pos,
  1674. use_wide_chan);
  1675. len += 2 + sizeof(struct ieee80211_ht_capability);
  1676. }
  1677. #endif /*CONFIG_IWL4965_HT */
  1678. fill_end:
  1679. return (u16)len;
  1680. }
  1681. /*
  1682. * QoS support
  1683. */
  1684. #ifdef CONFIG_IWL4965_QOS
  1685. static int iwl4965_send_qos_params_command(struct iwl4965_priv *priv,
  1686. struct iwl4965_qosparam_cmd *qos)
  1687. {
  1688. return iwl4965_send_cmd_pdu(priv, REPLY_QOS_PARAM,
  1689. sizeof(struct iwl4965_qosparam_cmd), qos);
  1690. }
  1691. static void iwl4965_reset_qos(struct iwl4965_priv *priv)
  1692. {
  1693. u16 cw_min = 15;
  1694. u16 cw_max = 1023;
  1695. u8 aifs = 2;
  1696. u8 is_legacy = 0;
  1697. unsigned long flags;
  1698. int i;
  1699. spin_lock_irqsave(&priv->lock, flags);
  1700. priv->qos_data.qos_active = 0;
  1701. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) {
  1702. if (priv->qos_data.qos_enable)
  1703. priv->qos_data.qos_active = 1;
  1704. if (!(priv->active_rate & 0xfff0)) {
  1705. cw_min = 31;
  1706. is_legacy = 1;
  1707. }
  1708. } else if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  1709. if (priv->qos_data.qos_enable)
  1710. priv->qos_data.qos_active = 1;
  1711. } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
  1712. cw_min = 31;
  1713. is_legacy = 1;
  1714. }
  1715. if (priv->qos_data.qos_active)
  1716. aifs = 3;
  1717. priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
  1718. priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
  1719. priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
  1720. priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
  1721. priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
  1722. if (priv->qos_data.qos_active) {
  1723. i = 1;
  1724. priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
  1725. priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
  1726. priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
  1727. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  1728. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1729. i = 2;
  1730. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1731. cpu_to_le16((cw_min + 1) / 2 - 1);
  1732. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1733. cpu_to_le16(cw_max);
  1734. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  1735. if (is_legacy)
  1736. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1737. cpu_to_le16(6016);
  1738. else
  1739. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1740. cpu_to_le16(3008);
  1741. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1742. i = 3;
  1743. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1744. cpu_to_le16((cw_min + 1) / 4 - 1);
  1745. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1746. cpu_to_le16((cw_max + 1) / 2 - 1);
  1747. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  1748. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1749. if (is_legacy)
  1750. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1751. cpu_to_le16(3264);
  1752. else
  1753. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1754. cpu_to_le16(1504);
  1755. } else {
  1756. for (i = 1; i < 4; i++) {
  1757. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1758. cpu_to_le16(cw_min);
  1759. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1760. cpu_to_le16(cw_max);
  1761. priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
  1762. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  1763. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1764. }
  1765. }
  1766. IWL_DEBUG_QOS("set QoS to default \n");
  1767. spin_unlock_irqrestore(&priv->lock, flags);
  1768. }
  1769. static void iwl4965_activate_qos(struct iwl4965_priv *priv, u8 force)
  1770. {
  1771. unsigned long flags;
  1772. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1773. return;
  1774. if (!priv->qos_data.qos_enable)
  1775. return;
  1776. spin_lock_irqsave(&priv->lock, flags);
  1777. priv->qos_data.def_qos_parm.qos_flags = 0;
  1778. if (priv->qos_data.qos_cap.q_AP.queue_request &&
  1779. !priv->qos_data.qos_cap.q_AP.txop_request)
  1780. priv->qos_data.def_qos_parm.qos_flags |=
  1781. QOS_PARAM_FLG_TXOP_TYPE_MSK;
  1782. if (priv->qos_data.qos_active)
  1783. priv->qos_data.def_qos_parm.qos_flags |=
  1784. QOS_PARAM_FLG_UPDATE_EDCA_MSK;
  1785. #ifdef CONFIG_IWL4965_HT
  1786. if (priv->is_ht_enabled && priv->current_assoc_ht.is_ht)
  1787. priv->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
  1788. #endif /* CONFIG_IWL4965_HT */
  1789. spin_unlock_irqrestore(&priv->lock, flags);
  1790. if (force || iwl4965_is_associated(priv)) {
  1791. IWL_DEBUG_QOS("send QoS cmd with Qos active=%d FLAGS=0x%X\n",
  1792. priv->qos_data.qos_active,
  1793. priv->qos_data.def_qos_parm.qos_flags);
  1794. iwl4965_send_qos_params_command(priv,
  1795. &(priv->qos_data.def_qos_parm));
  1796. }
  1797. }
  1798. #endif /* CONFIG_IWL4965_QOS */
  1799. /*
  1800. * Power management (not Tx power!) functions
  1801. */
  1802. #define MSEC_TO_USEC 1024
  1803. #define NOSLP __constant_cpu_to_le16(0), 0, 0
  1804. #define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0
  1805. #define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
  1806. #define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
  1807. __constant_cpu_to_le32(X1), \
  1808. __constant_cpu_to_le32(X2), \
  1809. __constant_cpu_to_le32(X3), \
  1810. __constant_cpu_to_le32(X4)}
  1811. /* default power management (not Tx power) table values */
  1812. /* for tim 0-10 */
  1813. static struct iwl4965_power_vec_entry range_0[IWL_POWER_AC] = {
  1814. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1815. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
  1816. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
  1817. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
  1818. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
  1819. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
  1820. };
  1821. /* for tim > 10 */
  1822. static struct iwl4965_power_vec_entry range_1[IWL_POWER_AC] = {
  1823. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1824. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
  1825. SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
  1826. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
  1827. SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
  1828. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
  1829. SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
  1830. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
  1831. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
  1832. SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
  1833. };
  1834. int iwl4965_power_init_handle(struct iwl4965_priv *priv)
  1835. {
  1836. int rc = 0, i;
  1837. struct iwl4965_power_mgr *pow_data;
  1838. int size = sizeof(struct iwl4965_power_vec_entry) * IWL_POWER_AC;
  1839. u16 pci_pm;
  1840. IWL_DEBUG_POWER("Initialize power \n");
  1841. pow_data = &(priv->power_data);
  1842. memset(pow_data, 0, sizeof(*pow_data));
  1843. pow_data->active_index = IWL_POWER_RANGE_0;
  1844. pow_data->dtim_val = 0xffff;
  1845. memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
  1846. memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
  1847. rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
  1848. if (rc != 0)
  1849. return 0;
  1850. else {
  1851. struct iwl4965_powertable_cmd *cmd;
  1852. IWL_DEBUG_POWER("adjust power command flags\n");
  1853. for (i = 0; i < IWL_POWER_AC; i++) {
  1854. cmd = &pow_data->pwr_range_0[i].cmd;
  1855. if (pci_pm & 0x1)
  1856. cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
  1857. else
  1858. cmd->flags |= IWL_POWER_PCI_PM_MSK;
  1859. }
  1860. }
  1861. return rc;
  1862. }
  1863. static int iwl4965_update_power_cmd(struct iwl4965_priv *priv,
  1864. struct iwl4965_powertable_cmd *cmd, u32 mode)
  1865. {
  1866. int rc = 0, i;
  1867. u8 skip;
  1868. u32 max_sleep = 0;
  1869. struct iwl4965_power_vec_entry *range;
  1870. u8 period = 0;
  1871. struct iwl4965_power_mgr *pow_data;
  1872. if (mode > IWL_POWER_INDEX_5) {
  1873. IWL_DEBUG_POWER("Error invalid power mode \n");
  1874. return -1;
  1875. }
  1876. pow_data = &(priv->power_data);
  1877. if (pow_data->active_index == IWL_POWER_RANGE_0)
  1878. range = &pow_data->pwr_range_0[0];
  1879. else
  1880. range = &pow_data->pwr_range_1[1];
  1881. memcpy(cmd, &range[mode].cmd, sizeof(struct iwl4965_powertable_cmd));
  1882. #ifdef IWL_MAC80211_DISABLE
  1883. if (priv->assoc_network != NULL) {
  1884. unsigned long flags;
  1885. period = priv->assoc_network->tim.tim_period;
  1886. }
  1887. #endif /*IWL_MAC80211_DISABLE */
  1888. skip = range[mode].no_dtim;
  1889. if (period == 0) {
  1890. period = 1;
  1891. skip = 0;
  1892. }
  1893. if (skip == 0) {
  1894. max_sleep = period;
  1895. cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1896. } else {
  1897. __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
  1898. max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
  1899. cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1900. }
  1901. for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
  1902. if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
  1903. cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
  1904. }
  1905. IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
  1906. IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
  1907. IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
  1908. IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
  1909. le32_to_cpu(cmd->sleep_interval[0]),
  1910. le32_to_cpu(cmd->sleep_interval[1]),
  1911. le32_to_cpu(cmd->sleep_interval[2]),
  1912. le32_to_cpu(cmd->sleep_interval[3]),
  1913. le32_to_cpu(cmd->sleep_interval[4]));
  1914. return rc;
  1915. }
  1916. static int iwl4965_send_power_mode(struct iwl4965_priv *priv, u32 mode)
  1917. {
  1918. u32 uninitialized_var(final_mode);
  1919. int rc;
  1920. struct iwl4965_powertable_cmd cmd;
  1921. /* If on battery, set to 3,
  1922. * if plugged into AC power, set to CAM ("continuously aware mode"),
  1923. * else user level */
  1924. switch (mode) {
  1925. case IWL_POWER_BATTERY:
  1926. final_mode = IWL_POWER_INDEX_3;
  1927. break;
  1928. case IWL_POWER_AC:
  1929. final_mode = IWL_POWER_MODE_CAM;
  1930. break;
  1931. default:
  1932. final_mode = mode;
  1933. break;
  1934. }
  1935. cmd.keep_alive_beacons = 0;
  1936. iwl4965_update_power_cmd(priv, &cmd, final_mode);
  1937. rc = iwl4965_send_cmd_pdu(priv, POWER_TABLE_CMD, sizeof(cmd), &cmd);
  1938. if (final_mode == IWL_POWER_MODE_CAM)
  1939. clear_bit(STATUS_POWER_PMI, &priv->status);
  1940. else
  1941. set_bit(STATUS_POWER_PMI, &priv->status);
  1942. return rc;
  1943. }
  1944. int iwl4965_is_network_packet(struct iwl4965_priv *priv, struct ieee80211_hdr *header)
  1945. {
  1946. /* Filter incoming packets to determine if they are targeted toward
  1947. * this network, discarding packets coming from ourselves */
  1948. switch (priv->iw_mode) {
  1949. case IEEE80211_IF_TYPE_IBSS: /* Header: Dest. | Source | BSSID */
  1950. /* packets from our adapter are dropped (echo) */
  1951. if (!compare_ether_addr(header->addr2, priv->mac_addr))
  1952. return 0;
  1953. /* {broad,multi}cast packets to our IBSS go through */
  1954. if (is_multicast_ether_addr(header->addr1))
  1955. return !compare_ether_addr(header->addr3, priv->bssid);
  1956. /* packets to our adapter go through */
  1957. return !compare_ether_addr(header->addr1, priv->mac_addr);
  1958. case IEEE80211_IF_TYPE_STA: /* Header: Dest. | AP{BSSID} | Source */
  1959. /* packets from our adapter are dropped (echo) */
  1960. if (!compare_ether_addr(header->addr3, priv->mac_addr))
  1961. return 0;
  1962. /* {broad,multi}cast packets to our BSS go through */
  1963. if (is_multicast_ether_addr(header->addr1))
  1964. return !compare_ether_addr(header->addr2, priv->bssid);
  1965. /* packets to our adapter go through */
  1966. return !compare_ether_addr(header->addr1, priv->mac_addr);
  1967. }
  1968. return 1;
  1969. }
  1970. #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
  1971. static const char *iwl4965_get_tx_fail_reason(u32 status)
  1972. {
  1973. switch (status & TX_STATUS_MSK) {
  1974. case TX_STATUS_SUCCESS:
  1975. return "SUCCESS";
  1976. TX_STATUS_ENTRY(SHORT_LIMIT);
  1977. TX_STATUS_ENTRY(LONG_LIMIT);
  1978. TX_STATUS_ENTRY(FIFO_UNDERRUN);
  1979. TX_STATUS_ENTRY(MGMNT_ABORT);
  1980. TX_STATUS_ENTRY(NEXT_FRAG);
  1981. TX_STATUS_ENTRY(LIFE_EXPIRE);
  1982. TX_STATUS_ENTRY(DEST_PS);
  1983. TX_STATUS_ENTRY(ABORTED);
  1984. TX_STATUS_ENTRY(BT_RETRY);
  1985. TX_STATUS_ENTRY(STA_INVALID);
  1986. TX_STATUS_ENTRY(FRAG_DROPPED);
  1987. TX_STATUS_ENTRY(TID_DISABLE);
  1988. TX_STATUS_ENTRY(FRAME_FLUSHED);
  1989. TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
  1990. TX_STATUS_ENTRY(TX_LOCKED);
  1991. TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
  1992. }
  1993. return "UNKNOWN";
  1994. }
  1995. /**
  1996. * iwl4965_scan_cancel - Cancel any currently executing HW scan
  1997. *
  1998. * NOTE: priv->mutex is not required before calling this function
  1999. */
  2000. static int iwl4965_scan_cancel(struct iwl4965_priv *priv)
  2001. {
  2002. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  2003. clear_bit(STATUS_SCANNING, &priv->status);
  2004. return 0;
  2005. }
  2006. if (test_bit(STATUS_SCANNING, &priv->status)) {
  2007. if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  2008. IWL_DEBUG_SCAN("Queuing scan abort.\n");
  2009. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  2010. queue_work(priv->workqueue, &priv->abort_scan);
  2011. } else
  2012. IWL_DEBUG_SCAN("Scan abort already in progress.\n");
  2013. return test_bit(STATUS_SCANNING, &priv->status);
  2014. }
  2015. return 0;
  2016. }
  2017. /**
  2018. * iwl4965_scan_cancel_timeout - Cancel any currently executing HW scan
  2019. * @ms: amount of time to wait (in milliseconds) for scan to abort
  2020. *
  2021. * NOTE: priv->mutex must be held before calling this function
  2022. */
  2023. static int iwl4965_scan_cancel_timeout(struct iwl4965_priv *priv, unsigned long ms)
  2024. {
  2025. unsigned long now = jiffies;
  2026. int ret;
  2027. ret = iwl4965_scan_cancel(priv);
  2028. if (ret && ms) {
  2029. mutex_unlock(&priv->mutex);
  2030. while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
  2031. test_bit(STATUS_SCANNING, &priv->status))
  2032. msleep(1);
  2033. mutex_lock(&priv->mutex);
  2034. return test_bit(STATUS_SCANNING, &priv->status);
  2035. }
  2036. return ret;
  2037. }
  2038. static void iwl4965_sequence_reset(struct iwl4965_priv *priv)
  2039. {
  2040. /* Reset ieee stats */
  2041. /* We don't reset the net_device_stats (ieee->stats) on
  2042. * re-association */
  2043. priv->last_seq_num = -1;
  2044. priv->last_frag_num = -1;
  2045. priv->last_packet_time = 0;
  2046. iwl4965_scan_cancel(priv);
  2047. }
  2048. #define MAX_UCODE_BEACON_INTERVAL 4096
  2049. #define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
  2050. static __le16 iwl4965_adjust_beacon_interval(u16 beacon_val)
  2051. {
  2052. u16 new_val = 0;
  2053. u16 beacon_factor = 0;
  2054. beacon_factor =
  2055. (beacon_val + MAX_UCODE_BEACON_INTERVAL)
  2056. / MAX_UCODE_BEACON_INTERVAL;
  2057. new_val = beacon_val / beacon_factor;
  2058. return cpu_to_le16(new_val);
  2059. }
  2060. static void iwl4965_setup_rxon_timing(struct iwl4965_priv *priv)
  2061. {
  2062. u64 interval_tm_unit;
  2063. u64 tsf, result;
  2064. unsigned long flags;
  2065. struct ieee80211_conf *conf = NULL;
  2066. u16 beacon_int = 0;
  2067. conf = ieee80211_get_hw_conf(priv->hw);
  2068. spin_lock_irqsave(&priv->lock, flags);
  2069. priv->rxon_timing.timestamp.dw[1] = cpu_to_le32(priv->timestamp1);
  2070. priv->rxon_timing.timestamp.dw[0] = cpu_to_le32(priv->timestamp0);
  2071. priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
  2072. tsf = priv->timestamp1;
  2073. tsf = ((tsf << 32) | priv->timestamp0);
  2074. beacon_int = priv->beacon_int;
  2075. spin_unlock_irqrestore(&priv->lock, flags);
  2076. if (priv->iw_mode == IEEE80211_IF_TYPE_STA) {
  2077. if (beacon_int == 0) {
  2078. priv->rxon_timing.beacon_interval = cpu_to_le16(100);
  2079. priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
  2080. } else {
  2081. priv->rxon_timing.beacon_interval =
  2082. cpu_to_le16(beacon_int);
  2083. priv->rxon_timing.beacon_interval =
  2084. iwl4965_adjust_beacon_interval(
  2085. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2086. }
  2087. priv->rxon_timing.atim_window = 0;
  2088. } else {
  2089. priv->rxon_timing.beacon_interval =
  2090. iwl4965_adjust_beacon_interval(conf->beacon_int);
  2091. /* TODO: we need to get atim_window from upper stack
  2092. * for now we set to 0 */
  2093. priv->rxon_timing.atim_window = 0;
  2094. }
  2095. interval_tm_unit =
  2096. (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
  2097. result = do_div(tsf, interval_tm_unit);
  2098. priv->rxon_timing.beacon_init_val =
  2099. cpu_to_le32((u32) ((u64) interval_tm_unit - result));
  2100. IWL_DEBUG_ASSOC
  2101. ("beacon interval %d beacon timer %d beacon tim %d\n",
  2102. le16_to_cpu(priv->rxon_timing.beacon_interval),
  2103. le32_to_cpu(priv->rxon_timing.beacon_init_val),
  2104. le16_to_cpu(priv->rxon_timing.atim_window));
  2105. }
  2106. static int iwl4965_scan_initiate(struct iwl4965_priv *priv)
  2107. {
  2108. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  2109. IWL_ERROR("APs don't scan.\n");
  2110. return 0;
  2111. }
  2112. if (!iwl4965_is_ready_rf(priv)) {
  2113. IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
  2114. return -EIO;
  2115. }
  2116. if (test_bit(STATUS_SCANNING, &priv->status)) {
  2117. IWL_DEBUG_SCAN("Scan already in progress.\n");
  2118. return -EAGAIN;
  2119. }
  2120. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  2121. IWL_DEBUG_SCAN("Scan request while abort pending. "
  2122. "Queuing.\n");
  2123. return -EAGAIN;
  2124. }
  2125. IWL_DEBUG_INFO("Starting scan...\n");
  2126. priv->scan_bands = 2;
  2127. set_bit(STATUS_SCANNING, &priv->status);
  2128. priv->scan_start = jiffies;
  2129. priv->scan_pass_start = priv->scan_start;
  2130. queue_work(priv->workqueue, &priv->request_scan);
  2131. return 0;
  2132. }
  2133. static int iwl4965_set_rxon_hwcrypto(struct iwl4965_priv *priv, int hw_decrypt)
  2134. {
  2135. struct iwl4965_rxon_cmd *rxon = &priv->staging_rxon;
  2136. if (hw_decrypt)
  2137. rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
  2138. else
  2139. rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
  2140. return 0;
  2141. }
  2142. static void iwl4965_set_flags_for_phymode(struct iwl4965_priv *priv, u8 phymode)
  2143. {
  2144. if (phymode == MODE_IEEE80211A) {
  2145. priv->staging_rxon.flags &=
  2146. ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
  2147. | RXON_FLG_CCK_MSK);
  2148. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  2149. } else {
  2150. /* Copied from iwl4965_bg_post_associate() */
  2151. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  2152. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  2153. else
  2154. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  2155. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
  2156. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  2157. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  2158. priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
  2159. priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
  2160. }
  2161. }
  2162. /*
  2163. * initialize rxon structure with default values from eeprom
  2164. */
  2165. static void iwl4965_connection_init_rx_config(struct iwl4965_priv *priv)
  2166. {
  2167. const struct iwl4965_channel_info *ch_info;
  2168. memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
  2169. switch (priv->iw_mode) {
  2170. case IEEE80211_IF_TYPE_AP:
  2171. priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
  2172. break;
  2173. case IEEE80211_IF_TYPE_STA:
  2174. priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
  2175. priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
  2176. break;
  2177. case IEEE80211_IF_TYPE_IBSS:
  2178. priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
  2179. priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
  2180. priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
  2181. RXON_FILTER_ACCEPT_GRP_MSK;
  2182. break;
  2183. case IEEE80211_IF_TYPE_MNTR:
  2184. priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
  2185. priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
  2186. RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
  2187. break;
  2188. }
  2189. #if 0
  2190. /* TODO: Figure out when short_preamble would be set and cache from
  2191. * that */
  2192. if (!hw_to_local(priv->hw)->short_preamble)
  2193. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2194. else
  2195. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  2196. #endif
  2197. ch_info = iwl4965_get_channel_info(priv, priv->phymode,
  2198. le16_to_cpu(priv->staging_rxon.channel));
  2199. if (!ch_info)
  2200. ch_info = &priv->channel_info[0];
  2201. /*
  2202. * in some case A channels are all non IBSS
  2203. * in this case force B/G channel
  2204. */
  2205. if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) &&
  2206. !(is_channel_ibss(ch_info)))
  2207. ch_info = &priv->channel_info[0];
  2208. priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
  2209. if (is_channel_a_band(ch_info))
  2210. priv->phymode = MODE_IEEE80211A;
  2211. else
  2212. priv->phymode = MODE_IEEE80211G;
  2213. iwl4965_set_flags_for_phymode(priv, priv->phymode);
  2214. priv->staging_rxon.ofdm_basic_rates =
  2215. (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  2216. priv->staging_rxon.cck_basic_rates =
  2217. (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  2218. priv->staging_rxon.flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
  2219. RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
  2220. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  2221. memcpy(priv->staging_rxon.wlap_bssid_addr, priv->mac_addr, ETH_ALEN);
  2222. priv->staging_rxon.ofdm_ht_single_stream_basic_rates = 0xff;
  2223. priv->staging_rxon.ofdm_ht_dual_stream_basic_rates = 0xff;
  2224. iwl4965_set_rxon_chain(priv);
  2225. }
  2226. static int iwl4965_set_mode(struct iwl4965_priv *priv, int mode)
  2227. {
  2228. if (!iwl4965_is_ready_rf(priv))
  2229. return -EAGAIN;
  2230. if (mode == IEEE80211_IF_TYPE_IBSS) {
  2231. const struct iwl4965_channel_info *ch_info;
  2232. ch_info = iwl4965_get_channel_info(priv,
  2233. priv->phymode,
  2234. le16_to_cpu(priv->staging_rxon.channel));
  2235. if (!ch_info || !is_channel_ibss(ch_info)) {
  2236. IWL_ERROR("channel %d not IBSS channel\n",
  2237. le16_to_cpu(priv->staging_rxon.channel));
  2238. return -EINVAL;
  2239. }
  2240. }
  2241. cancel_delayed_work(&priv->scan_check);
  2242. if (iwl4965_scan_cancel_timeout(priv, 100)) {
  2243. IWL_WARNING("Aborted scan still in progress after 100ms\n");
  2244. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  2245. return -EAGAIN;
  2246. }
  2247. priv->iw_mode = mode;
  2248. iwl4965_connection_init_rx_config(priv);
  2249. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  2250. iwl4965_clear_stations_table(priv);
  2251. iwl4965_commit_rxon(priv);
  2252. return 0;
  2253. }
  2254. static void iwl4965_build_tx_cmd_hwcrypto(struct iwl4965_priv *priv,
  2255. struct ieee80211_tx_control *ctl,
  2256. struct iwl4965_cmd *cmd,
  2257. struct sk_buff *skb_frag,
  2258. int last_frag)
  2259. {
  2260. struct iwl4965_hw_key *keyinfo = &priv->stations[ctl->key_idx].keyinfo;
  2261. switch (keyinfo->alg) {
  2262. case ALG_CCMP:
  2263. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM;
  2264. memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen);
  2265. IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n");
  2266. break;
  2267. case ALG_TKIP:
  2268. #if 0
  2269. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP;
  2270. if (last_frag)
  2271. memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8,
  2272. 8);
  2273. else
  2274. memset(cmd->cmd.tx.tkip_mic.byte, 0, 8);
  2275. #endif
  2276. break;
  2277. case ALG_WEP:
  2278. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP |
  2279. (ctl->key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
  2280. if (keyinfo->keylen == 13)
  2281. cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
  2282. memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen);
  2283. IWL_DEBUG_TX("Configuring packet for WEP encryption "
  2284. "with key %d\n", ctl->key_idx);
  2285. break;
  2286. default:
  2287. printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg);
  2288. break;
  2289. }
  2290. }
  2291. /*
  2292. * handle build REPLY_TX command notification.
  2293. */
  2294. static void iwl4965_build_tx_cmd_basic(struct iwl4965_priv *priv,
  2295. struct iwl4965_cmd *cmd,
  2296. struct ieee80211_tx_control *ctrl,
  2297. struct ieee80211_hdr *hdr,
  2298. int is_unicast, u8 std_id)
  2299. {
  2300. __le16 *qc;
  2301. u16 fc = le16_to_cpu(hdr->frame_control);
  2302. __le32 tx_flags = cmd->cmd.tx.tx_flags;
  2303. cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  2304. if (!(ctrl->flags & IEEE80211_TXCTL_NO_ACK)) {
  2305. tx_flags |= TX_CMD_FLG_ACK_MSK;
  2306. if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT)
  2307. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  2308. if (ieee80211_is_probe_response(fc) &&
  2309. !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
  2310. tx_flags |= TX_CMD_FLG_TSF_MSK;
  2311. } else {
  2312. tx_flags &= (~TX_CMD_FLG_ACK_MSK);
  2313. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  2314. }
  2315. cmd->cmd.tx.sta_id = std_id;
  2316. if (ieee80211_get_morefrag(hdr))
  2317. tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
  2318. qc = ieee80211_get_qos_ctrl(hdr);
  2319. if (qc) {
  2320. cmd->cmd.tx.tid_tspec = (u8) (le16_to_cpu(*qc) & 0xf);
  2321. tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
  2322. } else
  2323. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  2324. if (ctrl->flags & IEEE80211_TXCTL_USE_RTS_CTS) {
  2325. tx_flags |= TX_CMD_FLG_RTS_MSK;
  2326. tx_flags &= ~TX_CMD_FLG_CTS_MSK;
  2327. } else if (ctrl->flags & IEEE80211_TXCTL_USE_CTS_PROTECT) {
  2328. tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  2329. tx_flags |= TX_CMD_FLG_CTS_MSK;
  2330. }
  2331. if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
  2332. tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
  2333. tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
  2334. if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) {
  2335. if ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_ASSOC_REQ ||
  2336. (fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_REASSOC_REQ)
  2337. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
  2338. else
  2339. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
  2340. } else
  2341. cmd->cmd.tx.timeout.pm_frame_timeout = 0;
  2342. cmd->cmd.tx.driver_txop = 0;
  2343. cmd->cmd.tx.tx_flags = tx_flags;
  2344. cmd->cmd.tx.next_frame_len = 0;
  2345. }
  2346. /**
  2347. * iwl4965_get_sta_id - Find station's index within station table
  2348. *
  2349. * If new IBSS station, create new entry in station table
  2350. */
  2351. static int iwl4965_get_sta_id(struct iwl4965_priv *priv,
  2352. struct ieee80211_hdr *hdr)
  2353. {
  2354. int sta_id;
  2355. u16 fc = le16_to_cpu(hdr->frame_control);
  2356. DECLARE_MAC_BUF(mac);
  2357. /* If this frame is broadcast or management, use broadcast station id */
  2358. if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
  2359. is_multicast_ether_addr(hdr->addr1))
  2360. return priv->hw_setting.bcast_sta_id;
  2361. switch (priv->iw_mode) {
  2362. /* If we are a client station in a BSS network, use the special
  2363. * AP station entry (that's the only station we communicate with) */
  2364. case IEEE80211_IF_TYPE_STA:
  2365. return IWL_AP_ID;
  2366. /* If we are an AP, then find the station, or use BCAST */
  2367. case IEEE80211_IF_TYPE_AP:
  2368. sta_id = iwl4965_hw_find_station(priv, hdr->addr1);
  2369. if (sta_id != IWL_INVALID_STATION)
  2370. return sta_id;
  2371. return priv->hw_setting.bcast_sta_id;
  2372. /* If this frame is going out to an IBSS network, find the station,
  2373. * or create a new station table entry */
  2374. case IEEE80211_IF_TYPE_IBSS:
  2375. sta_id = iwl4965_hw_find_station(priv, hdr->addr1);
  2376. if (sta_id != IWL_INVALID_STATION)
  2377. return sta_id;
  2378. /* Create new station table entry */
  2379. sta_id = iwl4965_add_station_flags(priv, hdr->addr1, 0, CMD_ASYNC);
  2380. if (sta_id != IWL_INVALID_STATION)
  2381. return sta_id;
  2382. IWL_DEBUG_DROP("Station %s not in station map. "
  2383. "Defaulting to broadcast...\n",
  2384. print_mac(mac, hdr->addr1));
  2385. iwl4965_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
  2386. return priv->hw_setting.bcast_sta_id;
  2387. default:
  2388. IWL_WARNING("Unknown mode of operation: %d", priv->iw_mode);
  2389. return priv->hw_setting.bcast_sta_id;
  2390. }
  2391. }
  2392. /*
  2393. * start REPLY_TX command process
  2394. */
  2395. static int iwl4965_tx_skb(struct iwl4965_priv *priv,
  2396. struct sk_buff *skb, struct ieee80211_tx_control *ctl)
  2397. {
  2398. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  2399. struct iwl4965_tfd_frame *tfd;
  2400. u32 *control_flags;
  2401. int txq_id = ctl->queue;
  2402. struct iwl4965_tx_queue *txq = NULL;
  2403. struct iwl4965_queue *q = NULL;
  2404. dma_addr_t phys_addr;
  2405. dma_addr_t txcmd_phys;
  2406. struct iwl4965_cmd *out_cmd = NULL;
  2407. u16 len, idx, len_org;
  2408. u8 id, hdr_len, unicast;
  2409. u8 sta_id;
  2410. u16 seq_number = 0;
  2411. u16 fc;
  2412. __le16 *qc;
  2413. u8 wait_write_ptr = 0;
  2414. unsigned long flags;
  2415. int rc;
  2416. spin_lock_irqsave(&priv->lock, flags);
  2417. if (iwl4965_is_rfkill(priv)) {
  2418. IWL_DEBUG_DROP("Dropping - RF KILL\n");
  2419. goto drop_unlock;
  2420. }
  2421. if (!priv->interface_id) {
  2422. IWL_DEBUG_DROP("Dropping - !priv->interface_id\n");
  2423. goto drop_unlock;
  2424. }
  2425. if ((ctl->tx_rate & 0xFF) == IWL_INVALID_RATE) {
  2426. IWL_ERROR("ERROR: No TX rate available.\n");
  2427. goto drop_unlock;
  2428. }
  2429. unicast = !is_multicast_ether_addr(hdr->addr1);
  2430. id = 0;
  2431. fc = le16_to_cpu(hdr->frame_control);
  2432. #ifdef CONFIG_IWL4965_DEBUG
  2433. if (ieee80211_is_auth(fc))
  2434. IWL_DEBUG_TX("Sending AUTH frame\n");
  2435. else if (ieee80211_is_assoc_request(fc))
  2436. IWL_DEBUG_TX("Sending ASSOC frame\n");
  2437. else if (ieee80211_is_reassoc_request(fc))
  2438. IWL_DEBUG_TX("Sending REASSOC frame\n");
  2439. #endif
  2440. /* drop all data frame if we are not associated */
  2441. if (!iwl4965_is_associated(priv) && !priv->assoc_id &&
  2442. ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA)) {
  2443. IWL_DEBUG_DROP("Dropping - !iwl4965_is_associated\n");
  2444. goto drop_unlock;
  2445. }
  2446. spin_unlock_irqrestore(&priv->lock, flags);
  2447. hdr_len = ieee80211_get_hdrlen(fc);
  2448. /* Find (or create) index into station table for destination station */
  2449. sta_id = iwl4965_get_sta_id(priv, hdr);
  2450. if (sta_id == IWL_INVALID_STATION) {
  2451. DECLARE_MAC_BUF(mac);
  2452. IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n",
  2453. print_mac(mac, hdr->addr1));
  2454. goto drop;
  2455. }
  2456. IWL_DEBUG_RATE("station Id %d\n", sta_id);
  2457. qc = ieee80211_get_qos_ctrl(hdr);
  2458. if (qc) {
  2459. u8 tid = (u8)(le16_to_cpu(*qc) & 0xf);
  2460. seq_number = priv->stations[sta_id].tid[tid].seq_number &
  2461. IEEE80211_SCTL_SEQ;
  2462. hdr->seq_ctrl = cpu_to_le16(seq_number) |
  2463. (hdr->seq_ctrl &
  2464. __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
  2465. seq_number += 0x10;
  2466. #ifdef CONFIG_IWL4965_HT
  2467. #ifdef CONFIG_IWL4965_HT_AGG
  2468. /* aggregation is on for this <sta,tid> */
  2469. if (ctl->flags & IEEE80211_TXCTL_HT_MPDU_AGG)
  2470. txq_id = priv->stations[sta_id].tid[tid].agg.txq_id;
  2471. #endif /* CONFIG_IWL4965_HT_AGG */
  2472. #endif /* CONFIG_IWL4965_HT */
  2473. }
  2474. /* Descriptor for chosen Tx queue */
  2475. txq = &priv->txq[txq_id];
  2476. q = &txq->q;
  2477. spin_lock_irqsave(&priv->lock, flags);
  2478. /* Set up first empty TFD within this queue's circular TFD buffer */
  2479. tfd = &txq->bd[q->write_ptr];
  2480. memset(tfd, 0, sizeof(*tfd));
  2481. control_flags = (u32 *) tfd;
  2482. idx = get_cmd_index(q, q->write_ptr, 0);
  2483. /* Set up driver data for this TFD */
  2484. memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl4965_tx_info));
  2485. txq->txb[q->write_ptr].skb[0] = skb;
  2486. memcpy(&(txq->txb[q->write_ptr].status.control),
  2487. ctl, sizeof(struct ieee80211_tx_control));
  2488. /* Set up first empty entry in queue's array of Tx/cmd buffers */
  2489. out_cmd = &txq->cmd[idx];
  2490. memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
  2491. memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
  2492. /*
  2493. * Set up the Tx-command (not MAC!) header.
  2494. * Store the chosen Tx queue and TFD index within the sequence field;
  2495. * after Tx, uCode's Tx response will return this value so driver can
  2496. * locate the frame within the tx queue and do post-tx processing.
  2497. */
  2498. out_cmd->hdr.cmd = REPLY_TX;
  2499. out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
  2500. INDEX_TO_SEQ(q->write_ptr)));
  2501. /* Copy MAC header from skb into command buffer */
  2502. memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len);
  2503. /*
  2504. * Use the first empty entry in this queue's command buffer array
  2505. * to contain the Tx command and MAC header concatenated together
  2506. * (payload data will be in another buffer).
  2507. * Size of this varies, due to varying MAC header length.
  2508. * If end is not dword aligned, we'll have 2 extra bytes at the end
  2509. * of the MAC header (device reads on dword boundaries).
  2510. * We'll tell device about this padding later.
  2511. */
  2512. len = priv->hw_setting.tx_cmd_len +
  2513. sizeof(struct iwl4965_cmd_header) + hdr_len;
  2514. len_org = len;
  2515. len = (len + 3) & ~3;
  2516. if (len_org != len)
  2517. len_org = 1;
  2518. else
  2519. len_org = 0;
  2520. /* Physical address of this Tx command's header (not MAC header!),
  2521. * within command buffer array. */
  2522. txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl4965_cmd) * idx +
  2523. offsetof(struct iwl4965_cmd, hdr);
  2524. /* Add buffer containing Tx command and MAC(!) header to TFD's
  2525. * first entry */
  2526. iwl4965_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
  2527. if (!(ctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT))
  2528. iwl4965_build_tx_cmd_hwcrypto(priv, ctl, out_cmd, skb, 0);
  2529. /* Set up TFD's 2nd entry to point directly to remainder of skb,
  2530. * if any (802.11 null frames have no payload). */
  2531. len = skb->len - hdr_len;
  2532. if (len) {
  2533. phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
  2534. len, PCI_DMA_TODEVICE);
  2535. iwl4965_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
  2536. }
  2537. /* Tell 4965 about any 2-byte padding after MAC header */
  2538. if (len_org)
  2539. out_cmd->cmd.tx.tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
  2540. /* Total # bytes to be transmitted */
  2541. len = (u16)skb->len;
  2542. out_cmd->cmd.tx.len = cpu_to_le16(len);
  2543. /* TODO need this for burst mode later on */
  2544. iwl4965_build_tx_cmd_basic(priv, out_cmd, ctl, hdr, unicast, sta_id);
  2545. /* set is_hcca to 0; it probably will never be implemented */
  2546. iwl4965_hw_build_tx_cmd_rate(priv, out_cmd, ctl, hdr, sta_id, 0);
  2547. iwl4965_tx_cmd(priv, out_cmd, sta_id, txcmd_phys,
  2548. hdr, hdr_len, ctl, NULL);
  2549. if (!ieee80211_get_morefrag(hdr)) {
  2550. txq->need_update = 1;
  2551. if (qc) {
  2552. u8 tid = (u8)(le16_to_cpu(*qc) & 0xf);
  2553. priv->stations[sta_id].tid[tid].seq_number = seq_number;
  2554. }
  2555. } else {
  2556. wait_write_ptr = 1;
  2557. txq->need_update = 0;
  2558. }
  2559. iwl4965_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload,
  2560. sizeof(out_cmd->cmd.tx));
  2561. iwl4965_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
  2562. ieee80211_get_hdrlen(fc));
  2563. /* Set up entry for this TFD in Tx byte-count array */
  2564. iwl4965_tx_queue_update_wr_ptr(priv, txq, len);
  2565. /* Tell device the write index *just past* this latest filled TFD */
  2566. q->write_ptr = iwl4965_queue_inc_wrap(q->write_ptr, q->n_bd);
  2567. rc = iwl4965_tx_queue_update_write_ptr(priv, txq);
  2568. spin_unlock_irqrestore(&priv->lock, flags);
  2569. if (rc)
  2570. return rc;
  2571. if ((iwl4965_queue_space(q) < q->high_mark)
  2572. && priv->mac80211_registered) {
  2573. if (wait_write_ptr) {
  2574. spin_lock_irqsave(&priv->lock, flags);
  2575. txq->need_update = 1;
  2576. iwl4965_tx_queue_update_write_ptr(priv, txq);
  2577. spin_unlock_irqrestore(&priv->lock, flags);
  2578. }
  2579. ieee80211_stop_queue(priv->hw, ctl->queue);
  2580. }
  2581. return 0;
  2582. drop_unlock:
  2583. spin_unlock_irqrestore(&priv->lock, flags);
  2584. drop:
  2585. return -1;
  2586. }
  2587. static void iwl4965_set_rate(struct iwl4965_priv *priv)
  2588. {
  2589. const struct ieee80211_hw_mode *hw = NULL;
  2590. struct ieee80211_rate *rate;
  2591. int i;
  2592. hw = iwl4965_get_hw_mode(priv, priv->phymode);
  2593. if (!hw) {
  2594. IWL_ERROR("Failed to set rate: unable to get hw mode\n");
  2595. return;
  2596. }
  2597. priv->active_rate = 0;
  2598. priv->active_rate_basic = 0;
  2599. IWL_DEBUG_RATE("Setting rates for 802.11%c\n",
  2600. hw->mode == MODE_IEEE80211A ?
  2601. 'a' : ((hw->mode == MODE_IEEE80211B) ? 'b' : 'g'));
  2602. for (i = 0; i < hw->num_rates; i++) {
  2603. rate = &(hw->rates[i]);
  2604. if ((rate->val < IWL_RATE_COUNT) &&
  2605. (rate->flags & IEEE80211_RATE_SUPPORTED)) {
  2606. IWL_DEBUG_RATE("Adding rate index %d (plcp %d)%s\n",
  2607. rate->val, iwl4965_rates[rate->val].plcp,
  2608. (rate->flags & IEEE80211_RATE_BASIC) ?
  2609. "*" : "");
  2610. priv->active_rate |= (1 << rate->val);
  2611. if (rate->flags & IEEE80211_RATE_BASIC)
  2612. priv->active_rate_basic |= (1 << rate->val);
  2613. } else
  2614. IWL_DEBUG_RATE("Not adding rate %d (plcp %d)\n",
  2615. rate->val, iwl4965_rates[rate->val].plcp);
  2616. }
  2617. IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
  2618. priv->active_rate, priv->active_rate_basic);
  2619. /*
  2620. * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
  2621. * otherwise set it to the default of all CCK rates and 6, 12, 24 for
  2622. * OFDM
  2623. */
  2624. if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
  2625. priv->staging_rxon.cck_basic_rates =
  2626. ((priv->active_rate_basic &
  2627. IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
  2628. else
  2629. priv->staging_rxon.cck_basic_rates =
  2630. (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  2631. if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
  2632. priv->staging_rxon.ofdm_basic_rates =
  2633. ((priv->active_rate_basic &
  2634. (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
  2635. IWL_FIRST_OFDM_RATE) & 0xFF;
  2636. else
  2637. priv->staging_rxon.ofdm_basic_rates =
  2638. (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  2639. }
  2640. static void iwl4965_radio_kill_sw(struct iwl4965_priv *priv, int disable_radio)
  2641. {
  2642. unsigned long flags;
  2643. if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
  2644. return;
  2645. IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
  2646. disable_radio ? "OFF" : "ON");
  2647. if (disable_radio) {
  2648. iwl4965_scan_cancel(priv);
  2649. /* FIXME: This is a workaround for AP */
  2650. if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
  2651. spin_lock_irqsave(&priv->lock, flags);
  2652. iwl4965_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2653. CSR_UCODE_SW_BIT_RFKILL);
  2654. spin_unlock_irqrestore(&priv->lock, flags);
  2655. iwl4965_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
  2656. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2657. }
  2658. return;
  2659. }
  2660. spin_lock_irqsave(&priv->lock, flags);
  2661. iwl4965_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2662. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2663. spin_unlock_irqrestore(&priv->lock, flags);
  2664. /* wake up ucode */
  2665. msleep(10);
  2666. spin_lock_irqsave(&priv->lock, flags);
  2667. iwl4965_read32(priv, CSR_UCODE_DRV_GP1);
  2668. if (!iwl4965_grab_nic_access(priv))
  2669. iwl4965_release_nic_access(priv);
  2670. spin_unlock_irqrestore(&priv->lock, flags);
  2671. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  2672. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  2673. "disabled by HW switch\n");
  2674. return;
  2675. }
  2676. queue_work(priv->workqueue, &priv->restart);
  2677. return;
  2678. }
  2679. void iwl4965_set_decrypted_flag(struct iwl4965_priv *priv, struct sk_buff *skb,
  2680. u32 decrypt_res, struct ieee80211_rx_status *stats)
  2681. {
  2682. u16 fc =
  2683. le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
  2684. if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  2685. return;
  2686. if (!(fc & IEEE80211_FCTL_PROTECTED))
  2687. return;
  2688. IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
  2689. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  2690. case RX_RES_STATUS_SEC_TYPE_TKIP:
  2691. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2692. RX_RES_STATUS_BAD_ICV_MIC)
  2693. stats->flag |= RX_FLAG_MMIC_ERROR;
  2694. case RX_RES_STATUS_SEC_TYPE_WEP:
  2695. case RX_RES_STATUS_SEC_TYPE_CCMP:
  2696. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2697. RX_RES_STATUS_DECRYPT_OK) {
  2698. IWL_DEBUG_RX("hw decrypt successfully!!!\n");
  2699. stats->flag |= RX_FLAG_DECRYPTED;
  2700. }
  2701. break;
  2702. default:
  2703. break;
  2704. }
  2705. }
  2706. void iwl4965_handle_data_packet_monitor(struct iwl4965_priv *priv,
  2707. struct iwl4965_rx_mem_buffer *rxb,
  2708. void *data, short len,
  2709. struct ieee80211_rx_status *stats,
  2710. u16 phy_flags)
  2711. {
  2712. struct iwl4965_rt_rx_hdr *iwl4965_rt;
  2713. /* First cache any information we need before we overwrite
  2714. * the information provided in the skb from the hardware */
  2715. s8 signal = stats->ssi;
  2716. s8 noise = 0;
  2717. int rate = stats->rate;
  2718. u64 tsf = stats->mactime;
  2719. __le16 phy_flags_hw = cpu_to_le16(phy_flags);
  2720. /* We received data from the HW, so stop the watchdog */
  2721. if (len > IWL_RX_BUF_SIZE - sizeof(*iwl4965_rt)) {
  2722. IWL_DEBUG_DROP("Dropping too large packet in monitor\n");
  2723. return;
  2724. }
  2725. /* copy the frame data to write after where the radiotap header goes */
  2726. iwl4965_rt = (void *)rxb->skb->data;
  2727. memmove(iwl4965_rt->payload, data, len);
  2728. iwl4965_rt->rt_hdr.it_version = PKTHDR_RADIOTAP_VERSION;
  2729. iwl4965_rt->rt_hdr.it_pad = 0; /* always good to zero */
  2730. /* total header + data */
  2731. iwl4965_rt->rt_hdr.it_len = cpu_to_le16(sizeof(*iwl4965_rt));
  2732. /* Set the size of the skb to the size of the frame */
  2733. skb_put(rxb->skb, sizeof(*iwl4965_rt) + len);
  2734. /* Big bitfield of all the fields we provide in radiotap */
  2735. iwl4965_rt->rt_hdr.it_present =
  2736. cpu_to_le32((1 << IEEE80211_RADIOTAP_TSFT) |
  2737. (1 << IEEE80211_RADIOTAP_FLAGS) |
  2738. (1 << IEEE80211_RADIOTAP_RATE) |
  2739. (1 << IEEE80211_RADIOTAP_CHANNEL) |
  2740. (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
  2741. (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) |
  2742. (1 << IEEE80211_RADIOTAP_ANTENNA));
  2743. /* Zero the flags, we'll add to them as we go */
  2744. iwl4965_rt->rt_flags = 0;
  2745. iwl4965_rt->rt_tsf = cpu_to_le64(tsf);
  2746. /* Convert to dBm */
  2747. iwl4965_rt->rt_dbmsignal = signal;
  2748. iwl4965_rt->rt_dbmnoise = noise;
  2749. /* Convert the channel frequency and set the flags */
  2750. iwl4965_rt->rt_channelMHz = cpu_to_le16(stats->freq);
  2751. if (!(phy_flags_hw & RX_RES_PHY_FLAGS_BAND_24_MSK))
  2752. iwl4965_rt->rt_chbitmask =
  2753. cpu_to_le16((IEEE80211_CHAN_OFDM | IEEE80211_CHAN_5GHZ));
  2754. else if (phy_flags_hw & RX_RES_PHY_FLAGS_MOD_CCK_MSK)
  2755. iwl4965_rt->rt_chbitmask =
  2756. cpu_to_le16((IEEE80211_CHAN_CCK | IEEE80211_CHAN_2GHZ));
  2757. else /* 802.11g */
  2758. iwl4965_rt->rt_chbitmask =
  2759. cpu_to_le16((IEEE80211_CHAN_OFDM | IEEE80211_CHAN_2GHZ));
  2760. rate = iwl4965_rate_index_from_plcp(rate);
  2761. if (rate == -1)
  2762. iwl4965_rt->rt_rate = 0;
  2763. else
  2764. iwl4965_rt->rt_rate = iwl4965_rates[rate].ieee;
  2765. /* antenna number */
  2766. iwl4965_rt->rt_antenna =
  2767. le16_to_cpu(phy_flags_hw & RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
  2768. /* set the preamble flag if we have it */
  2769. if (phy_flags_hw & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
  2770. iwl4965_rt->rt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
  2771. IWL_DEBUG_RX("Rx packet of %d bytes.\n", rxb->skb->len);
  2772. stats->flag |= RX_FLAG_RADIOTAP;
  2773. ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
  2774. rxb->skb = NULL;
  2775. }
  2776. #define IWL_PACKET_RETRY_TIME HZ
  2777. int iwl4965_is_duplicate_packet(struct iwl4965_priv *priv, struct ieee80211_hdr *header)
  2778. {
  2779. u16 sc = le16_to_cpu(header->seq_ctrl);
  2780. u16 seq = (sc & IEEE80211_SCTL_SEQ) >> 4;
  2781. u16 frag = sc & IEEE80211_SCTL_FRAG;
  2782. u16 *last_seq, *last_frag;
  2783. unsigned long *last_time;
  2784. switch (priv->iw_mode) {
  2785. case IEEE80211_IF_TYPE_IBSS:{
  2786. struct list_head *p;
  2787. struct iwl4965_ibss_seq *entry = NULL;
  2788. u8 *mac = header->addr2;
  2789. int index = mac[5] & (IWL_IBSS_MAC_HASH_SIZE - 1);
  2790. __list_for_each(p, &priv->ibss_mac_hash[index]) {
  2791. entry = list_entry(p, struct iwl4965_ibss_seq, list);
  2792. if (!compare_ether_addr(entry->mac, mac))
  2793. break;
  2794. }
  2795. if (p == &priv->ibss_mac_hash[index]) {
  2796. entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
  2797. if (!entry) {
  2798. IWL_ERROR("Cannot malloc new mac entry\n");
  2799. return 0;
  2800. }
  2801. memcpy(entry->mac, mac, ETH_ALEN);
  2802. entry->seq_num = seq;
  2803. entry->frag_num = frag;
  2804. entry->packet_time = jiffies;
  2805. list_add(&entry->list, &priv->ibss_mac_hash[index]);
  2806. return 0;
  2807. }
  2808. last_seq = &entry->seq_num;
  2809. last_frag = &entry->frag_num;
  2810. last_time = &entry->packet_time;
  2811. break;
  2812. }
  2813. case IEEE80211_IF_TYPE_STA:
  2814. last_seq = &priv->last_seq_num;
  2815. last_frag = &priv->last_frag_num;
  2816. last_time = &priv->last_packet_time;
  2817. break;
  2818. default:
  2819. return 0;
  2820. }
  2821. if ((*last_seq == seq) &&
  2822. time_after(*last_time + IWL_PACKET_RETRY_TIME, jiffies)) {
  2823. if (*last_frag == frag)
  2824. goto drop;
  2825. if (*last_frag + 1 != frag)
  2826. /* out-of-order fragment */
  2827. goto drop;
  2828. } else
  2829. *last_seq = seq;
  2830. *last_frag = frag;
  2831. *last_time = jiffies;
  2832. return 0;
  2833. drop:
  2834. return 1;
  2835. }
  2836. #ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT
  2837. #include "iwl-spectrum.h"
  2838. #define BEACON_TIME_MASK_LOW 0x00FFFFFF
  2839. #define BEACON_TIME_MASK_HIGH 0xFF000000
  2840. #define TIME_UNIT 1024
  2841. /*
  2842. * extended beacon time format
  2843. * time in usec will be changed into a 32-bit value in 8:24 format
  2844. * the high 1 byte is the beacon counts
  2845. * the lower 3 bytes is the time in usec within one beacon interval
  2846. */
  2847. static u32 iwl4965_usecs_to_beacons(u32 usec, u32 beacon_interval)
  2848. {
  2849. u32 quot;
  2850. u32 rem;
  2851. u32 interval = beacon_interval * 1024;
  2852. if (!interval || !usec)
  2853. return 0;
  2854. quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
  2855. rem = (usec % interval) & BEACON_TIME_MASK_LOW;
  2856. return (quot << 24) + rem;
  2857. }
  2858. /* base is usually what we get from ucode with each received frame,
  2859. * the same as HW timer counter counting down
  2860. */
  2861. static __le32 iwl4965_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
  2862. {
  2863. u32 base_low = base & BEACON_TIME_MASK_LOW;
  2864. u32 addon_low = addon & BEACON_TIME_MASK_LOW;
  2865. u32 interval = beacon_interval * TIME_UNIT;
  2866. u32 res = (base & BEACON_TIME_MASK_HIGH) +
  2867. (addon & BEACON_TIME_MASK_HIGH);
  2868. if (base_low > addon_low)
  2869. res += base_low - addon_low;
  2870. else if (base_low < addon_low) {
  2871. res += interval + base_low - addon_low;
  2872. res += (1 << 24);
  2873. } else
  2874. res += (1 << 24);
  2875. return cpu_to_le32(res);
  2876. }
  2877. static int iwl4965_get_measurement(struct iwl4965_priv *priv,
  2878. struct ieee80211_measurement_params *params,
  2879. u8 type)
  2880. {
  2881. struct iwl4965_spectrum_cmd spectrum;
  2882. struct iwl4965_rx_packet *res;
  2883. struct iwl4965_host_cmd cmd = {
  2884. .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
  2885. .data = (void *)&spectrum,
  2886. .meta.flags = CMD_WANT_SKB,
  2887. };
  2888. u32 add_time = le64_to_cpu(params->start_time);
  2889. int rc;
  2890. int spectrum_resp_status;
  2891. int duration = le16_to_cpu(params->duration);
  2892. if (iwl4965_is_associated(priv))
  2893. add_time =
  2894. iwl4965_usecs_to_beacons(
  2895. le64_to_cpu(params->start_time) - priv->last_tsf,
  2896. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2897. memset(&spectrum, 0, sizeof(spectrum));
  2898. spectrum.channel_count = cpu_to_le16(1);
  2899. spectrum.flags =
  2900. RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
  2901. spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
  2902. cmd.len = sizeof(spectrum);
  2903. spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
  2904. if (iwl4965_is_associated(priv))
  2905. spectrum.start_time =
  2906. iwl4965_add_beacon_time(priv->last_beacon_time,
  2907. add_time,
  2908. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2909. else
  2910. spectrum.start_time = 0;
  2911. spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
  2912. spectrum.channels[0].channel = params->channel;
  2913. spectrum.channels[0].type = type;
  2914. if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
  2915. spectrum.flags |= RXON_FLG_BAND_24G_MSK |
  2916. RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
  2917. rc = iwl4965_send_cmd_sync(priv, &cmd);
  2918. if (rc)
  2919. return rc;
  2920. res = (struct iwl4965_rx_packet *)cmd.meta.u.skb->data;
  2921. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  2922. IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n");
  2923. rc = -EIO;
  2924. }
  2925. spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
  2926. switch (spectrum_resp_status) {
  2927. case 0: /* Command will be handled */
  2928. if (res->u.spectrum.id != 0xff) {
  2929. IWL_DEBUG_INFO
  2930. ("Replaced existing measurement: %d\n",
  2931. res->u.spectrum.id);
  2932. priv->measurement_status &= ~MEASUREMENT_READY;
  2933. }
  2934. priv->measurement_status |= MEASUREMENT_ACTIVE;
  2935. rc = 0;
  2936. break;
  2937. case 1: /* Command will not be handled */
  2938. rc = -EAGAIN;
  2939. break;
  2940. }
  2941. dev_kfree_skb_any(cmd.meta.u.skb);
  2942. return rc;
  2943. }
  2944. #endif
  2945. static void iwl4965_txstatus_to_ieee(struct iwl4965_priv *priv,
  2946. struct iwl4965_tx_info *tx_sta)
  2947. {
  2948. tx_sta->status.ack_signal = 0;
  2949. tx_sta->status.excessive_retries = 0;
  2950. tx_sta->status.queue_length = 0;
  2951. tx_sta->status.queue_number = 0;
  2952. if (in_interrupt())
  2953. ieee80211_tx_status_irqsafe(priv->hw,
  2954. tx_sta->skb[0], &(tx_sta->status));
  2955. else
  2956. ieee80211_tx_status(priv->hw,
  2957. tx_sta->skb[0], &(tx_sta->status));
  2958. tx_sta->skb[0] = NULL;
  2959. }
  2960. /**
  2961. * iwl4965_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
  2962. *
  2963. * When FW advances 'R' index, all entries between old and new 'R' index
  2964. * need to be reclaimed. As result, some free space forms. If there is
  2965. * enough free space (> low mark), wake the stack that feeds us.
  2966. */
  2967. int iwl4965_tx_queue_reclaim(struct iwl4965_priv *priv, int txq_id, int index)
  2968. {
  2969. struct iwl4965_tx_queue *txq = &priv->txq[txq_id];
  2970. struct iwl4965_queue *q = &txq->q;
  2971. int nfreed = 0;
  2972. if ((index >= q->n_bd) || (x2_queue_used(q, index) == 0)) {
  2973. IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
  2974. "is out of range [0-%d] %d %d.\n", txq_id,
  2975. index, q->n_bd, q->write_ptr, q->read_ptr);
  2976. return 0;
  2977. }
  2978. for (index = iwl4965_queue_inc_wrap(index, q->n_bd);
  2979. q->read_ptr != index;
  2980. q->read_ptr = iwl4965_queue_inc_wrap(q->read_ptr, q->n_bd)) {
  2981. if (txq_id != IWL_CMD_QUEUE_NUM) {
  2982. iwl4965_txstatus_to_ieee(priv,
  2983. &(txq->txb[txq->q.read_ptr]));
  2984. iwl4965_hw_txq_free_tfd(priv, txq);
  2985. } else if (nfreed > 1) {
  2986. IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
  2987. q->write_ptr, q->read_ptr);
  2988. queue_work(priv->workqueue, &priv->restart);
  2989. }
  2990. nfreed++;
  2991. }
  2992. if (iwl4965_queue_space(q) > q->low_mark && (txq_id >= 0) &&
  2993. (txq_id != IWL_CMD_QUEUE_NUM) &&
  2994. priv->mac80211_registered)
  2995. ieee80211_wake_queue(priv->hw, txq_id);
  2996. return nfreed;
  2997. }
  2998. static int iwl4965_is_tx_success(u32 status)
  2999. {
  3000. status &= TX_STATUS_MSK;
  3001. return (status == TX_STATUS_SUCCESS)
  3002. || (status == TX_STATUS_DIRECT_DONE);
  3003. }
  3004. /******************************************************************************
  3005. *
  3006. * Generic RX handler implementations
  3007. *
  3008. ******************************************************************************/
  3009. #ifdef CONFIG_IWL4965_HT
  3010. #ifdef CONFIG_IWL4965_HT_AGG
  3011. static inline int iwl4965_get_ra_sta_id(struct iwl4965_priv *priv,
  3012. struct ieee80211_hdr *hdr)
  3013. {
  3014. if (priv->iw_mode == IEEE80211_IF_TYPE_STA)
  3015. return IWL_AP_ID;
  3016. else {
  3017. u8 *da = ieee80211_get_DA(hdr);
  3018. return iwl4965_hw_find_station(priv, da);
  3019. }
  3020. }
  3021. static struct ieee80211_hdr *iwl4965_tx_queue_get_hdr(
  3022. struct iwl4965_priv *priv, int txq_id, int idx)
  3023. {
  3024. if (priv->txq[txq_id].txb[idx].skb[0])
  3025. return (struct ieee80211_hdr *)priv->txq[txq_id].
  3026. txb[idx].skb[0]->data;
  3027. return NULL;
  3028. }
  3029. static inline u32 iwl4965_get_scd_ssn(struct iwl4965_tx_resp *tx_resp)
  3030. {
  3031. __le32 *scd_ssn = (__le32 *)((u32 *)&tx_resp->status +
  3032. tx_resp->frame_count);
  3033. return le32_to_cpu(*scd_ssn) & MAX_SN;
  3034. }
  3035. /**
  3036. * iwl4965_tx_status_reply_tx - Handle Tx rspnse for frames in aggregation queue
  3037. */
  3038. static int iwl4965_tx_status_reply_tx(struct iwl4965_priv *priv,
  3039. struct iwl4965_ht_agg *agg,
  3040. struct iwl4965_tx_resp *tx_resp,
  3041. u16 start_idx)
  3042. {
  3043. u32 status;
  3044. __le32 *frame_status = &tx_resp->status;
  3045. struct ieee80211_tx_status *tx_status = NULL;
  3046. struct ieee80211_hdr *hdr = NULL;
  3047. int i, sh;
  3048. int txq_id, idx;
  3049. u16 seq;
  3050. if (agg->wait_for_ba)
  3051. IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n");
  3052. agg->frame_count = tx_resp->frame_count;
  3053. agg->start_idx = start_idx;
  3054. agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
  3055. agg->bitmap0 = agg->bitmap1 = 0;
  3056. /* # frames attempted by Tx command */
  3057. if (agg->frame_count == 1) {
  3058. /* Only one frame was attempted; no block-ack will arrive */
  3059. struct iwl4965_tx_queue *txq ;
  3060. status = le32_to_cpu(frame_status[0]);
  3061. txq_id = agg->txq_id;
  3062. txq = &priv->txq[txq_id];
  3063. /* FIXME: code repetition */
  3064. IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d \n",
  3065. agg->frame_count, agg->start_idx);
  3066. tx_status = &(priv->txq[txq_id].txb[txq->q.read_ptr].status);
  3067. tx_status->retry_count = tx_resp->failure_frame;
  3068. tx_status->queue_number = status & 0xff;
  3069. tx_status->queue_length = tx_resp->bt_kill_count;
  3070. tx_status->queue_length |= tx_resp->failure_rts;
  3071. tx_status->flags = iwl4965_is_tx_success(status)?
  3072. IEEE80211_TX_STATUS_ACK : 0;
  3073. tx_status->control.tx_rate =
  3074. iwl4965_hw_get_rate_n_flags(tx_resp->rate_n_flags);
  3075. /* FIXME: code repetition end */
  3076. IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n",
  3077. status & 0xff, tx_resp->failure_frame);
  3078. IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n",
  3079. iwl4965_hw_get_rate_n_flags(tx_resp->rate_n_flags));
  3080. agg->wait_for_ba = 0;
  3081. } else {
  3082. /* Two or more frames were attempted; expect block-ack */
  3083. u64 bitmap = 0;
  3084. int start = agg->start_idx;
  3085. /* Construct bit-map of pending frames within Tx window */
  3086. for (i = 0; i < agg->frame_count; i++) {
  3087. u16 sc;
  3088. status = le32_to_cpu(frame_status[i]);
  3089. seq = status >> 16;
  3090. idx = SEQ_TO_INDEX(seq);
  3091. txq_id = SEQ_TO_QUEUE(seq);
  3092. if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
  3093. AGG_TX_STATE_ABORT_MSK))
  3094. continue;
  3095. IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
  3096. agg->frame_count, txq_id, idx);
  3097. hdr = iwl4965_tx_queue_get_hdr(priv, txq_id, idx);
  3098. sc = le16_to_cpu(hdr->seq_ctrl);
  3099. if (idx != (SEQ_TO_SN(sc) & 0xff)) {
  3100. IWL_ERROR("BUG_ON idx doesn't match seq control"
  3101. " idx=%d, seq_idx=%d, seq=%d\n",
  3102. idx, SEQ_TO_SN(sc),
  3103. hdr->seq_ctrl);
  3104. return -1;
  3105. }
  3106. IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n",
  3107. i, idx, SEQ_TO_SN(sc));
  3108. sh = idx - start;
  3109. if (sh > 64) {
  3110. sh = (start - idx) + 0xff;
  3111. bitmap = bitmap << sh;
  3112. sh = 0;
  3113. start = idx;
  3114. } else if (sh < -64)
  3115. sh = 0xff - (start - idx);
  3116. else if (sh < 0) {
  3117. sh = start - idx;
  3118. start = idx;
  3119. bitmap = bitmap << sh;
  3120. sh = 0;
  3121. }
  3122. bitmap |= (1 << sh);
  3123. IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%x\n",
  3124. start, (u32)(bitmap & 0xFFFFFFFF));
  3125. }
  3126. agg->bitmap0 = bitmap & 0xFFFFFFFF;
  3127. agg->bitmap1 = bitmap >> 32;
  3128. agg->start_idx = start;
  3129. agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
  3130. IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%x\n",
  3131. agg->frame_count, agg->start_idx,
  3132. agg->bitmap0);
  3133. if (bitmap)
  3134. agg->wait_for_ba = 1;
  3135. }
  3136. return 0;
  3137. }
  3138. #endif
  3139. #endif
  3140. /**
  3141. * iwl4965_rx_reply_tx - Handle standard (non-aggregation) Tx response
  3142. */
  3143. static void iwl4965_rx_reply_tx(struct iwl4965_priv *priv,
  3144. struct iwl4965_rx_mem_buffer *rxb)
  3145. {
  3146. struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
  3147. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  3148. int txq_id = SEQ_TO_QUEUE(sequence);
  3149. int index = SEQ_TO_INDEX(sequence);
  3150. struct iwl4965_tx_queue *txq = &priv->txq[txq_id];
  3151. struct ieee80211_tx_status *tx_status;
  3152. struct iwl4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
  3153. u32 status = le32_to_cpu(tx_resp->status);
  3154. #ifdef CONFIG_IWL4965_HT
  3155. #ifdef CONFIG_IWL4965_HT_AGG
  3156. int tid, sta_id;
  3157. #endif
  3158. #endif
  3159. if ((index >= txq->q.n_bd) || (x2_queue_used(&txq->q, index) == 0)) {
  3160. IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
  3161. "is out of range [0-%d] %d %d\n", txq_id,
  3162. index, txq->q.n_bd, txq->q.write_ptr,
  3163. txq->q.read_ptr);
  3164. return;
  3165. }
  3166. #ifdef CONFIG_IWL4965_HT
  3167. #ifdef CONFIG_IWL4965_HT_AGG
  3168. if (txq->sched_retry) {
  3169. const u32 scd_ssn = iwl4965_get_scd_ssn(tx_resp);
  3170. struct ieee80211_hdr *hdr =
  3171. iwl4965_tx_queue_get_hdr(priv, txq_id, index);
  3172. struct iwl4965_ht_agg *agg = NULL;
  3173. __le16 *qc = ieee80211_get_qos_ctrl(hdr);
  3174. if (qc == NULL) {
  3175. IWL_ERROR("BUG_ON qc is null!!!!\n");
  3176. return;
  3177. }
  3178. tid = le16_to_cpu(*qc) & 0xf;
  3179. sta_id = iwl4965_get_ra_sta_id(priv, hdr);
  3180. if (unlikely(sta_id == IWL_INVALID_STATION)) {
  3181. IWL_ERROR("Station not known for\n");
  3182. return;
  3183. }
  3184. agg = &priv->stations[sta_id].tid[tid].agg;
  3185. iwl4965_tx_status_reply_tx(priv, agg, tx_resp, index);
  3186. if ((tx_resp->frame_count == 1) &&
  3187. !iwl4965_is_tx_success(status)) {
  3188. /* TODO: send BAR */
  3189. }
  3190. if ((txq->q.read_ptr != (scd_ssn & 0xff))) {
  3191. index = iwl4965_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
  3192. IWL_DEBUG_TX_REPLY("Retry scheduler reclaim scd_ssn "
  3193. "%d index %d\n", scd_ssn , index);
  3194. iwl4965_tx_queue_reclaim(priv, txq_id, index);
  3195. }
  3196. } else {
  3197. #endif /* CONFIG_IWL4965_HT_AGG */
  3198. #endif /* CONFIG_IWL4965_HT */
  3199. tx_status = &(txq->txb[txq->q.read_ptr].status);
  3200. tx_status->retry_count = tx_resp->failure_frame;
  3201. tx_status->queue_number = status;
  3202. tx_status->queue_length = tx_resp->bt_kill_count;
  3203. tx_status->queue_length |= tx_resp->failure_rts;
  3204. tx_status->flags =
  3205. iwl4965_is_tx_success(status) ? IEEE80211_TX_STATUS_ACK : 0;
  3206. tx_status->control.tx_rate =
  3207. iwl4965_hw_get_rate_n_flags(tx_resp->rate_n_flags);
  3208. IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) rate_n_flags 0x%x "
  3209. "retries %d\n", txq_id, iwl4965_get_tx_fail_reason(status),
  3210. status, le32_to_cpu(tx_resp->rate_n_flags),
  3211. tx_resp->failure_frame);
  3212. IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
  3213. if (index != -1)
  3214. iwl4965_tx_queue_reclaim(priv, txq_id, index);
  3215. #ifdef CONFIG_IWL4965_HT
  3216. #ifdef CONFIG_IWL4965_HT_AGG
  3217. }
  3218. #endif /* CONFIG_IWL4965_HT_AGG */
  3219. #endif /* CONFIG_IWL4965_HT */
  3220. if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
  3221. IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
  3222. }
  3223. static void iwl4965_rx_reply_alive(struct iwl4965_priv *priv,
  3224. struct iwl4965_rx_mem_buffer *rxb)
  3225. {
  3226. struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
  3227. struct iwl4965_alive_resp *palive;
  3228. struct delayed_work *pwork;
  3229. palive = &pkt->u.alive_frame;
  3230. IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
  3231. "0x%01X 0x%01X\n",
  3232. palive->is_valid, palive->ver_type,
  3233. palive->ver_subtype);
  3234. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  3235. IWL_DEBUG_INFO("Initialization Alive received.\n");
  3236. memcpy(&priv->card_alive_init,
  3237. &pkt->u.alive_frame,
  3238. sizeof(struct iwl4965_init_alive_resp));
  3239. pwork = &priv->init_alive_start;
  3240. } else {
  3241. IWL_DEBUG_INFO("Runtime Alive received.\n");
  3242. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  3243. sizeof(struct iwl4965_alive_resp));
  3244. pwork = &priv->alive_start;
  3245. }
  3246. /* We delay the ALIVE response by 5ms to
  3247. * give the HW RF Kill time to activate... */
  3248. if (palive->is_valid == UCODE_VALID_OK)
  3249. queue_delayed_work(priv->workqueue, pwork,
  3250. msecs_to_jiffies(5));
  3251. else
  3252. IWL_WARNING("uCode did not respond OK.\n");
  3253. }
  3254. static void iwl4965_rx_reply_add_sta(struct iwl4965_priv *priv,
  3255. struct iwl4965_rx_mem_buffer *rxb)
  3256. {
  3257. struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
  3258. IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
  3259. return;
  3260. }
  3261. static void iwl4965_rx_reply_error(struct iwl4965_priv *priv,
  3262. struct iwl4965_rx_mem_buffer *rxb)
  3263. {
  3264. struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
  3265. IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) "
  3266. "seq 0x%04X ser 0x%08X\n",
  3267. le32_to_cpu(pkt->u.err_resp.error_type),
  3268. get_cmd_string(pkt->u.err_resp.cmd_id),
  3269. pkt->u.err_resp.cmd_id,
  3270. le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
  3271. le32_to_cpu(pkt->u.err_resp.error_info));
  3272. }
  3273. #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
  3274. static void iwl4965_rx_csa(struct iwl4965_priv *priv, struct iwl4965_rx_mem_buffer *rxb)
  3275. {
  3276. struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
  3277. struct iwl4965_rxon_cmd *rxon = (void *)&priv->active_rxon;
  3278. struct iwl4965_csa_notification *csa = &(pkt->u.csa_notif);
  3279. IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
  3280. le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
  3281. rxon->channel = csa->channel;
  3282. priv->staging_rxon.channel = csa->channel;
  3283. }
  3284. static void iwl4965_rx_spectrum_measure_notif(struct iwl4965_priv *priv,
  3285. struct iwl4965_rx_mem_buffer *rxb)
  3286. {
  3287. #ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT
  3288. struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
  3289. struct iwl4965_spectrum_notification *report = &(pkt->u.spectrum_notif);
  3290. if (!report->state) {
  3291. IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
  3292. "Spectrum Measure Notification: Start\n");
  3293. return;
  3294. }
  3295. memcpy(&priv->measure_report, report, sizeof(*report));
  3296. priv->measurement_status |= MEASUREMENT_READY;
  3297. #endif
  3298. }
  3299. static void iwl4965_rx_pm_sleep_notif(struct iwl4965_priv *priv,
  3300. struct iwl4965_rx_mem_buffer *rxb)
  3301. {
  3302. #ifdef CONFIG_IWL4965_DEBUG
  3303. struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
  3304. struct iwl4965_sleep_notification *sleep = &(pkt->u.sleep_notif);
  3305. IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
  3306. sleep->pm_sleep_mode, sleep->pm_wakeup_src);
  3307. #endif
  3308. }
  3309. static void iwl4965_rx_pm_debug_statistics_notif(struct iwl4965_priv *priv,
  3310. struct iwl4965_rx_mem_buffer *rxb)
  3311. {
  3312. struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
  3313. IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
  3314. "notification for %s:\n",
  3315. le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
  3316. iwl4965_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
  3317. }
  3318. static void iwl4965_bg_beacon_update(struct work_struct *work)
  3319. {
  3320. struct iwl4965_priv *priv =
  3321. container_of(work, struct iwl4965_priv, beacon_update);
  3322. struct sk_buff *beacon;
  3323. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  3324. beacon = ieee80211_beacon_get(priv->hw, priv->interface_id, NULL);
  3325. if (!beacon) {
  3326. IWL_ERROR("update beacon failed\n");
  3327. return;
  3328. }
  3329. mutex_lock(&priv->mutex);
  3330. /* new beacon skb is allocated every time; dispose previous.*/
  3331. if (priv->ibss_beacon)
  3332. dev_kfree_skb(priv->ibss_beacon);
  3333. priv->ibss_beacon = beacon;
  3334. mutex_unlock(&priv->mutex);
  3335. iwl4965_send_beacon_cmd(priv);
  3336. }
  3337. static void iwl4965_rx_beacon_notif(struct iwl4965_priv *priv,
  3338. struct iwl4965_rx_mem_buffer *rxb)
  3339. {
  3340. #ifdef CONFIG_IWL4965_DEBUG
  3341. struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
  3342. struct iwl4965_beacon_notif *beacon = &(pkt->u.beacon_status);
  3343. u8 rate = iwl4965_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
  3344. IWL_DEBUG_RX("beacon status %x retries %d iss %d "
  3345. "tsf %d %d rate %d\n",
  3346. le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
  3347. beacon->beacon_notify_hdr.failure_frame,
  3348. le32_to_cpu(beacon->ibss_mgr_status),
  3349. le32_to_cpu(beacon->high_tsf),
  3350. le32_to_cpu(beacon->low_tsf), rate);
  3351. #endif
  3352. if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
  3353. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  3354. queue_work(priv->workqueue, &priv->beacon_update);
  3355. }
  3356. /* Service response to REPLY_SCAN_CMD (0x80) */
  3357. static void iwl4965_rx_reply_scan(struct iwl4965_priv *priv,
  3358. struct iwl4965_rx_mem_buffer *rxb)
  3359. {
  3360. #ifdef CONFIG_IWL4965_DEBUG
  3361. struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
  3362. struct iwl4965_scanreq_notification *notif =
  3363. (struct iwl4965_scanreq_notification *)pkt->u.raw;
  3364. IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
  3365. #endif
  3366. }
  3367. /* Service SCAN_START_NOTIFICATION (0x82) */
  3368. static void iwl4965_rx_scan_start_notif(struct iwl4965_priv *priv,
  3369. struct iwl4965_rx_mem_buffer *rxb)
  3370. {
  3371. struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
  3372. struct iwl4965_scanstart_notification *notif =
  3373. (struct iwl4965_scanstart_notification *)pkt->u.raw;
  3374. priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
  3375. IWL_DEBUG_SCAN("Scan start: "
  3376. "%d [802.11%s] "
  3377. "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
  3378. notif->channel,
  3379. notif->band ? "bg" : "a",
  3380. notif->tsf_high,
  3381. notif->tsf_low, notif->status, notif->beacon_timer);
  3382. }
  3383. /* Service SCAN_RESULTS_NOTIFICATION (0x83) */
  3384. static void iwl4965_rx_scan_results_notif(struct iwl4965_priv *priv,
  3385. struct iwl4965_rx_mem_buffer *rxb)
  3386. {
  3387. struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
  3388. struct iwl4965_scanresults_notification *notif =
  3389. (struct iwl4965_scanresults_notification *)pkt->u.raw;
  3390. IWL_DEBUG_SCAN("Scan ch.res: "
  3391. "%d [802.11%s] "
  3392. "(TSF: 0x%08X:%08X) - %d "
  3393. "elapsed=%lu usec (%dms since last)\n",
  3394. notif->channel,
  3395. notif->band ? "bg" : "a",
  3396. le32_to_cpu(notif->tsf_high),
  3397. le32_to_cpu(notif->tsf_low),
  3398. le32_to_cpu(notif->statistics[0]),
  3399. le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
  3400. jiffies_to_msecs(elapsed_jiffies
  3401. (priv->last_scan_jiffies, jiffies)));
  3402. priv->last_scan_jiffies = jiffies;
  3403. priv->next_scan_jiffies = 0;
  3404. }
  3405. /* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
  3406. static void iwl4965_rx_scan_complete_notif(struct iwl4965_priv *priv,
  3407. struct iwl4965_rx_mem_buffer *rxb)
  3408. {
  3409. struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
  3410. struct iwl4965_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
  3411. IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
  3412. scan_notif->scanned_channels,
  3413. scan_notif->tsf_low,
  3414. scan_notif->tsf_high, scan_notif->status);
  3415. /* The HW is no longer scanning */
  3416. clear_bit(STATUS_SCAN_HW, &priv->status);
  3417. /* The scan completion notification came in, so kill that timer... */
  3418. cancel_delayed_work(&priv->scan_check);
  3419. IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
  3420. (priv->scan_bands == 2) ? "2.4" : "5.2",
  3421. jiffies_to_msecs(elapsed_jiffies
  3422. (priv->scan_pass_start, jiffies)));
  3423. /* Remove this scanned band from the list
  3424. * of pending bands to scan */
  3425. priv->scan_bands--;
  3426. /* If a request to abort was given, or the scan did not succeed
  3427. * then we reset the scan state machine and terminate,
  3428. * re-queuing another scan if one has been requested */
  3429. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  3430. IWL_DEBUG_INFO("Aborted scan completed.\n");
  3431. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  3432. } else {
  3433. /* If there are more bands on this scan pass reschedule */
  3434. if (priv->scan_bands > 0)
  3435. goto reschedule;
  3436. }
  3437. priv->last_scan_jiffies = jiffies;
  3438. priv->next_scan_jiffies = 0;
  3439. IWL_DEBUG_INFO("Setting scan to off\n");
  3440. clear_bit(STATUS_SCANNING, &priv->status);
  3441. IWL_DEBUG_INFO("Scan took %dms\n",
  3442. jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
  3443. queue_work(priv->workqueue, &priv->scan_completed);
  3444. return;
  3445. reschedule:
  3446. priv->scan_pass_start = jiffies;
  3447. queue_work(priv->workqueue, &priv->request_scan);
  3448. }
  3449. /* Handle notification from uCode that card's power state is changing
  3450. * due to software, hardware, or critical temperature RFKILL */
  3451. static void iwl4965_rx_card_state_notif(struct iwl4965_priv *priv,
  3452. struct iwl4965_rx_mem_buffer *rxb)
  3453. {
  3454. struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
  3455. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  3456. unsigned long status = priv->status;
  3457. IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
  3458. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  3459. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  3460. if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
  3461. RF_CARD_DISABLED)) {
  3462. iwl4965_write32(priv, CSR_UCODE_DRV_GP1_SET,
  3463. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  3464. if (!iwl4965_grab_nic_access(priv)) {
  3465. iwl4965_write_direct32(
  3466. priv, HBUS_TARG_MBX_C,
  3467. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  3468. iwl4965_release_nic_access(priv);
  3469. }
  3470. if (!(flags & RXON_CARD_DISABLED)) {
  3471. iwl4965_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  3472. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  3473. if (!iwl4965_grab_nic_access(priv)) {
  3474. iwl4965_write_direct32(
  3475. priv, HBUS_TARG_MBX_C,
  3476. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  3477. iwl4965_release_nic_access(priv);
  3478. }
  3479. }
  3480. if (flags & RF_CARD_DISABLED) {
  3481. iwl4965_write32(priv, CSR_UCODE_DRV_GP1_SET,
  3482. CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
  3483. iwl4965_read32(priv, CSR_UCODE_DRV_GP1);
  3484. if (!iwl4965_grab_nic_access(priv))
  3485. iwl4965_release_nic_access(priv);
  3486. }
  3487. }
  3488. if (flags & HW_CARD_DISABLED)
  3489. set_bit(STATUS_RF_KILL_HW, &priv->status);
  3490. else
  3491. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  3492. if (flags & SW_CARD_DISABLED)
  3493. set_bit(STATUS_RF_KILL_SW, &priv->status);
  3494. else
  3495. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  3496. if (!(flags & RXON_CARD_DISABLED))
  3497. iwl4965_scan_cancel(priv);
  3498. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  3499. test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
  3500. (test_bit(STATUS_RF_KILL_SW, &status) !=
  3501. test_bit(STATUS_RF_KILL_SW, &priv->status)))
  3502. queue_work(priv->workqueue, &priv->rf_kill);
  3503. else
  3504. wake_up_interruptible(&priv->wait_command_queue);
  3505. }
  3506. /**
  3507. * iwl4965_setup_rx_handlers - Initialize Rx handler callbacks
  3508. *
  3509. * Setup the RX handlers for each of the reply types sent from the uCode
  3510. * to the host.
  3511. *
  3512. * This function chains into the hardware specific files for them to setup
  3513. * any hardware specific handlers as well.
  3514. */
  3515. static void iwl4965_setup_rx_handlers(struct iwl4965_priv *priv)
  3516. {
  3517. priv->rx_handlers[REPLY_ALIVE] = iwl4965_rx_reply_alive;
  3518. priv->rx_handlers[REPLY_ADD_STA] = iwl4965_rx_reply_add_sta;
  3519. priv->rx_handlers[REPLY_ERROR] = iwl4965_rx_reply_error;
  3520. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl4965_rx_csa;
  3521. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  3522. iwl4965_rx_spectrum_measure_notif;
  3523. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl4965_rx_pm_sleep_notif;
  3524. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  3525. iwl4965_rx_pm_debug_statistics_notif;
  3526. priv->rx_handlers[BEACON_NOTIFICATION] = iwl4965_rx_beacon_notif;
  3527. /*
  3528. * The same handler is used for both the REPLY to a discrete
  3529. * statistics request from the host as well as for the periodic
  3530. * statistics notifications (after received beacons) from the uCode.
  3531. */
  3532. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl4965_hw_rx_statistics;
  3533. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl4965_hw_rx_statistics;
  3534. priv->rx_handlers[REPLY_SCAN_CMD] = iwl4965_rx_reply_scan;
  3535. priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl4965_rx_scan_start_notif;
  3536. priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
  3537. iwl4965_rx_scan_results_notif;
  3538. priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
  3539. iwl4965_rx_scan_complete_notif;
  3540. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl4965_rx_card_state_notif;
  3541. priv->rx_handlers[REPLY_TX] = iwl4965_rx_reply_tx;
  3542. /* Set up hardware specific Rx handlers */
  3543. iwl4965_hw_rx_handler_setup(priv);
  3544. }
  3545. /**
  3546. * iwl4965_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
  3547. * @rxb: Rx buffer to reclaim
  3548. *
  3549. * If an Rx buffer has an async callback associated with it the callback
  3550. * will be executed. The attached skb (if present) will only be freed
  3551. * if the callback returns 1
  3552. */
  3553. static void iwl4965_tx_cmd_complete(struct iwl4965_priv *priv,
  3554. struct iwl4965_rx_mem_buffer *rxb)
  3555. {
  3556. struct iwl4965_rx_packet *pkt = (struct iwl4965_rx_packet *)rxb->skb->data;
  3557. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  3558. int txq_id = SEQ_TO_QUEUE(sequence);
  3559. int index = SEQ_TO_INDEX(sequence);
  3560. int huge = sequence & SEQ_HUGE_FRAME;
  3561. int cmd_index;
  3562. struct iwl4965_cmd *cmd;
  3563. /* If a Tx command is being handled and it isn't in the actual
  3564. * command queue then there a command routing bug has been introduced
  3565. * in the queue management code. */
  3566. if (txq_id != IWL_CMD_QUEUE_NUM)
  3567. IWL_ERROR("Error wrong command queue %d command id 0x%X\n",
  3568. txq_id, pkt->hdr.cmd);
  3569. BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
  3570. cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
  3571. cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
  3572. /* Input error checking is done when commands are added to queue. */
  3573. if (cmd->meta.flags & CMD_WANT_SKB) {
  3574. cmd->meta.source->u.skb = rxb->skb;
  3575. rxb->skb = NULL;
  3576. } else if (cmd->meta.u.callback &&
  3577. !cmd->meta.u.callback(priv, cmd, rxb->skb))
  3578. rxb->skb = NULL;
  3579. iwl4965_tx_queue_reclaim(priv, txq_id, index);
  3580. if (!(cmd->meta.flags & CMD_ASYNC)) {
  3581. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  3582. wake_up_interruptible(&priv->wait_command_queue);
  3583. }
  3584. }
  3585. /************************** RX-FUNCTIONS ****************************/
  3586. /*
  3587. * Rx theory of operation
  3588. *
  3589. * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
  3590. * each of which point to Receive Buffers to be filled by 4965. These get
  3591. * used not only for Rx frames, but for any command response or notification
  3592. * from the 4965. The driver and 4965 manage the Rx buffers by means
  3593. * of indexes into the circular buffer.
  3594. *
  3595. * Rx Queue Indexes
  3596. * The host/firmware share two index registers for managing the Rx buffers.
  3597. *
  3598. * The READ index maps to the first position that the firmware may be writing
  3599. * to -- the driver can read up to (but not including) this position and get
  3600. * good data.
  3601. * The READ index is managed by the firmware once the card is enabled.
  3602. *
  3603. * The WRITE index maps to the last position the driver has read from -- the
  3604. * position preceding WRITE is the last slot the firmware can place a packet.
  3605. *
  3606. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  3607. * WRITE = READ.
  3608. *
  3609. * During initialization, the host sets up the READ queue position to the first
  3610. * INDEX position, and WRITE to the last (READ - 1 wrapped)
  3611. *
  3612. * When the firmware places a packet in a buffer, it will advance the READ index
  3613. * and fire the RX interrupt. The driver can then query the READ index and
  3614. * process as many packets as possible, moving the WRITE index forward as it
  3615. * resets the Rx queue buffers with new memory.
  3616. *
  3617. * The management in the driver is as follows:
  3618. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  3619. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  3620. * to replenish the iwl->rxq->rx_free.
  3621. * + In iwl4965_rx_replenish (scheduled) if 'processed' != 'read' then the
  3622. * iwl->rxq is replenished and the READ INDEX is updated (updating the
  3623. * 'processed' and 'read' driver indexes as well)
  3624. * + A received packet is processed and handed to the kernel network stack,
  3625. * detached from the iwl->rxq. The driver 'processed' index is updated.
  3626. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  3627. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  3628. * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
  3629. * were enough free buffers and RX_STALLED is set it is cleared.
  3630. *
  3631. *
  3632. * Driver sequence:
  3633. *
  3634. * iwl4965_rx_queue_alloc() Allocates rx_free
  3635. * iwl4965_rx_replenish() Replenishes rx_free list from rx_used, and calls
  3636. * iwl4965_rx_queue_restock
  3637. * iwl4965_rx_queue_restock() Moves available buffers from rx_free into Rx
  3638. * queue, updates firmware pointers, and updates
  3639. * the WRITE index. If insufficient rx_free buffers
  3640. * are available, schedules iwl4965_rx_replenish
  3641. *
  3642. * -- enable interrupts --
  3643. * ISR - iwl4965_rx() Detach iwl4965_rx_mem_buffers from pool up to the
  3644. * READ INDEX, detaching the SKB from the pool.
  3645. * Moves the packet buffer from queue to rx_used.
  3646. * Calls iwl4965_rx_queue_restock to refill any empty
  3647. * slots.
  3648. * ...
  3649. *
  3650. */
  3651. /**
  3652. * iwl4965_rx_queue_space - Return number of free slots available in queue.
  3653. */
  3654. static int iwl4965_rx_queue_space(const struct iwl4965_rx_queue *q)
  3655. {
  3656. int s = q->read - q->write;
  3657. if (s <= 0)
  3658. s += RX_QUEUE_SIZE;
  3659. /* keep some buffer to not confuse full and empty queue */
  3660. s -= 2;
  3661. if (s < 0)
  3662. s = 0;
  3663. return s;
  3664. }
  3665. /**
  3666. * iwl4965_rx_queue_update_write_ptr - Update the write pointer for the RX queue
  3667. */
  3668. int iwl4965_rx_queue_update_write_ptr(struct iwl4965_priv *priv, struct iwl4965_rx_queue *q)
  3669. {
  3670. u32 reg = 0;
  3671. int rc = 0;
  3672. unsigned long flags;
  3673. spin_lock_irqsave(&q->lock, flags);
  3674. if (q->need_update == 0)
  3675. goto exit_unlock;
  3676. /* If power-saving is in use, make sure device is awake */
  3677. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  3678. reg = iwl4965_read32(priv, CSR_UCODE_DRV_GP1);
  3679. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  3680. iwl4965_set_bit(priv, CSR_GP_CNTRL,
  3681. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  3682. goto exit_unlock;
  3683. }
  3684. rc = iwl4965_grab_nic_access(priv);
  3685. if (rc)
  3686. goto exit_unlock;
  3687. /* Device expects a multiple of 8 */
  3688. iwl4965_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
  3689. q->write & ~0x7);
  3690. iwl4965_release_nic_access(priv);
  3691. /* Else device is assumed to be awake */
  3692. } else
  3693. /* Device expects a multiple of 8 */
  3694. iwl4965_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
  3695. q->need_update = 0;
  3696. exit_unlock:
  3697. spin_unlock_irqrestore(&q->lock, flags);
  3698. return rc;
  3699. }
  3700. /**
  3701. * iwl4965_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  3702. */
  3703. static inline __le32 iwl4965_dma_addr2rbd_ptr(struct iwl4965_priv *priv,
  3704. dma_addr_t dma_addr)
  3705. {
  3706. return cpu_to_le32((u32)(dma_addr >> 8));
  3707. }
  3708. /**
  3709. * iwl4965_rx_queue_restock - refill RX queue from pre-allocated pool
  3710. *
  3711. * If there are slots in the RX queue that need to be restocked,
  3712. * and we have free pre-allocated buffers, fill the ranks as much
  3713. * as we can, pulling from rx_free.
  3714. *
  3715. * This moves the 'write' index forward to catch up with 'processed', and
  3716. * also updates the memory address in the firmware to reference the new
  3717. * target buffer.
  3718. */
  3719. static int iwl4965_rx_queue_restock(struct iwl4965_priv *priv)
  3720. {
  3721. struct iwl4965_rx_queue *rxq = &priv->rxq;
  3722. struct list_head *element;
  3723. struct iwl4965_rx_mem_buffer *rxb;
  3724. unsigned long flags;
  3725. int write, rc;
  3726. spin_lock_irqsave(&rxq->lock, flags);
  3727. write = rxq->write & ~0x7;
  3728. while ((iwl4965_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
  3729. /* Get next free Rx buffer, remove from free list */
  3730. element = rxq->rx_free.next;
  3731. rxb = list_entry(element, struct iwl4965_rx_mem_buffer, list);
  3732. list_del(element);
  3733. /* Point to Rx buffer via next RBD in circular buffer */
  3734. rxq->bd[rxq->write] = iwl4965_dma_addr2rbd_ptr(priv, rxb->dma_addr);
  3735. rxq->queue[rxq->write] = rxb;
  3736. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  3737. rxq->free_count--;
  3738. }
  3739. spin_unlock_irqrestore(&rxq->lock, flags);
  3740. /* If the pre-allocated buffer pool is dropping low, schedule to
  3741. * refill it */
  3742. if (rxq->free_count <= RX_LOW_WATERMARK)
  3743. queue_work(priv->workqueue, &priv->rx_replenish);
  3744. /* If we've added more space for the firmware to place data, tell it.
  3745. * Increment device's write pointer in multiples of 8. */
  3746. if ((write != (rxq->write & ~0x7))
  3747. || (abs(rxq->write - rxq->read) > 7)) {
  3748. spin_lock_irqsave(&rxq->lock, flags);
  3749. rxq->need_update = 1;
  3750. spin_unlock_irqrestore(&rxq->lock, flags);
  3751. rc = iwl4965_rx_queue_update_write_ptr(priv, rxq);
  3752. if (rc)
  3753. return rc;
  3754. }
  3755. return 0;
  3756. }
  3757. /**
  3758. * iwl4965_rx_replenish - Move all used packet from rx_used to rx_free
  3759. *
  3760. * When moving to rx_free an SKB is allocated for the slot.
  3761. *
  3762. * Also restock the Rx queue via iwl4965_rx_queue_restock.
  3763. * This is called as a scheduled work item (except for during initialization)
  3764. */
  3765. static void iwl4965_rx_allocate(struct iwl4965_priv *priv)
  3766. {
  3767. struct iwl4965_rx_queue *rxq = &priv->rxq;
  3768. struct list_head *element;
  3769. struct iwl4965_rx_mem_buffer *rxb;
  3770. unsigned long flags;
  3771. spin_lock_irqsave(&rxq->lock, flags);
  3772. while (!list_empty(&rxq->rx_used)) {
  3773. element = rxq->rx_used.next;
  3774. rxb = list_entry(element, struct iwl4965_rx_mem_buffer, list);
  3775. /* Alloc a new receive buffer */
  3776. rxb->skb =
  3777. alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
  3778. if (!rxb->skb) {
  3779. if (net_ratelimit())
  3780. printk(KERN_CRIT DRV_NAME
  3781. ": Can not allocate SKB buffers\n");
  3782. /* We don't reschedule replenish work here -- we will
  3783. * call the restock method and if it still needs
  3784. * more buffers it will schedule replenish */
  3785. break;
  3786. }
  3787. priv->alloc_rxb_skb++;
  3788. list_del(element);
  3789. /* Get physical address of RB/SKB */
  3790. rxb->dma_addr =
  3791. pci_map_single(priv->pci_dev, rxb->skb->data,
  3792. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3793. list_add_tail(&rxb->list, &rxq->rx_free);
  3794. rxq->free_count++;
  3795. }
  3796. spin_unlock_irqrestore(&rxq->lock, flags);
  3797. }
  3798. /*
  3799. * this should be called while priv->lock is locked
  3800. */
  3801. void __iwl4965_rx_replenish(void *data)
  3802. {
  3803. struct iwl4965_priv *priv = data;
  3804. iwl4965_rx_allocate(priv);
  3805. iwl4965_rx_queue_restock(priv);
  3806. }
  3807. void iwl4965_rx_replenish(void *data)
  3808. {
  3809. struct iwl4965_priv *priv = data;
  3810. unsigned long flags;
  3811. iwl4965_rx_allocate(priv);
  3812. spin_lock_irqsave(&priv->lock, flags);
  3813. iwl4965_rx_queue_restock(priv);
  3814. spin_unlock_irqrestore(&priv->lock, flags);
  3815. }
  3816. /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
  3817. * If an SKB has been detached, the POOL needs to have its SKB set to NULL
  3818. * This free routine walks the list of POOL entries and if SKB is set to
  3819. * non NULL it is unmapped and freed
  3820. */
  3821. static void iwl4965_rx_queue_free(struct iwl4965_priv *priv, struct iwl4965_rx_queue *rxq)
  3822. {
  3823. int i;
  3824. for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
  3825. if (rxq->pool[i].skb != NULL) {
  3826. pci_unmap_single(priv->pci_dev,
  3827. rxq->pool[i].dma_addr,
  3828. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3829. dev_kfree_skb(rxq->pool[i].skb);
  3830. }
  3831. }
  3832. pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  3833. rxq->dma_addr);
  3834. rxq->bd = NULL;
  3835. }
  3836. int iwl4965_rx_queue_alloc(struct iwl4965_priv *priv)
  3837. {
  3838. struct iwl4965_rx_queue *rxq = &priv->rxq;
  3839. struct pci_dev *dev = priv->pci_dev;
  3840. int i;
  3841. spin_lock_init(&rxq->lock);
  3842. INIT_LIST_HEAD(&rxq->rx_free);
  3843. INIT_LIST_HEAD(&rxq->rx_used);
  3844. /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
  3845. rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
  3846. if (!rxq->bd)
  3847. return -ENOMEM;
  3848. /* Fill the rx_used queue with _all_ of the Rx buffers */
  3849. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
  3850. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  3851. /* Set us so that we have processed and used all buffers, but have
  3852. * not restocked the Rx queue with fresh buffers */
  3853. rxq->read = rxq->write = 0;
  3854. rxq->free_count = 0;
  3855. rxq->need_update = 0;
  3856. return 0;
  3857. }
  3858. void iwl4965_rx_queue_reset(struct iwl4965_priv *priv, struct iwl4965_rx_queue *rxq)
  3859. {
  3860. unsigned long flags;
  3861. int i;
  3862. spin_lock_irqsave(&rxq->lock, flags);
  3863. INIT_LIST_HEAD(&rxq->rx_free);
  3864. INIT_LIST_HEAD(&rxq->rx_used);
  3865. /* Fill the rx_used queue with _all_ of the Rx buffers */
  3866. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
  3867. /* In the reset function, these buffers may have been allocated
  3868. * to an SKB, so we need to unmap and free potential storage */
  3869. if (rxq->pool[i].skb != NULL) {
  3870. pci_unmap_single(priv->pci_dev,
  3871. rxq->pool[i].dma_addr,
  3872. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3873. priv->alloc_rxb_skb--;
  3874. dev_kfree_skb(rxq->pool[i].skb);
  3875. rxq->pool[i].skb = NULL;
  3876. }
  3877. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  3878. }
  3879. /* Set us so that we have processed and used all buffers, but have
  3880. * not restocked the Rx queue with fresh buffers */
  3881. rxq->read = rxq->write = 0;
  3882. rxq->free_count = 0;
  3883. spin_unlock_irqrestore(&rxq->lock, flags);
  3884. }
  3885. /* Convert linear signal-to-noise ratio into dB */
  3886. static u8 ratio2dB[100] = {
  3887. /* 0 1 2 3 4 5 6 7 8 9 */
  3888. 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
  3889. 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
  3890. 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
  3891. 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
  3892. 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
  3893. 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
  3894. 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
  3895. 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
  3896. 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
  3897. 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
  3898. };
  3899. /* Calculates a relative dB value from a ratio of linear
  3900. * (i.e. not dB) signal levels.
  3901. * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
  3902. int iwl4965_calc_db_from_ratio(int sig_ratio)
  3903. {
  3904. /* 1000:1 or higher just report as 60 dB */
  3905. if (sig_ratio >= 1000)
  3906. return 60;
  3907. /* 100:1 or higher, divide by 10 and use table,
  3908. * add 20 dB to make up for divide by 10 */
  3909. if (sig_ratio >= 100)
  3910. return (20 + (int)ratio2dB[sig_ratio/10]);
  3911. /* We shouldn't see this */
  3912. if (sig_ratio < 1)
  3913. return 0;
  3914. /* Use table for ratios 1:1 - 99:1 */
  3915. return (int)ratio2dB[sig_ratio];
  3916. }
  3917. #define PERFECT_RSSI (-20) /* dBm */
  3918. #define WORST_RSSI (-95) /* dBm */
  3919. #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
  3920. /* Calculate an indication of rx signal quality (a percentage, not dBm!).
  3921. * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
  3922. * about formulas used below. */
  3923. int iwl4965_calc_sig_qual(int rssi_dbm, int noise_dbm)
  3924. {
  3925. int sig_qual;
  3926. int degradation = PERFECT_RSSI - rssi_dbm;
  3927. /* If we get a noise measurement, use signal-to-noise ratio (SNR)
  3928. * as indicator; formula is (signal dbm - noise dbm).
  3929. * SNR at or above 40 is a great signal (100%).
  3930. * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
  3931. * Weakest usable signal is usually 10 - 15 dB SNR. */
  3932. if (noise_dbm) {
  3933. if (rssi_dbm - noise_dbm >= 40)
  3934. return 100;
  3935. else if (rssi_dbm < noise_dbm)
  3936. return 0;
  3937. sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
  3938. /* Else use just the signal level.
  3939. * This formula is a least squares fit of data points collected and
  3940. * compared with a reference system that had a percentage (%) display
  3941. * for signal quality. */
  3942. } else
  3943. sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
  3944. (15 * RSSI_RANGE + 62 * degradation)) /
  3945. (RSSI_RANGE * RSSI_RANGE);
  3946. if (sig_qual > 100)
  3947. sig_qual = 100;
  3948. else if (sig_qual < 1)
  3949. sig_qual = 0;
  3950. return sig_qual;
  3951. }
  3952. /**
  3953. * iwl4965_rx_handle - Main entry function for receiving responses from uCode
  3954. *
  3955. * Uses the priv->rx_handlers callback function array to invoke
  3956. * the appropriate handlers, including command responses,
  3957. * frame-received notifications, and other notifications.
  3958. */
  3959. static void iwl4965_rx_handle(struct iwl4965_priv *priv)
  3960. {
  3961. struct iwl4965_rx_mem_buffer *rxb;
  3962. struct iwl4965_rx_packet *pkt;
  3963. struct iwl4965_rx_queue *rxq = &priv->rxq;
  3964. u32 r, i;
  3965. int reclaim;
  3966. unsigned long flags;
  3967. u8 fill_rx = 0;
  3968. u32 count = 0;
  3969. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  3970. * buffer that the driver may process (last buffer filled by ucode). */
  3971. r = iwl4965_hw_get_rx_read(priv);
  3972. i = rxq->read;
  3973. /* Rx interrupt, but nothing sent from uCode */
  3974. if (i == r)
  3975. IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
  3976. if (iwl4965_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
  3977. fill_rx = 1;
  3978. while (i != r) {
  3979. rxb = rxq->queue[i];
  3980. /* If an RXB doesn't have a Rx queue slot associated with it,
  3981. * then a bug has been introduced in the queue refilling
  3982. * routines -- catch it here */
  3983. BUG_ON(rxb == NULL);
  3984. rxq->queue[i] = NULL;
  3985. pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr,
  3986. IWL_RX_BUF_SIZE,
  3987. PCI_DMA_FROMDEVICE);
  3988. pkt = (struct iwl4965_rx_packet *)rxb->skb->data;
  3989. /* Reclaim a command buffer only if this packet is a response
  3990. * to a (driver-originated) command.
  3991. * If the packet (e.g. Rx frame) originated from uCode,
  3992. * there is no command buffer to reclaim.
  3993. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  3994. * but apparently a few don't get set; catch them here. */
  3995. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  3996. (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
  3997. (pkt->hdr.cmd != REPLY_4965_RX) &&
  3998. (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
  3999. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  4000. (pkt->hdr.cmd != REPLY_TX);
  4001. /* Based on type of command response or notification,
  4002. * handle those that need handling via function in
  4003. * rx_handlers table. See iwl4965_setup_rx_handlers() */
  4004. if (priv->rx_handlers[pkt->hdr.cmd]) {
  4005. IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
  4006. "r = %d, i = %d, %s, 0x%02x\n", r, i,
  4007. get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  4008. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  4009. } else {
  4010. /* No handling needed */
  4011. IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
  4012. "r %d i %d No handler needed for %s, 0x%02x\n",
  4013. r, i, get_cmd_string(pkt->hdr.cmd),
  4014. pkt->hdr.cmd);
  4015. }
  4016. if (reclaim) {
  4017. /* Invoke any callbacks, transfer the skb to caller, and
  4018. * fire off the (possibly) blocking iwl4965_send_cmd()
  4019. * as we reclaim the driver command queue */
  4020. if (rxb && rxb->skb)
  4021. iwl4965_tx_cmd_complete(priv, rxb);
  4022. else
  4023. IWL_WARNING("Claim null rxb?\n");
  4024. }
  4025. /* For now we just don't re-use anything. We can tweak this
  4026. * later to try and re-use notification packets and SKBs that
  4027. * fail to Rx correctly */
  4028. if (rxb->skb != NULL) {
  4029. priv->alloc_rxb_skb--;
  4030. dev_kfree_skb_any(rxb->skb);
  4031. rxb->skb = NULL;
  4032. }
  4033. pci_unmap_single(priv->pci_dev, rxb->dma_addr,
  4034. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  4035. spin_lock_irqsave(&rxq->lock, flags);
  4036. list_add_tail(&rxb->list, &priv->rxq.rx_used);
  4037. spin_unlock_irqrestore(&rxq->lock, flags);
  4038. i = (i + 1) & RX_QUEUE_MASK;
  4039. /* If there are a lot of unused frames,
  4040. * restock the Rx queue so ucode wont assert. */
  4041. if (fill_rx) {
  4042. count++;
  4043. if (count >= 8) {
  4044. priv->rxq.read = i;
  4045. __iwl4965_rx_replenish(priv);
  4046. count = 0;
  4047. }
  4048. }
  4049. }
  4050. /* Backtrack one entry */
  4051. priv->rxq.read = i;
  4052. iwl4965_rx_queue_restock(priv);
  4053. }
  4054. /**
  4055. * iwl4965_tx_queue_update_write_ptr - Send new write index to hardware
  4056. */
  4057. static int iwl4965_tx_queue_update_write_ptr(struct iwl4965_priv *priv,
  4058. struct iwl4965_tx_queue *txq)
  4059. {
  4060. u32 reg = 0;
  4061. int rc = 0;
  4062. int txq_id = txq->q.id;
  4063. if (txq->need_update == 0)
  4064. return rc;
  4065. /* if we're trying to save power */
  4066. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  4067. /* wake up nic if it's powered down ...
  4068. * uCode will wake up, and interrupt us again, so next
  4069. * time we'll skip this part. */
  4070. reg = iwl4965_read32(priv, CSR_UCODE_DRV_GP1);
  4071. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  4072. IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
  4073. iwl4965_set_bit(priv, CSR_GP_CNTRL,
  4074. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  4075. return rc;
  4076. }
  4077. /* restore this queue's parameters in nic hardware. */
  4078. rc = iwl4965_grab_nic_access(priv);
  4079. if (rc)
  4080. return rc;
  4081. iwl4965_write_direct32(priv, HBUS_TARG_WRPTR,
  4082. txq->q.write_ptr | (txq_id << 8));
  4083. iwl4965_release_nic_access(priv);
  4084. /* else not in power-save mode, uCode will never sleep when we're
  4085. * trying to tx (during RFKILL, we're not trying to tx). */
  4086. } else
  4087. iwl4965_write32(priv, HBUS_TARG_WRPTR,
  4088. txq->q.write_ptr | (txq_id << 8));
  4089. txq->need_update = 0;
  4090. return rc;
  4091. }
  4092. #ifdef CONFIG_IWL4965_DEBUG
  4093. static void iwl4965_print_rx_config_cmd(struct iwl4965_rxon_cmd *rxon)
  4094. {
  4095. DECLARE_MAC_BUF(mac);
  4096. IWL_DEBUG_RADIO("RX CONFIG:\n");
  4097. iwl4965_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
  4098. IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
  4099. IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
  4100. IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
  4101. le32_to_cpu(rxon->filter_flags));
  4102. IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
  4103. IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
  4104. rxon->ofdm_basic_rates);
  4105. IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
  4106. IWL_DEBUG_RADIO("u8[6] node_addr: %s\n",
  4107. print_mac(mac, rxon->node_addr));
  4108. IWL_DEBUG_RADIO("u8[6] bssid_addr: %s\n",
  4109. print_mac(mac, rxon->bssid_addr));
  4110. IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
  4111. }
  4112. #endif
  4113. static void iwl4965_enable_interrupts(struct iwl4965_priv *priv)
  4114. {
  4115. IWL_DEBUG_ISR("Enabling interrupts\n");
  4116. set_bit(STATUS_INT_ENABLED, &priv->status);
  4117. iwl4965_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
  4118. }
  4119. static inline void iwl4965_disable_interrupts(struct iwl4965_priv *priv)
  4120. {
  4121. clear_bit(STATUS_INT_ENABLED, &priv->status);
  4122. /* disable interrupts from uCode/NIC to host */
  4123. iwl4965_write32(priv, CSR_INT_MASK, 0x00000000);
  4124. /* acknowledge/clear/reset any interrupts still pending
  4125. * from uCode or flow handler (Rx/Tx DMA) */
  4126. iwl4965_write32(priv, CSR_INT, 0xffffffff);
  4127. iwl4965_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
  4128. IWL_DEBUG_ISR("Disabled interrupts\n");
  4129. }
  4130. static const char *desc_lookup(int i)
  4131. {
  4132. switch (i) {
  4133. case 1:
  4134. return "FAIL";
  4135. case 2:
  4136. return "BAD_PARAM";
  4137. case 3:
  4138. return "BAD_CHECKSUM";
  4139. case 4:
  4140. return "NMI_INTERRUPT";
  4141. case 5:
  4142. return "SYSASSERT";
  4143. case 6:
  4144. return "FATAL_ERROR";
  4145. }
  4146. return "UNKNOWN";
  4147. }
  4148. #define ERROR_START_OFFSET (1 * sizeof(u32))
  4149. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  4150. static void iwl4965_dump_nic_error_log(struct iwl4965_priv *priv)
  4151. {
  4152. u32 data2, line;
  4153. u32 desc, time, count, base, data1;
  4154. u32 blink1, blink2, ilink1, ilink2;
  4155. int rc;
  4156. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  4157. if (!iwl4965_hw_valid_rtc_data_addr(base)) {
  4158. IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
  4159. return;
  4160. }
  4161. rc = iwl4965_grab_nic_access(priv);
  4162. if (rc) {
  4163. IWL_WARNING("Can not read from adapter at this time.\n");
  4164. return;
  4165. }
  4166. count = iwl4965_read_targ_mem(priv, base);
  4167. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  4168. IWL_ERROR("Start IWL Error Log Dump:\n");
  4169. IWL_ERROR("Status: 0x%08lX, Config: %08X count: %d\n",
  4170. priv->status, priv->config, count);
  4171. }
  4172. desc = iwl4965_read_targ_mem(priv, base + 1 * sizeof(u32));
  4173. blink1 = iwl4965_read_targ_mem(priv, base + 3 * sizeof(u32));
  4174. blink2 = iwl4965_read_targ_mem(priv, base + 4 * sizeof(u32));
  4175. ilink1 = iwl4965_read_targ_mem(priv, base + 5 * sizeof(u32));
  4176. ilink2 = iwl4965_read_targ_mem(priv, base + 6 * sizeof(u32));
  4177. data1 = iwl4965_read_targ_mem(priv, base + 7 * sizeof(u32));
  4178. data2 = iwl4965_read_targ_mem(priv, base + 8 * sizeof(u32));
  4179. line = iwl4965_read_targ_mem(priv, base + 9 * sizeof(u32));
  4180. time = iwl4965_read_targ_mem(priv, base + 11 * sizeof(u32));
  4181. IWL_ERROR("Desc Time "
  4182. "data1 data2 line\n");
  4183. IWL_ERROR("%-13s (#%d) %010u 0x%08X 0x%08X %u\n",
  4184. desc_lookup(desc), desc, time, data1, data2, line);
  4185. IWL_ERROR("blink1 blink2 ilink1 ilink2\n");
  4186. IWL_ERROR("0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
  4187. ilink1, ilink2);
  4188. iwl4965_release_nic_access(priv);
  4189. }
  4190. #define EVENT_START_OFFSET (4 * sizeof(u32))
  4191. /**
  4192. * iwl4965_print_event_log - Dump error event log to syslog
  4193. *
  4194. * NOTE: Must be called with iwl4965_grab_nic_access() already obtained!
  4195. */
  4196. static void iwl4965_print_event_log(struct iwl4965_priv *priv, u32 start_idx,
  4197. u32 num_events, u32 mode)
  4198. {
  4199. u32 i;
  4200. u32 base; /* SRAM byte address of event log header */
  4201. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  4202. u32 ptr; /* SRAM byte address of log data */
  4203. u32 ev, time, data; /* event log data */
  4204. if (num_events == 0)
  4205. return;
  4206. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  4207. if (mode == 0)
  4208. event_size = 2 * sizeof(u32);
  4209. else
  4210. event_size = 3 * sizeof(u32);
  4211. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  4212. /* "time" is actually "data" for mode 0 (no timestamp).
  4213. * place event id # at far right for easier visual parsing. */
  4214. for (i = 0; i < num_events; i++) {
  4215. ev = iwl4965_read_targ_mem(priv, ptr);
  4216. ptr += sizeof(u32);
  4217. time = iwl4965_read_targ_mem(priv, ptr);
  4218. ptr += sizeof(u32);
  4219. if (mode == 0)
  4220. IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
  4221. else {
  4222. data = iwl4965_read_targ_mem(priv, ptr);
  4223. ptr += sizeof(u32);
  4224. IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
  4225. }
  4226. }
  4227. }
  4228. static void iwl4965_dump_nic_event_log(struct iwl4965_priv *priv)
  4229. {
  4230. int rc;
  4231. u32 base; /* SRAM byte address of event log header */
  4232. u32 capacity; /* event log capacity in # entries */
  4233. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  4234. u32 num_wraps; /* # times uCode wrapped to top of log */
  4235. u32 next_entry; /* index of next entry to be written by uCode */
  4236. u32 size; /* # entries that we'll print */
  4237. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  4238. if (!iwl4965_hw_valid_rtc_data_addr(base)) {
  4239. IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
  4240. return;
  4241. }
  4242. rc = iwl4965_grab_nic_access(priv);
  4243. if (rc) {
  4244. IWL_WARNING("Can not read from adapter at this time.\n");
  4245. return;
  4246. }
  4247. /* event log header */
  4248. capacity = iwl4965_read_targ_mem(priv, base);
  4249. mode = iwl4965_read_targ_mem(priv, base + (1 * sizeof(u32)));
  4250. num_wraps = iwl4965_read_targ_mem(priv, base + (2 * sizeof(u32)));
  4251. next_entry = iwl4965_read_targ_mem(priv, base + (3 * sizeof(u32)));
  4252. size = num_wraps ? capacity : next_entry;
  4253. /* bail out if nothing in log */
  4254. if (size == 0) {
  4255. IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
  4256. iwl4965_release_nic_access(priv);
  4257. return;
  4258. }
  4259. IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
  4260. size, num_wraps);
  4261. /* if uCode has wrapped back to top of log, start at the oldest entry,
  4262. * i.e the next one that uCode would fill. */
  4263. if (num_wraps)
  4264. iwl4965_print_event_log(priv, next_entry,
  4265. capacity - next_entry, mode);
  4266. /* (then/else) start at top of log */
  4267. iwl4965_print_event_log(priv, 0, next_entry, mode);
  4268. iwl4965_release_nic_access(priv);
  4269. }
  4270. /**
  4271. * iwl4965_irq_handle_error - called for HW or SW error interrupt from card
  4272. */
  4273. static void iwl4965_irq_handle_error(struct iwl4965_priv *priv)
  4274. {
  4275. /* Set the FW error flag -- cleared on iwl4965_down */
  4276. set_bit(STATUS_FW_ERROR, &priv->status);
  4277. /* Cancel currently queued command. */
  4278. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  4279. #ifdef CONFIG_IWL4965_DEBUG
  4280. if (iwl4965_debug_level & IWL_DL_FW_ERRORS) {
  4281. iwl4965_dump_nic_error_log(priv);
  4282. iwl4965_dump_nic_event_log(priv);
  4283. iwl4965_print_rx_config_cmd(&priv->staging_rxon);
  4284. }
  4285. #endif
  4286. wake_up_interruptible(&priv->wait_command_queue);
  4287. /* Keep the restart process from trying to send host
  4288. * commands by clearing the INIT status bit */
  4289. clear_bit(STATUS_READY, &priv->status);
  4290. if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  4291. IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
  4292. "Restarting adapter due to uCode error.\n");
  4293. if (iwl4965_is_associated(priv)) {
  4294. memcpy(&priv->recovery_rxon, &priv->active_rxon,
  4295. sizeof(priv->recovery_rxon));
  4296. priv->error_recovering = 1;
  4297. }
  4298. queue_work(priv->workqueue, &priv->restart);
  4299. }
  4300. }
  4301. static void iwl4965_error_recovery(struct iwl4965_priv *priv)
  4302. {
  4303. unsigned long flags;
  4304. memcpy(&priv->staging_rxon, &priv->recovery_rxon,
  4305. sizeof(priv->staging_rxon));
  4306. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4307. iwl4965_commit_rxon(priv);
  4308. iwl4965_rxon_add_station(priv, priv->bssid, 1);
  4309. spin_lock_irqsave(&priv->lock, flags);
  4310. priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
  4311. priv->error_recovering = 0;
  4312. spin_unlock_irqrestore(&priv->lock, flags);
  4313. }
  4314. static void iwl4965_irq_tasklet(struct iwl4965_priv *priv)
  4315. {
  4316. u32 inta, handled = 0;
  4317. u32 inta_fh;
  4318. unsigned long flags;
  4319. #ifdef CONFIG_IWL4965_DEBUG
  4320. u32 inta_mask;
  4321. #endif
  4322. spin_lock_irqsave(&priv->lock, flags);
  4323. /* Ack/clear/reset pending uCode interrupts.
  4324. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  4325. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  4326. inta = iwl4965_read32(priv, CSR_INT);
  4327. iwl4965_write32(priv, CSR_INT, inta);
  4328. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  4329. * Any new interrupts that happen after this, either while we're
  4330. * in this tasklet, or later, will show up in next ISR/tasklet. */
  4331. inta_fh = iwl4965_read32(priv, CSR_FH_INT_STATUS);
  4332. iwl4965_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  4333. #ifdef CONFIG_IWL4965_DEBUG
  4334. if (iwl4965_debug_level & IWL_DL_ISR) {
  4335. /* just for debug */
  4336. inta_mask = iwl4965_read32(priv, CSR_INT_MASK);
  4337. IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  4338. inta, inta_mask, inta_fh);
  4339. }
  4340. #endif
  4341. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  4342. * atomic, make sure that inta covers all the interrupts that
  4343. * we've discovered, even if FH interrupt came in just after
  4344. * reading CSR_INT. */
  4345. if (inta_fh & CSR_FH_INT_RX_MASK)
  4346. inta |= CSR_INT_BIT_FH_RX;
  4347. if (inta_fh & CSR_FH_INT_TX_MASK)
  4348. inta |= CSR_INT_BIT_FH_TX;
  4349. /* Now service all interrupt bits discovered above. */
  4350. if (inta & CSR_INT_BIT_HW_ERR) {
  4351. IWL_ERROR("Microcode HW error detected. Restarting.\n");
  4352. /* Tell the device to stop sending interrupts */
  4353. iwl4965_disable_interrupts(priv);
  4354. iwl4965_irq_handle_error(priv);
  4355. handled |= CSR_INT_BIT_HW_ERR;
  4356. spin_unlock_irqrestore(&priv->lock, flags);
  4357. return;
  4358. }
  4359. #ifdef CONFIG_IWL4965_DEBUG
  4360. if (iwl4965_debug_level & (IWL_DL_ISR)) {
  4361. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  4362. if (inta & CSR_INT_BIT_MAC_CLK_ACTV)
  4363. IWL_DEBUG_ISR("Microcode started or stopped.\n");
  4364. /* Alive notification via Rx interrupt will do the real work */
  4365. if (inta & CSR_INT_BIT_ALIVE)
  4366. IWL_DEBUG_ISR("Alive interrupt\n");
  4367. }
  4368. #endif
  4369. /* Safely ignore these bits for debug checks below */
  4370. inta &= ~(CSR_INT_BIT_MAC_CLK_ACTV | CSR_INT_BIT_ALIVE);
  4371. /* HW RF KILL switch toggled */
  4372. if (inta & CSR_INT_BIT_RF_KILL) {
  4373. int hw_rf_kill = 0;
  4374. if (!(iwl4965_read32(priv, CSR_GP_CNTRL) &
  4375. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  4376. hw_rf_kill = 1;
  4377. IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL | IWL_DL_ISR,
  4378. "RF_KILL bit toggled to %s.\n",
  4379. hw_rf_kill ? "disable radio":"enable radio");
  4380. /* Queue restart only if RF_KILL switch was set to "kill"
  4381. * when we loaded driver, and is now set to "enable".
  4382. * After we're Alive, RF_KILL gets handled by
  4383. * iwl_rx_card_state_notif() */
  4384. if (!hw_rf_kill && !test_bit(STATUS_ALIVE, &priv->status)) {
  4385. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  4386. queue_work(priv->workqueue, &priv->restart);
  4387. }
  4388. handled |= CSR_INT_BIT_RF_KILL;
  4389. }
  4390. /* Chip got too hot and stopped itself */
  4391. if (inta & CSR_INT_BIT_CT_KILL) {
  4392. IWL_ERROR("Microcode CT kill error detected.\n");
  4393. handled |= CSR_INT_BIT_CT_KILL;
  4394. }
  4395. /* Error detected by uCode */
  4396. if (inta & CSR_INT_BIT_SW_ERR) {
  4397. IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n",
  4398. inta);
  4399. iwl4965_irq_handle_error(priv);
  4400. handled |= CSR_INT_BIT_SW_ERR;
  4401. }
  4402. /* uCode wakes up after power-down sleep */
  4403. if (inta & CSR_INT_BIT_WAKEUP) {
  4404. IWL_DEBUG_ISR("Wakeup interrupt\n");
  4405. iwl4965_rx_queue_update_write_ptr(priv, &priv->rxq);
  4406. iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[0]);
  4407. iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[1]);
  4408. iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[2]);
  4409. iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[3]);
  4410. iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[4]);
  4411. iwl4965_tx_queue_update_write_ptr(priv, &priv->txq[5]);
  4412. handled |= CSR_INT_BIT_WAKEUP;
  4413. }
  4414. /* All uCode command responses, including Tx command responses,
  4415. * Rx "responses" (frame-received notification), and other
  4416. * notifications from uCode come through here*/
  4417. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  4418. iwl4965_rx_handle(priv);
  4419. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  4420. }
  4421. if (inta & CSR_INT_BIT_FH_TX) {
  4422. IWL_DEBUG_ISR("Tx interrupt\n");
  4423. handled |= CSR_INT_BIT_FH_TX;
  4424. }
  4425. if (inta & ~handled)
  4426. IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
  4427. if (inta & ~CSR_INI_SET_MASK) {
  4428. IWL_WARNING("Disabled INTA bits 0x%08x were pending\n",
  4429. inta & ~CSR_INI_SET_MASK);
  4430. IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh);
  4431. }
  4432. /* Re-enable all interrupts */
  4433. iwl4965_enable_interrupts(priv);
  4434. #ifdef CONFIG_IWL4965_DEBUG
  4435. if (iwl4965_debug_level & (IWL_DL_ISR)) {
  4436. inta = iwl4965_read32(priv, CSR_INT);
  4437. inta_mask = iwl4965_read32(priv, CSR_INT_MASK);
  4438. inta_fh = iwl4965_read32(priv, CSR_FH_INT_STATUS);
  4439. IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  4440. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  4441. }
  4442. #endif
  4443. spin_unlock_irqrestore(&priv->lock, flags);
  4444. }
  4445. static irqreturn_t iwl4965_isr(int irq, void *data)
  4446. {
  4447. struct iwl4965_priv *priv = data;
  4448. u32 inta, inta_mask;
  4449. u32 inta_fh;
  4450. if (!priv)
  4451. return IRQ_NONE;
  4452. spin_lock(&priv->lock);
  4453. /* Disable (but don't clear!) interrupts here to avoid
  4454. * back-to-back ISRs and sporadic interrupts from our NIC.
  4455. * If we have something to service, the tasklet will re-enable ints.
  4456. * If we *don't* have something, we'll re-enable before leaving here. */
  4457. inta_mask = iwl4965_read32(priv, CSR_INT_MASK); /* just for debug */
  4458. iwl4965_write32(priv, CSR_INT_MASK, 0x00000000);
  4459. /* Discover which interrupts are active/pending */
  4460. inta = iwl4965_read32(priv, CSR_INT);
  4461. inta_fh = iwl4965_read32(priv, CSR_FH_INT_STATUS);
  4462. /* Ignore interrupt if there's nothing in NIC to service.
  4463. * This may be due to IRQ shared with another device,
  4464. * or due to sporadic interrupts thrown from our NIC. */
  4465. if (!inta && !inta_fh) {
  4466. IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
  4467. goto none;
  4468. }
  4469. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  4470. /* Hardware disappeared. It might have already raised
  4471. * an interrupt */
  4472. IWL_WARNING("HARDWARE GONE?? INTA == 0x%080x\n", inta);
  4473. goto unplugged;
  4474. }
  4475. IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  4476. inta, inta_mask, inta_fh);
  4477. /* iwl4965_irq_tasklet() will service interrupts and re-enable them */
  4478. tasklet_schedule(&priv->irq_tasklet);
  4479. unplugged:
  4480. spin_unlock(&priv->lock);
  4481. return IRQ_HANDLED;
  4482. none:
  4483. /* re-enable interrupts here since we don't have anything to service. */
  4484. iwl4965_enable_interrupts(priv);
  4485. spin_unlock(&priv->lock);
  4486. return IRQ_NONE;
  4487. }
  4488. /************************** EEPROM BANDS ****************************
  4489. *
  4490. * The iwl4965_eeprom_band definitions below provide the mapping from the
  4491. * EEPROM contents to the specific channel number supported for each
  4492. * band.
  4493. *
  4494. * For example, iwl4965_priv->eeprom.band_3_channels[4] from the band_3
  4495. * definition below maps to physical channel 42 in the 5.2GHz spectrum.
  4496. * The specific geography and calibration information for that channel
  4497. * is contained in the eeprom map itself.
  4498. *
  4499. * During init, we copy the eeprom information and channel map
  4500. * information into priv->channel_info_24/52 and priv->channel_map_24/52
  4501. *
  4502. * channel_map_24/52 provides the index in the channel_info array for a
  4503. * given channel. We have to have two separate maps as there is channel
  4504. * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
  4505. * band_2
  4506. *
  4507. * A value of 0xff stored in the channel_map indicates that the channel
  4508. * is not supported by the hardware at all.
  4509. *
  4510. * A value of 0xfe in the channel_map indicates that the channel is not
  4511. * valid for Tx with the current hardware. This means that
  4512. * while the system can tune and receive on a given channel, it may not
  4513. * be able to associate or transmit any frames on that
  4514. * channel. There is no corresponding channel information for that
  4515. * entry.
  4516. *
  4517. *********************************************************************/
  4518. /* 2.4 GHz */
  4519. static const u8 iwl4965_eeprom_band_1[14] = {
  4520. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
  4521. };
  4522. /* 5.2 GHz bands */
  4523. static const u8 iwl4965_eeprom_band_2[] = { /* 4915-5080MHz */
  4524. 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
  4525. };
  4526. static const u8 iwl4965_eeprom_band_3[] = { /* 5170-5320MHz */
  4527. 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
  4528. };
  4529. static const u8 iwl4965_eeprom_band_4[] = { /* 5500-5700MHz */
  4530. 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
  4531. };
  4532. static const u8 iwl4965_eeprom_band_5[] = { /* 5725-5825MHz */
  4533. 145, 149, 153, 157, 161, 165
  4534. };
  4535. static u8 iwl4965_eeprom_band_6[] = { /* 2.4 FAT channel */
  4536. 1, 2, 3, 4, 5, 6, 7
  4537. };
  4538. static u8 iwl4965_eeprom_band_7[] = { /* 5.2 FAT channel */
  4539. 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157
  4540. };
  4541. static void iwl4965_init_band_reference(const struct iwl4965_priv *priv,
  4542. int band,
  4543. int *eeprom_ch_count,
  4544. const struct iwl4965_eeprom_channel
  4545. **eeprom_ch_info,
  4546. const u8 **eeprom_ch_index)
  4547. {
  4548. switch (band) {
  4549. case 1: /* 2.4GHz band */
  4550. *eeprom_ch_count = ARRAY_SIZE(iwl4965_eeprom_band_1);
  4551. *eeprom_ch_info = priv->eeprom.band_1_channels;
  4552. *eeprom_ch_index = iwl4965_eeprom_band_1;
  4553. break;
  4554. case 2: /* 4.9GHz band */
  4555. *eeprom_ch_count = ARRAY_SIZE(iwl4965_eeprom_band_2);
  4556. *eeprom_ch_info = priv->eeprom.band_2_channels;
  4557. *eeprom_ch_index = iwl4965_eeprom_band_2;
  4558. break;
  4559. case 3: /* 5.2GHz band */
  4560. *eeprom_ch_count = ARRAY_SIZE(iwl4965_eeprom_band_3);
  4561. *eeprom_ch_info = priv->eeprom.band_3_channels;
  4562. *eeprom_ch_index = iwl4965_eeprom_band_3;
  4563. break;
  4564. case 4: /* 5.5GHz band */
  4565. *eeprom_ch_count = ARRAY_SIZE(iwl4965_eeprom_band_4);
  4566. *eeprom_ch_info = priv->eeprom.band_4_channels;
  4567. *eeprom_ch_index = iwl4965_eeprom_band_4;
  4568. break;
  4569. case 5: /* 5.7GHz band */
  4570. *eeprom_ch_count = ARRAY_SIZE(iwl4965_eeprom_band_5);
  4571. *eeprom_ch_info = priv->eeprom.band_5_channels;
  4572. *eeprom_ch_index = iwl4965_eeprom_band_5;
  4573. break;
  4574. case 6: /* 2.4GHz FAT channels */
  4575. *eeprom_ch_count = ARRAY_SIZE(iwl4965_eeprom_band_6);
  4576. *eeprom_ch_info = priv->eeprom.band_24_channels;
  4577. *eeprom_ch_index = iwl4965_eeprom_band_6;
  4578. break;
  4579. case 7: /* 5 GHz FAT channels */
  4580. *eeprom_ch_count = ARRAY_SIZE(iwl4965_eeprom_band_7);
  4581. *eeprom_ch_info = priv->eeprom.band_52_channels;
  4582. *eeprom_ch_index = iwl4965_eeprom_band_7;
  4583. break;
  4584. default:
  4585. BUG();
  4586. return;
  4587. }
  4588. }
  4589. /**
  4590. * iwl4965_get_channel_info - Find driver's private channel info
  4591. *
  4592. * Based on band and channel number.
  4593. */
  4594. const struct iwl4965_channel_info *iwl4965_get_channel_info(const struct iwl4965_priv *priv,
  4595. int phymode, u16 channel)
  4596. {
  4597. int i;
  4598. switch (phymode) {
  4599. case MODE_IEEE80211A:
  4600. for (i = 14; i < priv->channel_count; i++) {
  4601. if (priv->channel_info[i].channel == channel)
  4602. return &priv->channel_info[i];
  4603. }
  4604. break;
  4605. case MODE_IEEE80211B:
  4606. case MODE_IEEE80211G:
  4607. if (channel >= 1 && channel <= 14)
  4608. return &priv->channel_info[channel - 1];
  4609. break;
  4610. }
  4611. return NULL;
  4612. }
  4613. #define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
  4614. ? # x " " : "")
  4615. /**
  4616. * iwl4965_init_channel_map - Set up driver's info for all possible channels
  4617. */
  4618. static int iwl4965_init_channel_map(struct iwl4965_priv *priv)
  4619. {
  4620. int eeprom_ch_count = 0;
  4621. const u8 *eeprom_ch_index = NULL;
  4622. const struct iwl4965_eeprom_channel *eeprom_ch_info = NULL;
  4623. int band, ch;
  4624. struct iwl4965_channel_info *ch_info;
  4625. if (priv->channel_count) {
  4626. IWL_DEBUG_INFO("Channel map already initialized.\n");
  4627. return 0;
  4628. }
  4629. if (priv->eeprom.version < 0x2f) {
  4630. IWL_WARNING("Unsupported EEPROM version: 0x%04X\n",
  4631. priv->eeprom.version);
  4632. return -EINVAL;
  4633. }
  4634. IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
  4635. priv->channel_count =
  4636. ARRAY_SIZE(iwl4965_eeprom_band_1) +
  4637. ARRAY_SIZE(iwl4965_eeprom_band_2) +
  4638. ARRAY_SIZE(iwl4965_eeprom_band_3) +
  4639. ARRAY_SIZE(iwl4965_eeprom_band_4) +
  4640. ARRAY_SIZE(iwl4965_eeprom_band_5);
  4641. IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
  4642. priv->channel_info = kzalloc(sizeof(struct iwl4965_channel_info) *
  4643. priv->channel_count, GFP_KERNEL);
  4644. if (!priv->channel_info) {
  4645. IWL_ERROR("Could not allocate channel_info\n");
  4646. priv->channel_count = 0;
  4647. return -ENOMEM;
  4648. }
  4649. ch_info = priv->channel_info;
  4650. /* Loop through the 5 EEPROM bands adding them in order to the
  4651. * channel map we maintain (that contains additional information than
  4652. * what just in the EEPROM) */
  4653. for (band = 1; band <= 5; band++) {
  4654. iwl4965_init_band_reference(priv, band, &eeprom_ch_count,
  4655. &eeprom_ch_info, &eeprom_ch_index);
  4656. /* Loop through each band adding each of the channels */
  4657. for (ch = 0; ch < eeprom_ch_count; ch++) {
  4658. ch_info->channel = eeprom_ch_index[ch];
  4659. ch_info->phymode = (band == 1) ? MODE_IEEE80211B :
  4660. MODE_IEEE80211A;
  4661. /* permanently store EEPROM's channel regulatory flags
  4662. * and max power in channel info database. */
  4663. ch_info->eeprom = eeprom_ch_info[ch];
  4664. /* Copy the run-time flags so they are there even on
  4665. * invalid channels */
  4666. ch_info->flags = eeprom_ch_info[ch].flags;
  4667. if (!(is_channel_valid(ch_info))) {
  4668. IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
  4669. "No traffic\n",
  4670. ch_info->channel,
  4671. ch_info->flags,
  4672. is_channel_a_band(ch_info) ?
  4673. "5.2" : "2.4");
  4674. ch_info++;
  4675. continue;
  4676. }
  4677. /* Initialize regulatory-based run-time data */
  4678. ch_info->max_power_avg = ch_info->curr_txpow =
  4679. eeprom_ch_info[ch].max_power_avg;
  4680. ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
  4681. ch_info->min_power = 0;
  4682. IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
  4683. " %ddBm): Ad-Hoc %ssupported\n",
  4684. ch_info->channel,
  4685. is_channel_a_band(ch_info) ?
  4686. "5.2" : "2.4",
  4687. CHECK_AND_PRINT(IBSS),
  4688. CHECK_AND_PRINT(ACTIVE),
  4689. CHECK_AND_PRINT(RADAR),
  4690. CHECK_AND_PRINT(WIDE),
  4691. CHECK_AND_PRINT(NARROW),
  4692. CHECK_AND_PRINT(DFS),
  4693. eeprom_ch_info[ch].flags,
  4694. eeprom_ch_info[ch].max_power_avg,
  4695. ((eeprom_ch_info[ch].
  4696. flags & EEPROM_CHANNEL_IBSS)
  4697. && !(eeprom_ch_info[ch].
  4698. flags & EEPROM_CHANNEL_RADAR))
  4699. ? "" : "not ");
  4700. /* Set the user_txpower_limit to the highest power
  4701. * supported by any channel */
  4702. if (eeprom_ch_info[ch].max_power_avg >
  4703. priv->user_txpower_limit)
  4704. priv->user_txpower_limit =
  4705. eeprom_ch_info[ch].max_power_avg;
  4706. ch_info++;
  4707. }
  4708. }
  4709. /* Two additional EEPROM bands for 2.4 and 5 GHz FAT channels */
  4710. for (band = 6; band <= 7; band++) {
  4711. int phymode;
  4712. u8 fat_extension_chan;
  4713. iwl4965_init_band_reference(priv, band, &eeprom_ch_count,
  4714. &eeprom_ch_info, &eeprom_ch_index);
  4715. /* EEPROM band 6 is 2.4, band 7 is 5 GHz */
  4716. phymode = (band == 6) ? MODE_IEEE80211B : MODE_IEEE80211A;
  4717. /* Loop through each band adding each of the channels */
  4718. for (ch = 0; ch < eeprom_ch_count; ch++) {
  4719. if ((band == 6) &&
  4720. ((eeprom_ch_index[ch] == 5) ||
  4721. (eeprom_ch_index[ch] == 6) ||
  4722. (eeprom_ch_index[ch] == 7)))
  4723. fat_extension_chan = HT_IE_EXT_CHANNEL_MAX;
  4724. else
  4725. fat_extension_chan = HT_IE_EXT_CHANNEL_ABOVE;
  4726. /* Set up driver's info for lower half */
  4727. iwl4965_set_fat_chan_info(priv, phymode,
  4728. eeprom_ch_index[ch],
  4729. &(eeprom_ch_info[ch]),
  4730. fat_extension_chan);
  4731. /* Set up driver's info for upper half */
  4732. iwl4965_set_fat_chan_info(priv, phymode,
  4733. (eeprom_ch_index[ch] + 4),
  4734. &(eeprom_ch_info[ch]),
  4735. HT_IE_EXT_CHANNEL_BELOW);
  4736. }
  4737. }
  4738. return 0;
  4739. }
  4740. /* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
  4741. * sending probe req. This should be set long enough to hear probe responses
  4742. * from more than one AP. */
  4743. #define IWL_ACTIVE_DWELL_TIME_24 (20) /* all times in msec */
  4744. #define IWL_ACTIVE_DWELL_TIME_52 (10)
  4745. /* For faster active scanning, scan will move to the next channel if fewer than
  4746. * PLCP_QUIET_THRESH packets are heard on this channel within
  4747. * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
  4748. * time if it's a quiet channel (nothing responded to our probe, and there's
  4749. * no other traffic).
  4750. * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
  4751. #define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
  4752. #define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(5) /* msec */
  4753. /* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
  4754. * Must be set longer than active dwell time.
  4755. * For the most reliable scan, set > AP beacon interval (typically 100msec). */
  4756. #define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
  4757. #define IWL_PASSIVE_DWELL_TIME_52 (10)
  4758. #define IWL_PASSIVE_DWELL_BASE (100)
  4759. #define IWL_CHANNEL_TUNE_TIME 5
  4760. static inline u16 iwl4965_get_active_dwell_time(struct iwl4965_priv *priv, int phymode)
  4761. {
  4762. if (phymode == MODE_IEEE80211A)
  4763. return IWL_ACTIVE_DWELL_TIME_52;
  4764. else
  4765. return IWL_ACTIVE_DWELL_TIME_24;
  4766. }
  4767. static u16 iwl4965_get_passive_dwell_time(struct iwl4965_priv *priv, int phymode)
  4768. {
  4769. u16 active = iwl4965_get_active_dwell_time(priv, phymode);
  4770. u16 passive = (phymode != MODE_IEEE80211A) ?
  4771. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
  4772. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
  4773. if (iwl4965_is_associated(priv)) {
  4774. /* If we're associated, we clamp the maximum passive
  4775. * dwell time to be 98% of the beacon interval (minus
  4776. * 2 * channel tune time) */
  4777. passive = priv->beacon_int;
  4778. if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
  4779. passive = IWL_PASSIVE_DWELL_BASE;
  4780. passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
  4781. }
  4782. if (passive <= active)
  4783. passive = active + 1;
  4784. return passive;
  4785. }
  4786. static int iwl4965_get_channels_for_scan(struct iwl4965_priv *priv, int phymode,
  4787. u8 is_active, u8 direct_mask,
  4788. struct iwl4965_scan_channel *scan_ch)
  4789. {
  4790. const struct ieee80211_channel *channels = NULL;
  4791. const struct ieee80211_hw_mode *hw_mode;
  4792. const struct iwl4965_channel_info *ch_info;
  4793. u16 passive_dwell = 0;
  4794. u16 active_dwell = 0;
  4795. int added, i;
  4796. hw_mode = iwl4965_get_hw_mode(priv, phymode);
  4797. if (!hw_mode)
  4798. return 0;
  4799. channels = hw_mode->channels;
  4800. active_dwell = iwl4965_get_active_dwell_time(priv, phymode);
  4801. passive_dwell = iwl4965_get_passive_dwell_time(priv, phymode);
  4802. for (i = 0, added = 0; i < hw_mode->num_channels; i++) {
  4803. if (channels[i].chan ==
  4804. le16_to_cpu(priv->active_rxon.channel)) {
  4805. if (iwl4965_is_associated(priv)) {
  4806. IWL_DEBUG_SCAN
  4807. ("Skipping current channel %d\n",
  4808. le16_to_cpu(priv->active_rxon.channel));
  4809. continue;
  4810. }
  4811. } else if (priv->only_active_channel)
  4812. continue;
  4813. scan_ch->channel = channels[i].chan;
  4814. ch_info = iwl4965_get_channel_info(priv, phymode,
  4815. scan_ch->channel);
  4816. if (!is_channel_valid(ch_info)) {
  4817. IWL_DEBUG_SCAN("Channel %d is INVALID for this SKU.\n",
  4818. scan_ch->channel);
  4819. continue;
  4820. }
  4821. if (!is_active || is_channel_passive(ch_info) ||
  4822. !(channels[i].flag & IEEE80211_CHAN_W_ACTIVE_SCAN))
  4823. scan_ch->type = 0; /* passive */
  4824. else
  4825. scan_ch->type = 1; /* active */
  4826. if (scan_ch->type & 1)
  4827. scan_ch->type |= (direct_mask << 1);
  4828. if (is_channel_narrow(ch_info))
  4829. scan_ch->type |= (1 << 7);
  4830. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  4831. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  4832. /* Set txpower levels to defaults */
  4833. scan_ch->tpc.dsp_atten = 110;
  4834. /* scan_pwr_info->tpc.dsp_atten; */
  4835. /*scan_pwr_info->tpc.tx_gain; */
  4836. if (phymode == MODE_IEEE80211A)
  4837. scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
  4838. else {
  4839. scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
  4840. /* NOTE: if we were doing 6Mb OFDM for scans we'd use
  4841. * power level:
  4842. * scan_ch->tpc.tx_gain = ((1<<5) | (2 << 3)) | 3;
  4843. */
  4844. }
  4845. IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
  4846. scan_ch->channel,
  4847. (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
  4848. (scan_ch->type & 1) ?
  4849. active_dwell : passive_dwell);
  4850. scan_ch++;
  4851. added++;
  4852. }
  4853. IWL_DEBUG_SCAN("total channels to scan %d \n", added);
  4854. return added;
  4855. }
  4856. static void iwl4965_reset_channel_flag(struct iwl4965_priv *priv)
  4857. {
  4858. int i, j;
  4859. for (i = 0; i < 3; i++) {
  4860. struct ieee80211_hw_mode *hw_mode = (void *)&priv->modes[i];
  4861. for (j = 0; j < hw_mode->num_channels; j++)
  4862. hw_mode->channels[j].flag = hw_mode->channels[j].val;
  4863. }
  4864. }
  4865. static void iwl4965_init_hw_rates(struct iwl4965_priv *priv,
  4866. struct ieee80211_rate *rates)
  4867. {
  4868. int i;
  4869. for (i = 0; i < IWL_RATE_COUNT; i++) {
  4870. rates[i].rate = iwl4965_rates[i].ieee * 5;
  4871. rates[i].val = i; /* Rate scaling will work on indexes */
  4872. rates[i].val2 = i;
  4873. rates[i].flags = IEEE80211_RATE_SUPPORTED;
  4874. /* Only OFDM have the bits-per-symbol set */
  4875. if ((i <= IWL_LAST_OFDM_RATE) && (i >= IWL_FIRST_OFDM_RATE))
  4876. rates[i].flags |= IEEE80211_RATE_OFDM;
  4877. else {
  4878. /*
  4879. * If CCK 1M then set rate flag to CCK else CCK_2
  4880. * which is CCK | PREAMBLE2
  4881. */
  4882. rates[i].flags |= (iwl4965_rates[i].plcp == 10) ?
  4883. IEEE80211_RATE_CCK : IEEE80211_RATE_CCK_2;
  4884. }
  4885. /* Set up which ones are basic rates... */
  4886. if (IWL_BASIC_RATES_MASK & (1 << i))
  4887. rates[i].flags |= IEEE80211_RATE_BASIC;
  4888. }
  4889. }
  4890. /**
  4891. * iwl4965_init_geos - Initialize mac80211's geo/channel info based from eeprom
  4892. */
  4893. static int iwl4965_init_geos(struct iwl4965_priv *priv)
  4894. {
  4895. struct iwl4965_channel_info *ch;
  4896. struct ieee80211_hw_mode *modes;
  4897. struct ieee80211_channel *channels;
  4898. struct ieee80211_channel *geo_ch;
  4899. struct ieee80211_rate *rates;
  4900. int i = 0;
  4901. enum {
  4902. A = 0,
  4903. B = 1,
  4904. G = 2,
  4905. A_11N = 3,
  4906. G_11N = 4,
  4907. };
  4908. int mode_count = 5;
  4909. if (priv->modes) {
  4910. IWL_DEBUG_INFO("Geography modes already initialized.\n");
  4911. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4912. return 0;
  4913. }
  4914. modes = kzalloc(sizeof(struct ieee80211_hw_mode) * mode_count,
  4915. GFP_KERNEL);
  4916. if (!modes)
  4917. return -ENOMEM;
  4918. channels = kzalloc(sizeof(struct ieee80211_channel) *
  4919. priv->channel_count, GFP_KERNEL);
  4920. if (!channels) {
  4921. kfree(modes);
  4922. return -ENOMEM;
  4923. }
  4924. rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_MAX_RATES + 1)),
  4925. GFP_KERNEL);
  4926. if (!rates) {
  4927. kfree(modes);
  4928. kfree(channels);
  4929. return -ENOMEM;
  4930. }
  4931. /* 0 = 802.11a
  4932. * 1 = 802.11b
  4933. * 2 = 802.11g
  4934. */
  4935. /* 5.2GHz channels start after the 2.4GHz channels */
  4936. modes[A].mode = MODE_IEEE80211A;
  4937. modes[A].channels = &channels[ARRAY_SIZE(iwl4965_eeprom_band_1)];
  4938. modes[A].rates = rates;
  4939. modes[A].num_rates = 8; /* just OFDM */
  4940. modes[A].rates = &rates[4];
  4941. modes[A].num_channels = 0;
  4942. modes[B].mode = MODE_IEEE80211B;
  4943. modes[B].channels = channels;
  4944. modes[B].rates = rates;
  4945. modes[B].num_rates = 4; /* just CCK */
  4946. modes[B].num_channels = 0;
  4947. modes[G].mode = MODE_IEEE80211G;
  4948. modes[G].channels = channels;
  4949. modes[G].rates = rates;
  4950. modes[G].num_rates = 12; /* OFDM & CCK */
  4951. modes[G].num_channels = 0;
  4952. modes[G_11N].mode = MODE_IEEE80211G;
  4953. modes[G_11N].channels = channels;
  4954. modes[G_11N].num_rates = 13; /* OFDM & CCK */
  4955. modes[G_11N].rates = rates;
  4956. modes[G_11N].num_channels = 0;
  4957. modes[A_11N].mode = MODE_IEEE80211A;
  4958. modes[A_11N].channels = &channels[ARRAY_SIZE(iwl4965_eeprom_band_1)];
  4959. modes[A_11N].rates = &rates[4];
  4960. modes[A_11N].num_rates = 9; /* just OFDM */
  4961. modes[A_11N].num_channels = 0;
  4962. priv->ieee_channels = channels;
  4963. priv->ieee_rates = rates;
  4964. iwl4965_init_hw_rates(priv, rates);
  4965. for (i = 0, geo_ch = channels; i < priv->channel_count; i++) {
  4966. ch = &priv->channel_info[i];
  4967. if (!is_channel_valid(ch)) {
  4968. IWL_DEBUG_INFO("Channel %d [%sGHz] is restricted -- "
  4969. "skipping.\n",
  4970. ch->channel, is_channel_a_band(ch) ?
  4971. "5.2" : "2.4");
  4972. continue;
  4973. }
  4974. if (is_channel_a_band(ch)) {
  4975. geo_ch = &modes[A].channels[modes[A].num_channels++];
  4976. modes[A_11N].num_channels++;
  4977. } else {
  4978. geo_ch = &modes[B].channels[modes[B].num_channels++];
  4979. modes[G].num_channels++;
  4980. modes[G_11N].num_channels++;
  4981. }
  4982. geo_ch->freq = ieee80211chan2mhz(ch->channel);
  4983. geo_ch->chan = ch->channel;
  4984. geo_ch->power_level = ch->max_power_avg;
  4985. geo_ch->antenna_max = 0xff;
  4986. if (is_channel_valid(ch)) {
  4987. geo_ch->flag = IEEE80211_CHAN_W_SCAN;
  4988. if (ch->flags & EEPROM_CHANNEL_IBSS)
  4989. geo_ch->flag |= IEEE80211_CHAN_W_IBSS;
  4990. if (ch->flags & EEPROM_CHANNEL_ACTIVE)
  4991. geo_ch->flag |= IEEE80211_CHAN_W_ACTIVE_SCAN;
  4992. if (ch->flags & EEPROM_CHANNEL_RADAR)
  4993. geo_ch->flag |= IEEE80211_CHAN_W_RADAR_DETECT;
  4994. if (ch->max_power_avg > priv->max_channel_txpower_limit)
  4995. priv->max_channel_txpower_limit =
  4996. ch->max_power_avg;
  4997. }
  4998. geo_ch->val = geo_ch->flag;
  4999. }
  5000. if ((modes[A].num_channels == 0) && priv->is_abg) {
  5001. printk(KERN_INFO DRV_NAME
  5002. ": Incorrectly detected BG card as ABG. Please send "
  5003. "your PCI ID 0x%04X:0x%04X to maintainer.\n",
  5004. priv->pci_dev->device, priv->pci_dev->subsystem_device);
  5005. priv->is_abg = 0;
  5006. }
  5007. printk(KERN_INFO DRV_NAME
  5008. ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
  5009. modes[G].num_channels, modes[A].num_channels);
  5010. /*
  5011. * NOTE: We register these in preference of order -- the
  5012. * stack doesn't currently (as of 7.0.6 / Apr 24 '07) pick
  5013. * a phymode based on rates or AP capabilities but seems to
  5014. * configure it purely on if the channel being configured
  5015. * is supported by a mode -- and the first match is taken
  5016. */
  5017. if (modes[G].num_channels)
  5018. ieee80211_register_hwmode(priv->hw, &modes[G]);
  5019. if (modes[B].num_channels)
  5020. ieee80211_register_hwmode(priv->hw, &modes[B]);
  5021. if (modes[A].num_channels)
  5022. ieee80211_register_hwmode(priv->hw, &modes[A]);
  5023. priv->modes = modes;
  5024. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  5025. return 0;
  5026. }
  5027. /******************************************************************************
  5028. *
  5029. * uCode download functions
  5030. *
  5031. ******************************************************************************/
  5032. static void iwl4965_dealloc_ucode_pci(struct iwl4965_priv *priv)
  5033. {
  5034. if (priv->ucode_code.v_addr != NULL) {
  5035. pci_free_consistent(priv->pci_dev,
  5036. priv->ucode_code.len,
  5037. priv->ucode_code.v_addr,
  5038. priv->ucode_code.p_addr);
  5039. priv->ucode_code.v_addr = NULL;
  5040. }
  5041. if (priv->ucode_data.v_addr != NULL) {
  5042. pci_free_consistent(priv->pci_dev,
  5043. priv->ucode_data.len,
  5044. priv->ucode_data.v_addr,
  5045. priv->ucode_data.p_addr);
  5046. priv->ucode_data.v_addr = NULL;
  5047. }
  5048. if (priv->ucode_data_backup.v_addr != NULL) {
  5049. pci_free_consistent(priv->pci_dev,
  5050. priv->ucode_data_backup.len,
  5051. priv->ucode_data_backup.v_addr,
  5052. priv->ucode_data_backup.p_addr);
  5053. priv->ucode_data_backup.v_addr = NULL;
  5054. }
  5055. if (priv->ucode_init.v_addr != NULL) {
  5056. pci_free_consistent(priv->pci_dev,
  5057. priv->ucode_init.len,
  5058. priv->ucode_init.v_addr,
  5059. priv->ucode_init.p_addr);
  5060. priv->ucode_init.v_addr = NULL;
  5061. }
  5062. if (priv->ucode_init_data.v_addr != NULL) {
  5063. pci_free_consistent(priv->pci_dev,
  5064. priv->ucode_init_data.len,
  5065. priv->ucode_init_data.v_addr,
  5066. priv->ucode_init_data.p_addr);
  5067. priv->ucode_init_data.v_addr = NULL;
  5068. }
  5069. if (priv->ucode_boot.v_addr != NULL) {
  5070. pci_free_consistent(priv->pci_dev,
  5071. priv->ucode_boot.len,
  5072. priv->ucode_boot.v_addr,
  5073. priv->ucode_boot.p_addr);
  5074. priv->ucode_boot.v_addr = NULL;
  5075. }
  5076. }
  5077. /**
  5078. * iwl4965_verify_inst_full - verify runtime uCode image in card vs. host,
  5079. * looking at all data.
  5080. */
  5081. static int iwl4965_verify_inst_full(struct iwl4965_priv *priv, __le32 * image,
  5082. u32 len)
  5083. {
  5084. u32 val;
  5085. u32 save_len = len;
  5086. int rc = 0;
  5087. u32 errcnt;
  5088. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  5089. rc = iwl4965_grab_nic_access(priv);
  5090. if (rc)
  5091. return rc;
  5092. iwl4965_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
  5093. errcnt = 0;
  5094. for (; len > 0; len -= sizeof(u32), image++) {
  5095. /* read data comes through single port, auto-incr addr */
  5096. /* NOTE: Use the debugless read so we don't flood kernel log
  5097. * if IWL_DL_IO is set */
  5098. val = _iwl4965_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  5099. if (val != le32_to_cpu(*image)) {
  5100. IWL_ERROR("uCode INST section is invalid at "
  5101. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  5102. save_len - len, val, le32_to_cpu(*image));
  5103. rc = -EIO;
  5104. errcnt++;
  5105. if (errcnt >= 20)
  5106. break;
  5107. }
  5108. }
  5109. iwl4965_release_nic_access(priv);
  5110. if (!errcnt)
  5111. IWL_DEBUG_INFO
  5112. ("ucode image in INSTRUCTION memory is good\n");
  5113. return rc;
  5114. }
  5115. /**
  5116. * iwl4965_verify_inst_sparse - verify runtime uCode image in card vs. host,
  5117. * using sample data 100 bytes apart. If these sample points are good,
  5118. * it's a pretty good bet that everything between them is good, too.
  5119. */
  5120. static int iwl4965_verify_inst_sparse(struct iwl4965_priv *priv, __le32 *image, u32 len)
  5121. {
  5122. u32 val;
  5123. int rc = 0;
  5124. u32 errcnt = 0;
  5125. u32 i;
  5126. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  5127. rc = iwl4965_grab_nic_access(priv);
  5128. if (rc)
  5129. return rc;
  5130. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  5131. /* read data comes through single port, auto-incr addr */
  5132. /* NOTE: Use the debugless read so we don't flood kernel log
  5133. * if IWL_DL_IO is set */
  5134. iwl4965_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  5135. i + RTC_INST_LOWER_BOUND);
  5136. val = _iwl4965_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  5137. if (val != le32_to_cpu(*image)) {
  5138. #if 0 /* Enable this if you want to see details */
  5139. IWL_ERROR("uCode INST section is invalid at "
  5140. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  5141. i, val, *image);
  5142. #endif
  5143. rc = -EIO;
  5144. errcnt++;
  5145. if (errcnt >= 3)
  5146. break;
  5147. }
  5148. }
  5149. iwl4965_release_nic_access(priv);
  5150. return rc;
  5151. }
  5152. /**
  5153. * iwl4965_verify_ucode - determine which instruction image is in SRAM,
  5154. * and verify its contents
  5155. */
  5156. static int iwl4965_verify_ucode(struct iwl4965_priv *priv)
  5157. {
  5158. __le32 *image;
  5159. u32 len;
  5160. int rc = 0;
  5161. /* Try bootstrap */
  5162. image = (__le32 *)priv->ucode_boot.v_addr;
  5163. len = priv->ucode_boot.len;
  5164. rc = iwl4965_verify_inst_sparse(priv, image, len);
  5165. if (rc == 0) {
  5166. IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
  5167. return 0;
  5168. }
  5169. /* Try initialize */
  5170. image = (__le32 *)priv->ucode_init.v_addr;
  5171. len = priv->ucode_init.len;
  5172. rc = iwl4965_verify_inst_sparse(priv, image, len);
  5173. if (rc == 0) {
  5174. IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
  5175. return 0;
  5176. }
  5177. /* Try runtime/protocol */
  5178. image = (__le32 *)priv->ucode_code.v_addr;
  5179. len = priv->ucode_code.len;
  5180. rc = iwl4965_verify_inst_sparse(priv, image, len);
  5181. if (rc == 0) {
  5182. IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
  5183. return 0;
  5184. }
  5185. IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
  5186. /* Since nothing seems to match, show first several data entries in
  5187. * instruction SRAM, so maybe visual inspection will give a clue.
  5188. * Selection of bootstrap image (vs. other images) is arbitrary. */
  5189. image = (__le32 *)priv->ucode_boot.v_addr;
  5190. len = priv->ucode_boot.len;
  5191. rc = iwl4965_verify_inst_full(priv, image, len);
  5192. return rc;
  5193. }
  5194. /* check contents of special bootstrap uCode SRAM */
  5195. static int iwl4965_verify_bsm(struct iwl4965_priv *priv)
  5196. {
  5197. __le32 *image = priv->ucode_boot.v_addr;
  5198. u32 len = priv->ucode_boot.len;
  5199. u32 reg;
  5200. u32 val;
  5201. IWL_DEBUG_INFO("Begin verify bsm\n");
  5202. /* verify BSM SRAM contents */
  5203. val = iwl4965_read_prph(priv, BSM_WR_DWCOUNT_REG);
  5204. for (reg = BSM_SRAM_LOWER_BOUND;
  5205. reg < BSM_SRAM_LOWER_BOUND + len;
  5206. reg += sizeof(u32), image ++) {
  5207. val = iwl4965_read_prph(priv, reg);
  5208. if (val != le32_to_cpu(*image)) {
  5209. IWL_ERROR("BSM uCode verification failed at "
  5210. "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
  5211. BSM_SRAM_LOWER_BOUND,
  5212. reg - BSM_SRAM_LOWER_BOUND, len,
  5213. val, le32_to_cpu(*image));
  5214. return -EIO;
  5215. }
  5216. }
  5217. IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
  5218. return 0;
  5219. }
  5220. /**
  5221. * iwl4965_load_bsm - Load bootstrap instructions
  5222. *
  5223. * BSM operation:
  5224. *
  5225. * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
  5226. * in special SRAM that does not power down during RFKILL. When powering back
  5227. * up after power-saving sleeps (or during initial uCode load), the BSM loads
  5228. * the bootstrap program into the on-board processor, and starts it.
  5229. *
  5230. * The bootstrap program loads (via DMA) instructions and data for a new
  5231. * program from host DRAM locations indicated by the host driver in the
  5232. * BSM_DRAM_* registers. Once the new program is loaded, it starts
  5233. * automatically.
  5234. *
  5235. * When initializing the NIC, the host driver points the BSM to the
  5236. * "initialize" uCode image. This uCode sets up some internal data, then
  5237. * notifies host via "initialize alive" that it is complete.
  5238. *
  5239. * The host then replaces the BSM_DRAM_* pointer values to point to the
  5240. * normal runtime uCode instructions and a backup uCode data cache buffer
  5241. * (filled initially with starting data values for the on-board processor),
  5242. * then triggers the "initialize" uCode to load and launch the runtime uCode,
  5243. * which begins normal operation.
  5244. *
  5245. * When doing a power-save shutdown, runtime uCode saves data SRAM into
  5246. * the backup data cache in DRAM before SRAM is powered down.
  5247. *
  5248. * When powering back up, the BSM loads the bootstrap program. This reloads
  5249. * the runtime uCode instructions and the backup data cache into SRAM,
  5250. * and re-launches the runtime uCode from where it left off.
  5251. */
  5252. static int iwl4965_load_bsm(struct iwl4965_priv *priv)
  5253. {
  5254. __le32 *image = priv->ucode_boot.v_addr;
  5255. u32 len = priv->ucode_boot.len;
  5256. dma_addr_t pinst;
  5257. dma_addr_t pdata;
  5258. u32 inst_len;
  5259. u32 data_len;
  5260. int rc;
  5261. int i;
  5262. u32 done;
  5263. u32 reg_offset;
  5264. IWL_DEBUG_INFO("Begin load bsm\n");
  5265. /* make sure bootstrap program is no larger than BSM's SRAM size */
  5266. if (len > IWL_MAX_BSM_SIZE)
  5267. return -EINVAL;
  5268. /* Tell bootstrap uCode where to find the "Initialize" uCode
  5269. * in host DRAM ... host DRAM physical address bits 35:4 for 4965.
  5270. * NOTE: iwl4965_initialize_alive_start() will replace these values,
  5271. * after the "initialize" uCode has run, to point to
  5272. * runtime/protocol instructions and backup data cache. */
  5273. pinst = priv->ucode_init.p_addr >> 4;
  5274. pdata = priv->ucode_init_data.p_addr >> 4;
  5275. inst_len = priv->ucode_init.len;
  5276. data_len = priv->ucode_init_data.len;
  5277. rc = iwl4965_grab_nic_access(priv);
  5278. if (rc)
  5279. return rc;
  5280. iwl4965_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  5281. iwl4965_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  5282. iwl4965_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
  5283. iwl4965_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
  5284. /* Fill BSM memory with bootstrap instructions */
  5285. for (reg_offset = BSM_SRAM_LOWER_BOUND;
  5286. reg_offset < BSM_SRAM_LOWER_BOUND + len;
  5287. reg_offset += sizeof(u32), image++)
  5288. _iwl4965_write_prph(priv, reg_offset,
  5289. le32_to_cpu(*image));
  5290. rc = iwl4965_verify_bsm(priv);
  5291. if (rc) {
  5292. iwl4965_release_nic_access(priv);
  5293. return rc;
  5294. }
  5295. /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
  5296. iwl4965_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
  5297. iwl4965_write_prph(priv, BSM_WR_MEM_DST_REG,
  5298. RTC_INST_LOWER_BOUND);
  5299. iwl4965_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
  5300. /* Load bootstrap code into instruction SRAM now,
  5301. * to prepare to load "initialize" uCode */
  5302. iwl4965_write_prph(priv, BSM_WR_CTRL_REG,
  5303. BSM_WR_CTRL_REG_BIT_START);
  5304. /* Wait for load of bootstrap uCode to finish */
  5305. for (i = 0; i < 100; i++) {
  5306. done = iwl4965_read_prph(priv, BSM_WR_CTRL_REG);
  5307. if (!(done & BSM_WR_CTRL_REG_BIT_START))
  5308. break;
  5309. udelay(10);
  5310. }
  5311. if (i < 100)
  5312. IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
  5313. else {
  5314. IWL_ERROR("BSM write did not complete!\n");
  5315. return -EIO;
  5316. }
  5317. /* Enable future boot loads whenever power management unit triggers it
  5318. * (e.g. when powering back up after power-save shutdown) */
  5319. iwl4965_write_prph(priv, BSM_WR_CTRL_REG,
  5320. BSM_WR_CTRL_REG_BIT_START_EN);
  5321. iwl4965_release_nic_access(priv);
  5322. return 0;
  5323. }
  5324. static void iwl4965_nic_start(struct iwl4965_priv *priv)
  5325. {
  5326. /* Remove all resets to allow NIC to operate */
  5327. iwl4965_write32(priv, CSR_RESET, 0);
  5328. }
  5329. static int iwl4965_alloc_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc)
  5330. {
  5331. desc->v_addr = pci_alloc_consistent(pci_dev, desc->len, &desc->p_addr);
  5332. return (desc->v_addr != NULL) ? 0 : -ENOMEM;
  5333. }
  5334. /**
  5335. * iwl4965_read_ucode - Read uCode images from disk file.
  5336. *
  5337. * Copy into buffers for card to fetch via bus-mastering
  5338. */
  5339. static int iwl4965_read_ucode(struct iwl4965_priv *priv)
  5340. {
  5341. struct iwl4965_ucode *ucode;
  5342. int ret;
  5343. const struct firmware *ucode_raw;
  5344. const char *name = "iwlwifi-4965" IWL4965_UCODE_API ".ucode";
  5345. u8 *src;
  5346. size_t len;
  5347. u32 ver, inst_size, data_size, init_size, init_data_size, boot_size;
  5348. /* Ask kernel firmware_class module to get the boot firmware off disk.
  5349. * request_firmware() is synchronous, file is in memory on return. */
  5350. ret = request_firmware(&ucode_raw, name, &priv->pci_dev->dev);
  5351. if (ret < 0) {
  5352. IWL_ERROR("%s firmware file req failed: Reason %d\n",
  5353. name, ret);
  5354. goto error;
  5355. }
  5356. IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
  5357. name, ucode_raw->size);
  5358. /* Make sure that we got at least our header! */
  5359. if (ucode_raw->size < sizeof(*ucode)) {
  5360. IWL_ERROR("File size way too small!\n");
  5361. ret = -EINVAL;
  5362. goto err_release;
  5363. }
  5364. /* Data from ucode file: header followed by uCode images */
  5365. ucode = (void *)ucode_raw->data;
  5366. ver = le32_to_cpu(ucode->ver);
  5367. inst_size = le32_to_cpu(ucode->inst_size);
  5368. data_size = le32_to_cpu(ucode->data_size);
  5369. init_size = le32_to_cpu(ucode->init_size);
  5370. init_data_size = le32_to_cpu(ucode->init_data_size);
  5371. boot_size = le32_to_cpu(ucode->boot_size);
  5372. IWL_DEBUG_INFO("f/w package hdr ucode version = 0x%x\n", ver);
  5373. IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n",
  5374. inst_size);
  5375. IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n",
  5376. data_size);
  5377. IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n",
  5378. init_size);
  5379. IWL_DEBUG_INFO("f/w package hdr init data size = %u\n",
  5380. init_data_size);
  5381. IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n",
  5382. boot_size);
  5383. /* Verify size of file vs. image size info in file's header */
  5384. if (ucode_raw->size < sizeof(*ucode) +
  5385. inst_size + data_size + init_size +
  5386. init_data_size + boot_size) {
  5387. IWL_DEBUG_INFO("uCode file size %d too small\n",
  5388. (int)ucode_raw->size);
  5389. ret = -EINVAL;
  5390. goto err_release;
  5391. }
  5392. /* Verify that uCode images will fit in card's SRAM */
  5393. if (inst_size > IWL_MAX_INST_SIZE) {
  5394. IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
  5395. inst_size);
  5396. ret = -EINVAL;
  5397. goto err_release;
  5398. }
  5399. if (data_size > IWL_MAX_DATA_SIZE) {
  5400. IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
  5401. data_size);
  5402. ret = -EINVAL;
  5403. goto err_release;
  5404. }
  5405. if (init_size > IWL_MAX_INST_SIZE) {
  5406. IWL_DEBUG_INFO
  5407. ("uCode init instr len %d too large to fit in\n",
  5408. init_size);
  5409. ret = -EINVAL;
  5410. goto err_release;
  5411. }
  5412. if (init_data_size > IWL_MAX_DATA_SIZE) {
  5413. IWL_DEBUG_INFO
  5414. ("uCode init data len %d too large to fit in\n",
  5415. init_data_size);
  5416. ret = -EINVAL;
  5417. goto err_release;
  5418. }
  5419. if (boot_size > IWL_MAX_BSM_SIZE) {
  5420. IWL_DEBUG_INFO
  5421. ("uCode boot instr len %d too large to fit in\n",
  5422. boot_size);
  5423. ret = -EINVAL;
  5424. goto err_release;
  5425. }
  5426. /* Allocate ucode buffers for card's bus-master loading ... */
  5427. /* Runtime instructions and 2 copies of data:
  5428. * 1) unmodified from disk
  5429. * 2) backup cache for save/restore during power-downs */
  5430. priv->ucode_code.len = inst_size;
  5431. iwl4965_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  5432. priv->ucode_data.len = data_size;
  5433. iwl4965_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  5434. priv->ucode_data_backup.len = data_size;
  5435. iwl4965_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  5436. /* Initialization instructions and data */
  5437. if (init_size && init_data_size) {
  5438. priv->ucode_init.len = init_size;
  5439. iwl4965_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  5440. priv->ucode_init_data.len = init_data_size;
  5441. iwl4965_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  5442. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  5443. goto err_pci_alloc;
  5444. }
  5445. /* Bootstrap (instructions only, no data) */
  5446. if (boot_size) {
  5447. priv->ucode_boot.len = boot_size;
  5448. iwl4965_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  5449. if (!priv->ucode_boot.v_addr)
  5450. goto err_pci_alloc;
  5451. }
  5452. /* Copy images into buffers for card's bus-master reads ... */
  5453. /* Runtime instructions (first block of data in file) */
  5454. src = &ucode->data[0];
  5455. len = priv->ucode_code.len;
  5456. IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
  5457. memcpy(priv->ucode_code.v_addr, src, len);
  5458. IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  5459. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  5460. /* Runtime data (2nd block)
  5461. * NOTE: Copy into backup buffer will be done in iwl4965_up() */
  5462. src = &ucode->data[inst_size];
  5463. len = priv->ucode_data.len;
  5464. IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
  5465. memcpy(priv->ucode_data.v_addr, src, len);
  5466. memcpy(priv->ucode_data_backup.v_addr, src, len);
  5467. /* Initialization instructions (3rd block) */
  5468. if (init_size) {
  5469. src = &ucode->data[inst_size + data_size];
  5470. len = priv->ucode_init.len;
  5471. IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
  5472. len);
  5473. memcpy(priv->ucode_init.v_addr, src, len);
  5474. }
  5475. /* Initialization data (4th block) */
  5476. if (init_data_size) {
  5477. src = &ucode->data[inst_size + data_size + init_size];
  5478. len = priv->ucode_init_data.len;
  5479. IWL_DEBUG_INFO("Copying (but not loading) init data len %Zd\n",
  5480. len);
  5481. memcpy(priv->ucode_init_data.v_addr, src, len);
  5482. }
  5483. /* Bootstrap instructions (5th block) */
  5484. src = &ucode->data[inst_size + data_size + init_size + init_data_size];
  5485. len = priv->ucode_boot.len;
  5486. IWL_DEBUG_INFO("Copying (but not loading) boot instr len %Zd\n", len);
  5487. memcpy(priv->ucode_boot.v_addr, src, len);
  5488. /* We have our copies now, allow OS release its copies */
  5489. release_firmware(ucode_raw);
  5490. return 0;
  5491. err_pci_alloc:
  5492. IWL_ERROR("failed to allocate pci memory\n");
  5493. ret = -ENOMEM;
  5494. iwl4965_dealloc_ucode_pci(priv);
  5495. err_release:
  5496. release_firmware(ucode_raw);
  5497. error:
  5498. return ret;
  5499. }
  5500. /**
  5501. * iwl4965_set_ucode_ptrs - Set uCode address location
  5502. *
  5503. * Tell initialization uCode where to find runtime uCode.
  5504. *
  5505. * BSM registers initially contain pointers to initialization uCode.
  5506. * We need to replace them to load runtime uCode inst and data,
  5507. * and to save runtime data when powering down.
  5508. */
  5509. static int iwl4965_set_ucode_ptrs(struct iwl4965_priv *priv)
  5510. {
  5511. dma_addr_t pinst;
  5512. dma_addr_t pdata;
  5513. int rc = 0;
  5514. unsigned long flags;
  5515. /* bits 35:4 for 4965 */
  5516. pinst = priv->ucode_code.p_addr >> 4;
  5517. pdata = priv->ucode_data_backup.p_addr >> 4;
  5518. spin_lock_irqsave(&priv->lock, flags);
  5519. rc = iwl4965_grab_nic_access(priv);
  5520. if (rc) {
  5521. spin_unlock_irqrestore(&priv->lock, flags);
  5522. return rc;
  5523. }
  5524. /* Tell bootstrap uCode where to find image to load */
  5525. iwl4965_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  5526. iwl4965_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  5527. iwl4965_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
  5528. priv->ucode_data.len);
  5529. /* Inst bytecount must be last to set up, bit 31 signals uCode
  5530. * that all new ptr/size info is in place */
  5531. iwl4965_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
  5532. priv->ucode_code.len | BSM_DRAM_INST_LOAD);
  5533. iwl4965_release_nic_access(priv);
  5534. spin_unlock_irqrestore(&priv->lock, flags);
  5535. IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
  5536. return rc;
  5537. }
  5538. /**
  5539. * iwl4965_init_alive_start - Called after REPLY_ALIVE notification received
  5540. *
  5541. * Called after REPLY_ALIVE notification received from "initialize" uCode.
  5542. *
  5543. * The 4965 "initialize" ALIVE reply contains calibration data for:
  5544. * Voltage, temperature, and MIMO tx gain correction, now stored in priv
  5545. * (3945 does not contain this data).
  5546. *
  5547. * Tell "initialize" uCode to go ahead and load the runtime uCode.
  5548. */
  5549. static void iwl4965_init_alive_start(struct iwl4965_priv *priv)
  5550. {
  5551. /* Check alive response for "valid" sign from uCode */
  5552. if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
  5553. /* We had an error bringing up the hardware, so take it
  5554. * all the way back down so we can try again */
  5555. IWL_DEBUG_INFO("Initialize Alive failed.\n");
  5556. goto restart;
  5557. }
  5558. /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
  5559. * This is a paranoid check, because we would not have gotten the
  5560. * "initialize" alive if code weren't properly loaded. */
  5561. if (iwl4965_verify_ucode(priv)) {
  5562. /* Runtime instruction load was bad;
  5563. * take it all the way back down so we can try again */
  5564. IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
  5565. goto restart;
  5566. }
  5567. /* Calculate temperature */
  5568. priv->temperature = iwl4965_get_temperature(priv);
  5569. /* Send pointers to protocol/runtime uCode image ... init code will
  5570. * load and launch runtime uCode, which will send us another "Alive"
  5571. * notification. */
  5572. IWL_DEBUG_INFO("Initialization Alive received.\n");
  5573. if (iwl4965_set_ucode_ptrs(priv)) {
  5574. /* Runtime instruction load won't happen;
  5575. * take it all the way back down so we can try again */
  5576. IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
  5577. goto restart;
  5578. }
  5579. return;
  5580. restart:
  5581. queue_work(priv->workqueue, &priv->restart);
  5582. }
  5583. /**
  5584. * iwl4965_alive_start - called after REPLY_ALIVE notification received
  5585. * from protocol/runtime uCode (initialization uCode's
  5586. * Alive gets handled by iwl4965_init_alive_start()).
  5587. */
  5588. static void iwl4965_alive_start(struct iwl4965_priv *priv)
  5589. {
  5590. int rc = 0;
  5591. IWL_DEBUG_INFO("Runtime Alive received.\n");
  5592. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  5593. /* We had an error bringing up the hardware, so take it
  5594. * all the way back down so we can try again */
  5595. IWL_DEBUG_INFO("Alive failed.\n");
  5596. goto restart;
  5597. }
  5598. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  5599. * This is a paranoid check, because we would not have gotten the
  5600. * "runtime" alive if code weren't properly loaded. */
  5601. if (iwl4965_verify_ucode(priv)) {
  5602. /* Runtime instruction load was bad;
  5603. * take it all the way back down so we can try again */
  5604. IWL_DEBUG_INFO("Bad runtime uCode load.\n");
  5605. goto restart;
  5606. }
  5607. iwl4965_clear_stations_table(priv);
  5608. rc = iwl4965_alive_notify(priv);
  5609. if (rc) {
  5610. IWL_WARNING("Could not complete ALIVE transition [ntf]: %d\n",
  5611. rc);
  5612. goto restart;
  5613. }
  5614. /* After the ALIVE response, we can send host commands to 4965 uCode */
  5615. set_bit(STATUS_ALIVE, &priv->status);
  5616. /* Clear out the uCode error bit if it is set */
  5617. clear_bit(STATUS_FW_ERROR, &priv->status);
  5618. rc = iwl4965_init_channel_map(priv);
  5619. if (rc) {
  5620. IWL_ERROR("initializing regulatory failed: %d\n", rc);
  5621. return;
  5622. }
  5623. iwl4965_init_geos(priv);
  5624. if (iwl4965_is_rfkill(priv))
  5625. return;
  5626. if (!priv->mac80211_registered) {
  5627. /* Unlock so any user space entry points can call back into
  5628. * the driver without a deadlock... */
  5629. mutex_unlock(&priv->mutex);
  5630. iwl4965_rate_control_register(priv->hw);
  5631. rc = ieee80211_register_hw(priv->hw);
  5632. priv->hw->conf.beacon_int = 100;
  5633. mutex_lock(&priv->mutex);
  5634. if (rc) {
  5635. iwl4965_rate_control_unregister(priv->hw);
  5636. IWL_ERROR("Failed to register network "
  5637. "device (error %d)\n", rc);
  5638. return;
  5639. }
  5640. priv->mac80211_registered = 1;
  5641. iwl4965_reset_channel_flag(priv);
  5642. } else
  5643. ieee80211_start_queues(priv->hw);
  5644. priv->active_rate = priv->rates_mask;
  5645. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  5646. iwl4965_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
  5647. if (iwl4965_is_associated(priv)) {
  5648. struct iwl4965_rxon_cmd *active_rxon =
  5649. (struct iwl4965_rxon_cmd *)(&priv->active_rxon);
  5650. memcpy(&priv->staging_rxon, &priv->active_rxon,
  5651. sizeof(priv->staging_rxon));
  5652. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5653. } else {
  5654. /* Initialize our rx_config data */
  5655. iwl4965_connection_init_rx_config(priv);
  5656. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  5657. }
  5658. /* Configure Bluetooth device coexistence support */
  5659. iwl4965_send_bt_config(priv);
  5660. /* Configure the adapter for unassociated operation */
  5661. iwl4965_commit_rxon(priv);
  5662. /* At this point, the NIC is initialized and operational */
  5663. priv->notif_missed_beacons = 0;
  5664. set_bit(STATUS_READY, &priv->status);
  5665. iwl4965_rf_kill_ct_config(priv);
  5666. IWL_DEBUG_INFO("ALIVE processing complete.\n");
  5667. if (priv->error_recovering)
  5668. iwl4965_error_recovery(priv);
  5669. return;
  5670. restart:
  5671. queue_work(priv->workqueue, &priv->restart);
  5672. }
  5673. static void iwl4965_cancel_deferred_work(struct iwl4965_priv *priv);
  5674. static void __iwl4965_down(struct iwl4965_priv *priv)
  5675. {
  5676. unsigned long flags;
  5677. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  5678. struct ieee80211_conf *conf = NULL;
  5679. IWL_DEBUG_INFO(DRV_NAME " is going down\n");
  5680. conf = ieee80211_get_hw_conf(priv->hw);
  5681. if (!exit_pending)
  5682. set_bit(STATUS_EXIT_PENDING, &priv->status);
  5683. iwl4965_clear_stations_table(priv);
  5684. /* Unblock any waiting calls */
  5685. wake_up_interruptible_all(&priv->wait_command_queue);
  5686. /* Wipe out the EXIT_PENDING status bit if we are not actually
  5687. * exiting the module */
  5688. if (!exit_pending)
  5689. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  5690. /* stop and reset the on-board processor */
  5691. iwl4965_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  5692. /* tell the device to stop sending interrupts */
  5693. iwl4965_disable_interrupts(priv);
  5694. if (priv->mac80211_registered)
  5695. ieee80211_stop_queues(priv->hw);
  5696. /* If we have not previously called iwl4965_init() then
  5697. * clear all bits but the RF Kill and SUSPEND bits and return */
  5698. if (!iwl4965_is_init(priv)) {
  5699. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  5700. STATUS_RF_KILL_HW |
  5701. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  5702. STATUS_RF_KILL_SW |
  5703. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  5704. STATUS_IN_SUSPEND;
  5705. goto exit;
  5706. }
  5707. /* ...otherwise clear out all the status bits but the RF Kill and
  5708. * SUSPEND bits and continue taking the NIC down. */
  5709. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  5710. STATUS_RF_KILL_HW |
  5711. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  5712. STATUS_RF_KILL_SW |
  5713. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  5714. STATUS_IN_SUSPEND |
  5715. test_bit(STATUS_FW_ERROR, &priv->status) <<
  5716. STATUS_FW_ERROR;
  5717. spin_lock_irqsave(&priv->lock, flags);
  5718. iwl4965_clear_bit(priv, CSR_GP_CNTRL,
  5719. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  5720. spin_unlock_irqrestore(&priv->lock, flags);
  5721. iwl4965_hw_txq_ctx_stop(priv);
  5722. iwl4965_hw_rxq_stop(priv);
  5723. spin_lock_irqsave(&priv->lock, flags);
  5724. if (!iwl4965_grab_nic_access(priv)) {
  5725. iwl4965_write_prph(priv, APMG_CLK_DIS_REG,
  5726. APMG_CLK_VAL_DMA_CLK_RQT);
  5727. iwl4965_release_nic_access(priv);
  5728. }
  5729. spin_unlock_irqrestore(&priv->lock, flags);
  5730. udelay(5);
  5731. iwl4965_hw_nic_stop_master(priv);
  5732. iwl4965_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  5733. iwl4965_hw_nic_reset(priv);
  5734. exit:
  5735. memset(&priv->card_alive, 0, sizeof(struct iwl4965_alive_resp));
  5736. if (priv->ibss_beacon)
  5737. dev_kfree_skb(priv->ibss_beacon);
  5738. priv->ibss_beacon = NULL;
  5739. /* clear out any free frames */
  5740. iwl4965_clear_free_frames(priv);
  5741. }
  5742. static void iwl4965_down(struct iwl4965_priv *priv)
  5743. {
  5744. mutex_lock(&priv->mutex);
  5745. __iwl4965_down(priv);
  5746. mutex_unlock(&priv->mutex);
  5747. iwl4965_cancel_deferred_work(priv);
  5748. }
  5749. #define MAX_HW_RESTARTS 5
  5750. static int __iwl4965_up(struct iwl4965_priv *priv)
  5751. {
  5752. DECLARE_MAC_BUF(mac);
  5753. int rc, i;
  5754. u32 hw_rf_kill = 0;
  5755. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  5756. IWL_WARNING("Exit pending; will not bring the NIC up\n");
  5757. return -EIO;
  5758. }
  5759. if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
  5760. IWL_WARNING("Radio disabled by SW RF kill (module "
  5761. "parameter)\n");
  5762. return 0;
  5763. }
  5764. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  5765. IWL_ERROR("ucode not available for device bringup\n");
  5766. return -EIO;
  5767. }
  5768. iwl4965_write32(priv, CSR_INT, 0xFFFFFFFF);
  5769. rc = iwl4965_hw_nic_init(priv);
  5770. if (rc) {
  5771. IWL_ERROR("Unable to int nic\n");
  5772. return rc;
  5773. }
  5774. /* make sure rfkill handshake bits are cleared */
  5775. iwl4965_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  5776. iwl4965_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  5777. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  5778. /* clear (again), then enable host interrupts */
  5779. iwl4965_write32(priv, CSR_INT, 0xFFFFFFFF);
  5780. iwl4965_enable_interrupts(priv);
  5781. /* really make sure rfkill handshake bits are cleared */
  5782. iwl4965_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  5783. iwl4965_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  5784. /* Copy original ucode data image from disk into backup cache.
  5785. * This will be used to initialize the on-board processor's
  5786. * data SRAM for a clean start when the runtime program first loads. */
  5787. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  5788. priv->ucode_data.len);
  5789. /* If platform's RF_KILL switch is set to KILL,
  5790. * wait for BIT_INT_RF_KILL interrupt before loading uCode
  5791. * and getting things started */
  5792. if (!(iwl4965_read32(priv, CSR_GP_CNTRL) &
  5793. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  5794. hw_rf_kill = 1;
  5795. if (test_bit(STATUS_RF_KILL_HW, &priv->status) || hw_rf_kill) {
  5796. IWL_WARNING("Radio disabled by HW RF Kill switch\n");
  5797. return 0;
  5798. }
  5799. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  5800. iwl4965_clear_stations_table(priv);
  5801. /* load bootstrap state machine,
  5802. * load bootstrap program into processor's memory,
  5803. * prepare to load the "initialize" uCode */
  5804. rc = iwl4965_load_bsm(priv);
  5805. if (rc) {
  5806. IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc);
  5807. continue;
  5808. }
  5809. /* start card; "initialize" will load runtime ucode */
  5810. iwl4965_nic_start(priv);
  5811. /* MAC Address location in EEPROM is same for 3945/4965 */
  5812. get_eeprom_mac(priv, priv->mac_addr);
  5813. IWL_DEBUG_INFO("MAC address: %s\n",
  5814. print_mac(mac, priv->mac_addr));
  5815. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  5816. IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
  5817. return 0;
  5818. }
  5819. set_bit(STATUS_EXIT_PENDING, &priv->status);
  5820. __iwl4965_down(priv);
  5821. /* tried to restart and config the device for as long as our
  5822. * patience could withstand */
  5823. IWL_ERROR("Unable to initialize device after %d attempts.\n", i);
  5824. return -EIO;
  5825. }
  5826. /*****************************************************************************
  5827. *
  5828. * Workqueue callbacks
  5829. *
  5830. *****************************************************************************/
  5831. static void iwl4965_bg_init_alive_start(struct work_struct *data)
  5832. {
  5833. struct iwl4965_priv *priv =
  5834. container_of(data, struct iwl4965_priv, init_alive_start.work);
  5835. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5836. return;
  5837. mutex_lock(&priv->mutex);
  5838. iwl4965_init_alive_start(priv);
  5839. mutex_unlock(&priv->mutex);
  5840. }
  5841. static void iwl4965_bg_alive_start(struct work_struct *data)
  5842. {
  5843. struct iwl4965_priv *priv =
  5844. container_of(data, struct iwl4965_priv, alive_start.work);
  5845. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5846. return;
  5847. mutex_lock(&priv->mutex);
  5848. iwl4965_alive_start(priv);
  5849. mutex_unlock(&priv->mutex);
  5850. }
  5851. static void iwl4965_bg_rf_kill(struct work_struct *work)
  5852. {
  5853. struct iwl4965_priv *priv = container_of(work, struct iwl4965_priv, rf_kill);
  5854. wake_up_interruptible(&priv->wait_command_queue);
  5855. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5856. return;
  5857. mutex_lock(&priv->mutex);
  5858. if (!iwl4965_is_rfkill(priv)) {
  5859. IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
  5860. "HW and/or SW RF Kill no longer active, restarting "
  5861. "device\n");
  5862. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  5863. queue_work(priv->workqueue, &priv->restart);
  5864. } else {
  5865. if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
  5866. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  5867. "disabled by SW switch\n");
  5868. else
  5869. IWL_WARNING("Radio Frequency Kill Switch is On:\n"
  5870. "Kill switch must be turned off for "
  5871. "wireless networking to work.\n");
  5872. }
  5873. mutex_unlock(&priv->mutex);
  5874. }
  5875. #define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
  5876. static void iwl4965_bg_scan_check(struct work_struct *data)
  5877. {
  5878. struct iwl4965_priv *priv =
  5879. container_of(data, struct iwl4965_priv, scan_check.work);
  5880. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5881. return;
  5882. mutex_lock(&priv->mutex);
  5883. if (test_bit(STATUS_SCANNING, &priv->status) ||
  5884. test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  5885. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
  5886. "Scan completion watchdog resetting adapter (%dms)\n",
  5887. jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
  5888. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  5889. iwl4965_send_scan_abort(priv);
  5890. }
  5891. mutex_unlock(&priv->mutex);
  5892. }
  5893. static void iwl4965_bg_request_scan(struct work_struct *data)
  5894. {
  5895. struct iwl4965_priv *priv =
  5896. container_of(data, struct iwl4965_priv, request_scan);
  5897. struct iwl4965_host_cmd cmd = {
  5898. .id = REPLY_SCAN_CMD,
  5899. .len = sizeof(struct iwl4965_scan_cmd),
  5900. .meta.flags = CMD_SIZE_HUGE,
  5901. };
  5902. int rc = 0;
  5903. struct iwl4965_scan_cmd *scan;
  5904. struct ieee80211_conf *conf = NULL;
  5905. u8 direct_mask;
  5906. int phymode;
  5907. conf = ieee80211_get_hw_conf(priv->hw);
  5908. mutex_lock(&priv->mutex);
  5909. if (!iwl4965_is_ready(priv)) {
  5910. IWL_WARNING("request scan called when driver not ready.\n");
  5911. goto done;
  5912. }
  5913. /* Make sure the scan wasn't cancelled before this queued work
  5914. * was given the chance to run... */
  5915. if (!test_bit(STATUS_SCANNING, &priv->status))
  5916. goto done;
  5917. /* This should never be called or scheduled if there is currently
  5918. * a scan active in the hardware. */
  5919. if (test_bit(STATUS_SCAN_HW, &priv->status)) {
  5920. IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
  5921. "Ignoring second request.\n");
  5922. rc = -EIO;
  5923. goto done;
  5924. }
  5925. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  5926. IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
  5927. goto done;
  5928. }
  5929. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  5930. IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
  5931. goto done;
  5932. }
  5933. if (iwl4965_is_rfkill(priv)) {
  5934. IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
  5935. goto done;
  5936. }
  5937. if (!test_bit(STATUS_READY, &priv->status)) {
  5938. IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
  5939. goto done;
  5940. }
  5941. if (!priv->scan_bands) {
  5942. IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
  5943. goto done;
  5944. }
  5945. if (!priv->scan) {
  5946. priv->scan = kmalloc(sizeof(struct iwl4965_scan_cmd) +
  5947. IWL_MAX_SCAN_SIZE, GFP_KERNEL);
  5948. if (!priv->scan) {
  5949. rc = -ENOMEM;
  5950. goto done;
  5951. }
  5952. }
  5953. scan = priv->scan;
  5954. memset(scan, 0, sizeof(struct iwl4965_scan_cmd) + IWL_MAX_SCAN_SIZE);
  5955. scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
  5956. scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
  5957. if (iwl4965_is_associated(priv)) {
  5958. u16 interval = 0;
  5959. u32 extra;
  5960. u32 suspend_time = 100;
  5961. u32 scan_suspend_time = 100;
  5962. unsigned long flags;
  5963. IWL_DEBUG_INFO("Scanning while associated...\n");
  5964. spin_lock_irqsave(&priv->lock, flags);
  5965. interval = priv->beacon_int;
  5966. spin_unlock_irqrestore(&priv->lock, flags);
  5967. scan->suspend_time = 0;
  5968. scan->max_out_time = cpu_to_le32(200 * 1024);
  5969. if (!interval)
  5970. interval = suspend_time;
  5971. extra = (suspend_time / interval) << 22;
  5972. scan_suspend_time = (extra |
  5973. ((suspend_time % interval) * 1024));
  5974. scan->suspend_time = cpu_to_le32(scan_suspend_time);
  5975. IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
  5976. scan_suspend_time, interval);
  5977. }
  5978. /* We should add the ability for user to lock to PASSIVE ONLY */
  5979. if (priv->one_direct_scan) {
  5980. IWL_DEBUG_SCAN
  5981. ("Kicking off one direct scan for '%s'\n",
  5982. iwl4965_escape_essid(priv->direct_ssid,
  5983. priv->direct_ssid_len));
  5984. scan->direct_scan[0].id = WLAN_EID_SSID;
  5985. scan->direct_scan[0].len = priv->direct_ssid_len;
  5986. memcpy(scan->direct_scan[0].ssid,
  5987. priv->direct_ssid, priv->direct_ssid_len);
  5988. direct_mask = 1;
  5989. } else if (!iwl4965_is_associated(priv) && priv->essid_len) {
  5990. scan->direct_scan[0].id = WLAN_EID_SSID;
  5991. scan->direct_scan[0].len = priv->essid_len;
  5992. memcpy(scan->direct_scan[0].ssid, priv->essid, priv->essid_len);
  5993. direct_mask = 1;
  5994. } else
  5995. direct_mask = 0;
  5996. /* We don't build a direct scan probe request; the uCode will do
  5997. * that based on the direct_mask added to each channel entry */
  5998. scan->tx_cmd.len = cpu_to_le16(
  5999. iwl4965_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
  6000. IWL_MAX_SCAN_SIZE - sizeof(scan), 0));
  6001. scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
  6002. scan->tx_cmd.sta_id = priv->hw_setting.bcast_sta_id;
  6003. scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  6004. /* flags + rate selection */
  6005. scan->tx_cmd.tx_flags |= cpu_to_le32(0x200);
  6006. switch (priv->scan_bands) {
  6007. case 2:
  6008. scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
  6009. scan->tx_cmd.rate_n_flags =
  6010. iwl4965_hw_set_rate_n_flags(IWL_RATE_1M_PLCP,
  6011. RATE_MCS_ANT_B_MSK|RATE_MCS_CCK_MSK);
  6012. scan->good_CRC_th = 0;
  6013. phymode = MODE_IEEE80211G;
  6014. break;
  6015. case 1:
  6016. scan->tx_cmd.rate_n_flags =
  6017. iwl4965_hw_set_rate_n_flags(IWL_RATE_6M_PLCP,
  6018. RATE_MCS_ANT_B_MSK);
  6019. scan->good_CRC_th = IWL_GOOD_CRC_TH;
  6020. phymode = MODE_IEEE80211A;
  6021. break;
  6022. default:
  6023. IWL_WARNING("Invalid scan band count\n");
  6024. goto done;
  6025. }
  6026. /* select Rx chains */
  6027. /* Force use of chains B and C (0x6) for scan Rx.
  6028. * Avoid A (0x1) because of its off-channel reception on A-band.
  6029. * MIMO is not used here, but value is required to make uCode happy. */
  6030. scan->rx_chain = RXON_RX_CHAIN_DRIVER_FORCE_MSK |
  6031. cpu_to_le16((0x7 << RXON_RX_CHAIN_VALID_POS) |
  6032. (0x6 << RXON_RX_CHAIN_FORCE_SEL_POS) |
  6033. (0x7 << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS));
  6034. if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR)
  6035. scan->filter_flags = RXON_FILTER_PROMISC_MSK;
  6036. if (direct_mask)
  6037. IWL_DEBUG_SCAN
  6038. ("Initiating direct scan for %s.\n",
  6039. iwl4965_escape_essid(priv->essid, priv->essid_len));
  6040. else
  6041. IWL_DEBUG_SCAN("Initiating indirect scan.\n");
  6042. scan->channel_count =
  6043. iwl4965_get_channels_for_scan(
  6044. priv, phymode, 1, /* active */
  6045. direct_mask,
  6046. (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
  6047. cmd.len += le16_to_cpu(scan->tx_cmd.len) +
  6048. scan->channel_count * sizeof(struct iwl4965_scan_channel);
  6049. cmd.data = scan;
  6050. scan->len = cpu_to_le16(cmd.len);
  6051. set_bit(STATUS_SCAN_HW, &priv->status);
  6052. rc = iwl4965_send_cmd_sync(priv, &cmd);
  6053. if (rc)
  6054. goto done;
  6055. queue_delayed_work(priv->workqueue, &priv->scan_check,
  6056. IWL_SCAN_CHECK_WATCHDOG);
  6057. mutex_unlock(&priv->mutex);
  6058. return;
  6059. done:
  6060. /* inform mac80211 scan aborted */
  6061. queue_work(priv->workqueue, &priv->scan_completed);
  6062. mutex_unlock(&priv->mutex);
  6063. }
  6064. static void iwl4965_bg_up(struct work_struct *data)
  6065. {
  6066. struct iwl4965_priv *priv = container_of(data, struct iwl4965_priv, up);
  6067. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  6068. return;
  6069. mutex_lock(&priv->mutex);
  6070. __iwl4965_up(priv);
  6071. mutex_unlock(&priv->mutex);
  6072. }
  6073. static void iwl4965_bg_restart(struct work_struct *data)
  6074. {
  6075. struct iwl4965_priv *priv = container_of(data, struct iwl4965_priv, restart);
  6076. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  6077. return;
  6078. iwl4965_down(priv);
  6079. queue_work(priv->workqueue, &priv->up);
  6080. }
  6081. static void iwl4965_bg_rx_replenish(struct work_struct *data)
  6082. {
  6083. struct iwl4965_priv *priv =
  6084. container_of(data, struct iwl4965_priv, rx_replenish);
  6085. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  6086. return;
  6087. mutex_lock(&priv->mutex);
  6088. iwl4965_rx_replenish(priv);
  6089. mutex_unlock(&priv->mutex);
  6090. }
  6091. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  6092. static void iwl4965_bg_post_associate(struct work_struct *data)
  6093. {
  6094. struct iwl4965_priv *priv = container_of(data, struct iwl4965_priv,
  6095. post_associate.work);
  6096. int rc = 0;
  6097. struct ieee80211_conf *conf = NULL;
  6098. DECLARE_MAC_BUF(mac);
  6099. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  6100. IWL_ERROR("%s Should not be called in AP mode\n", __FUNCTION__);
  6101. return;
  6102. }
  6103. IWL_DEBUG_ASSOC("Associated as %d to: %s\n",
  6104. priv->assoc_id,
  6105. print_mac(mac, priv->active_rxon.bssid_addr));
  6106. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  6107. return;
  6108. mutex_lock(&priv->mutex);
  6109. if (!priv->interface_id || !priv->is_open) {
  6110. mutex_unlock(&priv->mutex);
  6111. return;
  6112. }
  6113. iwl4965_scan_cancel_timeout(priv, 200);
  6114. conf = ieee80211_get_hw_conf(priv->hw);
  6115. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  6116. iwl4965_commit_rxon(priv);
  6117. memset(&priv->rxon_timing, 0, sizeof(struct iwl4965_rxon_time_cmd));
  6118. iwl4965_setup_rxon_timing(priv);
  6119. rc = iwl4965_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  6120. sizeof(priv->rxon_timing), &priv->rxon_timing);
  6121. if (rc)
  6122. IWL_WARNING("REPLY_RXON_TIMING failed - "
  6123. "Attempting to continue.\n");
  6124. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  6125. #ifdef CONFIG_IWL4965_HT
  6126. if (priv->is_ht_enabled && priv->current_assoc_ht.is_ht)
  6127. iwl4965_set_rxon_ht(priv, &priv->current_assoc_ht);
  6128. else {
  6129. priv->active_rate_ht[0] = 0;
  6130. priv->active_rate_ht[1] = 0;
  6131. priv->current_channel_width = IWL_CHANNEL_WIDTH_20MHZ;
  6132. }
  6133. #endif /* CONFIG_IWL4965_HT*/
  6134. iwl4965_set_rxon_chain(priv);
  6135. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  6136. IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
  6137. priv->assoc_id, priv->beacon_int);
  6138. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  6139. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  6140. else
  6141. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  6142. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  6143. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  6144. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  6145. else
  6146. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  6147. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
  6148. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  6149. }
  6150. iwl4965_commit_rxon(priv);
  6151. switch (priv->iw_mode) {
  6152. case IEEE80211_IF_TYPE_STA:
  6153. iwl4965_rate_scale_init(priv->hw, IWL_AP_ID);
  6154. break;
  6155. case IEEE80211_IF_TYPE_IBSS:
  6156. /* clear out the station table */
  6157. iwl4965_clear_stations_table(priv);
  6158. iwl4965_rxon_add_station(priv, iwl4965_broadcast_addr, 0);
  6159. iwl4965_rxon_add_station(priv, priv->bssid, 0);
  6160. iwl4965_rate_scale_init(priv->hw, IWL_STA_ID);
  6161. iwl4965_send_beacon_cmd(priv);
  6162. break;
  6163. default:
  6164. IWL_ERROR("%s Should not be called in %d mode\n",
  6165. __FUNCTION__, priv->iw_mode);
  6166. break;
  6167. }
  6168. iwl4965_sequence_reset(priv);
  6169. #ifdef CONFIG_IWL4965_SENSITIVITY
  6170. /* Enable Rx differential gain and sensitivity calibrations */
  6171. iwl4965_chain_noise_reset(priv);
  6172. priv->start_calib = 1;
  6173. #endif /* CONFIG_IWL4965_SENSITIVITY */
  6174. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
  6175. priv->assoc_station_added = 1;
  6176. #ifdef CONFIG_IWL4965_QOS
  6177. iwl4965_activate_qos(priv, 0);
  6178. #endif /* CONFIG_IWL4965_QOS */
  6179. /* we have just associated, don't start scan too early */
  6180. priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
  6181. mutex_unlock(&priv->mutex);
  6182. }
  6183. static void iwl4965_bg_abort_scan(struct work_struct *work)
  6184. {
  6185. struct iwl4965_priv *priv = container_of(work, struct iwl4965_priv, abort_scan);
  6186. if (!iwl4965_is_ready(priv))
  6187. return;
  6188. mutex_lock(&priv->mutex);
  6189. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  6190. iwl4965_send_scan_abort(priv);
  6191. mutex_unlock(&priv->mutex);
  6192. }
  6193. static void iwl4965_bg_scan_completed(struct work_struct *work)
  6194. {
  6195. struct iwl4965_priv *priv =
  6196. container_of(work, struct iwl4965_priv, scan_completed);
  6197. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
  6198. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  6199. return;
  6200. ieee80211_scan_completed(priv->hw);
  6201. /* Since setting the TXPOWER may have been deferred while
  6202. * performing the scan, fire one off */
  6203. mutex_lock(&priv->mutex);
  6204. iwl4965_hw_reg_send_txpower(priv);
  6205. mutex_unlock(&priv->mutex);
  6206. }
  6207. /*****************************************************************************
  6208. *
  6209. * mac80211 entry point functions
  6210. *
  6211. *****************************************************************************/
  6212. static int iwl4965_mac_start(struct ieee80211_hw *hw)
  6213. {
  6214. struct iwl4965_priv *priv = hw->priv;
  6215. IWL_DEBUG_MAC80211("enter\n");
  6216. /* we should be verifying the device is ready to be opened */
  6217. mutex_lock(&priv->mutex);
  6218. priv->is_open = 1;
  6219. if (!iwl4965_is_rfkill(priv))
  6220. ieee80211_start_queues(priv->hw);
  6221. mutex_unlock(&priv->mutex);
  6222. IWL_DEBUG_MAC80211("leave\n");
  6223. return 0;
  6224. }
  6225. static void iwl4965_mac_stop(struct ieee80211_hw *hw)
  6226. {
  6227. struct iwl4965_priv *priv = hw->priv;
  6228. IWL_DEBUG_MAC80211("enter\n");
  6229. mutex_lock(&priv->mutex);
  6230. /* stop mac, cancel any scan request and clear
  6231. * RXON_FILTER_ASSOC_MSK BIT
  6232. */
  6233. priv->is_open = 0;
  6234. iwl4965_scan_cancel_timeout(priv, 100);
  6235. cancel_delayed_work(&priv->post_associate);
  6236. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  6237. iwl4965_commit_rxon(priv);
  6238. mutex_unlock(&priv->mutex);
  6239. IWL_DEBUG_MAC80211("leave\n");
  6240. }
  6241. static int iwl4965_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
  6242. struct ieee80211_tx_control *ctl)
  6243. {
  6244. struct iwl4965_priv *priv = hw->priv;
  6245. IWL_DEBUG_MAC80211("enter\n");
  6246. if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
  6247. IWL_DEBUG_MAC80211("leave - monitor\n");
  6248. return -1;
  6249. }
  6250. IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  6251. ctl->tx_rate);
  6252. if (iwl4965_tx_skb(priv, skb, ctl))
  6253. dev_kfree_skb_any(skb);
  6254. IWL_DEBUG_MAC80211("leave\n");
  6255. return 0;
  6256. }
  6257. static int iwl4965_mac_add_interface(struct ieee80211_hw *hw,
  6258. struct ieee80211_if_init_conf *conf)
  6259. {
  6260. struct iwl4965_priv *priv = hw->priv;
  6261. unsigned long flags;
  6262. DECLARE_MAC_BUF(mac);
  6263. IWL_DEBUG_MAC80211("enter: id %d, type %d\n", conf->if_id, conf->type);
  6264. if (priv->interface_id) {
  6265. IWL_DEBUG_MAC80211("leave - interface_id != 0\n");
  6266. return 0;
  6267. }
  6268. spin_lock_irqsave(&priv->lock, flags);
  6269. priv->interface_id = conf->if_id;
  6270. spin_unlock_irqrestore(&priv->lock, flags);
  6271. mutex_lock(&priv->mutex);
  6272. if (conf->mac_addr) {
  6273. IWL_DEBUG_MAC80211("Set %s\n", print_mac(mac, conf->mac_addr));
  6274. memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
  6275. }
  6276. iwl4965_set_mode(priv, conf->type);
  6277. IWL_DEBUG_MAC80211("leave\n");
  6278. mutex_unlock(&priv->mutex);
  6279. return 0;
  6280. }
  6281. /**
  6282. * iwl4965_mac_config - mac80211 config callback
  6283. *
  6284. * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
  6285. * be set inappropriately and the driver currently sets the hardware up to
  6286. * use it whenever needed.
  6287. */
  6288. static int iwl4965_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
  6289. {
  6290. struct iwl4965_priv *priv = hw->priv;
  6291. const struct iwl4965_channel_info *ch_info;
  6292. unsigned long flags;
  6293. mutex_lock(&priv->mutex);
  6294. IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel);
  6295. if (!iwl4965_is_ready(priv)) {
  6296. IWL_DEBUG_MAC80211("leave - not ready\n");
  6297. mutex_unlock(&priv->mutex);
  6298. return -EIO;
  6299. }
  6300. /* TODO: Figure out how to get ieee80211_local->sta_scanning w/ only
  6301. * what is exposed through include/ declarations */
  6302. if (unlikely(!iwl4965_param_disable_hw_scan &&
  6303. test_bit(STATUS_SCANNING, &priv->status))) {
  6304. IWL_DEBUG_MAC80211("leave - scanning\n");
  6305. mutex_unlock(&priv->mutex);
  6306. return 0;
  6307. }
  6308. spin_lock_irqsave(&priv->lock, flags);
  6309. ch_info = iwl4965_get_channel_info(priv, conf->phymode, conf->channel);
  6310. if (!is_channel_valid(ch_info)) {
  6311. IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this SKU.\n",
  6312. conf->channel, conf->phymode);
  6313. IWL_DEBUG_MAC80211("leave - invalid channel\n");
  6314. spin_unlock_irqrestore(&priv->lock, flags);
  6315. mutex_unlock(&priv->mutex);
  6316. return -EINVAL;
  6317. }
  6318. #ifdef CONFIG_IWL4965_HT
  6319. /* if we are switching fron ht to 2.4 clear flags
  6320. * from any ht related info since 2.4 does not
  6321. * support ht */
  6322. if ((le16_to_cpu(priv->staging_rxon.channel) != conf->channel)
  6323. #ifdef IEEE80211_CONF_CHANNEL_SWITCH
  6324. && !(conf->flags & IEEE80211_CONF_CHANNEL_SWITCH)
  6325. #endif
  6326. )
  6327. priv->staging_rxon.flags = 0;
  6328. #endif /* CONFIG_IWL4965_HT */
  6329. iwl4965_set_rxon_channel(priv, conf->phymode, conf->channel);
  6330. iwl4965_set_flags_for_phymode(priv, conf->phymode);
  6331. /* The list of supported rates and rate mask can be different
  6332. * for each phymode; since the phymode may have changed, reset
  6333. * the rate mask to what mac80211 lists */
  6334. iwl4965_set_rate(priv);
  6335. spin_unlock_irqrestore(&priv->lock, flags);
  6336. #ifdef IEEE80211_CONF_CHANNEL_SWITCH
  6337. if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
  6338. iwl4965_hw_channel_switch(priv, conf->channel);
  6339. mutex_unlock(&priv->mutex);
  6340. return 0;
  6341. }
  6342. #endif
  6343. iwl4965_radio_kill_sw(priv, !conf->radio_enabled);
  6344. if (!conf->radio_enabled) {
  6345. IWL_DEBUG_MAC80211("leave - radio disabled\n");
  6346. mutex_unlock(&priv->mutex);
  6347. return 0;
  6348. }
  6349. if (iwl4965_is_rfkill(priv)) {
  6350. IWL_DEBUG_MAC80211("leave - RF kill\n");
  6351. mutex_unlock(&priv->mutex);
  6352. return -EIO;
  6353. }
  6354. iwl4965_set_rate(priv);
  6355. if (memcmp(&priv->active_rxon,
  6356. &priv->staging_rxon, sizeof(priv->staging_rxon)))
  6357. iwl4965_commit_rxon(priv);
  6358. else
  6359. IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
  6360. IWL_DEBUG_MAC80211("leave\n");
  6361. mutex_unlock(&priv->mutex);
  6362. return 0;
  6363. }
  6364. static void iwl4965_config_ap(struct iwl4965_priv *priv)
  6365. {
  6366. int rc = 0;
  6367. if (priv->status & STATUS_EXIT_PENDING)
  6368. return;
  6369. /* The following should be done only at AP bring up */
  6370. if ((priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) == 0) {
  6371. /* RXON - unassoc (to set timing command) */
  6372. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  6373. iwl4965_commit_rxon(priv);
  6374. /* RXON Timing */
  6375. memset(&priv->rxon_timing, 0, sizeof(struct iwl4965_rxon_time_cmd));
  6376. iwl4965_setup_rxon_timing(priv);
  6377. rc = iwl4965_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  6378. sizeof(priv->rxon_timing), &priv->rxon_timing);
  6379. if (rc)
  6380. IWL_WARNING("REPLY_RXON_TIMING failed - "
  6381. "Attempting to continue.\n");
  6382. iwl4965_set_rxon_chain(priv);
  6383. /* FIXME: what should be the assoc_id for AP? */
  6384. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  6385. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  6386. priv->staging_rxon.flags |=
  6387. RXON_FLG_SHORT_PREAMBLE_MSK;
  6388. else
  6389. priv->staging_rxon.flags &=
  6390. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  6391. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  6392. if (priv->assoc_capability &
  6393. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  6394. priv->staging_rxon.flags |=
  6395. RXON_FLG_SHORT_SLOT_MSK;
  6396. else
  6397. priv->staging_rxon.flags &=
  6398. ~RXON_FLG_SHORT_SLOT_MSK;
  6399. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
  6400. priv->staging_rxon.flags &=
  6401. ~RXON_FLG_SHORT_SLOT_MSK;
  6402. }
  6403. /* restore RXON assoc */
  6404. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  6405. iwl4965_commit_rxon(priv);
  6406. #ifdef CONFIG_IWL4965_QOS
  6407. iwl4965_activate_qos(priv, 1);
  6408. #endif
  6409. iwl4965_rxon_add_station(priv, iwl4965_broadcast_addr, 0);
  6410. }
  6411. iwl4965_send_beacon_cmd(priv);
  6412. /* FIXME - we need to add code here to detect a totally new
  6413. * configuration, reset the AP, unassoc, rxon timing, assoc,
  6414. * clear sta table, add BCAST sta... */
  6415. }
  6416. static int iwl4965_mac_config_interface(struct ieee80211_hw *hw, int if_id,
  6417. struct ieee80211_if_conf *conf)
  6418. {
  6419. struct iwl4965_priv *priv = hw->priv;
  6420. DECLARE_MAC_BUF(mac);
  6421. unsigned long flags;
  6422. int rc;
  6423. if (conf == NULL)
  6424. return -EIO;
  6425. if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
  6426. (!conf->beacon || !conf->ssid_len)) {
  6427. IWL_DEBUG_MAC80211
  6428. ("Leaving in AP mode because HostAPD is not ready.\n");
  6429. return 0;
  6430. }
  6431. mutex_lock(&priv->mutex);
  6432. IWL_DEBUG_MAC80211("enter: interface id %d\n", if_id);
  6433. if (conf->bssid)
  6434. IWL_DEBUG_MAC80211("bssid: %s\n",
  6435. print_mac(mac, conf->bssid));
  6436. /*
  6437. * very dubious code was here; the probe filtering flag is never set:
  6438. *
  6439. if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
  6440. !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
  6441. */
  6442. if (unlikely(test_bit(STATUS_SCANNING, &priv->status))) {
  6443. IWL_DEBUG_MAC80211("leave - scanning\n");
  6444. mutex_unlock(&priv->mutex);
  6445. return 0;
  6446. }
  6447. if (priv->interface_id != if_id) {
  6448. IWL_DEBUG_MAC80211("leave - interface_id != if_id\n");
  6449. mutex_unlock(&priv->mutex);
  6450. return 0;
  6451. }
  6452. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  6453. if (!conf->bssid) {
  6454. conf->bssid = priv->mac_addr;
  6455. memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
  6456. IWL_DEBUG_MAC80211("bssid was set to: %s\n",
  6457. print_mac(mac, conf->bssid));
  6458. }
  6459. if (priv->ibss_beacon)
  6460. dev_kfree_skb(priv->ibss_beacon);
  6461. priv->ibss_beacon = conf->beacon;
  6462. }
  6463. if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
  6464. !is_multicast_ether_addr(conf->bssid)) {
  6465. /* If there is currently a HW scan going on in the background
  6466. * then we need to cancel it else the RXON below will fail. */
  6467. if (iwl4965_scan_cancel_timeout(priv, 100)) {
  6468. IWL_WARNING("Aborted scan still in progress "
  6469. "after 100ms\n");
  6470. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  6471. mutex_unlock(&priv->mutex);
  6472. return -EAGAIN;
  6473. }
  6474. memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN);
  6475. /* TODO: Audit driver for usage of these members and see
  6476. * if mac80211 deprecates them (priv->bssid looks like it
  6477. * shouldn't be there, but I haven't scanned the IBSS code
  6478. * to verify) - jpk */
  6479. memcpy(priv->bssid, conf->bssid, ETH_ALEN);
  6480. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  6481. iwl4965_config_ap(priv);
  6482. else {
  6483. rc = iwl4965_commit_rxon(priv);
  6484. if ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && rc)
  6485. iwl4965_rxon_add_station(
  6486. priv, priv->active_rxon.bssid_addr, 1);
  6487. }
  6488. } else {
  6489. iwl4965_scan_cancel_timeout(priv, 100);
  6490. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  6491. iwl4965_commit_rxon(priv);
  6492. }
  6493. spin_lock_irqsave(&priv->lock, flags);
  6494. if (!conf->ssid_len)
  6495. memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
  6496. else
  6497. memcpy(priv->essid, conf->ssid, conf->ssid_len);
  6498. priv->essid_len = conf->ssid_len;
  6499. spin_unlock_irqrestore(&priv->lock, flags);
  6500. IWL_DEBUG_MAC80211("leave\n");
  6501. mutex_unlock(&priv->mutex);
  6502. return 0;
  6503. }
  6504. static void iwl4965_configure_filter(struct ieee80211_hw *hw,
  6505. unsigned int changed_flags,
  6506. unsigned int *total_flags,
  6507. int mc_count, struct dev_addr_list *mc_list)
  6508. {
  6509. /*
  6510. * XXX: dummy
  6511. * see also iwl4965_connection_init_rx_config
  6512. */
  6513. *total_flags = 0;
  6514. }
  6515. static void iwl4965_mac_remove_interface(struct ieee80211_hw *hw,
  6516. struct ieee80211_if_init_conf *conf)
  6517. {
  6518. struct iwl4965_priv *priv = hw->priv;
  6519. IWL_DEBUG_MAC80211("enter\n");
  6520. mutex_lock(&priv->mutex);
  6521. iwl4965_scan_cancel_timeout(priv, 100);
  6522. cancel_delayed_work(&priv->post_associate);
  6523. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  6524. iwl4965_commit_rxon(priv);
  6525. if (priv->interface_id == conf->if_id) {
  6526. priv->interface_id = 0;
  6527. memset(priv->bssid, 0, ETH_ALEN);
  6528. memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
  6529. priv->essid_len = 0;
  6530. }
  6531. mutex_unlock(&priv->mutex);
  6532. IWL_DEBUG_MAC80211("leave\n");
  6533. }
  6534. static void iwl4965_mac_erp_ie_changed(struct ieee80211_hw *hw,
  6535. u8 changes, int cts_protection, int preamble)
  6536. {
  6537. struct iwl4965_priv *priv = hw->priv;
  6538. if (changes & IEEE80211_ERP_CHANGE_PREAMBLE) {
  6539. if (preamble == WLAN_ERP_PREAMBLE_SHORT)
  6540. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  6541. else
  6542. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  6543. }
  6544. if (changes & IEEE80211_ERP_CHANGE_PROTECTION) {
  6545. if (cts_protection && (priv->phymode != MODE_IEEE80211A))
  6546. priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
  6547. else
  6548. priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
  6549. }
  6550. if (iwl4965_is_associated(priv))
  6551. iwl4965_send_rxon_assoc(priv);
  6552. }
  6553. static int iwl4965_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
  6554. {
  6555. int rc = 0;
  6556. unsigned long flags;
  6557. struct iwl4965_priv *priv = hw->priv;
  6558. IWL_DEBUG_MAC80211("enter\n");
  6559. mutex_lock(&priv->mutex);
  6560. spin_lock_irqsave(&priv->lock, flags);
  6561. if (!iwl4965_is_ready_rf(priv)) {
  6562. rc = -EIO;
  6563. IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
  6564. goto out_unlock;
  6565. }
  6566. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { /* APs don't scan */
  6567. rc = -EIO;
  6568. IWL_ERROR("ERROR: APs don't scan\n");
  6569. goto out_unlock;
  6570. }
  6571. /* we don't schedule scan within next_scan_jiffies period */
  6572. if (priv->next_scan_jiffies &&
  6573. time_after(priv->next_scan_jiffies, jiffies)) {
  6574. rc = -EAGAIN;
  6575. goto out_unlock;
  6576. }
  6577. /* if we just finished scan ask for delay */
  6578. if (priv->last_scan_jiffies && time_after(priv->last_scan_jiffies +
  6579. IWL_DELAY_NEXT_SCAN, jiffies)) {
  6580. rc = -EAGAIN;
  6581. goto out_unlock;
  6582. }
  6583. if (len) {
  6584. IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
  6585. iwl4965_escape_essid(ssid, len), (int)len);
  6586. priv->one_direct_scan = 1;
  6587. priv->direct_ssid_len = (u8)
  6588. min((u8) len, (u8) IW_ESSID_MAX_SIZE);
  6589. memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
  6590. } else
  6591. priv->one_direct_scan = 0;
  6592. rc = iwl4965_scan_initiate(priv);
  6593. IWL_DEBUG_MAC80211("leave\n");
  6594. out_unlock:
  6595. spin_unlock_irqrestore(&priv->lock, flags);
  6596. mutex_unlock(&priv->mutex);
  6597. return rc;
  6598. }
  6599. static int iwl4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  6600. const u8 *local_addr, const u8 *addr,
  6601. struct ieee80211_key_conf *key)
  6602. {
  6603. struct iwl4965_priv *priv = hw->priv;
  6604. DECLARE_MAC_BUF(mac);
  6605. int rc = 0;
  6606. u8 sta_id;
  6607. IWL_DEBUG_MAC80211("enter\n");
  6608. if (!iwl4965_param_hwcrypto) {
  6609. IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
  6610. return -EOPNOTSUPP;
  6611. }
  6612. if (is_zero_ether_addr(addr))
  6613. /* only support pairwise keys */
  6614. return -EOPNOTSUPP;
  6615. sta_id = iwl4965_hw_find_station(priv, addr);
  6616. if (sta_id == IWL_INVALID_STATION) {
  6617. IWL_DEBUG_MAC80211("leave - %s not in station map.\n",
  6618. print_mac(mac, addr));
  6619. return -EINVAL;
  6620. }
  6621. mutex_lock(&priv->mutex);
  6622. iwl4965_scan_cancel_timeout(priv, 100);
  6623. switch (cmd) {
  6624. case SET_KEY:
  6625. rc = iwl4965_update_sta_key_info(priv, key, sta_id);
  6626. if (!rc) {
  6627. iwl4965_set_rxon_hwcrypto(priv, 1);
  6628. iwl4965_commit_rxon(priv);
  6629. key->hw_key_idx = sta_id;
  6630. IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
  6631. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  6632. }
  6633. break;
  6634. case DISABLE_KEY:
  6635. rc = iwl4965_clear_sta_key_info(priv, sta_id);
  6636. if (!rc) {
  6637. iwl4965_set_rxon_hwcrypto(priv, 0);
  6638. iwl4965_commit_rxon(priv);
  6639. IWL_DEBUG_MAC80211("disable hwcrypto key\n");
  6640. }
  6641. break;
  6642. default:
  6643. rc = -EINVAL;
  6644. }
  6645. IWL_DEBUG_MAC80211("leave\n");
  6646. mutex_unlock(&priv->mutex);
  6647. return rc;
  6648. }
  6649. static int iwl4965_mac_conf_tx(struct ieee80211_hw *hw, int queue,
  6650. const struct ieee80211_tx_queue_params *params)
  6651. {
  6652. struct iwl4965_priv *priv = hw->priv;
  6653. #ifdef CONFIG_IWL4965_QOS
  6654. unsigned long flags;
  6655. int q;
  6656. #endif /* CONFIG_IWL4965_QOS */
  6657. IWL_DEBUG_MAC80211("enter\n");
  6658. if (!iwl4965_is_ready_rf(priv)) {
  6659. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  6660. return -EIO;
  6661. }
  6662. if (queue >= AC_NUM) {
  6663. IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
  6664. return 0;
  6665. }
  6666. #ifdef CONFIG_IWL4965_QOS
  6667. if (!priv->qos_data.qos_enable) {
  6668. priv->qos_data.qos_active = 0;
  6669. IWL_DEBUG_MAC80211("leave - qos not enabled\n");
  6670. return 0;
  6671. }
  6672. q = AC_NUM - 1 - queue;
  6673. spin_lock_irqsave(&priv->lock, flags);
  6674. priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
  6675. priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
  6676. priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
  6677. priv->qos_data.def_qos_parm.ac[q].edca_txop =
  6678. cpu_to_le16((params->burst_time * 100));
  6679. priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
  6680. priv->qos_data.qos_active = 1;
  6681. spin_unlock_irqrestore(&priv->lock, flags);
  6682. mutex_lock(&priv->mutex);
  6683. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  6684. iwl4965_activate_qos(priv, 1);
  6685. else if (priv->assoc_id && iwl4965_is_associated(priv))
  6686. iwl4965_activate_qos(priv, 0);
  6687. mutex_unlock(&priv->mutex);
  6688. #endif /*CONFIG_IWL4965_QOS */
  6689. IWL_DEBUG_MAC80211("leave\n");
  6690. return 0;
  6691. }
  6692. static int iwl4965_mac_get_tx_stats(struct ieee80211_hw *hw,
  6693. struct ieee80211_tx_queue_stats *stats)
  6694. {
  6695. struct iwl4965_priv *priv = hw->priv;
  6696. int i, avail;
  6697. struct iwl4965_tx_queue *txq;
  6698. struct iwl4965_queue *q;
  6699. unsigned long flags;
  6700. IWL_DEBUG_MAC80211("enter\n");
  6701. if (!iwl4965_is_ready_rf(priv)) {
  6702. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  6703. return -EIO;
  6704. }
  6705. spin_lock_irqsave(&priv->lock, flags);
  6706. for (i = 0; i < AC_NUM; i++) {
  6707. txq = &priv->txq[i];
  6708. q = &txq->q;
  6709. avail = iwl4965_queue_space(q);
  6710. stats->data[i].len = q->n_window - avail;
  6711. stats->data[i].limit = q->n_window - q->high_mark;
  6712. stats->data[i].count = q->n_window;
  6713. }
  6714. spin_unlock_irqrestore(&priv->lock, flags);
  6715. IWL_DEBUG_MAC80211("leave\n");
  6716. return 0;
  6717. }
  6718. static int iwl4965_mac_get_stats(struct ieee80211_hw *hw,
  6719. struct ieee80211_low_level_stats *stats)
  6720. {
  6721. IWL_DEBUG_MAC80211("enter\n");
  6722. IWL_DEBUG_MAC80211("leave\n");
  6723. return 0;
  6724. }
  6725. static u64 iwl4965_mac_get_tsf(struct ieee80211_hw *hw)
  6726. {
  6727. IWL_DEBUG_MAC80211("enter\n");
  6728. IWL_DEBUG_MAC80211("leave\n");
  6729. return 0;
  6730. }
  6731. static void iwl4965_mac_reset_tsf(struct ieee80211_hw *hw)
  6732. {
  6733. struct iwl4965_priv *priv = hw->priv;
  6734. unsigned long flags;
  6735. mutex_lock(&priv->mutex);
  6736. IWL_DEBUG_MAC80211("enter\n");
  6737. priv->lq_mngr.lq_ready = 0;
  6738. #ifdef CONFIG_IWL4965_HT
  6739. spin_lock_irqsave(&priv->lock, flags);
  6740. memset(&priv->current_assoc_ht, 0, sizeof(struct sta_ht_info));
  6741. spin_unlock_irqrestore(&priv->lock, flags);
  6742. #ifdef CONFIG_IWL4965_HT_AGG
  6743. /* if (priv->lq_mngr.agg_ctrl.granted_ba)
  6744. iwl4965_turn_off_agg(priv, TID_ALL_SPECIFIED);*/
  6745. memset(&(priv->lq_mngr.agg_ctrl), 0, sizeof(struct iwl4965_agg_control));
  6746. priv->lq_mngr.agg_ctrl.tid_traffic_load_threshold = 10;
  6747. priv->lq_mngr.agg_ctrl.ba_timeout = 5000;
  6748. priv->lq_mngr.agg_ctrl.auto_agg = 1;
  6749. if (priv->lq_mngr.agg_ctrl.auto_agg)
  6750. priv->lq_mngr.agg_ctrl.requested_ba = TID_ALL_ENABLED;
  6751. #endif /*CONFIG_IWL4965_HT_AGG */
  6752. #endif /* CONFIG_IWL4965_HT */
  6753. #ifdef CONFIG_IWL4965_QOS
  6754. iwl4965_reset_qos(priv);
  6755. #endif
  6756. cancel_delayed_work(&priv->post_associate);
  6757. spin_lock_irqsave(&priv->lock, flags);
  6758. priv->assoc_id = 0;
  6759. priv->assoc_capability = 0;
  6760. priv->call_post_assoc_from_beacon = 0;
  6761. priv->assoc_station_added = 0;
  6762. /* new association get rid of ibss beacon skb */
  6763. if (priv->ibss_beacon)
  6764. dev_kfree_skb(priv->ibss_beacon);
  6765. priv->ibss_beacon = NULL;
  6766. priv->beacon_int = priv->hw->conf.beacon_int;
  6767. priv->timestamp1 = 0;
  6768. priv->timestamp0 = 0;
  6769. if ((priv->iw_mode == IEEE80211_IF_TYPE_STA))
  6770. priv->beacon_int = 0;
  6771. spin_unlock_irqrestore(&priv->lock, flags);
  6772. /* we are restarting association process
  6773. * clear RXON_FILTER_ASSOC_MSK bit
  6774. */
  6775. if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
  6776. iwl4965_scan_cancel_timeout(priv, 100);
  6777. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  6778. iwl4965_commit_rxon(priv);
  6779. }
  6780. /* Per mac80211.h: This is only used in IBSS mode... */
  6781. if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
  6782. IWL_DEBUG_MAC80211("leave - not in IBSS\n");
  6783. mutex_unlock(&priv->mutex);
  6784. return;
  6785. }
  6786. if (!iwl4965_is_ready_rf(priv)) {
  6787. IWL_DEBUG_MAC80211("leave - not ready\n");
  6788. mutex_unlock(&priv->mutex);
  6789. return;
  6790. }
  6791. priv->only_active_channel = 0;
  6792. iwl4965_set_rate(priv);
  6793. mutex_unlock(&priv->mutex);
  6794. IWL_DEBUG_MAC80211("leave\n");
  6795. }
  6796. static int iwl4965_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
  6797. struct ieee80211_tx_control *control)
  6798. {
  6799. struct iwl4965_priv *priv = hw->priv;
  6800. unsigned long flags;
  6801. mutex_lock(&priv->mutex);
  6802. IWL_DEBUG_MAC80211("enter\n");
  6803. if (!iwl4965_is_ready_rf(priv)) {
  6804. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  6805. mutex_unlock(&priv->mutex);
  6806. return -EIO;
  6807. }
  6808. if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
  6809. IWL_DEBUG_MAC80211("leave - not IBSS\n");
  6810. mutex_unlock(&priv->mutex);
  6811. return -EIO;
  6812. }
  6813. spin_lock_irqsave(&priv->lock, flags);
  6814. if (priv->ibss_beacon)
  6815. dev_kfree_skb(priv->ibss_beacon);
  6816. priv->ibss_beacon = skb;
  6817. priv->assoc_id = 0;
  6818. IWL_DEBUG_MAC80211("leave\n");
  6819. spin_unlock_irqrestore(&priv->lock, flags);
  6820. #ifdef CONFIG_IWL4965_QOS
  6821. iwl4965_reset_qos(priv);
  6822. #endif
  6823. queue_work(priv->workqueue, &priv->post_associate.work);
  6824. mutex_unlock(&priv->mutex);
  6825. return 0;
  6826. }
  6827. #ifdef CONFIG_IWL4965_HT
  6828. union ht_cap_info {
  6829. struct {
  6830. u16 advanced_coding_cap :1;
  6831. u16 supported_chan_width_set :1;
  6832. u16 mimo_power_save_mode :2;
  6833. u16 green_field :1;
  6834. u16 short_GI20 :1;
  6835. u16 short_GI40 :1;
  6836. u16 tx_stbc :1;
  6837. u16 rx_stbc :1;
  6838. u16 beam_forming :1;
  6839. u16 delayed_ba :1;
  6840. u16 maximal_amsdu_size :1;
  6841. u16 cck_mode_at_40MHz :1;
  6842. u16 psmp_support :1;
  6843. u16 stbc_ctrl_frame_support :1;
  6844. u16 sig_txop_protection_support :1;
  6845. };
  6846. u16 val;
  6847. } __attribute__ ((packed));
  6848. union ht_param_info{
  6849. struct {
  6850. u8 max_rx_ampdu_factor :2;
  6851. u8 mpdu_density :3;
  6852. u8 reserved :3;
  6853. };
  6854. u8 val;
  6855. } __attribute__ ((packed));
  6856. union ht_exra_param_info {
  6857. struct {
  6858. u8 ext_chan_offset :2;
  6859. u8 tx_chan_width :1;
  6860. u8 rifs_mode :1;
  6861. u8 controlled_access_only :1;
  6862. u8 service_interval_granularity :3;
  6863. };
  6864. u8 val;
  6865. } __attribute__ ((packed));
  6866. union ht_operation_mode{
  6867. struct {
  6868. u16 op_mode :2;
  6869. u16 non_GF :1;
  6870. u16 reserved :13;
  6871. };
  6872. u16 val;
  6873. } __attribute__ ((packed));
  6874. static int sta_ht_info_init(struct ieee80211_ht_capability *ht_cap,
  6875. struct ieee80211_ht_additional_info *ht_extra,
  6876. struct sta_ht_info *ht_info_ap,
  6877. struct sta_ht_info *ht_info)
  6878. {
  6879. union ht_cap_info cap;
  6880. union ht_operation_mode op_mode;
  6881. union ht_param_info param_info;
  6882. union ht_exra_param_info extra_param_info;
  6883. IWL_DEBUG_MAC80211("enter: \n");
  6884. if (!ht_info) {
  6885. IWL_DEBUG_MAC80211("leave: ht_info is NULL\n");
  6886. return -1;
  6887. }
  6888. if (ht_cap) {
  6889. cap.val = (u16) le16_to_cpu(ht_cap->capabilities_info);
  6890. param_info.val = ht_cap->mac_ht_params_info;
  6891. ht_info->is_ht = 1;
  6892. if (cap.short_GI20)
  6893. ht_info->sgf |= 0x1;
  6894. if (cap.short_GI40)
  6895. ht_info->sgf |= 0x2;
  6896. ht_info->is_green_field = cap.green_field;
  6897. ht_info->max_amsdu_size = cap.maximal_amsdu_size;
  6898. ht_info->supported_chan_width = cap.supported_chan_width_set;
  6899. ht_info->tx_mimo_ps_mode = cap.mimo_power_save_mode;
  6900. memcpy(ht_info->supp_rates, ht_cap->supported_mcs_set, 16);
  6901. ht_info->ampdu_factor = param_info.max_rx_ampdu_factor;
  6902. ht_info->mpdu_density = param_info.mpdu_density;
  6903. IWL_DEBUG_MAC80211("SISO mask 0x%X MIMO mask 0x%X \n",
  6904. ht_cap->supported_mcs_set[0],
  6905. ht_cap->supported_mcs_set[1]);
  6906. if (ht_info_ap) {
  6907. ht_info->control_channel = ht_info_ap->control_channel;
  6908. ht_info->extension_chan_offset =
  6909. ht_info_ap->extension_chan_offset;
  6910. ht_info->tx_chan_width = ht_info_ap->tx_chan_width;
  6911. ht_info->operating_mode = ht_info_ap->operating_mode;
  6912. }
  6913. if (ht_extra) {
  6914. extra_param_info.val = ht_extra->ht_param;
  6915. ht_info->control_channel = ht_extra->control_chan;
  6916. ht_info->extension_chan_offset =
  6917. extra_param_info.ext_chan_offset;
  6918. ht_info->tx_chan_width = extra_param_info.tx_chan_width;
  6919. op_mode.val = (u16)
  6920. le16_to_cpu(ht_extra->operation_mode);
  6921. ht_info->operating_mode = op_mode.op_mode;
  6922. IWL_DEBUG_MAC80211("control channel %d\n",
  6923. ht_extra->control_chan);
  6924. }
  6925. } else
  6926. ht_info->is_ht = 0;
  6927. IWL_DEBUG_MAC80211("leave\n");
  6928. return 0;
  6929. }
  6930. static int iwl4965_mac_conf_ht(struct ieee80211_hw *hw,
  6931. struct ieee80211_ht_capability *ht_cap,
  6932. struct ieee80211_ht_additional_info *ht_extra)
  6933. {
  6934. struct iwl4965_priv *priv = hw->priv;
  6935. int rs;
  6936. IWL_DEBUG_MAC80211("enter: \n");
  6937. rs = sta_ht_info_init(ht_cap, ht_extra, NULL, &priv->current_assoc_ht);
  6938. iwl4965_set_rxon_chain(priv);
  6939. if (priv && priv->assoc_id &&
  6940. (priv->iw_mode == IEEE80211_IF_TYPE_STA)) {
  6941. unsigned long flags;
  6942. spin_lock_irqsave(&priv->lock, flags);
  6943. if (priv->beacon_int)
  6944. queue_work(priv->workqueue, &priv->post_associate.work);
  6945. else
  6946. priv->call_post_assoc_from_beacon = 1;
  6947. spin_unlock_irqrestore(&priv->lock, flags);
  6948. }
  6949. IWL_DEBUG_MAC80211("leave: control channel %d\n",
  6950. ht_extra->control_chan);
  6951. return rs;
  6952. }
  6953. static void iwl4965_set_ht_capab(struct ieee80211_hw *hw,
  6954. struct ieee80211_ht_capability *ht_cap,
  6955. u8 use_wide_chan)
  6956. {
  6957. union ht_cap_info cap;
  6958. union ht_param_info param_info;
  6959. memset(&cap, 0, sizeof(union ht_cap_info));
  6960. memset(&param_info, 0, sizeof(union ht_param_info));
  6961. cap.maximal_amsdu_size = HT_IE_MAX_AMSDU_SIZE_4K;
  6962. cap.green_field = 1;
  6963. cap.short_GI20 = 1;
  6964. cap.short_GI40 = 1;
  6965. cap.supported_chan_width_set = use_wide_chan;
  6966. cap.mimo_power_save_mode = 0x3;
  6967. param_info.max_rx_ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
  6968. param_info.mpdu_density = CFG_HT_MPDU_DENSITY_DEF;
  6969. ht_cap->capabilities_info = (__le16) cpu_to_le16(cap.val);
  6970. ht_cap->mac_ht_params_info = (u8) param_info.val;
  6971. ht_cap->supported_mcs_set[0] = 0xff;
  6972. ht_cap->supported_mcs_set[1] = 0xff;
  6973. ht_cap->supported_mcs_set[4] =
  6974. (cap.supported_chan_width_set) ? 0x1: 0x0;
  6975. }
  6976. static void iwl4965_mac_get_ht_capab(struct ieee80211_hw *hw,
  6977. struct ieee80211_ht_capability *ht_cap)
  6978. {
  6979. u8 use_wide_channel = 1;
  6980. struct iwl4965_priv *priv = hw->priv;
  6981. IWL_DEBUG_MAC80211("enter: \n");
  6982. if (priv->channel_width != IWL_CHANNEL_WIDTH_40MHZ)
  6983. use_wide_channel = 0;
  6984. /* no fat tx allowed on 2.4GHZ */
  6985. if (priv->phymode != MODE_IEEE80211A)
  6986. use_wide_channel = 0;
  6987. iwl4965_set_ht_capab(hw, ht_cap, use_wide_channel);
  6988. IWL_DEBUG_MAC80211("leave: \n");
  6989. }
  6990. #endif /*CONFIG_IWL4965_HT*/
  6991. /*****************************************************************************
  6992. *
  6993. * sysfs attributes
  6994. *
  6995. *****************************************************************************/
  6996. #ifdef CONFIG_IWL4965_DEBUG
  6997. /*
  6998. * The following adds a new attribute to the sysfs representation
  6999. * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
  7000. * used for controlling the debug level.
  7001. *
  7002. * See the level definitions in iwl for details.
  7003. */
  7004. static ssize_t show_debug_level(struct device_driver *d, char *buf)
  7005. {
  7006. return sprintf(buf, "0x%08X\n", iwl4965_debug_level);
  7007. }
  7008. static ssize_t store_debug_level(struct device_driver *d,
  7009. const char *buf, size_t count)
  7010. {
  7011. char *p = (char *)buf;
  7012. u32 val;
  7013. val = simple_strtoul(p, &p, 0);
  7014. if (p == buf)
  7015. printk(KERN_INFO DRV_NAME
  7016. ": %s is not in hex or decimal form.\n", buf);
  7017. else
  7018. iwl4965_debug_level = val;
  7019. return strnlen(buf, count);
  7020. }
  7021. static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO,
  7022. show_debug_level, store_debug_level);
  7023. #endif /* CONFIG_IWL4965_DEBUG */
  7024. static ssize_t show_rf_kill(struct device *d,
  7025. struct device_attribute *attr, char *buf)
  7026. {
  7027. /*
  7028. * 0 - RF kill not enabled
  7029. * 1 - SW based RF kill active (sysfs)
  7030. * 2 - HW based RF kill active
  7031. * 3 - Both HW and SW based RF kill active
  7032. */
  7033. struct iwl4965_priv *priv = (struct iwl4965_priv *)d->driver_data;
  7034. int val = (test_bit(STATUS_RF_KILL_SW, &priv->status) ? 0x1 : 0x0) |
  7035. (test_bit(STATUS_RF_KILL_HW, &priv->status) ? 0x2 : 0x0);
  7036. return sprintf(buf, "%i\n", val);
  7037. }
  7038. static ssize_t store_rf_kill(struct device *d,
  7039. struct device_attribute *attr,
  7040. const char *buf, size_t count)
  7041. {
  7042. struct iwl4965_priv *priv = (struct iwl4965_priv *)d->driver_data;
  7043. mutex_lock(&priv->mutex);
  7044. iwl4965_radio_kill_sw(priv, buf[0] == '1');
  7045. mutex_unlock(&priv->mutex);
  7046. return count;
  7047. }
  7048. static DEVICE_ATTR(rf_kill, S_IWUSR | S_IRUGO, show_rf_kill, store_rf_kill);
  7049. static ssize_t show_temperature(struct device *d,
  7050. struct device_attribute *attr, char *buf)
  7051. {
  7052. struct iwl4965_priv *priv = (struct iwl4965_priv *)d->driver_data;
  7053. if (!iwl4965_is_alive(priv))
  7054. return -EAGAIN;
  7055. return sprintf(buf, "%d\n", iwl4965_hw_get_temperature(priv));
  7056. }
  7057. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  7058. static ssize_t show_rs_window(struct device *d,
  7059. struct device_attribute *attr,
  7060. char *buf)
  7061. {
  7062. struct iwl4965_priv *priv = d->driver_data;
  7063. return iwl4965_fill_rs_info(priv->hw, buf, IWL_AP_ID);
  7064. }
  7065. static DEVICE_ATTR(rs_window, S_IRUGO, show_rs_window, NULL);
  7066. static ssize_t show_tx_power(struct device *d,
  7067. struct device_attribute *attr, char *buf)
  7068. {
  7069. struct iwl4965_priv *priv = (struct iwl4965_priv *)d->driver_data;
  7070. return sprintf(buf, "%d\n", priv->user_txpower_limit);
  7071. }
  7072. static ssize_t store_tx_power(struct device *d,
  7073. struct device_attribute *attr,
  7074. const char *buf, size_t count)
  7075. {
  7076. struct iwl4965_priv *priv = (struct iwl4965_priv *)d->driver_data;
  7077. char *p = (char *)buf;
  7078. u32 val;
  7079. val = simple_strtoul(p, &p, 10);
  7080. if (p == buf)
  7081. printk(KERN_INFO DRV_NAME
  7082. ": %s is not in decimal form.\n", buf);
  7083. else
  7084. iwl4965_hw_reg_set_txpower(priv, val);
  7085. return count;
  7086. }
  7087. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  7088. static ssize_t show_flags(struct device *d,
  7089. struct device_attribute *attr, char *buf)
  7090. {
  7091. struct iwl4965_priv *priv = (struct iwl4965_priv *)d->driver_data;
  7092. return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
  7093. }
  7094. static ssize_t store_flags(struct device *d,
  7095. struct device_attribute *attr,
  7096. const char *buf, size_t count)
  7097. {
  7098. struct iwl4965_priv *priv = (struct iwl4965_priv *)d->driver_data;
  7099. u32 flags = simple_strtoul(buf, NULL, 0);
  7100. mutex_lock(&priv->mutex);
  7101. if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
  7102. /* Cancel any currently running scans... */
  7103. if (iwl4965_scan_cancel_timeout(priv, 100))
  7104. IWL_WARNING("Could not cancel scan.\n");
  7105. else {
  7106. IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
  7107. flags);
  7108. priv->staging_rxon.flags = cpu_to_le32(flags);
  7109. iwl4965_commit_rxon(priv);
  7110. }
  7111. }
  7112. mutex_unlock(&priv->mutex);
  7113. return count;
  7114. }
  7115. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  7116. static ssize_t show_filter_flags(struct device *d,
  7117. struct device_attribute *attr, char *buf)
  7118. {
  7119. struct iwl4965_priv *priv = (struct iwl4965_priv *)d->driver_data;
  7120. return sprintf(buf, "0x%04X\n",
  7121. le32_to_cpu(priv->active_rxon.filter_flags));
  7122. }
  7123. static ssize_t store_filter_flags(struct device *d,
  7124. struct device_attribute *attr,
  7125. const char *buf, size_t count)
  7126. {
  7127. struct iwl4965_priv *priv = (struct iwl4965_priv *)d->driver_data;
  7128. u32 filter_flags = simple_strtoul(buf, NULL, 0);
  7129. mutex_lock(&priv->mutex);
  7130. if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
  7131. /* Cancel any currently running scans... */
  7132. if (iwl4965_scan_cancel_timeout(priv, 100))
  7133. IWL_WARNING("Could not cancel scan.\n");
  7134. else {
  7135. IWL_DEBUG_INFO("Committing rxon.filter_flags = "
  7136. "0x%04X\n", filter_flags);
  7137. priv->staging_rxon.filter_flags =
  7138. cpu_to_le32(filter_flags);
  7139. iwl4965_commit_rxon(priv);
  7140. }
  7141. }
  7142. mutex_unlock(&priv->mutex);
  7143. return count;
  7144. }
  7145. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  7146. store_filter_flags);
  7147. static ssize_t show_tune(struct device *d,
  7148. struct device_attribute *attr, char *buf)
  7149. {
  7150. struct iwl4965_priv *priv = (struct iwl4965_priv *)d->driver_data;
  7151. return sprintf(buf, "0x%04X\n",
  7152. (priv->phymode << 8) |
  7153. le16_to_cpu(priv->active_rxon.channel));
  7154. }
  7155. static void iwl4965_set_flags_for_phymode(struct iwl4965_priv *priv, u8 phymode);
  7156. static ssize_t store_tune(struct device *d,
  7157. struct device_attribute *attr,
  7158. const char *buf, size_t count)
  7159. {
  7160. struct iwl4965_priv *priv = (struct iwl4965_priv *)d->driver_data;
  7161. char *p = (char *)buf;
  7162. u16 tune = simple_strtoul(p, &p, 0);
  7163. u8 phymode = (tune >> 8) & 0xff;
  7164. u16 channel = tune & 0xff;
  7165. IWL_DEBUG_INFO("Tune request to:%d channel:%d\n", phymode, channel);
  7166. mutex_lock(&priv->mutex);
  7167. if ((le16_to_cpu(priv->staging_rxon.channel) != channel) ||
  7168. (priv->phymode != phymode)) {
  7169. const struct iwl4965_channel_info *ch_info;
  7170. ch_info = iwl4965_get_channel_info(priv, phymode, channel);
  7171. if (!ch_info) {
  7172. IWL_WARNING("Requested invalid phymode/channel "
  7173. "combination: %d %d\n", phymode, channel);
  7174. mutex_unlock(&priv->mutex);
  7175. return -EINVAL;
  7176. }
  7177. /* Cancel any currently running scans... */
  7178. if (iwl4965_scan_cancel_timeout(priv, 100))
  7179. IWL_WARNING("Could not cancel scan.\n");
  7180. else {
  7181. IWL_DEBUG_INFO("Committing phymode and "
  7182. "rxon.channel = %d %d\n",
  7183. phymode, channel);
  7184. iwl4965_set_rxon_channel(priv, phymode, channel);
  7185. iwl4965_set_flags_for_phymode(priv, phymode);
  7186. iwl4965_set_rate(priv);
  7187. iwl4965_commit_rxon(priv);
  7188. }
  7189. }
  7190. mutex_unlock(&priv->mutex);
  7191. return count;
  7192. }
  7193. static DEVICE_ATTR(tune, S_IWUSR | S_IRUGO, show_tune, store_tune);
  7194. #ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT
  7195. static ssize_t show_measurement(struct device *d,
  7196. struct device_attribute *attr, char *buf)
  7197. {
  7198. struct iwl4965_priv *priv = dev_get_drvdata(d);
  7199. struct iwl4965_spectrum_notification measure_report;
  7200. u32 size = sizeof(measure_report), len = 0, ofs = 0;
  7201. u8 *data = (u8 *) & measure_report;
  7202. unsigned long flags;
  7203. spin_lock_irqsave(&priv->lock, flags);
  7204. if (!(priv->measurement_status & MEASUREMENT_READY)) {
  7205. spin_unlock_irqrestore(&priv->lock, flags);
  7206. return 0;
  7207. }
  7208. memcpy(&measure_report, &priv->measure_report, size);
  7209. priv->measurement_status = 0;
  7210. spin_unlock_irqrestore(&priv->lock, flags);
  7211. while (size && (PAGE_SIZE - len)) {
  7212. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  7213. PAGE_SIZE - len, 1);
  7214. len = strlen(buf);
  7215. if (PAGE_SIZE - len)
  7216. buf[len++] = '\n';
  7217. ofs += 16;
  7218. size -= min(size, 16U);
  7219. }
  7220. return len;
  7221. }
  7222. static ssize_t store_measurement(struct device *d,
  7223. struct device_attribute *attr,
  7224. const char *buf, size_t count)
  7225. {
  7226. struct iwl4965_priv *priv = dev_get_drvdata(d);
  7227. struct ieee80211_measurement_params params = {
  7228. .channel = le16_to_cpu(priv->active_rxon.channel),
  7229. .start_time = cpu_to_le64(priv->last_tsf),
  7230. .duration = cpu_to_le16(1),
  7231. };
  7232. u8 type = IWL_MEASURE_BASIC;
  7233. u8 buffer[32];
  7234. u8 channel;
  7235. if (count) {
  7236. char *p = buffer;
  7237. strncpy(buffer, buf, min(sizeof(buffer), count));
  7238. channel = simple_strtoul(p, NULL, 0);
  7239. if (channel)
  7240. params.channel = channel;
  7241. p = buffer;
  7242. while (*p && *p != ' ')
  7243. p++;
  7244. if (*p)
  7245. type = simple_strtoul(p + 1, NULL, 0);
  7246. }
  7247. IWL_DEBUG_INFO("Invoking measurement of type %d on "
  7248. "channel %d (for '%s')\n", type, params.channel, buf);
  7249. iwl4965_get_measurement(priv, &params, type);
  7250. return count;
  7251. }
  7252. static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
  7253. show_measurement, store_measurement);
  7254. #endif /* CONFIG_IWL4965_SPECTRUM_MEASUREMENT */
  7255. static ssize_t store_retry_rate(struct device *d,
  7256. struct device_attribute *attr,
  7257. const char *buf, size_t count)
  7258. {
  7259. struct iwl4965_priv *priv = dev_get_drvdata(d);
  7260. priv->retry_rate = simple_strtoul(buf, NULL, 0);
  7261. if (priv->retry_rate <= 0)
  7262. priv->retry_rate = 1;
  7263. return count;
  7264. }
  7265. static ssize_t show_retry_rate(struct device *d,
  7266. struct device_attribute *attr, char *buf)
  7267. {
  7268. struct iwl4965_priv *priv = dev_get_drvdata(d);
  7269. return sprintf(buf, "%d", priv->retry_rate);
  7270. }
  7271. static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
  7272. store_retry_rate);
  7273. static ssize_t store_power_level(struct device *d,
  7274. struct device_attribute *attr,
  7275. const char *buf, size_t count)
  7276. {
  7277. struct iwl4965_priv *priv = dev_get_drvdata(d);
  7278. int rc;
  7279. int mode;
  7280. mode = simple_strtoul(buf, NULL, 0);
  7281. mutex_lock(&priv->mutex);
  7282. if (!iwl4965_is_ready(priv)) {
  7283. rc = -EAGAIN;
  7284. goto out;
  7285. }
  7286. if ((mode < 1) || (mode > IWL_POWER_LIMIT) || (mode == IWL_POWER_AC))
  7287. mode = IWL_POWER_AC;
  7288. else
  7289. mode |= IWL_POWER_ENABLED;
  7290. if (mode != priv->power_mode) {
  7291. rc = iwl4965_send_power_mode(priv, IWL_POWER_LEVEL(mode));
  7292. if (rc) {
  7293. IWL_DEBUG_MAC80211("failed setting power mode.\n");
  7294. goto out;
  7295. }
  7296. priv->power_mode = mode;
  7297. }
  7298. rc = count;
  7299. out:
  7300. mutex_unlock(&priv->mutex);
  7301. return rc;
  7302. }
  7303. #define MAX_WX_STRING 80
  7304. /* Values are in microsecond */
  7305. static const s32 timeout_duration[] = {
  7306. 350000,
  7307. 250000,
  7308. 75000,
  7309. 37000,
  7310. 25000,
  7311. };
  7312. static const s32 period_duration[] = {
  7313. 400000,
  7314. 700000,
  7315. 1000000,
  7316. 1000000,
  7317. 1000000
  7318. };
  7319. static ssize_t show_power_level(struct device *d,
  7320. struct device_attribute *attr, char *buf)
  7321. {
  7322. struct iwl4965_priv *priv = dev_get_drvdata(d);
  7323. int level = IWL_POWER_LEVEL(priv->power_mode);
  7324. char *p = buf;
  7325. p += sprintf(p, "%d ", level);
  7326. switch (level) {
  7327. case IWL_POWER_MODE_CAM:
  7328. case IWL_POWER_AC:
  7329. p += sprintf(p, "(AC)");
  7330. break;
  7331. case IWL_POWER_BATTERY:
  7332. p += sprintf(p, "(BATTERY)");
  7333. break;
  7334. default:
  7335. p += sprintf(p,
  7336. "(Timeout %dms, Period %dms)",
  7337. timeout_duration[level - 1] / 1000,
  7338. period_duration[level - 1] / 1000);
  7339. }
  7340. if (!(priv->power_mode & IWL_POWER_ENABLED))
  7341. p += sprintf(p, " OFF\n");
  7342. else
  7343. p += sprintf(p, " \n");
  7344. return (p - buf + 1);
  7345. }
  7346. static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
  7347. store_power_level);
  7348. static ssize_t show_channels(struct device *d,
  7349. struct device_attribute *attr, char *buf)
  7350. {
  7351. struct iwl4965_priv *priv = dev_get_drvdata(d);
  7352. int len = 0, i;
  7353. struct ieee80211_channel *channels = NULL;
  7354. const struct ieee80211_hw_mode *hw_mode = NULL;
  7355. int count = 0;
  7356. if (!iwl4965_is_ready(priv))
  7357. return -EAGAIN;
  7358. hw_mode = iwl4965_get_hw_mode(priv, MODE_IEEE80211G);
  7359. if (!hw_mode)
  7360. hw_mode = iwl4965_get_hw_mode(priv, MODE_IEEE80211B);
  7361. if (hw_mode) {
  7362. channels = hw_mode->channels;
  7363. count = hw_mode->num_channels;
  7364. }
  7365. len +=
  7366. sprintf(&buf[len],
  7367. "Displaying %d channels in 2.4GHz band "
  7368. "(802.11bg):\n", count);
  7369. for (i = 0; i < count; i++)
  7370. len += sprintf(&buf[len], "%d: %ddBm: BSS%s%s, %s.\n",
  7371. channels[i].chan,
  7372. channels[i].power_level,
  7373. channels[i].
  7374. flag & IEEE80211_CHAN_W_RADAR_DETECT ?
  7375. " (IEEE 802.11h required)" : "",
  7376. (!(channels[i].flag & IEEE80211_CHAN_W_IBSS)
  7377. || (channels[i].
  7378. flag &
  7379. IEEE80211_CHAN_W_RADAR_DETECT)) ? "" :
  7380. ", IBSS",
  7381. channels[i].
  7382. flag & IEEE80211_CHAN_W_ACTIVE_SCAN ?
  7383. "active/passive" : "passive only");
  7384. hw_mode = iwl4965_get_hw_mode(priv, MODE_IEEE80211A);
  7385. if (hw_mode) {
  7386. channels = hw_mode->channels;
  7387. count = hw_mode->num_channels;
  7388. } else {
  7389. channels = NULL;
  7390. count = 0;
  7391. }
  7392. len += sprintf(&buf[len], "Displaying %d channels in 5.2GHz band "
  7393. "(802.11a):\n", count);
  7394. for (i = 0; i < count; i++)
  7395. len += sprintf(&buf[len], "%d: %ddBm: BSS%s%s, %s.\n",
  7396. channels[i].chan,
  7397. channels[i].power_level,
  7398. channels[i].
  7399. flag & IEEE80211_CHAN_W_RADAR_DETECT ?
  7400. " (IEEE 802.11h required)" : "",
  7401. (!(channels[i].flag & IEEE80211_CHAN_W_IBSS)
  7402. || (channels[i].
  7403. flag &
  7404. IEEE80211_CHAN_W_RADAR_DETECT)) ? "" :
  7405. ", IBSS",
  7406. channels[i].
  7407. flag & IEEE80211_CHAN_W_ACTIVE_SCAN ?
  7408. "active/passive" : "passive only");
  7409. return len;
  7410. }
  7411. static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
  7412. static ssize_t show_statistics(struct device *d,
  7413. struct device_attribute *attr, char *buf)
  7414. {
  7415. struct iwl4965_priv *priv = dev_get_drvdata(d);
  7416. u32 size = sizeof(struct iwl4965_notif_statistics);
  7417. u32 len = 0, ofs = 0;
  7418. u8 *data = (u8 *) & priv->statistics;
  7419. int rc = 0;
  7420. if (!iwl4965_is_alive(priv))
  7421. return -EAGAIN;
  7422. mutex_lock(&priv->mutex);
  7423. rc = iwl4965_send_statistics_request(priv);
  7424. mutex_unlock(&priv->mutex);
  7425. if (rc) {
  7426. len = sprintf(buf,
  7427. "Error sending statistics request: 0x%08X\n", rc);
  7428. return len;
  7429. }
  7430. while (size && (PAGE_SIZE - len)) {
  7431. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  7432. PAGE_SIZE - len, 1);
  7433. len = strlen(buf);
  7434. if (PAGE_SIZE - len)
  7435. buf[len++] = '\n';
  7436. ofs += 16;
  7437. size -= min(size, 16U);
  7438. }
  7439. return len;
  7440. }
  7441. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  7442. static ssize_t show_antenna(struct device *d,
  7443. struct device_attribute *attr, char *buf)
  7444. {
  7445. struct iwl4965_priv *priv = dev_get_drvdata(d);
  7446. if (!iwl4965_is_alive(priv))
  7447. return -EAGAIN;
  7448. return sprintf(buf, "%d\n", priv->antenna);
  7449. }
  7450. static ssize_t store_antenna(struct device *d,
  7451. struct device_attribute *attr,
  7452. const char *buf, size_t count)
  7453. {
  7454. int ant;
  7455. struct iwl4965_priv *priv = dev_get_drvdata(d);
  7456. if (count == 0)
  7457. return 0;
  7458. if (sscanf(buf, "%1i", &ant) != 1) {
  7459. IWL_DEBUG_INFO("not in hex or decimal form.\n");
  7460. return count;
  7461. }
  7462. if ((ant >= 0) && (ant <= 2)) {
  7463. IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
  7464. priv->antenna = (enum iwl4965_antenna)ant;
  7465. } else
  7466. IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
  7467. return count;
  7468. }
  7469. static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
  7470. static ssize_t show_status(struct device *d,
  7471. struct device_attribute *attr, char *buf)
  7472. {
  7473. struct iwl4965_priv *priv = (struct iwl4965_priv *)d->driver_data;
  7474. if (!iwl4965_is_alive(priv))
  7475. return -EAGAIN;
  7476. return sprintf(buf, "0x%08x\n", (int)priv->status);
  7477. }
  7478. static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
  7479. static ssize_t dump_error_log(struct device *d,
  7480. struct device_attribute *attr,
  7481. const char *buf, size_t count)
  7482. {
  7483. char *p = (char *)buf;
  7484. if (p[0] == '1')
  7485. iwl4965_dump_nic_error_log((struct iwl4965_priv *)d->driver_data);
  7486. return strnlen(buf, count);
  7487. }
  7488. static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
  7489. static ssize_t dump_event_log(struct device *d,
  7490. struct device_attribute *attr,
  7491. const char *buf, size_t count)
  7492. {
  7493. char *p = (char *)buf;
  7494. if (p[0] == '1')
  7495. iwl4965_dump_nic_event_log((struct iwl4965_priv *)d->driver_data);
  7496. return strnlen(buf, count);
  7497. }
  7498. static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
  7499. /*****************************************************************************
  7500. *
  7501. * driver setup and teardown
  7502. *
  7503. *****************************************************************************/
  7504. static void iwl4965_setup_deferred_work(struct iwl4965_priv *priv)
  7505. {
  7506. priv->workqueue = create_workqueue(DRV_NAME);
  7507. init_waitqueue_head(&priv->wait_command_queue);
  7508. INIT_WORK(&priv->up, iwl4965_bg_up);
  7509. INIT_WORK(&priv->restart, iwl4965_bg_restart);
  7510. INIT_WORK(&priv->rx_replenish, iwl4965_bg_rx_replenish);
  7511. INIT_WORK(&priv->scan_completed, iwl4965_bg_scan_completed);
  7512. INIT_WORK(&priv->request_scan, iwl4965_bg_request_scan);
  7513. INIT_WORK(&priv->abort_scan, iwl4965_bg_abort_scan);
  7514. INIT_WORK(&priv->rf_kill, iwl4965_bg_rf_kill);
  7515. INIT_WORK(&priv->beacon_update, iwl4965_bg_beacon_update);
  7516. INIT_DELAYED_WORK(&priv->post_associate, iwl4965_bg_post_associate);
  7517. INIT_DELAYED_WORK(&priv->init_alive_start, iwl4965_bg_init_alive_start);
  7518. INIT_DELAYED_WORK(&priv->alive_start, iwl4965_bg_alive_start);
  7519. INIT_DELAYED_WORK(&priv->scan_check, iwl4965_bg_scan_check);
  7520. iwl4965_hw_setup_deferred_work(priv);
  7521. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  7522. iwl4965_irq_tasklet, (unsigned long)priv);
  7523. }
  7524. static void iwl4965_cancel_deferred_work(struct iwl4965_priv *priv)
  7525. {
  7526. iwl4965_hw_cancel_deferred_work(priv);
  7527. cancel_delayed_work_sync(&priv->init_alive_start);
  7528. cancel_delayed_work(&priv->scan_check);
  7529. cancel_delayed_work(&priv->alive_start);
  7530. cancel_delayed_work(&priv->post_associate);
  7531. cancel_work_sync(&priv->beacon_update);
  7532. }
  7533. static struct attribute *iwl4965_sysfs_entries[] = {
  7534. &dev_attr_antenna.attr,
  7535. &dev_attr_channels.attr,
  7536. &dev_attr_dump_errors.attr,
  7537. &dev_attr_dump_events.attr,
  7538. &dev_attr_flags.attr,
  7539. &dev_attr_filter_flags.attr,
  7540. #ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT
  7541. &dev_attr_measurement.attr,
  7542. #endif
  7543. &dev_attr_power_level.attr,
  7544. &dev_attr_retry_rate.attr,
  7545. &dev_attr_rf_kill.attr,
  7546. &dev_attr_rs_window.attr,
  7547. &dev_attr_statistics.attr,
  7548. &dev_attr_status.attr,
  7549. &dev_attr_temperature.attr,
  7550. &dev_attr_tune.attr,
  7551. &dev_attr_tx_power.attr,
  7552. NULL
  7553. };
  7554. static struct attribute_group iwl4965_attribute_group = {
  7555. .name = NULL, /* put in device directory */
  7556. .attrs = iwl4965_sysfs_entries,
  7557. };
  7558. static struct ieee80211_ops iwl4965_hw_ops = {
  7559. .tx = iwl4965_mac_tx,
  7560. .start = iwl4965_mac_start,
  7561. .stop = iwl4965_mac_stop,
  7562. .add_interface = iwl4965_mac_add_interface,
  7563. .remove_interface = iwl4965_mac_remove_interface,
  7564. .config = iwl4965_mac_config,
  7565. .config_interface = iwl4965_mac_config_interface,
  7566. .configure_filter = iwl4965_configure_filter,
  7567. .set_key = iwl4965_mac_set_key,
  7568. .get_stats = iwl4965_mac_get_stats,
  7569. .get_tx_stats = iwl4965_mac_get_tx_stats,
  7570. .conf_tx = iwl4965_mac_conf_tx,
  7571. .get_tsf = iwl4965_mac_get_tsf,
  7572. .reset_tsf = iwl4965_mac_reset_tsf,
  7573. .beacon_update = iwl4965_mac_beacon_update,
  7574. .erp_ie_changed = iwl4965_mac_erp_ie_changed,
  7575. #ifdef CONFIG_IWL4965_HT
  7576. .conf_ht = iwl4965_mac_conf_ht,
  7577. .get_ht_capab = iwl4965_mac_get_ht_capab,
  7578. #ifdef CONFIG_IWL4965_HT_AGG
  7579. .ht_tx_agg_start = iwl4965_mac_ht_tx_agg_start,
  7580. .ht_tx_agg_stop = iwl4965_mac_ht_tx_agg_stop,
  7581. .ht_rx_agg_start = iwl4965_mac_ht_rx_agg_start,
  7582. .ht_rx_agg_stop = iwl4965_mac_ht_rx_agg_stop,
  7583. #endif /* CONFIG_IWL4965_HT_AGG */
  7584. #endif /* CONFIG_IWL4965_HT */
  7585. .hw_scan = iwl4965_mac_hw_scan
  7586. };
  7587. static int iwl4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  7588. {
  7589. int err = 0;
  7590. struct iwl4965_priv *priv;
  7591. struct ieee80211_hw *hw;
  7592. int i;
  7593. /* Disabling hardware scan means that mac80211 will perform scans
  7594. * "the hard way", rather than using device's scan. */
  7595. if (iwl4965_param_disable_hw_scan) {
  7596. IWL_DEBUG_INFO("Disabling hw_scan\n");
  7597. iwl4965_hw_ops.hw_scan = NULL;
  7598. }
  7599. if ((iwl4965_param_queues_num > IWL_MAX_NUM_QUEUES) ||
  7600. (iwl4965_param_queues_num < IWL_MIN_NUM_QUEUES)) {
  7601. IWL_ERROR("invalid queues_num, should be between %d and %d\n",
  7602. IWL_MIN_NUM_QUEUES, IWL_MAX_NUM_QUEUES);
  7603. err = -EINVAL;
  7604. goto out;
  7605. }
  7606. /* mac80211 allocates memory for this device instance, including
  7607. * space for this driver's private structure */
  7608. hw = ieee80211_alloc_hw(sizeof(struct iwl4965_priv), &iwl4965_hw_ops);
  7609. if (hw == NULL) {
  7610. IWL_ERROR("Can not allocate network device\n");
  7611. err = -ENOMEM;
  7612. goto out;
  7613. }
  7614. SET_IEEE80211_DEV(hw, &pdev->dev);
  7615. hw->rate_control_algorithm = "iwl-4965-rs";
  7616. IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
  7617. priv = hw->priv;
  7618. priv->hw = hw;
  7619. priv->pci_dev = pdev;
  7620. priv->antenna = (enum iwl4965_antenna)iwl4965_param_antenna;
  7621. #ifdef CONFIG_IWL4965_DEBUG
  7622. iwl4965_debug_level = iwl4965_param_debug;
  7623. atomic_set(&priv->restrict_refcnt, 0);
  7624. #endif
  7625. priv->retry_rate = 1;
  7626. priv->ibss_beacon = NULL;
  7627. /* Tell mac80211 and its clients (e.g. Wireless Extensions)
  7628. * the range of signal quality values that we'll provide.
  7629. * Negative values for level/noise indicate that we'll provide dBm.
  7630. * For WE, at least, non-0 values here *enable* display of values
  7631. * in app (iwconfig). */
  7632. hw->max_rssi = -20; /* signal level, negative indicates dBm */
  7633. hw->max_noise = -20; /* noise level, negative indicates dBm */
  7634. hw->max_signal = 100; /* link quality indication (%) */
  7635. /* Tell mac80211 our Tx characteristics */
  7636. hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE;
  7637. /* Default value; 4 EDCA QOS priorities */
  7638. hw->queues = 4;
  7639. #ifdef CONFIG_IWL4965_HT
  7640. #ifdef CONFIG_IWL4965_HT_AGG
  7641. /* Enhanced value; more queues, to support 11n aggregation */
  7642. hw->queues = 16;
  7643. #endif /* CONFIG_IWL4965_HT_AGG */
  7644. #endif /* CONFIG_IWL4965_HT */
  7645. spin_lock_init(&priv->lock);
  7646. spin_lock_init(&priv->power_data.lock);
  7647. spin_lock_init(&priv->sta_lock);
  7648. spin_lock_init(&priv->hcmd_lock);
  7649. spin_lock_init(&priv->lq_mngr.lock);
  7650. for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
  7651. INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
  7652. INIT_LIST_HEAD(&priv->free_frames);
  7653. mutex_init(&priv->mutex);
  7654. if (pci_enable_device(pdev)) {
  7655. err = -ENODEV;
  7656. goto out_ieee80211_free_hw;
  7657. }
  7658. pci_set_master(pdev);
  7659. /* Clear the driver's (not device's) station table */
  7660. iwl4965_clear_stations_table(priv);
  7661. priv->data_retry_limit = -1;
  7662. priv->ieee_channels = NULL;
  7663. priv->ieee_rates = NULL;
  7664. priv->phymode = -1;
  7665. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  7666. if (!err)
  7667. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  7668. if (err) {
  7669. printk(KERN_WARNING DRV_NAME ": No suitable DMA available.\n");
  7670. goto out_pci_disable_device;
  7671. }
  7672. pci_set_drvdata(pdev, priv);
  7673. err = pci_request_regions(pdev, DRV_NAME);
  7674. if (err)
  7675. goto out_pci_disable_device;
  7676. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  7677. * PCI Tx retries from interfering with C3 CPU state */
  7678. pci_write_config_byte(pdev, 0x41, 0x00);
  7679. priv->hw_base = pci_iomap(pdev, 0, 0);
  7680. if (!priv->hw_base) {
  7681. err = -ENODEV;
  7682. goto out_pci_release_regions;
  7683. }
  7684. IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
  7685. (unsigned long long) pci_resource_len(pdev, 0));
  7686. IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
  7687. /* Initialize module parameter values here */
  7688. /* Disable radio (SW RF KILL) via parameter when loading driver */
  7689. if (iwl4965_param_disable) {
  7690. set_bit(STATUS_RF_KILL_SW, &priv->status);
  7691. IWL_DEBUG_INFO("Radio disabled.\n");
  7692. }
  7693. priv->iw_mode = IEEE80211_IF_TYPE_STA;
  7694. priv->ps_mode = 0;
  7695. priv->use_ant_b_for_management_frame = 1; /* start with ant B */
  7696. priv->is_ht_enabled = 1;
  7697. priv->channel_width = IWL_CHANNEL_WIDTH_40MHZ;
  7698. priv->valid_antenna = 0x7; /* assume all 3 connected */
  7699. priv->ps_mode = IWL_MIMO_PS_NONE;
  7700. /* Choose which receivers/antennas to use */
  7701. iwl4965_set_rxon_chain(priv);
  7702. printk(KERN_INFO DRV_NAME
  7703. ": Detected Intel Wireless WiFi Link 4965AGN\n");
  7704. /* Device-specific setup */
  7705. if (iwl4965_hw_set_hw_setting(priv)) {
  7706. IWL_ERROR("failed to set hw settings\n");
  7707. mutex_unlock(&priv->mutex);
  7708. goto out_iounmap;
  7709. }
  7710. #ifdef CONFIG_IWL4965_QOS
  7711. if (iwl4965_param_qos_enable)
  7712. priv->qos_data.qos_enable = 1;
  7713. iwl4965_reset_qos(priv);
  7714. priv->qos_data.qos_active = 0;
  7715. priv->qos_data.qos_cap.val = 0;
  7716. #endif /* CONFIG_IWL4965_QOS */
  7717. iwl4965_set_rxon_channel(priv, MODE_IEEE80211G, 6);
  7718. iwl4965_setup_deferred_work(priv);
  7719. iwl4965_setup_rx_handlers(priv);
  7720. priv->rates_mask = IWL_RATES_MASK;
  7721. /* If power management is turned on, default to AC mode */
  7722. priv->power_mode = IWL_POWER_AC;
  7723. priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
  7724. iwl4965_disable_interrupts(priv);
  7725. pci_enable_msi(pdev);
  7726. err = request_irq(pdev->irq, iwl4965_isr, IRQF_SHARED, DRV_NAME, priv);
  7727. if (err) {
  7728. IWL_ERROR("Error allocating IRQ %d\n", pdev->irq);
  7729. goto out_disable_msi;
  7730. }
  7731. mutex_lock(&priv->mutex);
  7732. err = sysfs_create_group(&pdev->dev.kobj, &iwl4965_attribute_group);
  7733. if (err) {
  7734. IWL_ERROR("failed to create sysfs device attributes\n");
  7735. mutex_unlock(&priv->mutex);
  7736. goto out_release_irq;
  7737. }
  7738. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  7739. * ucode filename and max sizes are card-specific. */
  7740. err = iwl4965_read_ucode(priv);
  7741. if (err) {
  7742. IWL_ERROR("Could not read microcode: %d\n", err);
  7743. mutex_unlock(&priv->mutex);
  7744. goto out_pci_alloc;
  7745. }
  7746. mutex_unlock(&priv->mutex);
  7747. IWL_DEBUG_INFO("Queueing UP work.\n");
  7748. queue_work(priv->workqueue, &priv->up);
  7749. return 0;
  7750. out_pci_alloc:
  7751. iwl4965_dealloc_ucode_pci(priv);
  7752. sysfs_remove_group(&pdev->dev.kobj, &iwl4965_attribute_group);
  7753. out_release_irq:
  7754. free_irq(pdev->irq, priv);
  7755. out_disable_msi:
  7756. pci_disable_msi(pdev);
  7757. destroy_workqueue(priv->workqueue);
  7758. priv->workqueue = NULL;
  7759. iwl4965_unset_hw_setting(priv);
  7760. out_iounmap:
  7761. pci_iounmap(pdev, priv->hw_base);
  7762. out_pci_release_regions:
  7763. pci_release_regions(pdev);
  7764. out_pci_disable_device:
  7765. pci_disable_device(pdev);
  7766. pci_set_drvdata(pdev, NULL);
  7767. out_ieee80211_free_hw:
  7768. ieee80211_free_hw(priv->hw);
  7769. out:
  7770. return err;
  7771. }
  7772. static void iwl4965_pci_remove(struct pci_dev *pdev)
  7773. {
  7774. struct iwl4965_priv *priv = pci_get_drvdata(pdev);
  7775. struct list_head *p, *q;
  7776. int i;
  7777. if (!priv)
  7778. return;
  7779. IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
  7780. set_bit(STATUS_EXIT_PENDING, &priv->status);
  7781. iwl4965_down(priv);
  7782. /* Free MAC hash list for ADHOC */
  7783. for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++) {
  7784. list_for_each_safe(p, q, &priv->ibss_mac_hash[i]) {
  7785. list_del(p);
  7786. kfree(list_entry(p, struct iwl4965_ibss_seq, list));
  7787. }
  7788. }
  7789. sysfs_remove_group(&pdev->dev.kobj, &iwl4965_attribute_group);
  7790. iwl4965_dealloc_ucode_pci(priv);
  7791. if (priv->rxq.bd)
  7792. iwl4965_rx_queue_free(priv, &priv->rxq);
  7793. iwl4965_hw_txq_ctx_free(priv);
  7794. iwl4965_unset_hw_setting(priv);
  7795. iwl4965_clear_stations_table(priv);
  7796. if (priv->mac80211_registered) {
  7797. ieee80211_unregister_hw(priv->hw);
  7798. iwl4965_rate_control_unregister(priv->hw);
  7799. }
  7800. /*netif_stop_queue(dev); */
  7801. flush_workqueue(priv->workqueue);
  7802. /* ieee80211_unregister_hw calls iwl4965_mac_stop, which flushes
  7803. * priv->workqueue... so we can't take down the workqueue
  7804. * until now... */
  7805. destroy_workqueue(priv->workqueue);
  7806. priv->workqueue = NULL;
  7807. free_irq(pdev->irq, priv);
  7808. pci_disable_msi(pdev);
  7809. pci_iounmap(pdev, priv->hw_base);
  7810. pci_release_regions(pdev);
  7811. pci_disable_device(pdev);
  7812. pci_set_drvdata(pdev, NULL);
  7813. kfree(priv->channel_info);
  7814. kfree(priv->ieee_channels);
  7815. kfree(priv->ieee_rates);
  7816. if (priv->ibss_beacon)
  7817. dev_kfree_skb(priv->ibss_beacon);
  7818. ieee80211_free_hw(priv->hw);
  7819. }
  7820. #ifdef CONFIG_PM
  7821. static int iwl4965_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  7822. {
  7823. struct iwl4965_priv *priv = pci_get_drvdata(pdev);
  7824. set_bit(STATUS_IN_SUSPEND, &priv->status);
  7825. /* Take down the device; powers it off, etc. */
  7826. iwl4965_down(priv);
  7827. if (priv->mac80211_registered)
  7828. ieee80211_stop_queues(priv->hw);
  7829. pci_save_state(pdev);
  7830. pci_disable_device(pdev);
  7831. pci_set_power_state(pdev, PCI_D3hot);
  7832. return 0;
  7833. }
  7834. static void iwl4965_resume(struct iwl4965_priv *priv)
  7835. {
  7836. unsigned long flags;
  7837. /* The following it a temporary work around due to the
  7838. * suspend / resume not fully initializing the NIC correctly.
  7839. * Without all of the following, resume will not attempt to take
  7840. * down the NIC (it shouldn't really need to) and will just try
  7841. * and bring the NIC back up. However that fails during the
  7842. * ucode verification process. This then causes iwl4965_down to be
  7843. * called *after* iwl4965_hw_nic_init() has succeeded -- which
  7844. * then lets the next init sequence succeed. So, we've
  7845. * replicated all of that NIC init code here... */
  7846. iwl4965_write32(priv, CSR_INT, 0xFFFFFFFF);
  7847. iwl4965_hw_nic_init(priv);
  7848. iwl4965_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  7849. iwl4965_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  7850. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  7851. iwl4965_write32(priv, CSR_INT, 0xFFFFFFFF);
  7852. iwl4965_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  7853. iwl4965_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  7854. /* tell the device to stop sending interrupts */
  7855. iwl4965_disable_interrupts(priv);
  7856. spin_lock_irqsave(&priv->lock, flags);
  7857. iwl4965_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  7858. if (!iwl4965_grab_nic_access(priv)) {
  7859. iwl4965_write_prph(priv, APMG_CLK_DIS_REG,
  7860. APMG_CLK_VAL_DMA_CLK_RQT);
  7861. iwl4965_release_nic_access(priv);
  7862. }
  7863. spin_unlock_irqrestore(&priv->lock, flags);
  7864. udelay(5);
  7865. iwl4965_hw_nic_reset(priv);
  7866. /* Bring the device back up */
  7867. clear_bit(STATUS_IN_SUSPEND, &priv->status);
  7868. queue_work(priv->workqueue, &priv->up);
  7869. }
  7870. static int iwl4965_pci_resume(struct pci_dev *pdev)
  7871. {
  7872. struct iwl4965_priv *priv = pci_get_drvdata(pdev);
  7873. int err;
  7874. printk(KERN_INFO "Coming out of suspend...\n");
  7875. pci_set_power_state(pdev, PCI_D0);
  7876. err = pci_enable_device(pdev);
  7877. pci_restore_state(pdev);
  7878. /*
  7879. * Suspend/Resume resets the PCI configuration space, so we have to
  7880. * re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries
  7881. * from interfering with C3 CPU state. pci_restore_state won't help
  7882. * here since it only restores the first 64 bytes pci config header.
  7883. */
  7884. pci_write_config_byte(pdev, 0x41, 0x00);
  7885. iwl4965_resume(priv);
  7886. return 0;
  7887. }
  7888. #endif /* CONFIG_PM */
  7889. /*****************************************************************************
  7890. *
  7891. * driver and module entry point
  7892. *
  7893. *****************************************************************************/
  7894. static struct pci_driver iwl4965_driver = {
  7895. .name = DRV_NAME,
  7896. .id_table = iwl4965_hw_card_ids,
  7897. .probe = iwl4965_pci_probe,
  7898. .remove = __devexit_p(iwl4965_pci_remove),
  7899. #ifdef CONFIG_PM
  7900. .suspend = iwl4965_pci_suspend,
  7901. .resume = iwl4965_pci_resume,
  7902. #endif
  7903. };
  7904. static int __init iwl4965_init(void)
  7905. {
  7906. int ret;
  7907. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  7908. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  7909. ret = pci_register_driver(&iwl4965_driver);
  7910. if (ret) {
  7911. IWL_ERROR("Unable to initialize PCI module\n");
  7912. return ret;
  7913. }
  7914. #ifdef CONFIG_IWL4965_DEBUG
  7915. ret = driver_create_file(&iwl4965_driver.driver, &driver_attr_debug_level);
  7916. if (ret) {
  7917. IWL_ERROR("Unable to create driver sysfs file\n");
  7918. pci_unregister_driver(&iwl4965_driver);
  7919. return ret;
  7920. }
  7921. #endif
  7922. return ret;
  7923. }
  7924. static void __exit iwl4965_exit(void)
  7925. {
  7926. #ifdef CONFIG_IWL4965_DEBUG
  7927. driver_remove_file(&iwl4965_driver.driver, &driver_attr_debug_level);
  7928. #endif
  7929. pci_unregister_driver(&iwl4965_driver);
  7930. }
  7931. module_param_named(antenna, iwl4965_param_antenna, int, 0444);
  7932. MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
  7933. module_param_named(disable, iwl4965_param_disable, int, 0444);
  7934. MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
  7935. module_param_named(hwcrypto, iwl4965_param_hwcrypto, int, 0444);
  7936. MODULE_PARM_DESC(hwcrypto,
  7937. "using hardware crypto engine (default 0 [software])\n");
  7938. module_param_named(debug, iwl4965_param_debug, int, 0444);
  7939. MODULE_PARM_DESC(debug, "debug output mask");
  7940. module_param_named(disable_hw_scan, iwl4965_param_disable_hw_scan, int, 0444);
  7941. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  7942. module_param_named(queues_num, iwl4965_param_queues_num, int, 0444);
  7943. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  7944. /* QoS */
  7945. module_param_named(qos_enable, iwl4965_param_qos_enable, int, 0444);
  7946. MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
  7947. module_exit(iwl4965_exit);
  7948. module_init(iwl4965_init);