iwl3945-base.c 249 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2007 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * James P. Ketrenos <ipw2100-admin@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/version.h>
  32. #include <linux/init.h>
  33. #include <linux/pci.h>
  34. #include <linux/dma-mapping.h>
  35. #include <linux/delay.h>
  36. #include <linux/skbuff.h>
  37. #include <linux/netdevice.h>
  38. #include <linux/wireless.h>
  39. #include <linux/firmware.h>
  40. #include <linux/etherdevice.h>
  41. #include <linux/if_arp.h>
  42. #include <net/ieee80211_radiotap.h>
  43. #include <net/mac80211.h>
  44. #include <asm/div64.h>
  45. #include "iwl-3945.h"
  46. #include "iwl-helpers.h"
  47. #ifdef CONFIG_IWL3945_DEBUG
  48. u32 iwl3945_debug_level;
  49. #endif
  50. static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
  51. struct iwl3945_tx_queue *txq);
  52. /******************************************************************************
  53. *
  54. * module boiler plate
  55. *
  56. ******************************************************************************/
  57. /* module parameters */
  58. static int iwl3945_param_disable_hw_scan; /* def: 0 = use 3945's h/w scan */
  59. static int iwl3945_param_debug; /* def: 0 = minimal debug log messages */
  60. static int iwl3945_param_disable; /* def: 0 = enable radio */
  61. static int iwl3945_param_antenna; /* def: 0 = both antennas (use diversity) */
  62. int iwl3945_param_hwcrypto; /* def: 0 = use software encryption */
  63. static int iwl3945_param_qos_enable = 1; /* def: 1 = use quality of service */
  64. int iwl3945_param_queues_num = IWL_MAX_NUM_QUEUES; /* def: 8 Tx queues */
  65. /*
  66. * module name, copyright, version, etc.
  67. * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk
  68. */
  69. #define DRV_DESCRIPTION \
  70. "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
  71. #ifdef CONFIG_IWL3945_DEBUG
  72. #define VD "d"
  73. #else
  74. #define VD
  75. #endif
  76. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  77. #define VS "s"
  78. #else
  79. #define VS
  80. #endif
  81. #define IWLWIFI_VERSION "1.1.19k" VD VS
  82. #define DRV_COPYRIGHT "Copyright(c) 2003-2007 Intel Corporation"
  83. #define DRV_VERSION IWLWIFI_VERSION
  84. /* Change firmware file name, using "-" and incrementing number,
  85. * *only* when uCode interface or architecture changes so that it
  86. * is not compatible with earlier drivers.
  87. * This number will also appear in << 8 position of 1st dword of uCode file */
  88. #define IWL3945_UCODE_API "-1"
  89. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  90. MODULE_VERSION(DRV_VERSION);
  91. MODULE_AUTHOR(DRV_COPYRIGHT);
  92. MODULE_LICENSE("GPL");
  93. static __le16 *ieee80211_get_qos_ctrl(struct ieee80211_hdr *hdr)
  94. {
  95. u16 fc = le16_to_cpu(hdr->frame_control);
  96. int hdr_len = ieee80211_get_hdrlen(fc);
  97. if ((fc & 0x00cc) == (IEEE80211_STYPE_QOS_DATA | IEEE80211_FTYPE_DATA))
  98. return (__le16 *) ((u8 *) hdr + hdr_len - QOS_CONTROL_LEN);
  99. return NULL;
  100. }
  101. static const struct ieee80211_hw_mode *iwl3945_get_hw_mode(
  102. struct iwl3945_priv *priv, int mode)
  103. {
  104. int i;
  105. for (i = 0; i < 3; i++)
  106. if (priv->modes[i].mode == mode)
  107. return &priv->modes[i];
  108. return NULL;
  109. }
  110. static int iwl3945_is_empty_essid(const char *essid, int essid_len)
  111. {
  112. /* Single white space is for Linksys APs */
  113. if (essid_len == 1 && essid[0] == ' ')
  114. return 1;
  115. /* Otherwise, if the entire essid is 0, we assume it is hidden */
  116. while (essid_len) {
  117. essid_len--;
  118. if (essid[essid_len] != '\0')
  119. return 0;
  120. }
  121. return 1;
  122. }
  123. static const char *iwl3945_escape_essid(const char *essid, u8 essid_len)
  124. {
  125. static char escaped[IW_ESSID_MAX_SIZE * 2 + 1];
  126. const char *s = essid;
  127. char *d = escaped;
  128. if (iwl3945_is_empty_essid(essid, essid_len)) {
  129. memcpy(escaped, "<hidden>", sizeof("<hidden>"));
  130. return escaped;
  131. }
  132. essid_len = min(essid_len, (u8) IW_ESSID_MAX_SIZE);
  133. while (essid_len--) {
  134. if (*s == '\0') {
  135. *d++ = '\\';
  136. *d++ = '0';
  137. s++;
  138. } else
  139. *d++ = *s++;
  140. }
  141. *d = '\0';
  142. return escaped;
  143. }
  144. static void iwl3945_print_hex_dump(int level, void *p, u32 len)
  145. {
  146. #ifdef CONFIG_IWL3945_DEBUG
  147. if (!(iwl3945_debug_level & level))
  148. return;
  149. print_hex_dump(KERN_DEBUG, "iwl data: ", DUMP_PREFIX_OFFSET, 16, 1,
  150. p, len, 1);
  151. #endif
  152. }
  153. /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
  154. * DMA services
  155. *
  156. * Theory of operation
  157. *
  158. * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
  159. * of buffer descriptors, each of which points to one or more data buffers for
  160. * the device to read from or fill. Driver and device exchange status of each
  161. * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
  162. * entries in each circular buffer, to protect against confusing empty and full
  163. * queue states.
  164. *
  165. * The device reads or writes the data in the queues via the device's several
  166. * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
  167. *
  168. * For Tx queue, there are low mark and high mark limits. If, after queuing
  169. * the packet for Tx, free space become < low mark, Tx queue stopped. When
  170. * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
  171. * Tx queue resumed.
  172. *
  173. * The 3945 operates with six queues: One receive queue, one transmit queue
  174. * (#4) for sending commands to the device firmware, and four transmit queues
  175. * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused.
  176. ***************************************************/
  177. static int iwl3945_queue_space(const struct iwl3945_queue *q)
  178. {
  179. int s = q->read_ptr - q->write_ptr;
  180. if (q->read_ptr > q->write_ptr)
  181. s -= q->n_bd;
  182. if (s <= 0)
  183. s += q->n_window;
  184. /* keep some reserve to not confuse empty and full situations */
  185. s -= 2;
  186. if (s < 0)
  187. s = 0;
  188. return s;
  189. }
  190. /**
  191. * iwl3945_queue_inc_wrap - increment queue index, wrap back to beginning
  192. * @index -- current index
  193. * @n_bd -- total number of entries in queue (must be power of 2)
  194. */
  195. static inline int iwl3945_queue_inc_wrap(int index, int n_bd)
  196. {
  197. return ++index & (n_bd - 1);
  198. }
  199. /**
  200. * iwl3945_queue_dec_wrap - increment queue index, wrap back to end
  201. * @index -- current index
  202. * @n_bd -- total number of entries in queue (must be power of 2)
  203. */
  204. static inline int iwl3945_queue_dec_wrap(int index, int n_bd)
  205. {
  206. return --index & (n_bd - 1);
  207. }
  208. static inline int x2_queue_used(const struct iwl3945_queue *q, int i)
  209. {
  210. return q->write_ptr > q->read_ptr ?
  211. (i >= q->read_ptr && i < q->write_ptr) :
  212. !(i < q->read_ptr && i >= q->write_ptr);
  213. }
  214. static inline u8 get_cmd_index(struct iwl3945_queue *q, u32 index, int is_huge)
  215. {
  216. /* This is for scan command, the big buffer at end of command array */
  217. if (is_huge)
  218. return q->n_window; /* must be power of 2 */
  219. /* Otherwise, use normal size buffers */
  220. return index & (q->n_window - 1);
  221. }
  222. /**
  223. * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes
  224. */
  225. static int iwl3945_queue_init(struct iwl3945_priv *priv, struct iwl3945_queue *q,
  226. int count, int slots_num, u32 id)
  227. {
  228. q->n_bd = count;
  229. q->n_window = slots_num;
  230. q->id = id;
  231. /* count must be power-of-two size, otherwise iwl3945_queue_inc_wrap
  232. * and iwl3945_queue_dec_wrap are broken. */
  233. BUG_ON(!is_power_of_2(count));
  234. /* slots_num must be power-of-two size, otherwise
  235. * get_cmd_index is broken. */
  236. BUG_ON(!is_power_of_2(slots_num));
  237. q->low_mark = q->n_window / 4;
  238. if (q->low_mark < 4)
  239. q->low_mark = 4;
  240. q->high_mark = q->n_window / 8;
  241. if (q->high_mark < 2)
  242. q->high_mark = 2;
  243. q->write_ptr = q->read_ptr = 0;
  244. return 0;
  245. }
  246. /**
  247. * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
  248. */
  249. static int iwl3945_tx_queue_alloc(struct iwl3945_priv *priv,
  250. struct iwl3945_tx_queue *txq, u32 id)
  251. {
  252. struct pci_dev *dev = priv->pci_dev;
  253. /* Driver private data, only for Tx (not command) queues,
  254. * not shared with device. */
  255. if (id != IWL_CMD_QUEUE_NUM) {
  256. txq->txb = kmalloc(sizeof(txq->txb[0]) *
  257. TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
  258. if (!txq->txb) {
  259. IWL_ERROR("kmalloc for auxiliary BD "
  260. "structures failed\n");
  261. goto error;
  262. }
  263. } else
  264. txq->txb = NULL;
  265. /* Circular buffer of transmit frame descriptors (TFDs),
  266. * shared with device */
  267. txq->bd = pci_alloc_consistent(dev,
  268. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
  269. &txq->q.dma_addr);
  270. if (!txq->bd) {
  271. IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
  272. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
  273. goto error;
  274. }
  275. txq->q.id = id;
  276. return 0;
  277. error:
  278. if (txq->txb) {
  279. kfree(txq->txb);
  280. txq->txb = NULL;
  281. }
  282. return -ENOMEM;
  283. }
  284. /**
  285. * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
  286. */
  287. int iwl3945_tx_queue_init(struct iwl3945_priv *priv,
  288. struct iwl3945_tx_queue *txq, int slots_num, u32 txq_id)
  289. {
  290. struct pci_dev *dev = priv->pci_dev;
  291. int len;
  292. int rc = 0;
  293. /*
  294. * Alloc buffer array for commands (Tx or other types of commands).
  295. * For the command queue (#4), allocate command space + one big
  296. * command for scan, since scan command is very huge; the system will
  297. * not have two scans at the same time, so only one is needed.
  298. * For data Tx queues (all other queues), no super-size command
  299. * space is needed.
  300. */
  301. len = sizeof(struct iwl3945_cmd) * slots_num;
  302. if (txq_id == IWL_CMD_QUEUE_NUM)
  303. len += IWL_MAX_SCAN_SIZE;
  304. txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
  305. if (!txq->cmd)
  306. return -ENOMEM;
  307. /* Alloc driver data array and TFD circular buffer */
  308. rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
  309. if (rc) {
  310. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  311. return -ENOMEM;
  312. }
  313. txq->need_update = 0;
  314. /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
  315. * iwl3945_queue_inc_wrap and iwl3945_queue_dec_wrap are broken. */
  316. BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
  317. /* Initialize queue high/low-water, head/tail indexes */
  318. iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
  319. /* Tell device where to find queue, enable DMA channel. */
  320. iwl3945_hw_tx_queue_init(priv, txq);
  321. return 0;
  322. }
  323. /**
  324. * iwl3945_tx_queue_free - Deallocate DMA queue.
  325. * @txq: Transmit queue to deallocate.
  326. *
  327. * Empty queue by removing and destroying all BD's.
  328. * Free all buffers.
  329. * 0-fill, but do not free "txq" descriptor structure.
  330. */
  331. void iwl3945_tx_queue_free(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
  332. {
  333. struct iwl3945_queue *q = &txq->q;
  334. struct pci_dev *dev = priv->pci_dev;
  335. int len;
  336. if (q->n_bd == 0)
  337. return;
  338. /* first, empty all BD's */
  339. for (; q->write_ptr != q->read_ptr;
  340. q->read_ptr = iwl3945_queue_inc_wrap(q->read_ptr, q->n_bd))
  341. iwl3945_hw_txq_free_tfd(priv, txq);
  342. len = sizeof(struct iwl3945_cmd) * q->n_window;
  343. if (q->id == IWL_CMD_QUEUE_NUM)
  344. len += IWL_MAX_SCAN_SIZE;
  345. /* De-alloc array of command/tx buffers */
  346. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  347. /* De-alloc circular buffer of TFDs */
  348. if (txq->q.n_bd)
  349. pci_free_consistent(dev, sizeof(struct iwl3945_tfd_frame) *
  350. txq->q.n_bd, txq->bd, txq->q.dma_addr);
  351. /* De-alloc array of per-TFD driver data */
  352. if (txq->txb) {
  353. kfree(txq->txb);
  354. txq->txb = NULL;
  355. }
  356. /* 0-fill queue descriptor structure */
  357. memset(txq, 0, sizeof(*txq));
  358. }
  359. const u8 iwl3945_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
  360. /*************** STATION TABLE MANAGEMENT ****
  361. * mac80211 should be examined to determine if sta_info is duplicating
  362. * the functionality provided here
  363. */
  364. /**************************************************************/
  365. #if 0 /* temporary disable till we add real remove station */
  366. /**
  367. * iwl3945_remove_station - Remove driver's knowledge of station.
  368. *
  369. * NOTE: This does not remove station from device's station table.
  370. */
  371. static u8 iwl3945_remove_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap)
  372. {
  373. int index = IWL_INVALID_STATION;
  374. int i;
  375. unsigned long flags;
  376. spin_lock_irqsave(&priv->sta_lock, flags);
  377. if (is_ap)
  378. index = IWL_AP_ID;
  379. else if (is_broadcast_ether_addr(addr))
  380. index = priv->hw_setting.bcast_sta_id;
  381. else
  382. for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
  383. if (priv->stations[i].used &&
  384. !compare_ether_addr(priv->stations[i].sta.sta.addr,
  385. addr)) {
  386. index = i;
  387. break;
  388. }
  389. if (unlikely(index == IWL_INVALID_STATION))
  390. goto out;
  391. if (priv->stations[index].used) {
  392. priv->stations[index].used = 0;
  393. priv->num_stations--;
  394. }
  395. BUG_ON(priv->num_stations < 0);
  396. out:
  397. spin_unlock_irqrestore(&priv->sta_lock, flags);
  398. return 0;
  399. }
  400. #endif
  401. /**
  402. * iwl3945_clear_stations_table - Clear the driver's station table
  403. *
  404. * NOTE: This does not clear or otherwise alter the device's station table.
  405. */
  406. static void iwl3945_clear_stations_table(struct iwl3945_priv *priv)
  407. {
  408. unsigned long flags;
  409. spin_lock_irqsave(&priv->sta_lock, flags);
  410. priv->num_stations = 0;
  411. memset(priv->stations, 0, sizeof(priv->stations));
  412. spin_unlock_irqrestore(&priv->sta_lock, flags);
  413. }
  414. /**
  415. * iwl3945_add_station - Add station to station tables in driver and device
  416. */
  417. u8 iwl3945_add_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap, u8 flags)
  418. {
  419. int i;
  420. int index = IWL_INVALID_STATION;
  421. struct iwl3945_station_entry *station;
  422. unsigned long flags_spin;
  423. DECLARE_MAC_BUF(mac);
  424. u8 rate;
  425. spin_lock_irqsave(&priv->sta_lock, flags_spin);
  426. if (is_ap)
  427. index = IWL_AP_ID;
  428. else if (is_broadcast_ether_addr(addr))
  429. index = priv->hw_setting.bcast_sta_id;
  430. else
  431. for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) {
  432. if (!compare_ether_addr(priv->stations[i].sta.sta.addr,
  433. addr)) {
  434. index = i;
  435. break;
  436. }
  437. if (!priv->stations[i].used &&
  438. index == IWL_INVALID_STATION)
  439. index = i;
  440. }
  441. /* These two conditions has the same outcome but keep them separate
  442. since they have different meaning */
  443. if (unlikely(index == IWL_INVALID_STATION)) {
  444. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  445. return index;
  446. }
  447. if (priv->stations[index].used &&
  448. !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) {
  449. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  450. return index;
  451. }
  452. IWL_DEBUG_ASSOC("Add STA ID %d: %s\n", index, print_mac(mac, addr));
  453. station = &priv->stations[index];
  454. station->used = 1;
  455. priv->num_stations++;
  456. /* Set up the REPLY_ADD_STA command to send to device */
  457. memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
  458. memcpy(station->sta.sta.addr, addr, ETH_ALEN);
  459. station->sta.mode = 0;
  460. station->sta.sta.sta_id = index;
  461. station->sta.station_flags = 0;
  462. if (priv->phymode == MODE_IEEE80211A)
  463. rate = IWL_RATE_6M_PLCP;
  464. else
  465. rate = IWL_RATE_1M_PLCP;
  466. /* Turn on both antennas for the station... */
  467. station->sta.rate_n_flags =
  468. iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
  469. station->current_rate.rate_n_flags =
  470. le16_to_cpu(station->sta.rate_n_flags);
  471. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  472. /* Add station to device's station table */
  473. iwl3945_send_add_station(priv, &station->sta, flags);
  474. return index;
  475. }
  476. /*************** DRIVER STATUS FUNCTIONS *****/
  477. static inline int iwl3945_is_ready(struct iwl3945_priv *priv)
  478. {
  479. /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
  480. * set but EXIT_PENDING is not */
  481. return test_bit(STATUS_READY, &priv->status) &&
  482. test_bit(STATUS_GEO_CONFIGURED, &priv->status) &&
  483. !test_bit(STATUS_EXIT_PENDING, &priv->status);
  484. }
  485. static inline int iwl3945_is_alive(struct iwl3945_priv *priv)
  486. {
  487. return test_bit(STATUS_ALIVE, &priv->status);
  488. }
  489. static inline int iwl3945_is_init(struct iwl3945_priv *priv)
  490. {
  491. return test_bit(STATUS_INIT, &priv->status);
  492. }
  493. static inline int iwl3945_is_rfkill(struct iwl3945_priv *priv)
  494. {
  495. return test_bit(STATUS_RF_KILL_HW, &priv->status) ||
  496. test_bit(STATUS_RF_KILL_SW, &priv->status);
  497. }
  498. static inline int iwl3945_is_ready_rf(struct iwl3945_priv *priv)
  499. {
  500. if (iwl3945_is_rfkill(priv))
  501. return 0;
  502. return iwl3945_is_ready(priv);
  503. }
  504. /*************** HOST COMMAND QUEUE FUNCTIONS *****/
  505. #define IWL_CMD(x) case x : return #x
  506. static const char *get_cmd_string(u8 cmd)
  507. {
  508. switch (cmd) {
  509. IWL_CMD(REPLY_ALIVE);
  510. IWL_CMD(REPLY_ERROR);
  511. IWL_CMD(REPLY_RXON);
  512. IWL_CMD(REPLY_RXON_ASSOC);
  513. IWL_CMD(REPLY_QOS_PARAM);
  514. IWL_CMD(REPLY_RXON_TIMING);
  515. IWL_CMD(REPLY_ADD_STA);
  516. IWL_CMD(REPLY_REMOVE_STA);
  517. IWL_CMD(REPLY_REMOVE_ALL_STA);
  518. IWL_CMD(REPLY_3945_RX);
  519. IWL_CMD(REPLY_TX);
  520. IWL_CMD(REPLY_RATE_SCALE);
  521. IWL_CMD(REPLY_LEDS_CMD);
  522. IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
  523. IWL_CMD(RADAR_NOTIFICATION);
  524. IWL_CMD(REPLY_QUIET_CMD);
  525. IWL_CMD(REPLY_CHANNEL_SWITCH);
  526. IWL_CMD(CHANNEL_SWITCH_NOTIFICATION);
  527. IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD);
  528. IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION);
  529. IWL_CMD(POWER_TABLE_CMD);
  530. IWL_CMD(PM_SLEEP_NOTIFICATION);
  531. IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC);
  532. IWL_CMD(REPLY_SCAN_CMD);
  533. IWL_CMD(REPLY_SCAN_ABORT_CMD);
  534. IWL_CMD(SCAN_START_NOTIFICATION);
  535. IWL_CMD(SCAN_RESULTS_NOTIFICATION);
  536. IWL_CMD(SCAN_COMPLETE_NOTIFICATION);
  537. IWL_CMD(BEACON_NOTIFICATION);
  538. IWL_CMD(REPLY_TX_BEACON);
  539. IWL_CMD(WHO_IS_AWAKE_NOTIFICATION);
  540. IWL_CMD(QUIET_NOTIFICATION);
  541. IWL_CMD(REPLY_TX_PWR_TABLE_CMD);
  542. IWL_CMD(MEASURE_ABORT_NOTIFICATION);
  543. IWL_CMD(REPLY_BT_CONFIG);
  544. IWL_CMD(REPLY_STATISTICS_CMD);
  545. IWL_CMD(STATISTICS_NOTIFICATION);
  546. IWL_CMD(REPLY_CARD_STATE_CMD);
  547. IWL_CMD(CARD_STATE_NOTIFICATION);
  548. IWL_CMD(MISSED_BEACONS_NOTIFICATION);
  549. default:
  550. return "UNKNOWN";
  551. }
  552. }
  553. #define HOST_COMPLETE_TIMEOUT (HZ / 2)
  554. /**
  555. * iwl3945_enqueue_hcmd - enqueue a uCode command
  556. * @priv: device private data point
  557. * @cmd: a point to the ucode command structure
  558. *
  559. * The function returns < 0 values to indicate the operation is
  560. * failed. On success, it turns the index (> 0) of command in the
  561. * command queue.
  562. */
  563. static int iwl3945_enqueue_hcmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  564. {
  565. struct iwl3945_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
  566. struct iwl3945_queue *q = &txq->q;
  567. struct iwl3945_tfd_frame *tfd;
  568. u32 *control_flags;
  569. struct iwl3945_cmd *out_cmd;
  570. u32 idx;
  571. u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
  572. dma_addr_t phys_addr;
  573. int pad;
  574. u16 count;
  575. int ret;
  576. unsigned long flags;
  577. /* If any of the command structures end up being larger than
  578. * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
  579. * we will need to increase the size of the TFD entries */
  580. BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
  581. !(cmd->meta.flags & CMD_SIZE_HUGE));
  582. if (iwl3945_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
  583. IWL_ERROR("No space for Tx\n");
  584. return -ENOSPC;
  585. }
  586. spin_lock_irqsave(&priv->hcmd_lock, flags);
  587. tfd = &txq->bd[q->write_ptr];
  588. memset(tfd, 0, sizeof(*tfd));
  589. control_flags = (u32 *) tfd;
  590. idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
  591. out_cmd = &txq->cmd[idx];
  592. out_cmd->hdr.cmd = cmd->id;
  593. memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
  594. memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
  595. /* At this point, the out_cmd now has all of the incoming cmd
  596. * information */
  597. out_cmd->hdr.flags = 0;
  598. out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
  599. INDEX_TO_SEQ(q->write_ptr));
  600. if (out_cmd->meta.flags & CMD_SIZE_HUGE)
  601. out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME);
  602. phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
  603. offsetof(struct iwl3945_cmd, hdr);
  604. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
  605. pad = U32_PAD(cmd->len);
  606. count = TFD_CTL_COUNT_GET(*control_flags);
  607. *control_flags = TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad);
  608. IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
  609. "%d bytes at %d[%d]:%d\n",
  610. get_cmd_string(out_cmd->hdr.cmd),
  611. out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
  612. fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
  613. txq->need_update = 1;
  614. /* Increment and update queue's write index */
  615. q->write_ptr = iwl3945_queue_inc_wrap(q->write_ptr, q->n_bd);
  616. ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
  617. spin_unlock_irqrestore(&priv->hcmd_lock, flags);
  618. return ret ? ret : idx;
  619. }
  620. static int iwl3945_send_cmd_async(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  621. {
  622. int ret;
  623. BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
  624. /* An asynchronous command can not expect an SKB to be set. */
  625. BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
  626. /* An asynchronous command MUST have a callback. */
  627. BUG_ON(!cmd->meta.u.callback);
  628. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  629. return -EBUSY;
  630. ret = iwl3945_enqueue_hcmd(priv, cmd);
  631. if (ret < 0) {
  632. IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  633. get_cmd_string(cmd->id), ret);
  634. return ret;
  635. }
  636. return 0;
  637. }
  638. static int iwl3945_send_cmd_sync(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  639. {
  640. int cmd_idx;
  641. int ret;
  642. static atomic_t entry = ATOMIC_INIT(0); /* reentrance protection */
  643. BUG_ON(cmd->meta.flags & CMD_ASYNC);
  644. /* A synchronous command can not have a callback set. */
  645. BUG_ON(cmd->meta.u.callback != NULL);
  646. if (atomic_xchg(&entry, 1)) {
  647. IWL_ERROR("Error sending %s: Already sending a host command\n",
  648. get_cmd_string(cmd->id));
  649. return -EBUSY;
  650. }
  651. set_bit(STATUS_HCMD_ACTIVE, &priv->status);
  652. if (cmd->meta.flags & CMD_WANT_SKB)
  653. cmd->meta.source = &cmd->meta;
  654. cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
  655. if (cmd_idx < 0) {
  656. ret = cmd_idx;
  657. IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  658. get_cmd_string(cmd->id), ret);
  659. goto out;
  660. }
  661. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  662. !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
  663. HOST_COMPLETE_TIMEOUT);
  664. if (!ret) {
  665. if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
  666. IWL_ERROR("Error sending %s: time out after %dms.\n",
  667. get_cmd_string(cmd->id),
  668. jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
  669. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  670. ret = -ETIMEDOUT;
  671. goto cancel;
  672. }
  673. }
  674. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  675. IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
  676. get_cmd_string(cmd->id));
  677. ret = -ECANCELED;
  678. goto fail;
  679. }
  680. if (test_bit(STATUS_FW_ERROR, &priv->status)) {
  681. IWL_DEBUG_INFO("Command %s failed: FW Error\n",
  682. get_cmd_string(cmd->id));
  683. ret = -EIO;
  684. goto fail;
  685. }
  686. if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
  687. IWL_ERROR("Error: Response NULL in '%s'\n",
  688. get_cmd_string(cmd->id));
  689. ret = -EIO;
  690. goto out;
  691. }
  692. ret = 0;
  693. goto out;
  694. cancel:
  695. if (cmd->meta.flags & CMD_WANT_SKB) {
  696. struct iwl3945_cmd *qcmd;
  697. /* Cancel the CMD_WANT_SKB flag for the cmd in the
  698. * TX cmd queue. Otherwise in case the cmd comes
  699. * in later, it will possibly set an invalid
  700. * address (cmd->meta.source). */
  701. qcmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
  702. qcmd->meta.flags &= ~CMD_WANT_SKB;
  703. }
  704. fail:
  705. if (cmd->meta.u.skb) {
  706. dev_kfree_skb_any(cmd->meta.u.skb);
  707. cmd->meta.u.skb = NULL;
  708. }
  709. out:
  710. atomic_set(&entry, 0);
  711. return ret;
  712. }
  713. int iwl3945_send_cmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  714. {
  715. if (cmd->meta.flags & CMD_ASYNC)
  716. return iwl3945_send_cmd_async(priv, cmd);
  717. return iwl3945_send_cmd_sync(priv, cmd);
  718. }
  719. int iwl3945_send_cmd_pdu(struct iwl3945_priv *priv, u8 id, u16 len, const void *data)
  720. {
  721. struct iwl3945_host_cmd cmd = {
  722. .id = id,
  723. .len = len,
  724. .data = data,
  725. };
  726. return iwl3945_send_cmd_sync(priv, &cmd);
  727. }
  728. static int __must_check iwl3945_send_cmd_u32(struct iwl3945_priv *priv, u8 id, u32 val)
  729. {
  730. struct iwl3945_host_cmd cmd = {
  731. .id = id,
  732. .len = sizeof(val),
  733. .data = &val,
  734. };
  735. return iwl3945_send_cmd_sync(priv, &cmd);
  736. }
  737. int iwl3945_send_statistics_request(struct iwl3945_priv *priv)
  738. {
  739. return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
  740. }
  741. /**
  742. * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
  743. * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
  744. * @channel: Any channel valid for the requested phymode
  745. * In addition to setting the staging RXON, priv->phymode is also set.
  746. *
  747. * NOTE: Does not commit to the hardware; it sets appropriate bit fields
  748. * in the staging RXON flag structure based on the phymode
  749. */
  750. static int iwl3945_set_rxon_channel(struct iwl3945_priv *priv, u8 phymode, u16 channel)
  751. {
  752. if (!iwl3945_get_channel_info(priv, phymode, channel)) {
  753. IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
  754. channel, phymode);
  755. return -EINVAL;
  756. }
  757. if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
  758. (priv->phymode == phymode))
  759. return 0;
  760. priv->staging_rxon.channel = cpu_to_le16(channel);
  761. if (phymode == MODE_IEEE80211A)
  762. priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
  763. else
  764. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  765. priv->phymode = phymode;
  766. IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, phymode);
  767. return 0;
  768. }
  769. /**
  770. * iwl3945_check_rxon_cmd - validate RXON structure is valid
  771. *
  772. * NOTE: This is really only useful during development and can eventually
  773. * be #ifdef'd out once the driver is stable and folks aren't actively
  774. * making changes
  775. */
  776. static int iwl3945_check_rxon_cmd(struct iwl3945_rxon_cmd *rxon)
  777. {
  778. int error = 0;
  779. int counter = 1;
  780. if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
  781. error |= le32_to_cpu(rxon->flags &
  782. (RXON_FLG_TGJ_NARROW_BAND_MSK |
  783. RXON_FLG_RADAR_DETECT_MSK));
  784. if (error)
  785. IWL_WARNING("check 24G fields %d | %d\n",
  786. counter++, error);
  787. } else {
  788. error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
  789. 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
  790. if (error)
  791. IWL_WARNING("check 52 fields %d | %d\n",
  792. counter++, error);
  793. error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
  794. if (error)
  795. IWL_WARNING("check 52 CCK %d | %d\n",
  796. counter++, error);
  797. }
  798. error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
  799. if (error)
  800. IWL_WARNING("check mac addr %d | %d\n", counter++, error);
  801. /* make sure basic rates 6Mbps and 1Mbps are supported */
  802. error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
  803. ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
  804. if (error)
  805. IWL_WARNING("check basic rate %d | %d\n", counter++, error);
  806. error |= (le16_to_cpu(rxon->assoc_id) > 2007);
  807. if (error)
  808. IWL_WARNING("check assoc id %d | %d\n", counter++, error);
  809. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
  810. == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
  811. if (error)
  812. IWL_WARNING("check CCK and short slot %d | %d\n",
  813. counter++, error);
  814. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
  815. == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
  816. if (error)
  817. IWL_WARNING("check CCK & auto detect %d | %d\n",
  818. counter++, error);
  819. error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
  820. RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
  821. if (error)
  822. IWL_WARNING("check TGG and auto detect %d | %d\n",
  823. counter++, error);
  824. if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
  825. error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
  826. RXON_FLG_ANT_A_MSK)) == 0);
  827. if (error)
  828. IWL_WARNING("check antenna %d %d\n", counter++, error);
  829. if (error)
  830. IWL_WARNING("Tuning to channel %d\n",
  831. le16_to_cpu(rxon->channel));
  832. if (error) {
  833. IWL_ERROR("Not a valid iwl3945_rxon_assoc_cmd field values\n");
  834. return -1;
  835. }
  836. return 0;
  837. }
  838. /**
  839. * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
  840. * @priv: staging_rxon is compared to active_rxon
  841. *
  842. * If the RXON structure is changing enough to require a new tune,
  843. * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
  844. * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
  845. */
  846. static int iwl3945_full_rxon_required(struct iwl3945_priv *priv)
  847. {
  848. /* These items are only settable from the full RXON command */
  849. if (!(priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) ||
  850. compare_ether_addr(priv->staging_rxon.bssid_addr,
  851. priv->active_rxon.bssid_addr) ||
  852. compare_ether_addr(priv->staging_rxon.node_addr,
  853. priv->active_rxon.node_addr) ||
  854. compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
  855. priv->active_rxon.wlap_bssid_addr) ||
  856. (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
  857. (priv->staging_rxon.channel != priv->active_rxon.channel) ||
  858. (priv->staging_rxon.air_propagation !=
  859. priv->active_rxon.air_propagation) ||
  860. (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
  861. return 1;
  862. /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
  863. * be updated with the RXON_ASSOC command -- however only some
  864. * flag transitions are allowed using RXON_ASSOC */
  865. /* Check if we are not switching bands */
  866. if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
  867. (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
  868. return 1;
  869. /* Check if we are switching association toggle */
  870. if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
  871. (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
  872. return 1;
  873. return 0;
  874. }
  875. static int iwl3945_send_rxon_assoc(struct iwl3945_priv *priv)
  876. {
  877. int rc = 0;
  878. struct iwl3945_rx_packet *res = NULL;
  879. struct iwl3945_rxon_assoc_cmd rxon_assoc;
  880. struct iwl3945_host_cmd cmd = {
  881. .id = REPLY_RXON_ASSOC,
  882. .len = sizeof(rxon_assoc),
  883. .meta.flags = CMD_WANT_SKB,
  884. .data = &rxon_assoc,
  885. };
  886. const struct iwl3945_rxon_cmd *rxon1 = &priv->staging_rxon;
  887. const struct iwl3945_rxon_cmd *rxon2 = &priv->active_rxon;
  888. if ((rxon1->flags == rxon2->flags) &&
  889. (rxon1->filter_flags == rxon2->filter_flags) &&
  890. (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
  891. (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
  892. IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
  893. return 0;
  894. }
  895. rxon_assoc.flags = priv->staging_rxon.flags;
  896. rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
  897. rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
  898. rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
  899. rxon_assoc.reserved = 0;
  900. rc = iwl3945_send_cmd_sync(priv, &cmd);
  901. if (rc)
  902. return rc;
  903. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  904. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  905. IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n");
  906. rc = -EIO;
  907. }
  908. priv->alloc_rxb_skb--;
  909. dev_kfree_skb_any(cmd.meta.u.skb);
  910. return rc;
  911. }
  912. /**
  913. * iwl3945_commit_rxon - commit staging_rxon to hardware
  914. *
  915. * The RXON command in staging_rxon is committed to the hardware and
  916. * the active_rxon structure is updated with the new data. This
  917. * function correctly transitions out of the RXON_ASSOC_MSK state if
  918. * a HW tune is required based on the RXON structure changes.
  919. */
  920. static int iwl3945_commit_rxon(struct iwl3945_priv *priv)
  921. {
  922. /* cast away the const for active_rxon in this function */
  923. struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  924. int rc = 0;
  925. DECLARE_MAC_BUF(mac);
  926. if (!iwl3945_is_alive(priv))
  927. return -1;
  928. /* always get timestamp with Rx frame */
  929. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  930. /* select antenna */
  931. priv->staging_rxon.flags &=
  932. ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
  933. priv->staging_rxon.flags |= iwl3945_get_antenna_flags(priv);
  934. rc = iwl3945_check_rxon_cmd(&priv->staging_rxon);
  935. if (rc) {
  936. IWL_ERROR("Invalid RXON configuration. Not committing.\n");
  937. return -EINVAL;
  938. }
  939. /* If we don't need to send a full RXON, we can use
  940. * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
  941. * and other flags for the current radio configuration. */
  942. if (!iwl3945_full_rxon_required(priv)) {
  943. rc = iwl3945_send_rxon_assoc(priv);
  944. if (rc) {
  945. IWL_ERROR("Error setting RXON_ASSOC "
  946. "configuration (%d).\n", rc);
  947. return rc;
  948. }
  949. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  950. return 0;
  951. }
  952. /* If we are currently associated and the new config requires
  953. * an RXON_ASSOC and the new config wants the associated mask enabled,
  954. * we must clear the associated from the active configuration
  955. * before we apply the new config */
  956. if (iwl3945_is_associated(priv) &&
  957. (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
  958. IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
  959. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  960. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  961. sizeof(struct iwl3945_rxon_cmd),
  962. &priv->active_rxon);
  963. /* If the mask clearing failed then we set
  964. * active_rxon back to what it was previously */
  965. if (rc) {
  966. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  967. IWL_ERROR("Error clearing ASSOC_MSK on current "
  968. "configuration (%d).\n", rc);
  969. return rc;
  970. }
  971. }
  972. IWL_DEBUG_INFO("Sending RXON\n"
  973. "* with%s RXON_FILTER_ASSOC_MSK\n"
  974. "* channel = %d\n"
  975. "* bssid = %s\n",
  976. ((priv->staging_rxon.filter_flags &
  977. RXON_FILTER_ASSOC_MSK) ? "" : "out"),
  978. le16_to_cpu(priv->staging_rxon.channel),
  979. print_mac(mac, priv->staging_rxon.bssid_addr));
  980. /* Apply the new configuration */
  981. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  982. sizeof(struct iwl3945_rxon_cmd), &priv->staging_rxon);
  983. if (rc) {
  984. IWL_ERROR("Error setting new configuration (%d).\n", rc);
  985. return rc;
  986. }
  987. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  988. iwl3945_clear_stations_table(priv);
  989. /* If we issue a new RXON command which required a tune then we must
  990. * send a new TXPOWER command or we won't be able to Tx any frames */
  991. rc = iwl3945_hw_reg_send_txpower(priv);
  992. if (rc) {
  993. IWL_ERROR("Error setting Tx power (%d).\n", rc);
  994. return rc;
  995. }
  996. /* Add the broadcast address so we can send broadcast frames */
  997. if (iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0) ==
  998. IWL_INVALID_STATION) {
  999. IWL_ERROR("Error adding BROADCAST address for transmit.\n");
  1000. return -EIO;
  1001. }
  1002. /* If we have set the ASSOC_MSK and we are in BSS mode then
  1003. * add the IWL_AP_ID to the station rate table */
  1004. if (iwl3945_is_associated(priv) &&
  1005. (priv->iw_mode == IEEE80211_IF_TYPE_STA))
  1006. if (iwl3945_add_station(priv, priv->active_rxon.bssid_addr, 1, 0)
  1007. == IWL_INVALID_STATION) {
  1008. IWL_ERROR("Error adding AP address for transmit.\n");
  1009. return -EIO;
  1010. }
  1011. /* Init the hardware's rate fallback order based on the
  1012. * phymode */
  1013. rc = iwl3945_init_hw_rate_table(priv);
  1014. if (rc) {
  1015. IWL_ERROR("Error setting HW rate table: %02X\n", rc);
  1016. return -EIO;
  1017. }
  1018. return 0;
  1019. }
  1020. static int iwl3945_send_bt_config(struct iwl3945_priv *priv)
  1021. {
  1022. struct iwl3945_bt_cmd bt_cmd = {
  1023. .flags = 3,
  1024. .lead_time = 0xAA,
  1025. .max_kill = 1,
  1026. .kill_ack_mask = 0,
  1027. .kill_cts_mask = 0,
  1028. };
  1029. return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
  1030. sizeof(struct iwl3945_bt_cmd), &bt_cmd);
  1031. }
  1032. static int iwl3945_send_scan_abort(struct iwl3945_priv *priv)
  1033. {
  1034. int rc = 0;
  1035. struct iwl3945_rx_packet *res;
  1036. struct iwl3945_host_cmd cmd = {
  1037. .id = REPLY_SCAN_ABORT_CMD,
  1038. .meta.flags = CMD_WANT_SKB,
  1039. };
  1040. /* If there isn't a scan actively going on in the hardware
  1041. * then we are in between scan bands and not actually
  1042. * actively scanning, so don't send the abort command */
  1043. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  1044. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  1045. return 0;
  1046. }
  1047. rc = iwl3945_send_cmd_sync(priv, &cmd);
  1048. if (rc) {
  1049. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  1050. return rc;
  1051. }
  1052. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  1053. if (res->u.status != CAN_ABORT_STATUS) {
  1054. /* The scan abort will return 1 for success or
  1055. * 2 for "failure". A failure condition can be
  1056. * due to simply not being in an active scan which
  1057. * can occur if we send the scan abort before we
  1058. * the microcode has notified us that a scan is
  1059. * completed. */
  1060. IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
  1061. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  1062. clear_bit(STATUS_SCAN_HW, &priv->status);
  1063. }
  1064. dev_kfree_skb_any(cmd.meta.u.skb);
  1065. return rc;
  1066. }
  1067. static int iwl3945_card_state_sync_callback(struct iwl3945_priv *priv,
  1068. struct iwl3945_cmd *cmd,
  1069. struct sk_buff *skb)
  1070. {
  1071. return 1;
  1072. }
  1073. /*
  1074. * CARD_STATE_CMD
  1075. *
  1076. * Use: Sets the device's internal card state to enable, disable, or halt
  1077. *
  1078. * When in the 'enable' state the card operates as normal.
  1079. * When in the 'disable' state, the card enters into a low power mode.
  1080. * When in the 'halt' state, the card is shut down and must be fully
  1081. * restarted to come back on.
  1082. */
  1083. static int iwl3945_send_card_state(struct iwl3945_priv *priv, u32 flags, u8 meta_flag)
  1084. {
  1085. struct iwl3945_host_cmd cmd = {
  1086. .id = REPLY_CARD_STATE_CMD,
  1087. .len = sizeof(u32),
  1088. .data = &flags,
  1089. .meta.flags = meta_flag,
  1090. };
  1091. if (meta_flag & CMD_ASYNC)
  1092. cmd.meta.u.callback = iwl3945_card_state_sync_callback;
  1093. return iwl3945_send_cmd(priv, &cmd);
  1094. }
  1095. static int iwl3945_add_sta_sync_callback(struct iwl3945_priv *priv,
  1096. struct iwl3945_cmd *cmd, struct sk_buff *skb)
  1097. {
  1098. struct iwl3945_rx_packet *res = NULL;
  1099. if (!skb) {
  1100. IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n");
  1101. return 1;
  1102. }
  1103. res = (struct iwl3945_rx_packet *)skb->data;
  1104. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  1105. IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
  1106. res->hdr.flags);
  1107. return 1;
  1108. }
  1109. switch (res->u.add_sta.status) {
  1110. case ADD_STA_SUCCESS_MSK:
  1111. break;
  1112. default:
  1113. break;
  1114. }
  1115. /* We didn't cache the SKB; let the caller free it */
  1116. return 1;
  1117. }
  1118. int iwl3945_send_add_station(struct iwl3945_priv *priv,
  1119. struct iwl3945_addsta_cmd *sta, u8 flags)
  1120. {
  1121. struct iwl3945_rx_packet *res = NULL;
  1122. int rc = 0;
  1123. struct iwl3945_host_cmd cmd = {
  1124. .id = REPLY_ADD_STA,
  1125. .len = sizeof(struct iwl3945_addsta_cmd),
  1126. .meta.flags = flags,
  1127. .data = sta,
  1128. };
  1129. if (flags & CMD_ASYNC)
  1130. cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
  1131. else
  1132. cmd.meta.flags |= CMD_WANT_SKB;
  1133. rc = iwl3945_send_cmd(priv, &cmd);
  1134. if (rc || (flags & CMD_ASYNC))
  1135. return rc;
  1136. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  1137. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  1138. IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
  1139. res->hdr.flags);
  1140. rc = -EIO;
  1141. }
  1142. if (rc == 0) {
  1143. switch (res->u.add_sta.status) {
  1144. case ADD_STA_SUCCESS_MSK:
  1145. IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
  1146. break;
  1147. default:
  1148. rc = -EIO;
  1149. IWL_WARNING("REPLY_ADD_STA failed\n");
  1150. break;
  1151. }
  1152. }
  1153. priv->alloc_rxb_skb--;
  1154. dev_kfree_skb_any(cmd.meta.u.skb);
  1155. return rc;
  1156. }
  1157. static int iwl3945_update_sta_key_info(struct iwl3945_priv *priv,
  1158. struct ieee80211_key_conf *keyconf,
  1159. u8 sta_id)
  1160. {
  1161. unsigned long flags;
  1162. __le16 key_flags = 0;
  1163. switch (keyconf->alg) {
  1164. case ALG_CCMP:
  1165. key_flags |= STA_KEY_FLG_CCMP;
  1166. key_flags |= cpu_to_le16(
  1167. keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
  1168. key_flags &= ~STA_KEY_FLG_INVALID;
  1169. break;
  1170. case ALG_TKIP:
  1171. case ALG_WEP:
  1172. default:
  1173. return -EINVAL;
  1174. }
  1175. spin_lock_irqsave(&priv->sta_lock, flags);
  1176. priv->stations[sta_id].keyinfo.alg = keyconf->alg;
  1177. priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
  1178. memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
  1179. keyconf->keylen);
  1180. memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
  1181. keyconf->keylen);
  1182. priv->stations[sta_id].sta.key.key_flags = key_flags;
  1183. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1184. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1185. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1186. IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
  1187. iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
  1188. return 0;
  1189. }
  1190. static int iwl3945_clear_sta_key_info(struct iwl3945_priv *priv, u8 sta_id)
  1191. {
  1192. unsigned long flags;
  1193. spin_lock_irqsave(&priv->sta_lock, flags);
  1194. memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
  1195. memset(&priv->stations[sta_id].sta.key, 0, sizeof(struct iwl3945_keyinfo));
  1196. priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
  1197. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1198. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1199. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1200. IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
  1201. iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
  1202. return 0;
  1203. }
  1204. static void iwl3945_clear_free_frames(struct iwl3945_priv *priv)
  1205. {
  1206. struct list_head *element;
  1207. IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
  1208. priv->frames_count);
  1209. while (!list_empty(&priv->free_frames)) {
  1210. element = priv->free_frames.next;
  1211. list_del(element);
  1212. kfree(list_entry(element, struct iwl3945_frame, list));
  1213. priv->frames_count--;
  1214. }
  1215. if (priv->frames_count) {
  1216. IWL_WARNING("%d frames still in use. Did we lose one?\n",
  1217. priv->frames_count);
  1218. priv->frames_count = 0;
  1219. }
  1220. }
  1221. static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl3945_priv *priv)
  1222. {
  1223. struct iwl3945_frame *frame;
  1224. struct list_head *element;
  1225. if (list_empty(&priv->free_frames)) {
  1226. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  1227. if (!frame) {
  1228. IWL_ERROR("Could not allocate frame!\n");
  1229. return NULL;
  1230. }
  1231. priv->frames_count++;
  1232. return frame;
  1233. }
  1234. element = priv->free_frames.next;
  1235. list_del(element);
  1236. return list_entry(element, struct iwl3945_frame, list);
  1237. }
  1238. static void iwl3945_free_frame(struct iwl3945_priv *priv, struct iwl3945_frame *frame)
  1239. {
  1240. memset(frame, 0, sizeof(*frame));
  1241. list_add(&frame->list, &priv->free_frames);
  1242. }
  1243. unsigned int iwl3945_fill_beacon_frame(struct iwl3945_priv *priv,
  1244. struct ieee80211_hdr *hdr,
  1245. const u8 *dest, int left)
  1246. {
  1247. if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
  1248. ((priv->iw_mode != IEEE80211_IF_TYPE_IBSS) &&
  1249. (priv->iw_mode != IEEE80211_IF_TYPE_AP)))
  1250. return 0;
  1251. if (priv->ibss_beacon->len > left)
  1252. return 0;
  1253. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  1254. return priv->ibss_beacon->len;
  1255. }
  1256. static int iwl3945_rate_index_from_plcp(int plcp)
  1257. {
  1258. int i = 0;
  1259. for (i = 0; i < IWL_RATE_COUNT; i++)
  1260. if (iwl3945_rates[i].plcp == plcp)
  1261. return i;
  1262. return -1;
  1263. }
  1264. static u8 iwl3945_rate_get_lowest_plcp(int rate_mask)
  1265. {
  1266. u8 i;
  1267. for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
  1268. i = iwl3945_rates[i].next_ieee) {
  1269. if (rate_mask & (1 << i))
  1270. return iwl3945_rates[i].plcp;
  1271. }
  1272. return IWL_RATE_INVALID;
  1273. }
  1274. static int iwl3945_send_beacon_cmd(struct iwl3945_priv *priv)
  1275. {
  1276. struct iwl3945_frame *frame;
  1277. unsigned int frame_size;
  1278. int rc;
  1279. u8 rate;
  1280. frame = iwl3945_get_free_frame(priv);
  1281. if (!frame) {
  1282. IWL_ERROR("Could not obtain free frame buffer for beacon "
  1283. "command.\n");
  1284. return -ENOMEM;
  1285. }
  1286. if (!(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)) {
  1287. rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic &
  1288. 0xFF0);
  1289. if (rate == IWL_INVALID_RATE)
  1290. rate = IWL_RATE_6M_PLCP;
  1291. } else {
  1292. rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic & 0xF);
  1293. if (rate == IWL_INVALID_RATE)
  1294. rate = IWL_RATE_1M_PLCP;
  1295. }
  1296. frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
  1297. rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  1298. &frame->u.cmd[0]);
  1299. iwl3945_free_frame(priv, frame);
  1300. return rc;
  1301. }
  1302. /******************************************************************************
  1303. *
  1304. * EEPROM related functions
  1305. *
  1306. ******************************************************************************/
  1307. static void get_eeprom_mac(struct iwl3945_priv *priv, u8 *mac)
  1308. {
  1309. memcpy(mac, priv->eeprom.mac_address, 6);
  1310. }
  1311. /**
  1312. * iwl3945_eeprom_init - read EEPROM contents
  1313. *
  1314. * Load the EEPROM contents from adapter into priv->eeprom
  1315. *
  1316. * NOTE: This routine uses the non-debug IO access functions.
  1317. */
  1318. int iwl3945_eeprom_init(struct iwl3945_priv *priv)
  1319. {
  1320. u16 *e = (u16 *)&priv->eeprom;
  1321. u32 gp = iwl3945_read32(priv, CSR_EEPROM_GP);
  1322. u32 r;
  1323. int sz = sizeof(priv->eeprom);
  1324. int rc;
  1325. int i;
  1326. u16 addr;
  1327. /* The EEPROM structure has several padding buffers within it
  1328. * and when adding new EEPROM maps is subject to programmer errors
  1329. * which may be very difficult to identify without explicitly
  1330. * checking the resulting size of the eeprom map. */
  1331. BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE);
  1332. if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
  1333. IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x", gp);
  1334. return -ENOENT;
  1335. }
  1336. /* Make sure driver (instead of uCode) is allowed to read EEPROM */
  1337. rc = iwl3945_eeprom_acquire_semaphore(priv);
  1338. if (rc < 0) {
  1339. IWL_ERROR("Failed to acquire EEPROM semaphore.\n");
  1340. return -ENOENT;
  1341. }
  1342. /* eeprom is an array of 16bit values */
  1343. for (addr = 0; addr < sz; addr += sizeof(u16)) {
  1344. _iwl3945_write32(priv, CSR_EEPROM_REG, addr << 1);
  1345. _iwl3945_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
  1346. for (i = 0; i < IWL_EEPROM_ACCESS_TIMEOUT;
  1347. i += IWL_EEPROM_ACCESS_DELAY) {
  1348. r = _iwl3945_read_direct32(priv, CSR_EEPROM_REG);
  1349. if (r & CSR_EEPROM_REG_READ_VALID_MSK)
  1350. break;
  1351. udelay(IWL_EEPROM_ACCESS_DELAY);
  1352. }
  1353. if (!(r & CSR_EEPROM_REG_READ_VALID_MSK)) {
  1354. IWL_ERROR("Time out reading EEPROM[%d]", addr);
  1355. return -ETIMEDOUT;
  1356. }
  1357. e[addr / 2] = le16_to_cpu(r >> 16);
  1358. }
  1359. return 0;
  1360. }
  1361. /******************************************************************************
  1362. *
  1363. * Misc. internal state and helper functions
  1364. *
  1365. ******************************************************************************/
  1366. #ifdef CONFIG_IWL3945_DEBUG
  1367. /**
  1368. * iwl3945_report_frame - dump frame to syslog during debug sessions
  1369. *
  1370. * You may hack this function to show different aspects of received frames,
  1371. * including selective frame dumps.
  1372. * group100 parameter selects whether to show 1 out of 100 good frames.
  1373. */
  1374. void iwl3945_report_frame(struct iwl3945_priv *priv,
  1375. struct iwl3945_rx_packet *pkt,
  1376. struct ieee80211_hdr *header, int group100)
  1377. {
  1378. u32 to_us;
  1379. u32 print_summary = 0;
  1380. u32 print_dump = 0; /* set to 1 to dump all frames' contents */
  1381. u32 hundred = 0;
  1382. u32 dataframe = 0;
  1383. u16 fc;
  1384. u16 seq_ctl;
  1385. u16 channel;
  1386. u16 phy_flags;
  1387. int rate_sym;
  1388. u16 length;
  1389. u16 status;
  1390. u16 bcn_tmr;
  1391. u32 tsf_low;
  1392. u64 tsf;
  1393. u8 rssi;
  1394. u8 agc;
  1395. u16 sig_avg;
  1396. u16 noise_diff;
  1397. struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
  1398. struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
  1399. struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
  1400. u8 *data = IWL_RX_DATA(pkt);
  1401. /* MAC header */
  1402. fc = le16_to_cpu(header->frame_control);
  1403. seq_ctl = le16_to_cpu(header->seq_ctrl);
  1404. /* metadata */
  1405. channel = le16_to_cpu(rx_hdr->channel);
  1406. phy_flags = le16_to_cpu(rx_hdr->phy_flags);
  1407. rate_sym = rx_hdr->rate;
  1408. length = le16_to_cpu(rx_hdr->len);
  1409. /* end-of-frame status and timestamp */
  1410. status = le32_to_cpu(rx_end->status);
  1411. bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
  1412. tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
  1413. tsf = le64_to_cpu(rx_end->timestamp);
  1414. /* signal statistics */
  1415. rssi = rx_stats->rssi;
  1416. agc = rx_stats->agc;
  1417. sig_avg = le16_to_cpu(rx_stats->sig_avg);
  1418. noise_diff = le16_to_cpu(rx_stats->noise_diff);
  1419. to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
  1420. /* if data frame is to us and all is good,
  1421. * (optionally) print summary for only 1 out of every 100 */
  1422. if (to_us && (fc & ~IEEE80211_FCTL_PROTECTED) ==
  1423. (IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
  1424. dataframe = 1;
  1425. if (!group100)
  1426. print_summary = 1; /* print each frame */
  1427. else if (priv->framecnt_to_us < 100) {
  1428. priv->framecnt_to_us++;
  1429. print_summary = 0;
  1430. } else {
  1431. priv->framecnt_to_us = 0;
  1432. print_summary = 1;
  1433. hundred = 1;
  1434. }
  1435. } else {
  1436. /* print summary for all other frames */
  1437. print_summary = 1;
  1438. }
  1439. if (print_summary) {
  1440. char *title;
  1441. u32 rate;
  1442. if (hundred)
  1443. title = "100Frames";
  1444. else if (fc & IEEE80211_FCTL_RETRY)
  1445. title = "Retry";
  1446. else if (ieee80211_is_assoc_response(fc))
  1447. title = "AscRsp";
  1448. else if (ieee80211_is_reassoc_response(fc))
  1449. title = "RasRsp";
  1450. else if (ieee80211_is_probe_response(fc)) {
  1451. title = "PrbRsp";
  1452. print_dump = 1; /* dump frame contents */
  1453. } else if (ieee80211_is_beacon(fc)) {
  1454. title = "Beacon";
  1455. print_dump = 1; /* dump frame contents */
  1456. } else if (ieee80211_is_atim(fc))
  1457. title = "ATIM";
  1458. else if (ieee80211_is_auth(fc))
  1459. title = "Auth";
  1460. else if (ieee80211_is_deauth(fc))
  1461. title = "DeAuth";
  1462. else if (ieee80211_is_disassoc(fc))
  1463. title = "DisAssoc";
  1464. else
  1465. title = "Frame";
  1466. rate = iwl3945_rate_index_from_plcp(rate_sym);
  1467. if (rate == -1)
  1468. rate = 0;
  1469. else
  1470. rate = iwl3945_rates[rate].ieee / 2;
  1471. /* print frame summary.
  1472. * MAC addresses show just the last byte (for brevity),
  1473. * but you can hack it to show more, if you'd like to. */
  1474. if (dataframe)
  1475. IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
  1476. "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
  1477. title, fc, header->addr1[5],
  1478. length, rssi, channel, rate);
  1479. else {
  1480. /* src/dst addresses assume managed mode */
  1481. IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
  1482. "src=0x%02x, rssi=%u, tim=%lu usec, "
  1483. "phy=0x%02x, chnl=%d\n",
  1484. title, fc, header->addr1[5],
  1485. header->addr3[5], rssi,
  1486. tsf_low - priv->scan_start_tsf,
  1487. phy_flags, channel);
  1488. }
  1489. }
  1490. if (print_dump)
  1491. iwl3945_print_hex_dump(IWL_DL_RX, data, length);
  1492. }
  1493. #endif
  1494. static void iwl3945_unset_hw_setting(struct iwl3945_priv *priv)
  1495. {
  1496. if (priv->hw_setting.shared_virt)
  1497. pci_free_consistent(priv->pci_dev,
  1498. sizeof(struct iwl3945_shared),
  1499. priv->hw_setting.shared_virt,
  1500. priv->hw_setting.shared_phys);
  1501. }
  1502. /**
  1503. * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
  1504. *
  1505. * return : set the bit for each supported rate insert in ie
  1506. */
  1507. static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
  1508. u16 basic_rate, int *left)
  1509. {
  1510. u16 ret_rates = 0, bit;
  1511. int i;
  1512. u8 *cnt = ie;
  1513. u8 *rates = ie + 1;
  1514. for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
  1515. if (bit & supported_rate) {
  1516. ret_rates |= bit;
  1517. rates[*cnt] = iwl3945_rates[i].ieee |
  1518. ((bit & basic_rate) ? 0x80 : 0x00);
  1519. (*cnt)++;
  1520. (*left)--;
  1521. if ((*left <= 0) ||
  1522. (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
  1523. break;
  1524. }
  1525. }
  1526. return ret_rates;
  1527. }
  1528. /**
  1529. * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
  1530. */
  1531. static u16 iwl3945_fill_probe_req(struct iwl3945_priv *priv,
  1532. struct ieee80211_mgmt *frame,
  1533. int left, int is_direct)
  1534. {
  1535. int len = 0;
  1536. u8 *pos = NULL;
  1537. u16 active_rates, ret_rates, cck_rates;
  1538. /* Make sure there is enough space for the probe request,
  1539. * two mandatory IEs and the data */
  1540. left -= 24;
  1541. if (left < 0)
  1542. return 0;
  1543. len += 24;
  1544. frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
  1545. memcpy(frame->da, iwl3945_broadcast_addr, ETH_ALEN);
  1546. memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
  1547. memcpy(frame->bssid, iwl3945_broadcast_addr, ETH_ALEN);
  1548. frame->seq_ctrl = 0;
  1549. /* fill in our indirect SSID IE */
  1550. /* ...next IE... */
  1551. left -= 2;
  1552. if (left < 0)
  1553. return 0;
  1554. len += 2;
  1555. pos = &(frame->u.probe_req.variable[0]);
  1556. *pos++ = WLAN_EID_SSID;
  1557. *pos++ = 0;
  1558. /* fill in our direct SSID IE... */
  1559. if (is_direct) {
  1560. /* ...next IE... */
  1561. left -= 2 + priv->essid_len;
  1562. if (left < 0)
  1563. return 0;
  1564. /* ... fill it in... */
  1565. *pos++ = WLAN_EID_SSID;
  1566. *pos++ = priv->essid_len;
  1567. memcpy(pos, priv->essid, priv->essid_len);
  1568. pos += priv->essid_len;
  1569. len += 2 + priv->essid_len;
  1570. }
  1571. /* fill in supported rate */
  1572. /* ...next IE... */
  1573. left -= 2;
  1574. if (left < 0)
  1575. return 0;
  1576. /* ... fill it in... */
  1577. *pos++ = WLAN_EID_SUPP_RATES;
  1578. *pos = 0;
  1579. priv->active_rate = priv->rates_mask;
  1580. active_rates = priv->active_rate;
  1581. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1582. cck_rates = IWL_CCK_RATES_MASK & active_rates;
  1583. ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
  1584. priv->active_rate_basic, &left);
  1585. active_rates &= ~ret_rates;
  1586. ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
  1587. priv->active_rate_basic, &left);
  1588. active_rates &= ~ret_rates;
  1589. len += 2 + *pos;
  1590. pos += (*pos) + 1;
  1591. if (active_rates == 0)
  1592. goto fill_end;
  1593. /* fill in supported extended rate */
  1594. /* ...next IE... */
  1595. left -= 2;
  1596. if (left < 0)
  1597. return 0;
  1598. /* ... fill it in... */
  1599. *pos++ = WLAN_EID_EXT_SUPP_RATES;
  1600. *pos = 0;
  1601. iwl3945_supported_rate_to_ie(pos, active_rates,
  1602. priv->active_rate_basic, &left);
  1603. if (*pos > 0)
  1604. len += 2 + *pos;
  1605. fill_end:
  1606. return (u16)len;
  1607. }
  1608. /*
  1609. * QoS support
  1610. */
  1611. #ifdef CONFIG_IWL3945_QOS
  1612. static int iwl3945_send_qos_params_command(struct iwl3945_priv *priv,
  1613. struct iwl3945_qosparam_cmd *qos)
  1614. {
  1615. return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
  1616. sizeof(struct iwl3945_qosparam_cmd), qos);
  1617. }
  1618. static void iwl3945_reset_qos(struct iwl3945_priv *priv)
  1619. {
  1620. u16 cw_min = 15;
  1621. u16 cw_max = 1023;
  1622. u8 aifs = 2;
  1623. u8 is_legacy = 0;
  1624. unsigned long flags;
  1625. int i;
  1626. spin_lock_irqsave(&priv->lock, flags);
  1627. priv->qos_data.qos_active = 0;
  1628. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) {
  1629. if (priv->qos_data.qos_enable)
  1630. priv->qos_data.qos_active = 1;
  1631. if (!(priv->active_rate & 0xfff0)) {
  1632. cw_min = 31;
  1633. is_legacy = 1;
  1634. }
  1635. } else if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  1636. if (priv->qos_data.qos_enable)
  1637. priv->qos_data.qos_active = 1;
  1638. } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
  1639. cw_min = 31;
  1640. is_legacy = 1;
  1641. }
  1642. if (priv->qos_data.qos_active)
  1643. aifs = 3;
  1644. priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
  1645. priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
  1646. priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
  1647. priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
  1648. priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
  1649. if (priv->qos_data.qos_active) {
  1650. i = 1;
  1651. priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
  1652. priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
  1653. priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
  1654. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  1655. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1656. i = 2;
  1657. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1658. cpu_to_le16((cw_min + 1) / 2 - 1);
  1659. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1660. cpu_to_le16(cw_max);
  1661. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  1662. if (is_legacy)
  1663. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1664. cpu_to_le16(6016);
  1665. else
  1666. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1667. cpu_to_le16(3008);
  1668. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1669. i = 3;
  1670. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1671. cpu_to_le16((cw_min + 1) / 4 - 1);
  1672. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1673. cpu_to_le16((cw_max + 1) / 2 - 1);
  1674. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  1675. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1676. if (is_legacy)
  1677. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1678. cpu_to_le16(3264);
  1679. else
  1680. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1681. cpu_to_le16(1504);
  1682. } else {
  1683. for (i = 1; i < 4; i++) {
  1684. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1685. cpu_to_le16(cw_min);
  1686. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1687. cpu_to_le16(cw_max);
  1688. priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
  1689. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  1690. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1691. }
  1692. }
  1693. IWL_DEBUG_QOS("set QoS to default \n");
  1694. spin_unlock_irqrestore(&priv->lock, flags);
  1695. }
  1696. static void iwl3945_activate_qos(struct iwl3945_priv *priv, u8 force)
  1697. {
  1698. unsigned long flags;
  1699. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1700. return;
  1701. if (!priv->qos_data.qos_enable)
  1702. return;
  1703. spin_lock_irqsave(&priv->lock, flags);
  1704. priv->qos_data.def_qos_parm.qos_flags = 0;
  1705. if (priv->qos_data.qos_cap.q_AP.queue_request &&
  1706. !priv->qos_data.qos_cap.q_AP.txop_request)
  1707. priv->qos_data.def_qos_parm.qos_flags |=
  1708. QOS_PARAM_FLG_TXOP_TYPE_MSK;
  1709. if (priv->qos_data.qos_active)
  1710. priv->qos_data.def_qos_parm.qos_flags |=
  1711. QOS_PARAM_FLG_UPDATE_EDCA_MSK;
  1712. spin_unlock_irqrestore(&priv->lock, flags);
  1713. if (force || iwl3945_is_associated(priv)) {
  1714. IWL_DEBUG_QOS("send QoS cmd with Qos active %d \n",
  1715. priv->qos_data.qos_active);
  1716. iwl3945_send_qos_params_command(priv,
  1717. &(priv->qos_data.def_qos_parm));
  1718. }
  1719. }
  1720. #endif /* CONFIG_IWL3945_QOS */
  1721. /*
  1722. * Power management (not Tx power!) functions
  1723. */
  1724. #define MSEC_TO_USEC 1024
  1725. #define NOSLP __constant_cpu_to_le32(0)
  1726. #define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK
  1727. #define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
  1728. #define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
  1729. __constant_cpu_to_le32(X1), \
  1730. __constant_cpu_to_le32(X2), \
  1731. __constant_cpu_to_le32(X3), \
  1732. __constant_cpu_to_le32(X4)}
  1733. /* default power management (not Tx power) table values */
  1734. /* for tim 0-10 */
  1735. static struct iwl3945_power_vec_entry range_0[IWL_POWER_AC] = {
  1736. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1737. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
  1738. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
  1739. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
  1740. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
  1741. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
  1742. };
  1743. /* for tim > 10 */
  1744. static struct iwl3945_power_vec_entry range_1[IWL_POWER_AC] = {
  1745. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1746. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
  1747. SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
  1748. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
  1749. SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
  1750. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
  1751. SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
  1752. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
  1753. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
  1754. SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
  1755. };
  1756. int iwl3945_power_init_handle(struct iwl3945_priv *priv)
  1757. {
  1758. int rc = 0, i;
  1759. struct iwl3945_power_mgr *pow_data;
  1760. int size = sizeof(struct iwl3945_power_vec_entry) * IWL_POWER_AC;
  1761. u16 pci_pm;
  1762. IWL_DEBUG_POWER("Initialize power \n");
  1763. pow_data = &(priv->power_data);
  1764. memset(pow_data, 0, sizeof(*pow_data));
  1765. pow_data->active_index = IWL_POWER_RANGE_0;
  1766. pow_data->dtim_val = 0xffff;
  1767. memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
  1768. memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
  1769. rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
  1770. if (rc != 0)
  1771. return 0;
  1772. else {
  1773. struct iwl3945_powertable_cmd *cmd;
  1774. IWL_DEBUG_POWER("adjust power command flags\n");
  1775. for (i = 0; i < IWL_POWER_AC; i++) {
  1776. cmd = &pow_data->pwr_range_0[i].cmd;
  1777. if (pci_pm & 0x1)
  1778. cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
  1779. else
  1780. cmd->flags |= IWL_POWER_PCI_PM_MSK;
  1781. }
  1782. }
  1783. return rc;
  1784. }
  1785. static int iwl3945_update_power_cmd(struct iwl3945_priv *priv,
  1786. struct iwl3945_powertable_cmd *cmd, u32 mode)
  1787. {
  1788. int rc = 0, i;
  1789. u8 skip;
  1790. u32 max_sleep = 0;
  1791. struct iwl3945_power_vec_entry *range;
  1792. u8 period = 0;
  1793. struct iwl3945_power_mgr *pow_data;
  1794. if (mode > IWL_POWER_INDEX_5) {
  1795. IWL_DEBUG_POWER("Error invalid power mode \n");
  1796. return -1;
  1797. }
  1798. pow_data = &(priv->power_data);
  1799. if (pow_data->active_index == IWL_POWER_RANGE_0)
  1800. range = &pow_data->pwr_range_0[0];
  1801. else
  1802. range = &pow_data->pwr_range_1[1];
  1803. memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
  1804. #ifdef IWL_MAC80211_DISABLE
  1805. if (priv->assoc_network != NULL) {
  1806. unsigned long flags;
  1807. period = priv->assoc_network->tim.tim_period;
  1808. }
  1809. #endif /*IWL_MAC80211_DISABLE */
  1810. skip = range[mode].no_dtim;
  1811. if (period == 0) {
  1812. period = 1;
  1813. skip = 0;
  1814. }
  1815. if (skip == 0) {
  1816. max_sleep = period;
  1817. cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1818. } else {
  1819. __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
  1820. max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
  1821. cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1822. }
  1823. for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
  1824. if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
  1825. cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
  1826. }
  1827. IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
  1828. IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
  1829. IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
  1830. IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
  1831. le32_to_cpu(cmd->sleep_interval[0]),
  1832. le32_to_cpu(cmd->sleep_interval[1]),
  1833. le32_to_cpu(cmd->sleep_interval[2]),
  1834. le32_to_cpu(cmd->sleep_interval[3]),
  1835. le32_to_cpu(cmd->sleep_interval[4]));
  1836. return rc;
  1837. }
  1838. static int iwl3945_send_power_mode(struct iwl3945_priv *priv, u32 mode)
  1839. {
  1840. u32 uninitialized_var(final_mode);
  1841. int rc;
  1842. struct iwl3945_powertable_cmd cmd;
  1843. /* If on battery, set to 3,
  1844. * if plugged into AC power, set to CAM ("continuously aware mode"),
  1845. * else user level */
  1846. switch (mode) {
  1847. case IWL_POWER_BATTERY:
  1848. final_mode = IWL_POWER_INDEX_3;
  1849. break;
  1850. case IWL_POWER_AC:
  1851. final_mode = IWL_POWER_MODE_CAM;
  1852. break;
  1853. default:
  1854. final_mode = mode;
  1855. break;
  1856. }
  1857. iwl3945_update_power_cmd(priv, &cmd, final_mode);
  1858. rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD, sizeof(cmd), &cmd);
  1859. if (final_mode == IWL_POWER_MODE_CAM)
  1860. clear_bit(STATUS_POWER_PMI, &priv->status);
  1861. else
  1862. set_bit(STATUS_POWER_PMI, &priv->status);
  1863. return rc;
  1864. }
  1865. int iwl3945_is_network_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header)
  1866. {
  1867. /* Filter incoming packets to determine if they are targeted toward
  1868. * this network, discarding packets coming from ourselves */
  1869. switch (priv->iw_mode) {
  1870. case IEEE80211_IF_TYPE_IBSS: /* Header: Dest. | Source | BSSID */
  1871. /* packets from our adapter are dropped (echo) */
  1872. if (!compare_ether_addr(header->addr2, priv->mac_addr))
  1873. return 0;
  1874. /* {broad,multi}cast packets to our IBSS go through */
  1875. if (is_multicast_ether_addr(header->addr1))
  1876. return !compare_ether_addr(header->addr3, priv->bssid);
  1877. /* packets to our adapter go through */
  1878. return !compare_ether_addr(header->addr1, priv->mac_addr);
  1879. case IEEE80211_IF_TYPE_STA: /* Header: Dest. | AP{BSSID} | Source */
  1880. /* packets from our adapter are dropped (echo) */
  1881. if (!compare_ether_addr(header->addr3, priv->mac_addr))
  1882. return 0;
  1883. /* {broad,multi}cast packets to our BSS go through */
  1884. if (is_multicast_ether_addr(header->addr1))
  1885. return !compare_ether_addr(header->addr2, priv->bssid);
  1886. /* packets to our adapter go through */
  1887. return !compare_ether_addr(header->addr1, priv->mac_addr);
  1888. }
  1889. return 1;
  1890. }
  1891. #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
  1892. static const char *iwl3945_get_tx_fail_reason(u32 status)
  1893. {
  1894. switch (status & TX_STATUS_MSK) {
  1895. case TX_STATUS_SUCCESS:
  1896. return "SUCCESS";
  1897. TX_STATUS_ENTRY(SHORT_LIMIT);
  1898. TX_STATUS_ENTRY(LONG_LIMIT);
  1899. TX_STATUS_ENTRY(FIFO_UNDERRUN);
  1900. TX_STATUS_ENTRY(MGMNT_ABORT);
  1901. TX_STATUS_ENTRY(NEXT_FRAG);
  1902. TX_STATUS_ENTRY(LIFE_EXPIRE);
  1903. TX_STATUS_ENTRY(DEST_PS);
  1904. TX_STATUS_ENTRY(ABORTED);
  1905. TX_STATUS_ENTRY(BT_RETRY);
  1906. TX_STATUS_ENTRY(STA_INVALID);
  1907. TX_STATUS_ENTRY(FRAG_DROPPED);
  1908. TX_STATUS_ENTRY(TID_DISABLE);
  1909. TX_STATUS_ENTRY(FRAME_FLUSHED);
  1910. TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
  1911. TX_STATUS_ENTRY(TX_LOCKED);
  1912. TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
  1913. }
  1914. return "UNKNOWN";
  1915. }
  1916. /**
  1917. * iwl3945_scan_cancel - Cancel any currently executing HW scan
  1918. *
  1919. * NOTE: priv->mutex is not required before calling this function
  1920. */
  1921. static int iwl3945_scan_cancel(struct iwl3945_priv *priv)
  1922. {
  1923. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  1924. clear_bit(STATUS_SCANNING, &priv->status);
  1925. return 0;
  1926. }
  1927. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1928. if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1929. IWL_DEBUG_SCAN("Queuing scan abort.\n");
  1930. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  1931. queue_work(priv->workqueue, &priv->abort_scan);
  1932. } else
  1933. IWL_DEBUG_SCAN("Scan abort already in progress.\n");
  1934. return test_bit(STATUS_SCANNING, &priv->status);
  1935. }
  1936. return 0;
  1937. }
  1938. /**
  1939. * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
  1940. * @ms: amount of time to wait (in milliseconds) for scan to abort
  1941. *
  1942. * NOTE: priv->mutex must be held before calling this function
  1943. */
  1944. static int iwl3945_scan_cancel_timeout(struct iwl3945_priv *priv, unsigned long ms)
  1945. {
  1946. unsigned long now = jiffies;
  1947. int ret;
  1948. ret = iwl3945_scan_cancel(priv);
  1949. if (ret && ms) {
  1950. mutex_unlock(&priv->mutex);
  1951. while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
  1952. test_bit(STATUS_SCANNING, &priv->status))
  1953. msleep(1);
  1954. mutex_lock(&priv->mutex);
  1955. return test_bit(STATUS_SCANNING, &priv->status);
  1956. }
  1957. return ret;
  1958. }
  1959. static void iwl3945_sequence_reset(struct iwl3945_priv *priv)
  1960. {
  1961. /* Reset ieee stats */
  1962. /* We don't reset the net_device_stats (ieee->stats) on
  1963. * re-association */
  1964. priv->last_seq_num = -1;
  1965. priv->last_frag_num = -1;
  1966. priv->last_packet_time = 0;
  1967. iwl3945_scan_cancel(priv);
  1968. }
  1969. #define MAX_UCODE_BEACON_INTERVAL 1024
  1970. #define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
  1971. static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
  1972. {
  1973. u16 new_val = 0;
  1974. u16 beacon_factor = 0;
  1975. beacon_factor =
  1976. (beacon_val + MAX_UCODE_BEACON_INTERVAL)
  1977. / MAX_UCODE_BEACON_INTERVAL;
  1978. new_val = beacon_val / beacon_factor;
  1979. return cpu_to_le16(new_val);
  1980. }
  1981. static void iwl3945_setup_rxon_timing(struct iwl3945_priv *priv)
  1982. {
  1983. u64 interval_tm_unit;
  1984. u64 tsf, result;
  1985. unsigned long flags;
  1986. struct ieee80211_conf *conf = NULL;
  1987. u16 beacon_int = 0;
  1988. conf = ieee80211_get_hw_conf(priv->hw);
  1989. spin_lock_irqsave(&priv->lock, flags);
  1990. priv->rxon_timing.timestamp.dw[1] = cpu_to_le32(priv->timestamp1);
  1991. priv->rxon_timing.timestamp.dw[0] = cpu_to_le32(priv->timestamp0);
  1992. priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
  1993. tsf = priv->timestamp1;
  1994. tsf = ((tsf << 32) | priv->timestamp0);
  1995. beacon_int = priv->beacon_int;
  1996. spin_unlock_irqrestore(&priv->lock, flags);
  1997. if (priv->iw_mode == IEEE80211_IF_TYPE_STA) {
  1998. if (beacon_int == 0) {
  1999. priv->rxon_timing.beacon_interval = cpu_to_le16(100);
  2000. priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
  2001. } else {
  2002. priv->rxon_timing.beacon_interval =
  2003. cpu_to_le16(beacon_int);
  2004. priv->rxon_timing.beacon_interval =
  2005. iwl3945_adjust_beacon_interval(
  2006. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2007. }
  2008. priv->rxon_timing.atim_window = 0;
  2009. } else {
  2010. priv->rxon_timing.beacon_interval =
  2011. iwl3945_adjust_beacon_interval(conf->beacon_int);
  2012. /* TODO: we need to get atim_window from upper stack
  2013. * for now we set to 0 */
  2014. priv->rxon_timing.atim_window = 0;
  2015. }
  2016. interval_tm_unit =
  2017. (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
  2018. result = do_div(tsf, interval_tm_unit);
  2019. priv->rxon_timing.beacon_init_val =
  2020. cpu_to_le32((u32) ((u64) interval_tm_unit - result));
  2021. IWL_DEBUG_ASSOC
  2022. ("beacon interval %d beacon timer %d beacon tim %d\n",
  2023. le16_to_cpu(priv->rxon_timing.beacon_interval),
  2024. le32_to_cpu(priv->rxon_timing.beacon_init_val),
  2025. le16_to_cpu(priv->rxon_timing.atim_window));
  2026. }
  2027. static int iwl3945_scan_initiate(struct iwl3945_priv *priv)
  2028. {
  2029. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  2030. IWL_ERROR("APs don't scan.\n");
  2031. return 0;
  2032. }
  2033. if (!iwl3945_is_ready_rf(priv)) {
  2034. IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
  2035. return -EIO;
  2036. }
  2037. if (test_bit(STATUS_SCANNING, &priv->status)) {
  2038. IWL_DEBUG_SCAN("Scan already in progress.\n");
  2039. return -EAGAIN;
  2040. }
  2041. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  2042. IWL_DEBUG_SCAN("Scan request while abort pending. "
  2043. "Queuing.\n");
  2044. return -EAGAIN;
  2045. }
  2046. IWL_DEBUG_INFO("Starting scan...\n");
  2047. priv->scan_bands = 2;
  2048. set_bit(STATUS_SCANNING, &priv->status);
  2049. priv->scan_start = jiffies;
  2050. priv->scan_pass_start = priv->scan_start;
  2051. queue_work(priv->workqueue, &priv->request_scan);
  2052. return 0;
  2053. }
  2054. static int iwl3945_set_rxon_hwcrypto(struct iwl3945_priv *priv, int hw_decrypt)
  2055. {
  2056. struct iwl3945_rxon_cmd *rxon = &priv->staging_rxon;
  2057. if (hw_decrypt)
  2058. rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
  2059. else
  2060. rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
  2061. return 0;
  2062. }
  2063. static void iwl3945_set_flags_for_phymode(struct iwl3945_priv *priv, u8 phymode)
  2064. {
  2065. if (phymode == MODE_IEEE80211A) {
  2066. priv->staging_rxon.flags &=
  2067. ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
  2068. | RXON_FLG_CCK_MSK);
  2069. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  2070. } else {
  2071. /* Copied from iwl3945_bg_post_associate() */
  2072. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  2073. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  2074. else
  2075. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  2076. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
  2077. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  2078. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  2079. priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
  2080. priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
  2081. }
  2082. }
  2083. /*
  2084. * initialize rxon structure with default values from eeprom
  2085. */
  2086. static void iwl3945_connection_init_rx_config(struct iwl3945_priv *priv)
  2087. {
  2088. const struct iwl3945_channel_info *ch_info;
  2089. memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
  2090. switch (priv->iw_mode) {
  2091. case IEEE80211_IF_TYPE_AP:
  2092. priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
  2093. break;
  2094. case IEEE80211_IF_TYPE_STA:
  2095. priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
  2096. priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
  2097. break;
  2098. case IEEE80211_IF_TYPE_IBSS:
  2099. priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
  2100. priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
  2101. priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
  2102. RXON_FILTER_ACCEPT_GRP_MSK;
  2103. break;
  2104. case IEEE80211_IF_TYPE_MNTR:
  2105. priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
  2106. priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
  2107. RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
  2108. break;
  2109. }
  2110. #if 0
  2111. /* TODO: Figure out when short_preamble would be set and cache from
  2112. * that */
  2113. if (!hw_to_local(priv->hw)->short_preamble)
  2114. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2115. else
  2116. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  2117. #endif
  2118. ch_info = iwl3945_get_channel_info(priv, priv->phymode,
  2119. le16_to_cpu(priv->staging_rxon.channel));
  2120. if (!ch_info)
  2121. ch_info = &priv->channel_info[0];
  2122. /*
  2123. * in some case A channels are all non IBSS
  2124. * in this case force B/G channel
  2125. */
  2126. if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) &&
  2127. !(is_channel_ibss(ch_info)))
  2128. ch_info = &priv->channel_info[0];
  2129. priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
  2130. if (is_channel_a_band(ch_info))
  2131. priv->phymode = MODE_IEEE80211A;
  2132. else
  2133. priv->phymode = MODE_IEEE80211G;
  2134. iwl3945_set_flags_for_phymode(priv, priv->phymode);
  2135. priv->staging_rxon.ofdm_basic_rates =
  2136. (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  2137. priv->staging_rxon.cck_basic_rates =
  2138. (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  2139. }
  2140. static int iwl3945_set_mode(struct iwl3945_priv *priv, int mode)
  2141. {
  2142. if (!iwl3945_is_ready_rf(priv))
  2143. return -EAGAIN;
  2144. if (mode == IEEE80211_IF_TYPE_IBSS) {
  2145. const struct iwl3945_channel_info *ch_info;
  2146. ch_info = iwl3945_get_channel_info(priv,
  2147. priv->phymode,
  2148. le16_to_cpu(priv->staging_rxon.channel));
  2149. if (!ch_info || !is_channel_ibss(ch_info)) {
  2150. IWL_ERROR("channel %d not IBSS channel\n",
  2151. le16_to_cpu(priv->staging_rxon.channel));
  2152. return -EINVAL;
  2153. }
  2154. }
  2155. cancel_delayed_work(&priv->scan_check);
  2156. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  2157. IWL_WARNING("Aborted scan still in progress after 100ms\n");
  2158. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  2159. return -EAGAIN;
  2160. }
  2161. priv->iw_mode = mode;
  2162. iwl3945_connection_init_rx_config(priv);
  2163. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  2164. iwl3945_clear_stations_table(priv);
  2165. iwl3945_commit_rxon(priv);
  2166. return 0;
  2167. }
  2168. static void iwl3945_build_tx_cmd_hwcrypto(struct iwl3945_priv *priv,
  2169. struct ieee80211_tx_control *ctl,
  2170. struct iwl3945_cmd *cmd,
  2171. struct sk_buff *skb_frag,
  2172. int last_frag)
  2173. {
  2174. struct iwl3945_hw_key *keyinfo = &priv->stations[ctl->key_idx].keyinfo;
  2175. switch (keyinfo->alg) {
  2176. case ALG_CCMP:
  2177. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM;
  2178. memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen);
  2179. IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n");
  2180. break;
  2181. case ALG_TKIP:
  2182. #if 0
  2183. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP;
  2184. if (last_frag)
  2185. memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8,
  2186. 8);
  2187. else
  2188. memset(cmd->cmd.tx.tkip_mic.byte, 0, 8);
  2189. #endif
  2190. break;
  2191. case ALG_WEP:
  2192. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP |
  2193. (ctl->key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
  2194. if (keyinfo->keylen == 13)
  2195. cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
  2196. memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen);
  2197. IWL_DEBUG_TX("Configuring packet for WEP encryption "
  2198. "with key %d\n", ctl->key_idx);
  2199. break;
  2200. default:
  2201. printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg);
  2202. break;
  2203. }
  2204. }
  2205. /*
  2206. * handle build REPLY_TX command notification.
  2207. */
  2208. static void iwl3945_build_tx_cmd_basic(struct iwl3945_priv *priv,
  2209. struct iwl3945_cmd *cmd,
  2210. struct ieee80211_tx_control *ctrl,
  2211. struct ieee80211_hdr *hdr,
  2212. int is_unicast, u8 std_id)
  2213. {
  2214. __le16 *qc;
  2215. u16 fc = le16_to_cpu(hdr->frame_control);
  2216. __le32 tx_flags = cmd->cmd.tx.tx_flags;
  2217. cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  2218. if (!(ctrl->flags & IEEE80211_TXCTL_NO_ACK)) {
  2219. tx_flags |= TX_CMD_FLG_ACK_MSK;
  2220. if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT)
  2221. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  2222. if (ieee80211_is_probe_response(fc) &&
  2223. !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
  2224. tx_flags |= TX_CMD_FLG_TSF_MSK;
  2225. } else {
  2226. tx_flags &= (~TX_CMD_FLG_ACK_MSK);
  2227. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  2228. }
  2229. cmd->cmd.tx.sta_id = std_id;
  2230. if (ieee80211_get_morefrag(hdr))
  2231. tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
  2232. qc = ieee80211_get_qos_ctrl(hdr);
  2233. if (qc) {
  2234. cmd->cmd.tx.tid_tspec = (u8) (le16_to_cpu(*qc) & 0xf);
  2235. tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
  2236. } else
  2237. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  2238. if (ctrl->flags & IEEE80211_TXCTL_USE_RTS_CTS) {
  2239. tx_flags |= TX_CMD_FLG_RTS_MSK;
  2240. tx_flags &= ~TX_CMD_FLG_CTS_MSK;
  2241. } else if (ctrl->flags & IEEE80211_TXCTL_USE_CTS_PROTECT) {
  2242. tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  2243. tx_flags |= TX_CMD_FLG_CTS_MSK;
  2244. }
  2245. if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
  2246. tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
  2247. tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
  2248. if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) {
  2249. if ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_ASSOC_REQ ||
  2250. (fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_REASSOC_REQ)
  2251. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
  2252. else
  2253. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
  2254. } else
  2255. cmd->cmd.tx.timeout.pm_frame_timeout = 0;
  2256. cmd->cmd.tx.driver_txop = 0;
  2257. cmd->cmd.tx.tx_flags = tx_flags;
  2258. cmd->cmd.tx.next_frame_len = 0;
  2259. }
  2260. /**
  2261. * iwl3945_get_sta_id - Find station's index within station table
  2262. */
  2263. static int iwl3945_get_sta_id(struct iwl3945_priv *priv, struct ieee80211_hdr *hdr)
  2264. {
  2265. int sta_id;
  2266. u16 fc = le16_to_cpu(hdr->frame_control);
  2267. /* If this frame is broadcast or management, use broadcast station id */
  2268. if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
  2269. is_multicast_ether_addr(hdr->addr1))
  2270. return priv->hw_setting.bcast_sta_id;
  2271. switch (priv->iw_mode) {
  2272. /* If we are a client station in a BSS network, use the special
  2273. * AP station entry (that's the only station we communicate with) */
  2274. case IEEE80211_IF_TYPE_STA:
  2275. return IWL_AP_ID;
  2276. /* If we are an AP, then find the station, or use BCAST */
  2277. case IEEE80211_IF_TYPE_AP:
  2278. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  2279. if (sta_id != IWL_INVALID_STATION)
  2280. return sta_id;
  2281. return priv->hw_setting.bcast_sta_id;
  2282. /* If this frame is going out to an IBSS network, find the station,
  2283. * or create a new station table entry */
  2284. case IEEE80211_IF_TYPE_IBSS: {
  2285. DECLARE_MAC_BUF(mac);
  2286. /* Create new station table entry */
  2287. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  2288. if (sta_id != IWL_INVALID_STATION)
  2289. return sta_id;
  2290. sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
  2291. if (sta_id != IWL_INVALID_STATION)
  2292. return sta_id;
  2293. IWL_DEBUG_DROP("Station %s not in station map. "
  2294. "Defaulting to broadcast...\n",
  2295. print_mac(mac, hdr->addr1));
  2296. iwl3945_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
  2297. return priv->hw_setting.bcast_sta_id;
  2298. }
  2299. default:
  2300. IWL_WARNING("Unknown mode of operation: %d", priv->iw_mode);
  2301. return priv->hw_setting.bcast_sta_id;
  2302. }
  2303. }
  2304. /*
  2305. * start REPLY_TX command process
  2306. */
  2307. static int iwl3945_tx_skb(struct iwl3945_priv *priv,
  2308. struct sk_buff *skb, struct ieee80211_tx_control *ctl)
  2309. {
  2310. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  2311. struct iwl3945_tfd_frame *tfd;
  2312. u32 *control_flags;
  2313. int txq_id = ctl->queue;
  2314. struct iwl3945_tx_queue *txq = NULL;
  2315. struct iwl3945_queue *q = NULL;
  2316. dma_addr_t phys_addr;
  2317. dma_addr_t txcmd_phys;
  2318. struct iwl3945_cmd *out_cmd = NULL;
  2319. u16 len, idx, len_org;
  2320. u8 id, hdr_len, unicast;
  2321. u8 sta_id;
  2322. u16 seq_number = 0;
  2323. u16 fc;
  2324. __le16 *qc;
  2325. u8 wait_write_ptr = 0;
  2326. unsigned long flags;
  2327. int rc;
  2328. spin_lock_irqsave(&priv->lock, flags);
  2329. if (iwl3945_is_rfkill(priv)) {
  2330. IWL_DEBUG_DROP("Dropping - RF KILL\n");
  2331. goto drop_unlock;
  2332. }
  2333. if (!priv->interface_id) {
  2334. IWL_DEBUG_DROP("Dropping - !priv->interface_id\n");
  2335. goto drop_unlock;
  2336. }
  2337. if ((ctl->tx_rate & 0xFF) == IWL_INVALID_RATE) {
  2338. IWL_ERROR("ERROR: No TX rate available.\n");
  2339. goto drop_unlock;
  2340. }
  2341. unicast = !is_multicast_ether_addr(hdr->addr1);
  2342. id = 0;
  2343. fc = le16_to_cpu(hdr->frame_control);
  2344. #ifdef CONFIG_IWL3945_DEBUG
  2345. if (ieee80211_is_auth(fc))
  2346. IWL_DEBUG_TX("Sending AUTH frame\n");
  2347. else if (ieee80211_is_assoc_request(fc))
  2348. IWL_DEBUG_TX("Sending ASSOC frame\n");
  2349. else if (ieee80211_is_reassoc_request(fc))
  2350. IWL_DEBUG_TX("Sending REASSOC frame\n");
  2351. #endif
  2352. /* drop all data frame if we are not associated */
  2353. if (!iwl3945_is_associated(priv) && !priv->assoc_id &&
  2354. ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA)) {
  2355. IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
  2356. goto drop_unlock;
  2357. }
  2358. spin_unlock_irqrestore(&priv->lock, flags);
  2359. hdr_len = ieee80211_get_hdrlen(fc);
  2360. /* Find (or create) index into station table for destination station */
  2361. sta_id = iwl3945_get_sta_id(priv, hdr);
  2362. if (sta_id == IWL_INVALID_STATION) {
  2363. DECLARE_MAC_BUF(mac);
  2364. IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n",
  2365. print_mac(mac, hdr->addr1));
  2366. goto drop;
  2367. }
  2368. IWL_DEBUG_RATE("station Id %d\n", sta_id);
  2369. qc = ieee80211_get_qos_ctrl(hdr);
  2370. if (qc) {
  2371. u8 tid = (u8)(le16_to_cpu(*qc) & 0xf);
  2372. seq_number = priv->stations[sta_id].tid[tid].seq_number &
  2373. IEEE80211_SCTL_SEQ;
  2374. hdr->seq_ctrl = cpu_to_le16(seq_number) |
  2375. (hdr->seq_ctrl &
  2376. __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
  2377. seq_number += 0x10;
  2378. }
  2379. /* Descriptor for chosen Tx queue */
  2380. txq = &priv->txq[txq_id];
  2381. q = &txq->q;
  2382. spin_lock_irqsave(&priv->lock, flags);
  2383. /* Set up first empty TFD within this queue's circular TFD buffer */
  2384. tfd = &txq->bd[q->write_ptr];
  2385. memset(tfd, 0, sizeof(*tfd));
  2386. control_flags = (u32 *) tfd;
  2387. idx = get_cmd_index(q, q->write_ptr, 0);
  2388. /* Set up driver data for this TFD */
  2389. memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info));
  2390. txq->txb[q->write_ptr].skb[0] = skb;
  2391. memcpy(&(txq->txb[q->write_ptr].status.control),
  2392. ctl, sizeof(struct ieee80211_tx_control));
  2393. /* Init first empty entry in queue's array of Tx/cmd buffers */
  2394. out_cmd = &txq->cmd[idx];
  2395. memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
  2396. memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
  2397. /*
  2398. * Set up the Tx-command (not MAC!) header.
  2399. * Store the chosen Tx queue and TFD index within the sequence field;
  2400. * after Tx, uCode's Tx response will return this value so driver can
  2401. * locate the frame within the tx queue and do post-tx processing.
  2402. */
  2403. out_cmd->hdr.cmd = REPLY_TX;
  2404. out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
  2405. INDEX_TO_SEQ(q->write_ptr)));
  2406. /* Copy MAC header from skb into command buffer */
  2407. memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len);
  2408. /*
  2409. * Use the first empty entry in this queue's command buffer array
  2410. * to contain the Tx command and MAC header concatenated together
  2411. * (payload data will be in another buffer).
  2412. * Size of this varies, due to varying MAC header length.
  2413. * If end is not dword aligned, we'll have 2 extra bytes at the end
  2414. * of the MAC header (device reads on dword boundaries).
  2415. * We'll tell device about this padding later.
  2416. */
  2417. len = priv->hw_setting.tx_cmd_len +
  2418. sizeof(struct iwl3945_cmd_header) + hdr_len;
  2419. len_org = len;
  2420. len = (len + 3) & ~3;
  2421. if (len_org != len)
  2422. len_org = 1;
  2423. else
  2424. len_org = 0;
  2425. /* Physical address of this Tx command's header (not MAC header!),
  2426. * within command buffer array. */
  2427. txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl3945_cmd) * idx +
  2428. offsetof(struct iwl3945_cmd, hdr);
  2429. /* Add buffer containing Tx command and MAC(!) header to TFD's
  2430. * first entry */
  2431. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
  2432. if (!(ctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT))
  2433. iwl3945_build_tx_cmd_hwcrypto(priv, ctl, out_cmd, skb, 0);
  2434. /* Set up TFD's 2nd entry to point directly to remainder of skb,
  2435. * if any (802.11 null frames have no payload). */
  2436. len = skb->len - hdr_len;
  2437. if (len) {
  2438. phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
  2439. len, PCI_DMA_TODEVICE);
  2440. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
  2441. }
  2442. if (!len)
  2443. /* If there is no payload, then we use only one Tx buffer */
  2444. *control_flags = TFD_CTL_COUNT_SET(1);
  2445. else
  2446. /* Else use 2 buffers.
  2447. * Tell 3945 about any padding after MAC header */
  2448. *control_flags = TFD_CTL_COUNT_SET(2) |
  2449. TFD_CTL_PAD_SET(U32_PAD(len));
  2450. /* Total # bytes to be transmitted */
  2451. len = (u16)skb->len;
  2452. out_cmd->cmd.tx.len = cpu_to_le16(len);
  2453. /* TODO need this for burst mode later on */
  2454. iwl3945_build_tx_cmd_basic(priv, out_cmd, ctl, hdr, unicast, sta_id);
  2455. /* set is_hcca to 0; it probably will never be implemented */
  2456. iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, ctl, hdr, sta_id, 0);
  2457. out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
  2458. out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
  2459. if (!ieee80211_get_morefrag(hdr)) {
  2460. txq->need_update = 1;
  2461. if (qc) {
  2462. u8 tid = (u8)(le16_to_cpu(*qc) & 0xf);
  2463. priv->stations[sta_id].tid[tid].seq_number = seq_number;
  2464. }
  2465. } else {
  2466. wait_write_ptr = 1;
  2467. txq->need_update = 0;
  2468. }
  2469. iwl3945_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload,
  2470. sizeof(out_cmd->cmd.tx));
  2471. iwl3945_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
  2472. ieee80211_get_hdrlen(fc));
  2473. /* Tell device the write index *just past* this latest filled TFD */
  2474. q->write_ptr = iwl3945_queue_inc_wrap(q->write_ptr, q->n_bd);
  2475. rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
  2476. spin_unlock_irqrestore(&priv->lock, flags);
  2477. if (rc)
  2478. return rc;
  2479. if ((iwl3945_queue_space(q) < q->high_mark)
  2480. && priv->mac80211_registered) {
  2481. if (wait_write_ptr) {
  2482. spin_lock_irqsave(&priv->lock, flags);
  2483. txq->need_update = 1;
  2484. iwl3945_tx_queue_update_write_ptr(priv, txq);
  2485. spin_unlock_irqrestore(&priv->lock, flags);
  2486. }
  2487. ieee80211_stop_queue(priv->hw, ctl->queue);
  2488. }
  2489. return 0;
  2490. drop_unlock:
  2491. spin_unlock_irqrestore(&priv->lock, flags);
  2492. drop:
  2493. return -1;
  2494. }
  2495. static void iwl3945_set_rate(struct iwl3945_priv *priv)
  2496. {
  2497. const struct ieee80211_hw_mode *hw = NULL;
  2498. struct ieee80211_rate *rate;
  2499. int i;
  2500. hw = iwl3945_get_hw_mode(priv, priv->phymode);
  2501. if (!hw) {
  2502. IWL_ERROR("Failed to set rate: unable to get hw mode\n");
  2503. return;
  2504. }
  2505. priv->active_rate = 0;
  2506. priv->active_rate_basic = 0;
  2507. IWL_DEBUG_RATE("Setting rates for 802.11%c\n",
  2508. hw->mode == MODE_IEEE80211A ?
  2509. 'a' : ((hw->mode == MODE_IEEE80211B) ? 'b' : 'g'));
  2510. for (i = 0; i < hw->num_rates; i++) {
  2511. rate = &(hw->rates[i]);
  2512. if ((rate->val < IWL_RATE_COUNT) &&
  2513. (rate->flags & IEEE80211_RATE_SUPPORTED)) {
  2514. IWL_DEBUG_RATE("Adding rate index %d (plcp %d)%s\n",
  2515. rate->val, iwl3945_rates[rate->val].plcp,
  2516. (rate->flags & IEEE80211_RATE_BASIC) ?
  2517. "*" : "");
  2518. priv->active_rate |= (1 << rate->val);
  2519. if (rate->flags & IEEE80211_RATE_BASIC)
  2520. priv->active_rate_basic |= (1 << rate->val);
  2521. } else
  2522. IWL_DEBUG_RATE("Not adding rate %d (plcp %d)\n",
  2523. rate->val, iwl3945_rates[rate->val].plcp);
  2524. }
  2525. IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
  2526. priv->active_rate, priv->active_rate_basic);
  2527. /*
  2528. * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
  2529. * otherwise set it to the default of all CCK rates and 6, 12, 24 for
  2530. * OFDM
  2531. */
  2532. if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
  2533. priv->staging_rxon.cck_basic_rates =
  2534. ((priv->active_rate_basic &
  2535. IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
  2536. else
  2537. priv->staging_rxon.cck_basic_rates =
  2538. (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  2539. if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
  2540. priv->staging_rxon.ofdm_basic_rates =
  2541. ((priv->active_rate_basic &
  2542. (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
  2543. IWL_FIRST_OFDM_RATE) & 0xFF;
  2544. else
  2545. priv->staging_rxon.ofdm_basic_rates =
  2546. (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  2547. }
  2548. static void iwl3945_radio_kill_sw(struct iwl3945_priv *priv, int disable_radio)
  2549. {
  2550. unsigned long flags;
  2551. if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
  2552. return;
  2553. IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
  2554. disable_radio ? "OFF" : "ON");
  2555. if (disable_radio) {
  2556. iwl3945_scan_cancel(priv);
  2557. /* FIXME: This is a workaround for AP */
  2558. if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
  2559. spin_lock_irqsave(&priv->lock, flags);
  2560. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2561. CSR_UCODE_SW_BIT_RFKILL);
  2562. spin_unlock_irqrestore(&priv->lock, flags);
  2563. iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
  2564. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2565. }
  2566. return;
  2567. }
  2568. spin_lock_irqsave(&priv->lock, flags);
  2569. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2570. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2571. spin_unlock_irqrestore(&priv->lock, flags);
  2572. /* wake up ucode */
  2573. msleep(10);
  2574. spin_lock_irqsave(&priv->lock, flags);
  2575. iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  2576. if (!iwl3945_grab_nic_access(priv))
  2577. iwl3945_release_nic_access(priv);
  2578. spin_unlock_irqrestore(&priv->lock, flags);
  2579. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  2580. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  2581. "disabled by HW switch\n");
  2582. return;
  2583. }
  2584. queue_work(priv->workqueue, &priv->restart);
  2585. return;
  2586. }
  2587. void iwl3945_set_decrypted_flag(struct iwl3945_priv *priv, struct sk_buff *skb,
  2588. u32 decrypt_res, struct ieee80211_rx_status *stats)
  2589. {
  2590. u16 fc =
  2591. le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
  2592. if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  2593. return;
  2594. if (!(fc & IEEE80211_FCTL_PROTECTED))
  2595. return;
  2596. IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
  2597. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  2598. case RX_RES_STATUS_SEC_TYPE_TKIP:
  2599. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2600. RX_RES_STATUS_BAD_ICV_MIC)
  2601. stats->flag |= RX_FLAG_MMIC_ERROR;
  2602. case RX_RES_STATUS_SEC_TYPE_WEP:
  2603. case RX_RES_STATUS_SEC_TYPE_CCMP:
  2604. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2605. RX_RES_STATUS_DECRYPT_OK) {
  2606. IWL_DEBUG_RX("hw decrypt successfully!!!\n");
  2607. stats->flag |= RX_FLAG_DECRYPTED;
  2608. }
  2609. break;
  2610. default:
  2611. break;
  2612. }
  2613. }
  2614. void iwl3945_handle_data_packet_monitor(struct iwl3945_priv *priv,
  2615. struct iwl3945_rx_mem_buffer *rxb,
  2616. void *data, short len,
  2617. struct ieee80211_rx_status *stats,
  2618. u16 phy_flags)
  2619. {
  2620. struct iwl3945_rt_rx_hdr *iwl3945_rt;
  2621. /* First cache any information we need before we overwrite
  2622. * the information provided in the skb from the hardware */
  2623. s8 signal = stats->ssi;
  2624. s8 noise = 0;
  2625. int rate = stats->rate;
  2626. u64 tsf = stats->mactime;
  2627. __le16 phy_flags_hw = cpu_to_le16(phy_flags);
  2628. /* We received data from the HW, so stop the watchdog */
  2629. if (len > IWL_RX_BUF_SIZE - sizeof(*iwl3945_rt)) {
  2630. IWL_DEBUG_DROP("Dropping too large packet in monitor\n");
  2631. return;
  2632. }
  2633. /* copy the frame data to write after where the radiotap header goes */
  2634. iwl3945_rt = (void *)rxb->skb->data;
  2635. memmove(iwl3945_rt->payload, data, len);
  2636. iwl3945_rt->rt_hdr.it_version = PKTHDR_RADIOTAP_VERSION;
  2637. iwl3945_rt->rt_hdr.it_pad = 0; /* always good to zero */
  2638. /* total header + data */
  2639. iwl3945_rt->rt_hdr.it_len = cpu_to_le16(sizeof(*iwl3945_rt));
  2640. /* Set the size of the skb to the size of the frame */
  2641. skb_put(rxb->skb, sizeof(*iwl3945_rt) + len);
  2642. /* Big bitfield of all the fields we provide in radiotap */
  2643. iwl3945_rt->rt_hdr.it_present =
  2644. cpu_to_le32((1 << IEEE80211_RADIOTAP_TSFT) |
  2645. (1 << IEEE80211_RADIOTAP_FLAGS) |
  2646. (1 << IEEE80211_RADIOTAP_RATE) |
  2647. (1 << IEEE80211_RADIOTAP_CHANNEL) |
  2648. (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
  2649. (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) |
  2650. (1 << IEEE80211_RADIOTAP_ANTENNA));
  2651. /* Zero the flags, we'll add to them as we go */
  2652. iwl3945_rt->rt_flags = 0;
  2653. iwl3945_rt->rt_tsf = cpu_to_le64(tsf);
  2654. /* Convert to dBm */
  2655. iwl3945_rt->rt_dbmsignal = signal;
  2656. iwl3945_rt->rt_dbmnoise = noise;
  2657. /* Convert the channel frequency and set the flags */
  2658. iwl3945_rt->rt_channelMHz = cpu_to_le16(stats->freq);
  2659. if (!(phy_flags_hw & RX_RES_PHY_FLAGS_BAND_24_MSK))
  2660. iwl3945_rt->rt_chbitmask =
  2661. cpu_to_le16((IEEE80211_CHAN_OFDM | IEEE80211_CHAN_5GHZ));
  2662. else if (phy_flags_hw & RX_RES_PHY_FLAGS_MOD_CCK_MSK)
  2663. iwl3945_rt->rt_chbitmask =
  2664. cpu_to_le16((IEEE80211_CHAN_CCK | IEEE80211_CHAN_2GHZ));
  2665. else /* 802.11g */
  2666. iwl3945_rt->rt_chbitmask =
  2667. cpu_to_le16((IEEE80211_CHAN_OFDM | IEEE80211_CHAN_2GHZ));
  2668. rate = iwl3945_rate_index_from_plcp(rate);
  2669. if (rate == -1)
  2670. iwl3945_rt->rt_rate = 0;
  2671. else
  2672. iwl3945_rt->rt_rate = iwl3945_rates[rate].ieee;
  2673. /* antenna number */
  2674. iwl3945_rt->rt_antenna =
  2675. le16_to_cpu(phy_flags_hw & RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
  2676. /* set the preamble flag if we have it */
  2677. if (phy_flags_hw & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
  2678. iwl3945_rt->rt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
  2679. IWL_DEBUG_RX("Rx packet of %d bytes.\n", rxb->skb->len);
  2680. stats->flag |= RX_FLAG_RADIOTAP;
  2681. ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
  2682. rxb->skb = NULL;
  2683. }
  2684. #define IWL_PACKET_RETRY_TIME HZ
  2685. int iwl3945_is_duplicate_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header)
  2686. {
  2687. u16 sc = le16_to_cpu(header->seq_ctrl);
  2688. u16 seq = (sc & IEEE80211_SCTL_SEQ) >> 4;
  2689. u16 frag = sc & IEEE80211_SCTL_FRAG;
  2690. u16 *last_seq, *last_frag;
  2691. unsigned long *last_time;
  2692. switch (priv->iw_mode) {
  2693. case IEEE80211_IF_TYPE_IBSS:{
  2694. struct list_head *p;
  2695. struct iwl3945_ibss_seq *entry = NULL;
  2696. u8 *mac = header->addr2;
  2697. int index = mac[5] & (IWL_IBSS_MAC_HASH_SIZE - 1);
  2698. __list_for_each(p, &priv->ibss_mac_hash[index]) {
  2699. entry = list_entry(p, struct iwl3945_ibss_seq, list);
  2700. if (!compare_ether_addr(entry->mac, mac))
  2701. break;
  2702. }
  2703. if (p == &priv->ibss_mac_hash[index]) {
  2704. entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
  2705. if (!entry) {
  2706. IWL_ERROR("Cannot malloc new mac entry\n");
  2707. return 0;
  2708. }
  2709. memcpy(entry->mac, mac, ETH_ALEN);
  2710. entry->seq_num = seq;
  2711. entry->frag_num = frag;
  2712. entry->packet_time = jiffies;
  2713. list_add(&entry->list, &priv->ibss_mac_hash[index]);
  2714. return 0;
  2715. }
  2716. last_seq = &entry->seq_num;
  2717. last_frag = &entry->frag_num;
  2718. last_time = &entry->packet_time;
  2719. break;
  2720. }
  2721. case IEEE80211_IF_TYPE_STA:
  2722. last_seq = &priv->last_seq_num;
  2723. last_frag = &priv->last_frag_num;
  2724. last_time = &priv->last_packet_time;
  2725. break;
  2726. default:
  2727. return 0;
  2728. }
  2729. if ((*last_seq == seq) &&
  2730. time_after(*last_time + IWL_PACKET_RETRY_TIME, jiffies)) {
  2731. if (*last_frag == frag)
  2732. goto drop;
  2733. if (*last_frag + 1 != frag)
  2734. /* out-of-order fragment */
  2735. goto drop;
  2736. } else
  2737. *last_seq = seq;
  2738. *last_frag = frag;
  2739. *last_time = jiffies;
  2740. return 0;
  2741. drop:
  2742. return 1;
  2743. }
  2744. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2745. #include "iwl-spectrum.h"
  2746. #define BEACON_TIME_MASK_LOW 0x00FFFFFF
  2747. #define BEACON_TIME_MASK_HIGH 0xFF000000
  2748. #define TIME_UNIT 1024
  2749. /*
  2750. * extended beacon time format
  2751. * time in usec will be changed into a 32-bit value in 8:24 format
  2752. * the high 1 byte is the beacon counts
  2753. * the lower 3 bytes is the time in usec within one beacon interval
  2754. */
  2755. static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
  2756. {
  2757. u32 quot;
  2758. u32 rem;
  2759. u32 interval = beacon_interval * 1024;
  2760. if (!interval || !usec)
  2761. return 0;
  2762. quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
  2763. rem = (usec % interval) & BEACON_TIME_MASK_LOW;
  2764. return (quot << 24) + rem;
  2765. }
  2766. /* base is usually what we get from ucode with each received frame,
  2767. * the same as HW timer counter counting down
  2768. */
  2769. static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
  2770. {
  2771. u32 base_low = base & BEACON_TIME_MASK_LOW;
  2772. u32 addon_low = addon & BEACON_TIME_MASK_LOW;
  2773. u32 interval = beacon_interval * TIME_UNIT;
  2774. u32 res = (base & BEACON_TIME_MASK_HIGH) +
  2775. (addon & BEACON_TIME_MASK_HIGH);
  2776. if (base_low > addon_low)
  2777. res += base_low - addon_low;
  2778. else if (base_low < addon_low) {
  2779. res += interval + base_low - addon_low;
  2780. res += (1 << 24);
  2781. } else
  2782. res += (1 << 24);
  2783. return cpu_to_le32(res);
  2784. }
  2785. static int iwl3945_get_measurement(struct iwl3945_priv *priv,
  2786. struct ieee80211_measurement_params *params,
  2787. u8 type)
  2788. {
  2789. struct iwl3945_spectrum_cmd spectrum;
  2790. struct iwl3945_rx_packet *res;
  2791. struct iwl3945_host_cmd cmd = {
  2792. .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
  2793. .data = (void *)&spectrum,
  2794. .meta.flags = CMD_WANT_SKB,
  2795. };
  2796. u32 add_time = le64_to_cpu(params->start_time);
  2797. int rc;
  2798. int spectrum_resp_status;
  2799. int duration = le16_to_cpu(params->duration);
  2800. if (iwl3945_is_associated(priv))
  2801. add_time =
  2802. iwl3945_usecs_to_beacons(
  2803. le64_to_cpu(params->start_time) - priv->last_tsf,
  2804. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2805. memset(&spectrum, 0, sizeof(spectrum));
  2806. spectrum.channel_count = cpu_to_le16(1);
  2807. spectrum.flags =
  2808. RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
  2809. spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
  2810. cmd.len = sizeof(spectrum);
  2811. spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
  2812. if (iwl3945_is_associated(priv))
  2813. spectrum.start_time =
  2814. iwl3945_add_beacon_time(priv->last_beacon_time,
  2815. add_time,
  2816. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2817. else
  2818. spectrum.start_time = 0;
  2819. spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
  2820. spectrum.channels[0].channel = params->channel;
  2821. spectrum.channels[0].type = type;
  2822. if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
  2823. spectrum.flags |= RXON_FLG_BAND_24G_MSK |
  2824. RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
  2825. rc = iwl3945_send_cmd_sync(priv, &cmd);
  2826. if (rc)
  2827. return rc;
  2828. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  2829. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  2830. IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n");
  2831. rc = -EIO;
  2832. }
  2833. spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
  2834. switch (spectrum_resp_status) {
  2835. case 0: /* Command will be handled */
  2836. if (res->u.spectrum.id != 0xff) {
  2837. IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
  2838. res->u.spectrum.id);
  2839. priv->measurement_status &= ~MEASUREMENT_READY;
  2840. }
  2841. priv->measurement_status |= MEASUREMENT_ACTIVE;
  2842. rc = 0;
  2843. break;
  2844. case 1: /* Command will not be handled */
  2845. rc = -EAGAIN;
  2846. break;
  2847. }
  2848. dev_kfree_skb_any(cmd.meta.u.skb);
  2849. return rc;
  2850. }
  2851. #endif
  2852. static void iwl3945_txstatus_to_ieee(struct iwl3945_priv *priv,
  2853. struct iwl3945_tx_info *tx_sta)
  2854. {
  2855. tx_sta->status.ack_signal = 0;
  2856. tx_sta->status.excessive_retries = 0;
  2857. tx_sta->status.queue_length = 0;
  2858. tx_sta->status.queue_number = 0;
  2859. if (in_interrupt())
  2860. ieee80211_tx_status_irqsafe(priv->hw,
  2861. tx_sta->skb[0], &(tx_sta->status));
  2862. else
  2863. ieee80211_tx_status(priv->hw,
  2864. tx_sta->skb[0], &(tx_sta->status));
  2865. tx_sta->skb[0] = NULL;
  2866. }
  2867. /**
  2868. * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
  2869. *
  2870. * When FW advances 'R' index, all entries between old and new 'R' index
  2871. * need to be reclaimed. As result, some free space forms. If there is
  2872. * enough free space (> low mark), wake the stack that feeds us.
  2873. */
  2874. static int iwl3945_tx_queue_reclaim(struct iwl3945_priv *priv, int txq_id, int index)
  2875. {
  2876. struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
  2877. struct iwl3945_queue *q = &txq->q;
  2878. int nfreed = 0;
  2879. if ((index >= q->n_bd) || (x2_queue_used(q, index) == 0)) {
  2880. IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
  2881. "is out of range [0-%d] %d %d.\n", txq_id,
  2882. index, q->n_bd, q->write_ptr, q->read_ptr);
  2883. return 0;
  2884. }
  2885. for (index = iwl3945_queue_inc_wrap(index, q->n_bd);
  2886. q->read_ptr != index;
  2887. q->read_ptr = iwl3945_queue_inc_wrap(q->read_ptr, q->n_bd)) {
  2888. if (txq_id != IWL_CMD_QUEUE_NUM) {
  2889. iwl3945_txstatus_to_ieee(priv,
  2890. &(txq->txb[txq->q.read_ptr]));
  2891. iwl3945_hw_txq_free_tfd(priv, txq);
  2892. } else if (nfreed > 1) {
  2893. IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
  2894. q->write_ptr, q->read_ptr);
  2895. queue_work(priv->workqueue, &priv->restart);
  2896. }
  2897. nfreed++;
  2898. }
  2899. if (iwl3945_queue_space(q) > q->low_mark && (txq_id >= 0) &&
  2900. (txq_id != IWL_CMD_QUEUE_NUM) &&
  2901. priv->mac80211_registered)
  2902. ieee80211_wake_queue(priv->hw, txq_id);
  2903. return nfreed;
  2904. }
  2905. static int iwl3945_is_tx_success(u32 status)
  2906. {
  2907. return (status & 0xFF) == 0x1;
  2908. }
  2909. /******************************************************************************
  2910. *
  2911. * Generic RX handler implementations
  2912. *
  2913. ******************************************************************************/
  2914. /**
  2915. * iwl3945_rx_reply_tx - Handle Tx response
  2916. */
  2917. static void iwl3945_rx_reply_tx(struct iwl3945_priv *priv,
  2918. struct iwl3945_rx_mem_buffer *rxb)
  2919. {
  2920. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2921. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  2922. int txq_id = SEQ_TO_QUEUE(sequence);
  2923. int index = SEQ_TO_INDEX(sequence);
  2924. struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
  2925. struct ieee80211_tx_status *tx_status;
  2926. struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
  2927. u32 status = le32_to_cpu(tx_resp->status);
  2928. if ((index >= txq->q.n_bd) || (x2_queue_used(&txq->q, index) == 0)) {
  2929. IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
  2930. "is out of range [0-%d] %d %d\n", txq_id,
  2931. index, txq->q.n_bd, txq->q.write_ptr,
  2932. txq->q.read_ptr);
  2933. return;
  2934. }
  2935. tx_status = &(txq->txb[txq->q.read_ptr].status);
  2936. tx_status->retry_count = tx_resp->failure_frame;
  2937. tx_status->queue_number = status;
  2938. tx_status->queue_length = tx_resp->bt_kill_count;
  2939. tx_status->queue_length |= tx_resp->failure_rts;
  2940. tx_status->flags =
  2941. iwl3945_is_tx_success(status) ? IEEE80211_TX_STATUS_ACK : 0;
  2942. tx_status->control.tx_rate = iwl3945_rate_index_from_plcp(tx_resp->rate);
  2943. IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
  2944. txq_id, iwl3945_get_tx_fail_reason(status), status,
  2945. tx_resp->rate, tx_resp->failure_frame);
  2946. IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
  2947. if (index != -1)
  2948. iwl3945_tx_queue_reclaim(priv, txq_id, index);
  2949. if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
  2950. IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
  2951. }
  2952. static void iwl3945_rx_reply_alive(struct iwl3945_priv *priv,
  2953. struct iwl3945_rx_mem_buffer *rxb)
  2954. {
  2955. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2956. struct iwl3945_alive_resp *palive;
  2957. struct delayed_work *pwork;
  2958. palive = &pkt->u.alive_frame;
  2959. IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
  2960. "0x%01X 0x%01X\n",
  2961. palive->is_valid, palive->ver_type,
  2962. palive->ver_subtype);
  2963. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  2964. IWL_DEBUG_INFO("Initialization Alive received.\n");
  2965. memcpy(&priv->card_alive_init,
  2966. &pkt->u.alive_frame,
  2967. sizeof(struct iwl3945_init_alive_resp));
  2968. pwork = &priv->init_alive_start;
  2969. } else {
  2970. IWL_DEBUG_INFO("Runtime Alive received.\n");
  2971. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  2972. sizeof(struct iwl3945_alive_resp));
  2973. pwork = &priv->alive_start;
  2974. iwl3945_disable_events(priv);
  2975. }
  2976. /* We delay the ALIVE response by 5ms to
  2977. * give the HW RF Kill time to activate... */
  2978. if (palive->is_valid == UCODE_VALID_OK)
  2979. queue_delayed_work(priv->workqueue, pwork,
  2980. msecs_to_jiffies(5));
  2981. else
  2982. IWL_WARNING("uCode did not respond OK.\n");
  2983. }
  2984. static void iwl3945_rx_reply_add_sta(struct iwl3945_priv *priv,
  2985. struct iwl3945_rx_mem_buffer *rxb)
  2986. {
  2987. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2988. IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
  2989. return;
  2990. }
  2991. static void iwl3945_rx_reply_error(struct iwl3945_priv *priv,
  2992. struct iwl3945_rx_mem_buffer *rxb)
  2993. {
  2994. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2995. IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) "
  2996. "seq 0x%04X ser 0x%08X\n",
  2997. le32_to_cpu(pkt->u.err_resp.error_type),
  2998. get_cmd_string(pkt->u.err_resp.cmd_id),
  2999. pkt->u.err_resp.cmd_id,
  3000. le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
  3001. le32_to_cpu(pkt->u.err_resp.error_info));
  3002. }
  3003. #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
  3004. static void iwl3945_rx_csa(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
  3005. {
  3006. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  3007. struct iwl3945_rxon_cmd *rxon = (void *)&priv->active_rxon;
  3008. struct iwl3945_csa_notification *csa = &(pkt->u.csa_notif);
  3009. IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
  3010. le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
  3011. rxon->channel = csa->channel;
  3012. priv->staging_rxon.channel = csa->channel;
  3013. }
  3014. static void iwl3945_rx_spectrum_measure_notif(struct iwl3945_priv *priv,
  3015. struct iwl3945_rx_mem_buffer *rxb)
  3016. {
  3017. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  3018. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  3019. struct iwl3945_spectrum_notification *report = &(pkt->u.spectrum_notif);
  3020. if (!report->state) {
  3021. IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
  3022. "Spectrum Measure Notification: Start\n");
  3023. return;
  3024. }
  3025. memcpy(&priv->measure_report, report, sizeof(*report));
  3026. priv->measurement_status |= MEASUREMENT_READY;
  3027. #endif
  3028. }
  3029. static void iwl3945_rx_pm_sleep_notif(struct iwl3945_priv *priv,
  3030. struct iwl3945_rx_mem_buffer *rxb)
  3031. {
  3032. #ifdef CONFIG_IWL3945_DEBUG
  3033. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  3034. struct iwl3945_sleep_notification *sleep = &(pkt->u.sleep_notif);
  3035. IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
  3036. sleep->pm_sleep_mode, sleep->pm_wakeup_src);
  3037. #endif
  3038. }
  3039. static void iwl3945_rx_pm_debug_statistics_notif(struct iwl3945_priv *priv,
  3040. struct iwl3945_rx_mem_buffer *rxb)
  3041. {
  3042. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  3043. IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
  3044. "notification for %s:\n",
  3045. le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
  3046. iwl3945_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
  3047. }
  3048. static void iwl3945_bg_beacon_update(struct work_struct *work)
  3049. {
  3050. struct iwl3945_priv *priv =
  3051. container_of(work, struct iwl3945_priv, beacon_update);
  3052. struct sk_buff *beacon;
  3053. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  3054. beacon = ieee80211_beacon_get(priv->hw, priv->interface_id, NULL);
  3055. if (!beacon) {
  3056. IWL_ERROR("update beacon failed\n");
  3057. return;
  3058. }
  3059. mutex_lock(&priv->mutex);
  3060. /* new beacon skb is allocated every time; dispose previous.*/
  3061. if (priv->ibss_beacon)
  3062. dev_kfree_skb(priv->ibss_beacon);
  3063. priv->ibss_beacon = beacon;
  3064. mutex_unlock(&priv->mutex);
  3065. iwl3945_send_beacon_cmd(priv);
  3066. }
  3067. static void iwl3945_rx_beacon_notif(struct iwl3945_priv *priv,
  3068. struct iwl3945_rx_mem_buffer *rxb)
  3069. {
  3070. #ifdef CONFIG_IWL3945_DEBUG
  3071. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  3072. struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
  3073. u8 rate = beacon->beacon_notify_hdr.rate;
  3074. IWL_DEBUG_RX("beacon status %x retries %d iss %d "
  3075. "tsf %d %d rate %d\n",
  3076. le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
  3077. beacon->beacon_notify_hdr.failure_frame,
  3078. le32_to_cpu(beacon->ibss_mgr_status),
  3079. le32_to_cpu(beacon->high_tsf),
  3080. le32_to_cpu(beacon->low_tsf), rate);
  3081. #endif
  3082. if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
  3083. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  3084. queue_work(priv->workqueue, &priv->beacon_update);
  3085. }
  3086. /* Service response to REPLY_SCAN_CMD (0x80) */
  3087. static void iwl3945_rx_reply_scan(struct iwl3945_priv *priv,
  3088. struct iwl3945_rx_mem_buffer *rxb)
  3089. {
  3090. #ifdef CONFIG_IWL3945_DEBUG
  3091. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  3092. struct iwl3945_scanreq_notification *notif =
  3093. (struct iwl3945_scanreq_notification *)pkt->u.raw;
  3094. IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
  3095. #endif
  3096. }
  3097. /* Service SCAN_START_NOTIFICATION (0x82) */
  3098. static void iwl3945_rx_scan_start_notif(struct iwl3945_priv *priv,
  3099. struct iwl3945_rx_mem_buffer *rxb)
  3100. {
  3101. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  3102. struct iwl3945_scanstart_notification *notif =
  3103. (struct iwl3945_scanstart_notification *)pkt->u.raw;
  3104. priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
  3105. IWL_DEBUG_SCAN("Scan start: "
  3106. "%d [802.11%s] "
  3107. "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
  3108. notif->channel,
  3109. notif->band ? "bg" : "a",
  3110. notif->tsf_high,
  3111. notif->tsf_low, notif->status, notif->beacon_timer);
  3112. }
  3113. /* Service SCAN_RESULTS_NOTIFICATION (0x83) */
  3114. static void iwl3945_rx_scan_results_notif(struct iwl3945_priv *priv,
  3115. struct iwl3945_rx_mem_buffer *rxb)
  3116. {
  3117. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  3118. struct iwl3945_scanresults_notification *notif =
  3119. (struct iwl3945_scanresults_notification *)pkt->u.raw;
  3120. IWL_DEBUG_SCAN("Scan ch.res: "
  3121. "%d [802.11%s] "
  3122. "(TSF: 0x%08X:%08X) - %d "
  3123. "elapsed=%lu usec (%dms since last)\n",
  3124. notif->channel,
  3125. notif->band ? "bg" : "a",
  3126. le32_to_cpu(notif->tsf_high),
  3127. le32_to_cpu(notif->tsf_low),
  3128. le32_to_cpu(notif->statistics[0]),
  3129. le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
  3130. jiffies_to_msecs(elapsed_jiffies
  3131. (priv->last_scan_jiffies, jiffies)));
  3132. priv->last_scan_jiffies = jiffies;
  3133. priv->next_scan_jiffies = 0;
  3134. }
  3135. /* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
  3136. static void iwl3945_rx_scan_complete_notif(struct iwl3945_priv *priv,
  3137. struct iwl3945_rx_mem_buffer *rxb)
  3138. {
  3139. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  3140. struct iwl3945_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
  3141. IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
  3142. scan_notif->scanned_channels,
  3143. scan_notif->tsf_low,
  3144. scan_notif->tsf_high, scan_notif->status);
  3145. /* The HW is no longer scanning */
  3146. clear_bit(STATUS_SCAN_HW, &priv->status);
  3147. /* The scan completion notification came in, so kill that timer... */
  3148. cancel_delayed_work(&priv->scan_check);
  3149. IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
  3150. (priv->scan_bands == 2) ? "2.4" : "5.2",
  3151. jiffies_to_msecs(elapsed_jiffies
  3152. (priv->scan_pass_start, jiffies)));
  3153. /* Remove this scanned band from the list
  3154. * of pending bands to scan */
  3155. priv->scan_bands--;
  3156. /* If a request to abort was given, or the scan did not succeed
  3157. * then we reset the scan state machine and terminate,
  3158. * re-queuing another scan if one has been requested */
  3159. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  3160. IWL_DEBUG_INFO("Aborted scan completed.\n");
  3161. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  3162. } else {
  3163. /* If there are more bands on this scan pass reschedule */
  3164. if (priv->scan_bands > 0)
  3165. goto reschedule;
  3166. }
  3167. priv->last_scan_jiffies = jiffies;
  3168. priv->next_scan_jiffies = 0;
  3169. IWL_DEBUG_INFO("Setting scan to off\n");
  3170. clear_bit(STATUS_SCANNING, &priv->status);
  3171. IWL_DEBUG_INFO("Scan took %dms\n",
  3172. jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
  3173. queue_work(priv->workqueue, &priv->scan_completed);
  3174. return;
  3175. reschedule:
  3176. priv->scan_pass_start = jiffies;
  3177. queue_work(priv->workqueue, &priv->request_scan);
  3178. }
  3179. /* Handle notification from uCode that card's power state is changing
  3180. * due to software, hardware, or critical temperature RFKILL */
  3181. static void iwl3945_rx_card_state_notif(struct iwl3945_priv *priv,
  3182. struct iwl3945_rx_mem_buffer *rxb)
  3183. {
  3184. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  3185. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  3186. unsigned long status = priv->status;
  3187. IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
  3188. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  3189. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  3190. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
  3191. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  3192. if (flags & HW_CARD_DISABLED)
  3193. set_bit(STATUS_RF_KILL_HW, &priv->status);
  3194. else
  3195. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  3196. if (flags & SW_CARD_DISABLED)
  3197. set_bit(STATUS_RF_KILL_SW, &priv->status);
  3198. else
  3199. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  3200. iwl3945_scan_cancel(priv);
  3201. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  3202. test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
  3203. (test_bit(STATUS_RF_KILL_SW, &status) !=
  3204. test_bit(STATUS_RF_KILL_SW, &priv->status)))
  3205. queue_work(priv->workqueue, &priv->rf_kill);
  3206. else
  3207. wake_up_interruptible(&priv->wait_command_queue);
  3208. }
  3209. /**
  3210. * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
  3211. *
  3212. * Setup the RX handlers for each of the reply types sent from the uCode
  3213. * to the host.
  3214. *
  3215. * This function chains into the hardware specific files for them to setup
  3216. * any hardware specific handlers as well.
  3217. */
  3218. static void iwl3945_setup_rx_handlers(struct iwl3945_priv *priv)
  3219. {
  3220. priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
  3221. priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
  3222. priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
  3223. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
  3224. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  3225. iwl3945_rx_spectrum_measure_notif;
  3226. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
  3227. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  3228. iwl3945_rx_pm_debug_statistics_notif;
  3229. priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
  3230. /*
  3231. * The same handler is used for both the REPLY to a discrete
  3232. * statistics request from the host as well as for the periodic
  3233. * statistics notifications (after received beacons) from the uCode.
  3234. */
  3235. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
  3236. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
  3237. priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
  3238. priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
  3239. priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
  3240. iwl3945_rx_scan_results_notif;
  3241. priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
  3242. iwl3945_rx_scan_complete_notif;
  3243. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
  3244. priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
  3245. /* Set up hardware specific Rx handlers */
  3246. iwl3945_hw_rx_handler_setup(priv);
  3247. }
  3248. /**
  3249. * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
  3250. * @rxb: Rx buffer to reclaim
  3251. *
  3252. * If an Rx buffer has an async callback associated with it the callback
  3253. * will be executed. The attached skb (if present) will only be freed
  3254. * if the callback returns 1
  3255. */
  3256. static void iwl3945_tx_cmd_complete(struct iwl3945_priv *priv,
  3257. struct iwl3945_rx_mem_buffer *rxb)
  3258. {
  3259. struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
  3260. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  3261. int txq_id = SEQ_TO_QUEUE(sequence);
  3262. int index = SEQ_TO_INDEX(sequence);
  3263. int huge = sequence & SEQ_HUGE_FRAME;
  3264. int cmd_index;
  3265. struct iwl3945_cmd *cmd;
  3266. /* If a Tx command is being handled and it isn't in the actual
  3267. * command queue then there a command routing bug has been introduced
  3268. * in the queue management code. */
  3269. if (txq_id != IWL_CMD_QUEUE_NUM)
  3270. IWL_ERROR("Error wrong command queue %d command id 0x%X\n",
  3271. txq_id, pkt->hdr.cmd);
  3272. BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
  3273. cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
  3274. cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
  3275. /* Input error checking is done when commands are added to queue. */
  3276. if (cmd->meta.flags & CMD_WANT_SKB) {
  3277. cmd->meta.source->u.skb = rxb->skb;
  3278. rxb->skb = NULL;
  3279. } else if (cmd->meta.u.callback &&
  3280. !cmd->meta.u.callback(priv, cmd, rxb->skb))
  3281. rxb->skb = NULL;
  3282. iwl3945_tx_queue_reclaim(priv, txq_id, index);
  3283. if (!(cmd->meta.flags & CMD_ASYNC)) {
  3284. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  3285. wake_up_interruptible(&priv->wait_command_queue);
  3286. }
  3287. }
  3288. /************************** RX-FUNCTIONS ****************************/
  3289. /*
  3290. * Rx theory of operation
  3291. *
  3292. * The host allocates 32 DMA target addresses and passes the host address
  3293. * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
  3294. * 0 to 31
  3295. *
  3296. * Rx Queue Indexes
  3297. * The host/firmware share two index registers for managing the Rx buffers.
  3298. *
  3299. * The READ index maps to the first position that the firmware may be writing
  3300. * to -- the driver can read up to (but not including) this position and get
  3301. * good data.
  3302. * The READ index is managed by the firmware once the card is enabled.
  3303. *
  3304. * The WRITE index maps to the last position the driver has read from -- the
  3305. * position preceding WRITE is the last slot the firmware can place a packet.
  3306. *
  3307. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  3308. * WRITE = READ.
  3309. *
  3310. * During initialization, the host sets up the READ queue position to the first
  3311. * INDEX position, and WRITE to the last (READ - 1 wrapped)
  3312. *
  3313. * When the firmware places a packet in a buffer, it will advance the READ index
  3314. * and fire the RX interrupt. The driver can then query the READ index and
  3315. * process as many packets as possible, moving the WRITE index forward as it
  3316. * resets the Rx queue buffers with new memory.
  3317. *
  3318. * The management in the driver is as follows:
  3319. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  3320. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  3321. * to replenish the iwl->rxq->rx_free.
  3322. * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
  3323. * iwl->rxq is replenished and the READ INDEX is updated (updating the
  3324. * 'processed' and 'read' driver indexes as well)
  3325. * + A received packet is processed and handed to the kernel network stack,
  3326. * detached from the iwl->rxq. The driver 'processed' index is updated.
  3327. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  3328. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  3329. * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
  3330. * were enough free buffers and RX_STALLED is set it is cleared.
  3331. *
  3332. *
  3333. * Driver sequence:
  3334. *
  3335. * iwl3945_rx_queue_alloc() Allocates rx_free
  3336. * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
  3337. * iwl3945_rx_queue_restock
  3338. * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
  3339. * queue, updates firmware pointers, and updates
  3340. * the WRITE index. If insufficient rx_free buffers
  3341. * are available, schedules iwl3945_rx_replenish
  3342. *
  3343. * -- enable interrupts --
  3344. * ISR - iwl3945_rx() Detach iwl3945_rx_mem_buffers from pool up to the
  3345. * READ INDEX, detaching the SKB from the pool.
  3346. * Moves the packet buffer from queue to rx_used.
  3347. * Calls iwl3945_rx_queue_restock to refill any empty
  3348. * slots.
  3349. * ...
  3350. *
  3351. */
  3352. /**
  3353. * iwl3945_rx_queue_space - Return number of free slots available in queue.
  3354. */
  3355. static int iwl3945_rx_queue_space(const struct iwl3945_rx_queue *q)
  3356. {
  3357. int s = q->read - q->write;
  3358. if (s <= 0)
  3359. s += RX_QUEUE_SIZE;
  3360. /* keep some buffer to not confuse full and empty queue */
  3361. s -= 2;
  3362. if (s < 0)
  3363. s = 0;
  3364. return s;
  3365. }
  3366. /**
  3367. * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue
  3368. */
  3369. int iwl3945_rx_queue_update_write_ptr(struct iwl3945_priv *priv, struct iwl3945_rx_queue *q)
  3370. {
  3371. u32 reg = 0;
  3372. int rc = 0;
  3373. unsigned long flags;
  3374. spin_lock_irqsave(&q->lock, flags);
  3375. if (q->need_update == 0)
  3376. goto exit_unlock;
  3377. /* If power-saving is in use, make sure device is awake */
  3378. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  3379. reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  3380. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  3381. iwl3945_set_bit(priv, CSR_GP_CNTRL,
  3382. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  3383. goto exit_unlock;
  3384. }
  3385. rc = iwl3945_grab_nic_access(priv);
  3386. if (rc)
  3387. goto exit_unlock;
  3388. /* Device expects a multiple of 8 */
  3389. iwl3945_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
  3390. q->write & ~0x7);
  3391. iwl3945_release_nic_access(priv);
  3392. /* Else device is assumed to be awake */
  3393. } else
  3394. /* Device expects a multiple of 8 */
  3395. iwl3945_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
  3396. q->need_update = 0;
  3397. exit_unlock:
  3398. spin_unlock_irqrestore(&q->lock, flags);
  3399. return rc;
  3400. }
  3401. /**
  3402. * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  3403. */
  3404. static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl3945_priv *priv,
  3405. dma_addr_t dma_addr)
  3406. {
  3407. return cpu_to_le32((u32)dma_addr);
  3408. }
  3409. /**
  3410. * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
  3411. *
  3412. * If there are slots in the RX queue that need to be restocked,
  3413. * and we have free pre-allocated buffers, fill the ranks as much
  3414. * as we can, pulling from rx_free.
  3415. *
  3416. * This moves the 'write' index forward to catch up with 'processed', and
  3417. * also updates the memory address in the firmware to reference the new
  3418. * target buffer.
  3419. */
  3420. static int iwl3945_rx_queue_restock(struct iwl3945_priv *priv)
  3421. {
  3422. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3423. struct list_head *element;
  3424. struct iwl3945_rx_mem_buffer *rxb;
  3425. unsigned long flags;
  3426. int write, rc;
  3427. spin_lock_irqsave(&rxq->lock, flags);
  3428. write = rxq->write & ~0x7;
  3429. while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
  3430. /* Get next free Rx buffer, remove from free list */
  3431. element = rxq->rx_free.next;
  3432. rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
  3433. list_del(element);
  3434. /* Point to Rx buffer via next RBD in circular buffer */
  3435. rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->dma_addr);
  3436. rxq->queue[rxq->write] = rxb;
  3437. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  3438. rxq->free_count--;
  3439. }
  3440. spin_unlock_irqrestore(&rxq->lock, flags);
  3441. /* If the pre-allocated buffer pool is dropping low, schedule to
  3442. * refill it */
  3443. if (rxq->free_count <= RX_LOW_WATERMARK)
  3444. queue_work(priv->workqueue, &priv->rx_replenish);
  3445. /* If we've added more space for the firmware to place data, tell it.
  3446. * Increment device's write pointer in multiples of 8. */
  3447. if ((write != (rxq->write & ~0x7))
  3448. || (abs(rxq->write - rxq->read) > 7)) {
  3449. spin_lock_irqsave(&rxq->lock, flags);
  3450. rxq->need_update = 1;
  3451. spin_unlock_irqrestore(&rxq->lock, flags);
  3452. rc = iwl3945_rx_queue_update_write_ptr(priv, rxq);
  3453. if (rc)
  3454. return rc;
  3455. }
  3456. return 0;
  3457. }
  3458. /**
  3459. * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
  3460. *
  3461. * When moving to rx_free an SKB is allocated for the slot.
  3462. *
  3463. * Also restock the Rx queue via iwl3945_rx_queue_restock.
  3464. * This is called as a scheduled work item (except for during initialization)
  3465. */
  3466. static void iwl3945_rx_allocate(struct iwl3945_priv *priv)
  3467. {
  3468. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3469. struct list_head *element;
  3470. struct iwl3945_rx_mem_buffer *rxb;
  3471. unsigned long flags;
  3472. spin_lock_irqsave(&rxq->lock, flags);
  3473. while (!list_empty(&rxq->rx_used)) {
  3474. element = rxq->rx_used.next;
  3475. rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
  3476. /* Alloc a new receive buffer */
  3477. rxb->skb =
  3478. alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
  3479. if (!rxb->skb) {
  3480. if (net_ratelimit())
  3481. printk(KERN_CRIT DRV_NAME
  3482. ": Can not allocate SKB buffers\n");
  3483. /* We don't reschedule replenish work here -- we will
  3484. * call the restock method and if it still needs
  3485. * more buffers it will schedule replenish */
  3486. break;
  3487. }
  3488. priv->alloc_rxb_skb++;
  3489. list_del(element);
  3490. /* Get physical address of RB/SKB */
  3491. rxb->dma_addr =
  3492. pci_map_single(priv->pci_dev, rxb->skb->data,
  3493. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3494. list_add_tail(&rxb->list, &rxq->rx_free);
  3495. rxq->free_count++;
  3496. }
  3497. spin_unlock_irqrestore(&rxq->lock, flags);
  3498. }
  3499. /*
  3500. * this should be called while priv->lock is locked
  3501. */
  3502. void __iwl3945_rx_replenish(void *data)
  3503. {
  3504. struct iwl3945_priv *priv = data;
  3505. iwl3945_rx_allocate(priv);
  3506. iwl3945_rx_queue_restock(priv);
  3507. }
  3508. void iwl3945_rx_replenish(void *data)
  3509. {
  3510. struct iwl3945_priv *priv = data;
  3511. unsigned long flags;
  3512. iwl3945_rx_allocate(priv);
  3513. spin_lock_irqsave(&priv->lock, flags);
  3514. iwl3945_rx_queue_restock(priv);
  3515. spin_unlock_irqrestore(&priv->lock, flags);
  3516. }
  3517. /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
  3518. * If an SKB has been detached, the POOL needs to have its SKB set to NULL
  3519. * This free routine walks the list of POOL entries and if SKB is set to
  3520. * non NULL it is unmapped and freed
  3521. */
  3522. static void iwl3945_rx_queue_free(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
  3523. {
  3524. int i;
  3525. for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
  3526. if (rxq->pool[i].skb != NULL) {
  3527. pci_unmap_single(priv->pci_dev,
  3528. rxq->pool[i].dma_addr,
  3529. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3530. dev_kfree_skb(rxq->pool[i].skb);
  3531. }
  3532. }
  3533. pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  3534. rxq->dma_addr);
  3535. rxq->bd = NULL;
  3536. }
  3537. int iwl3945_rx_queue_alloc(struct iwl3945_priv *priv)
  3538. {
  3539. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3540. struct pci_dev *dev = priv->pci_dev;
  3541. int i;
  3542. spin_lock_init(&rxq->lock);
  3543. INIT_LIST_HEAD(&rxq->rx_free);
  3544. INIT_LIST_HEAD(&rxq->rx_used);
  3545. /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
  3546. rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
  3547. if (!rxq->bd)
  3548. return -ENOMEM;
  3549. /* Fill the rx_used queue with _all_ of the Rx buffers */
  3550. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
  3551. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  3552. /* Set us so that we have processed and used all buffers, but have
  3553. * not restocked the Rx queue with fresh buffers */
  3554. rxq->read = rxq->write = 0;
  3555. rxq->free_count = 0;
  3556. rxq->need_update = 0;
  3557. return 0;
  3558. }
  3559. void iwl3945_rx_queue_reset(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
  3560. {
  3561. unsigned long flags;
  3562. int i;
  3563. spin_lock_irqsave(&rxq->lock, flags);
  3564. INIT_LIST_HEAD(&rxq->rx_free);
  3565. INIT_LIST_HEAD(&rxq->rx_used);
  3566. /* Fill the rx_used queue with _all_ of the Rx buffers */
  3567. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
  3568. /* In the reset function, these buffers may have been allocated
  3569. * to an SKB, so we need to unmap and free potential storage */
  3570. if (rxq->pool[i].skb != NULL) {
  3571. pci_unmap_single(priv->pci_dev,
  3572. rxq->pool[i].dma_addr,
  3573. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3574. priv->alloc_rxb_skb--;
  3575. dev_kfree_skb(rxq->pool[i].skb);
  3576. rxq->pool[i].skb = NULL;
  3577. }
  3578. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  3579. }
  3580. /* Set us so that we have processed and used all buffers, but have
  3581. * not restocked the Rx queue with fresh buffers */
  3582. rxq->read = rxq->write = 0;
  3583. rxq->free_count = 0;
  3584. spin_unlock_irqrestore(&rxq->lock, flags);
  3585. }
  3586. /* Convert linear signal-to-noise ratio into dB */
  3587. static u8 ratio2dB[100] = {
  3588. /* 0 1 2 3 4 5 6 7 8 9 */
  3589. 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
  3590. 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
  3591. 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
  3592. 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
  3593. 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
  3594. 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
  3595. 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
  3596. 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
  3597. 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
  3598. 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
  3599. };
  3600. /* Calculates a relative dB value from a ratio of linear
  3601. * (i.e. not dB) signal levels.
  3602. * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
  3603. int iwl3945_calc_db_from_ratio(int sig_ratio)
  3604. {
  3605. /* Anything above 1000:1 just report as 60 dB */
  3606. if (sig_ratio > 1000)
  3607. return 60;
  3608. /* Above 100:1, divide by 10 and use table,
  3609. * add 20 dB to make up for divide by 10 */
  3610. if (sig_ratio > 100)
  3611. return (20 + (int)ratio2dB[sig_ratio/10]);
  3612. /* We shouldn't see this */
  3613. if (sig_ratio < 1)
  3614. return 0;
  3615. /* Use table for ratios 1:1 - 99:1 */
  3616. return (int)ratio2dB[sig_ratio];
  3617. }
  3618. #define PERFECT_RSSI (-20) /* dBm */
  3619. #define WORST_RSSI (-95) /* dBm */
  3620. #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
  3621. /* Calculate an indication of rx signal quality (a percentage, not dBm!).
  3622. * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
  3623. * about formulas used below. */
  3624. int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
  3625. {
  3626. int sig_qual;
  3627. int degradation = PERFECT_RSSI - rssi_dbm;
  3628. /* If we get a noise measurement, use signal-to-noise ratio (SNR)
  3629. * as indicator; formula is (signal dbm - noise dbm).
  3630. * SNR at or above 40 is a great signal (100%).
  3631. * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
  3632. * Weakest usable signal is usually 10 - 15 dB SNR. */
  3633. if (noise_dbm) {
  3634. if (rssi_dbm - noise_dbm >= 40)
  3635. return 100;
  3636. else if (rssi_dbm < noise_dbm)
  3637. return 0;
  3638. sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
  3639. /* Else use just the signal level.
  3640. * This formula is a least squares fit of data points collected and
  3641. * compared with a reference system that had a percentage (%) display
  3642. * for signal quality. */
  3643. } else
  3644. sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
  3645. (15 * RSSI_RANGE + 62 * degradation)) /
  3646. (RSSI_RANGE * RSSI_RANGE);
  3647. if (sig_qual > 100)
  3648. sig_qual = 100;
  3649. else if (sig_qual < 1)
  3650. sig_qual = 0;
  3651. return sig_qual;
  3652. }
  3653. /**
  3654. * iwl3945_rx_handle - Main entry function for receiving responses from uCode
  3655. *
  3656. * Uses the priv->rx_handlers callback function array to invoke
  3657. * the appropriate handlers, including command responses,
  3658. * frame-received notifications, and other notifications.
  3659. */
  3660. static void iwl3945_rx_handle(struct iwl3945_priv *priv)
  3661. {
  3662. struct iwl3945_rx_mem_buffer *rxb;
  3663. struct iwl3945_rx_packet *pkt;
  3664. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3665. u32 r, i;
  3666. int reclaim;
  3667. unsigned long flags;
  3668. u8 fill_rx = 0;
  3669. u32 count = 0;
  3670. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  3671. * buffer that the driver may process (last buffer filled by ucode). */
  3672. r = iwl3945_hw_get_rx_read(priv);
  3673. i = rxq->read;
  3674. if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
  3675. fill_rx = 1;
  3676. /* Rx interrupt, but nothing sent from uCode */
  3677. if (i == r)
  3678. IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
  3679. while (i != r) {
  3680. rxb = rxq->queue[i];
  3681. /* If an RXB doesn't have a Rx queue slot associated with it,
  3682. * then a bug has been introduced in the queue refilling
  3683. * routines -- catch it here */
  3684. BUG_ON(rxb == NULL);
  3685. rxq->queue[i] = NULL;
  3686. pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr,
  3687. IWL_RX_BUF_SIZE,
  3688. PCI_DMA_FROMDEVICE);
  3689. pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
  3690. /* Reclaim a command buffer only if this packet is a response
  3691. * to a (driver-originated) command.
  3692. * If the packet (e.g. Rx frame) originated from uCode,
  3693. * there is no command buffer to reclaim.
  3694. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  3695. * but apparently a few don't get set; catch them here. */
  3696. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  3697. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  3698. (pkt->hdr.cmd != REPLY_TX);
  3699. /* Based on type of command response or notification,
  3700. * handle those that need handling via function in
  3701. * rx_handlers table. See iwl3945_setup_rx_handlers() */
  3702. if (priv->rx_handlers[pkt->hdr.cmd]) {
  3703. IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
  3704. "r = %d, i = %d, %s, 0x%02x\n", r, i,
  3705. get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  3706. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  3707. } else {
  3708. /* No handling needed */
  3709. IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
  3710. "r %d i %d No handler needed for %s, 0x%02x\n",
  3711. r, i, get_cmd_string(pkt->hdr.cmd),
  3712. pkt->hdr.cmd);
  3713. }
  3714. if (reclaim) {
  3715. /* Invoke any callbacks, transfer the skb to caller, and
  3716. * fire off the (possibly) blocking iwl3945_send_cmd()
  3717. * as we reclaim the driver command queue */
  3718. if (rxb && rxb->skb)
  3719. iwl3945_tx_cmd_complete(priv, rxb);
  3720. else
  3721. IWL_WARNING("Claim null rxb?\n");
  3722. }
  3723. /* For now we just don't re-use anything. We can tweak this
  3724. * later to try and re-use notification packets and SKBs that
  3725. * fail to Rx correctly */
  3726. if (rxb->skb != NULL) {
  3727. priv->alloc_rxb_skb--;
  3728. dev_kfree_skb_any(rxb->skb);
  3729. rxb->skb = NULL;
  3730. }
  3731. pci_unmap_single(priv->pci_dev, rxb->dma_addr,
  3732. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3733. spin_lock_irqsave(&rxq->lock, flags);
  3734. list_add_tail(&rxb->list, &priv->rxq.rx_used);
  3735. spin_unlock_irqrestore(&rxq->lock, flags);
  3736. i = (i + 1) & RX_QUEUE_MASK;
  3737. /* If there are a lot of unused frames,
  3738. * restock the Rx queue so ucode won't assert. */
  3739. if (fill_rx) {
  3740. count++;
  3741. if (count >= 8) {
  3742. priv->rxq.read = i;
  3743. __iwl3945_rx_replenish(priv);
  3744. count = 0;
  3745. }
  3746. }
  3747. }
  3748. /* Backtrack one entry */
  3749. priv->rxq.read = i;
  3750. iwl3945_rx_queue_restock(priv);
  3751. }
  3752. /**
  3753. * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware
  3754. */
  3755. static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
  3756. struct iwl3945_tx_queue *txq)
  3757. {
  3758. u32 reg = 0;
  3759. int rc = 0;
  3760. int txq_id = txq->q.id;
  3761. if (txq->need_update == 0)
  3762. return rc;
  3763. /* if we're trying to save power */
  3764. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  3765. /* wake up nic if it's powered down ...
  3766. * uCode will wake up, and interrupt us again, so next
  3767. * time we'll skip this part. */
  3768. reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  3769. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  3770. IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
  3771. iwl3945_set_bit(priv, CSR_GP_CNTRL,
  3772. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  3773. return rc;
  3774. }
  3775. /* restore this queue's parameters in nic hardware. */
  3776. rc = iwl3945_grab_nic_access(priv);
  3777. if (rc)
  3778. return rc;
  3779. iwl3945_write_direct32(priv, HBUS_TARG_WRPTR,
  3780. txq->q.write_ptr | (txq_id << 8));
  3781. iwl3945_release_nic_access(priv);
  3782. /* else not in power-save mode, uCode will never sleep when we're
  3783. * trying to tx (during RFKILL, we're not trying to tx). */
  3784. } else
  3785. iwl3945_write32(priv, HBUS_TARG_WRPTR,
  3786. txq->q.write_ptr | (txq_id << 8));
  3787. txq->need_update = 0;
  3788. return rc;
  3789. }
  3790. #ifdef CONFIG_IWL3945_DEBUG
  3791. static void iwl3945_print_rx_config_cmd(struct iwl3945_rxon_cmd *rxon)
  3792. {
  3793. DECLARE_MAC_BUF(mac);
  3794. IWL_DEBUG_RADIO("RX CONFIG:\n");
  3795. iwl3945_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
  3796. IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
  3797. IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
  3798. IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
  3799. le32_to_cpu(rxon->filter_flags));
  3800. IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
  3801. IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
  3802. rxon->ofdm_basic_rates);
  3803. IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
  3804. IWL_DEBUG_RADIO("u8[6] node_addr: %s\n",
  3805. print_mac(mac, rxon->node_addr));
  3806. IWL_DEBUG_RADIO("u8[6] bssid_addr: %s\n",
  3807. print_mac(mac, rxon->bssid_addr));
  3808. IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
  3809. }
  3810. #endif
  3811. static void iwl3945_enable_interrupts(struct iwl3945_priv *priv)
  3812. {
  3813. IWL_DEBUG_ISR("Enabling interrupts\n");
  3814. set_bit(STATUS_INT_ENABLED, &priv->status);
  3815. iwl3945_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
  3816. }
  3817. static inline void iwl3945_disable_interrupts(struct iwl3945_priv *priv)
  3818. {
  3819. clear_bit(STATUS_INT_ENABLED, &priv->status);
  3820. /* disable interrupts from uCode/NIC to host */
  3821. iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
  3822. /* acknowledge/clear/reset any interrupts still pending
  3823. * from uCode or flow handler (Rx/Tx DMA) */
  3824. iwl3945_write32(priv, CSR_INT, 0xffffffff);
  3825. iwl3945_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
  3826. IWL_DEBUG_ISR("Disabled interrupts\n");
  3827. }
  3828. static const char *desc_lookup(int i)
  3829. {
  3830. switch (i) {
  3831. case 1:
  3832. return "FAIL";
  3833. case 2:
  3834. return "BAD_PARAM";
  3835. case 3:
  3836. return "BAD_CHECKSUM";
  3837. case 4:
  3838. return "NMI_INTERRUPT";
  3839. case 5:
  3840. return "SYSASSERT";
  3841. case 6:
  3842. return "FATAL_ERROR";
  3843. }
  3844. return "UNKNOWN";
  3845. }
  3846. #define ERROR_START_OFFSET (1 * sizeof(u32))
  3847. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  3848. static void iwl3945_dump_nic_error_log(struct iwl3945_priv *priv)
  3849. {
  3850. u32 i;
  3851. u32 desc, time, count, base, data1;
  3852. u32 blink1, blink2, ilink1, ilink2;
  3853. int rc;
  3854. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  3855. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3856. IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
  3857. return;
  3858. }
  3859. rc = iwl3945_grab_nic_access(priv);
  3860. if (rc) {
  3861. IWL_WARNING("Can not read from adapter at this time.\n");
  3862. return;
  3863. }
  3864. count = iwl3945_read_targ_mem(priv, base);
  3865. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  3866. IWL_ERROR("Start IWL Error Log Dump:\n");
  3867. IWL_ERROR("Status: 0x%08lX, Config: %08X count: %d\n",
  3868. priv->status, priv->config, count);
  3869. }
  3870. IWL_ERROR("Desc Time asrtPC blink2 "
  3871. "ilink1 nmiPC Line\n");
  3872. for (i = ERROR_START_OFFSET;
  3873. i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
  3874. i += ERROR_ELEM_SIZE) {
  3875. desc = iwl3945_read_targ_mem(priv, base + i);
  3876. time =
  3877. iwl3945_read_targ_mem(priv, base + i + 1 * sizeof(u32));
  3878. blink1 =
  3879. iwl3945_read_targ_mem(priv, base + i + 2 * sizeof(u32));
  3880. blink2 =
  3881. iwl3945_read_targ_mem(priv, base + i + 3 * sizeof(u32));
  3882. ilink1 =
  3883. iwl3945_read_targ_mem(priv, base + i + 4 * sizeof(u32));
  3884. ilink2 =
  3885. iwl3945_read_targ_mem(priv, base + i + 5 * sizeof(u32));
  3886. data1 =
  3887. iwl3945_read_targ_mem(priv, base + i + 6 * sizeof(u32));
  3888. IWL_ERROR
  3889. ("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
  3890. desc_lookup(desc), desc, time, blink1, blink2,
  3891. ilink1, ilink2, data1);
  3892. }
  3893. iwl3945_release_nic_access(priv);
  3894. }
  3895. #define EVENT_START_OFFSET (6 * sizeof(u32))
  3896. /**
  3897. * iwl3945_print_event_log - Dump error event log to syslog
  3898. *
  3899. * NOTE: Must be called with iwl3945_grab_nic_access() already obtained!
  3900. */
  3901. static void iwl3945_print_event_log(struct iwl3945_priv *priv, u32 start_idx,
  3902. u32 num_events, u32 mode)
  3903. {
  3904. u32 i;
  3905. u32 base; /* SRAM byte address of event log header */
  3906. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  3907. u32 ptr; /* SRAM byte address of log data */
  3908. u32 ev, time, data; /* event log data */
  3909. if (num_events == 0)
  3910. return;
  3911. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3912. if (mode == 0)
  3913. event_size = 2 * sizeof(u32);
  3914. else
  3915. event_size = 3 * sizeof(u32);
  3916. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  3917. /* "time" is actually "data" for mode 0 (no timestamp).
  3918. * place event id # at far right for easier visual parsing. */
  3919. for (i = 0; i < num_events; i++) {
  3920. ev = iwl3945_read_targ_mem(priv, ptr);
  3921. ptr += sizeof(u32);
  3922. time = iwl3945_read_targ_mem(priv, ptr);
  3923. ptr += sizeof(u32);
  3924. if (mode == 0)
  3925. IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
  3926. else {
  3927. data = iwl3945_read_targ_mem(priv, ptr);
  3928. ptr += sizeof(u32);
  3929. IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
  3930. }
  3931. }
  3932. }
  3933. static void iwl3945_dump_nic_event_log(struct iwl3945_priv *priv)
  3934. {
  3935. int rc;
  3936. u32 base; /* SRAM byte address of event log header */
  3937. u32 capacity; /* event log capacity in # entries */
  3938. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  3939. u32 num_wraps; /* # times uCode wrapped to top of log */
  3940. u32 next_entry; /* index of next entry to be written by uCode */
  3941. u32 size; /* # entries that we'll print */
  3942. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3943. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3944. IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
  3945. return;
  3946. }
  3947. rc = iwl3945_grab_nic_access(priv);
  3948. if (rc) {
  3949. IWL_WARNING("Can not read from adapter at this time.\n");
  3950. return;
  3951. }
  3952. /* event log header */
  3953. capacity = iwl3945_read_targ_mem(priv, base);
  3954. mode = iwl3945_read_targ_mem(priv, base + (1 * sizeof(u32)));
  3955. num_wraps = iwl3945_read_targ_mem(priv, base + (2 * sizeof(u32)));
  3956. next_entry = iwl3945_read_targ_mem(priv, base + (3 * sizeof(u32)));
  3957. size = num_wraps ? capacity : next_entry;
  3958. /* bail out if nothing in log */
  3959. if (size == 0) {
  3960. IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
  3961. iwl3945_release_nic_access(priv);
  3962. return;
  3963. }
  3964. IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
  3965. size, num_wraps);
  3966. /* if uCode has wrapped back to top of log, start at the oldest entry,
  3967. * i.e the next one that uCode would fill. */
  3968. if (num_wraps)
  3969. iwl3945_print_event_log(priv, next_entry,
  3970. capacity - next_entry, mode);
  3971. /* (then/else) start at top of log */
  3972. iwl3945_print_event_log(priv, 0, next_entry, mode);
  3973. iwl3945_release_nic_access(priv);
  3974. }
  3975. /**
  3976. * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
  3977. */
  3978. static void iwl3945_irq_handle_error(struct iwl3945_priv *priv)
  3979. {
  3980. /* Set the FW error flag -- cleared on iwl3945_down */
  3981. set_bit(STATUS_FW_ERROR, &priv->status);
  3982. /* Cancel currently queued command. */
  3983. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  3984. #ifdef CONFIG_IWL3945_DEBUG
  3985. if (iwl3945_debug_level & IWL_DL_FW_ERRORS) {
  3986. iwl3945_dump_nic_error_log(priv);
  3987. iwl3945_dump_nic_event_log(priv);
  3988. iwl3945_print_rx_config_cmd(&priv->staging_rxon);
  3989. }
  3990. #endif
  3991. wake_up_interruptible(&priv->wait_command_queue);
  3992. /* Keep the restart process from trying to send host
  3993. * commands by clearing the INIT status bit */
  3994. clear_bit(STATUS_READY, &priv->status);
  3995. if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  3996. IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
  3997. "Restarting adapter due to uCode error.\n");
  3998. if (iwl3945_is_associated(priv)) {
  3999. memcpy(&priv->recovery_rxon, &priv->active_rxon,
  4000. sizeof(priv->recovery_rxon));
  4001. priv->error_recovering = 1;
  4002. }
  4003. queue_work(priv->workqueue, &priv->restart);
  4004. }
  4005. }
  4006. static void iwl3945_error_recovery(struct iwl3945_priv *priv)
  4007. {
  4008. unsigned long flags;
  4009. memcpy(&priv->staging_rxon, &priv->recovery_rxon,
  4010. sizeof(priv->staging_rxon));
  4011. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4012. iwl3945_commit_rxon(priv);
  4013. iwl3945_add_station(priv, priv->bssid, 1, 0);
  4014. spin_lock_irqsave(&priv->lock, flags);
  4015. priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
  4016. priv->error_recovering = 0;
  4017. spin_unlock_irqrestore(&priv->lock, flags);
  4018. }
  4019. static void iwl3945_irq_tasklet(struct iwl3945_priv *priv)
  4020. {
  4021. u32 inta, handled = 0;
  4022. u32 inta_fh;
  4023. unsigned long flags;
  4024. #ifdef CONFIG_IWL3945_DEBUG
  4025. u32 inta_mask;
  4026. #endif
  4027. spin_lock_irqsave(&priv->lock, flags);
  4028. /* Ack/clear/reset pending uCode interrupts.
  4029. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  4030. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  4031. inta = iwl3945_read32(priv, CSR_INT);
  4032. iwl3945_write32(priv, CSR_INT, inta);
  4033. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  4034. * Any new interrupts that happen after this, either while we're
  4035. * in this tasklet, or later, will show up in next ISR/tasklet. */
  4036. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  4037. iwl3945_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  4038. #ifdef CONFIG_IWL3945_DEBUG
  4039. if (iwl3945_debug_level & IWL_DL_ISR) {
  4040. /* just for debug */
  4041. inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
  4042. IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  4043. inta, inta_mask, inta_fh);
  4044. }
  4045. #endif
  4046. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  4047. * atomic, make sure that inta covers all the interrupts that
  4048. * we've discovered, even if FH interrupt came in just after
  4049. * reading CSR_INT. */
  4050. if (inta_fh & CSR_FH_INT_RX_MASK)
  4051. inta |= CSR_INT_BIT_FH_RX;
  4052. if (inta_fh & CSR_FH_INT_TX_MASK)
  4053. inta |= CSR_INT_BIT_FH_TX;
  4054. /* Now service all interrupt bits discovered above. */
  4055. if (inta & CSR_INT_BIT_HW_ERR) {
  4056. IWL_ERROR("Microcode HW error detected. Restarting.\n");
  4057. /* Tell the device to stop sending interrupts */
  4058. iwl3945_disable_interrupts(priv);
  4059. iwl3945_irq_handle_error(priv);
  4060. handled |= CSR_INT_BIT_HW_ERR;
  4061. spin_unlock_irqrestore(&priv->lock, flags);
  4062. return;
  4063. }
  4064. #ifdef CONFIG_IWL3945_DEBUG
  4065. if (iwl3945_debug_level & (IWL_DL_ISR)) {
  4066. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  4067. if (inta & CSR_INT_BIT_MAC_CLK_ACTV)
  4068. IWL_DEBUG_ISR("Microcode started or stopped.\n");
  4069. /* Alive notification via Rx interrupt will do the real work */
  4070. if (inta & CSR_INT_BIT_ALIVE)
  4071. IWL_DEBUG_ISR("Alive interrupt\n");
  4072. }
  4073. #endif
  4074. /* Safely ignore these bits for debug checks below */
  4075. inta &= ~(CSR_INT_BIT_MAC_CLK_ACTV | CSR_INT_BIT_ALIVE);
  4076. /* HW RF KILL switch toggled (4965 only) */
  4077. if (inta & CSR_INT_BIT_RF_KILL) {
  4078. int hw_rf_kill = 0;
  4079. if (!(iwl3945_read32(priv, CSR_GP_CNTRL) &
  4080. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  4081. hw_rf_kill = 1;
  4082. IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL | IWL_DL_ISR,
  4083. "RF_KILL bit toggled to %s.\n",
  4084. hw_rf_kill ? "disable radio":"enable radio");
  4085. /* Queue restart only if RF_KILL switch was set to "kill"
  4086. * when we loaded driver, and is now set to "enable".
  4087. * After we're Alive, RF_KILL gets handled by
  4088. * iwl_rx_card_state_notif() */
  4089. if (!hw_rf_kill && !test_bit(STATUS_ALIVE, &priv->status)) {
  4090. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  4091. queue_work(priv->workqueue, &priv->restart);
  4092. }
  4093. handled |= CSR_INT_BIT_RF_KILL;
  4094. }
  4095. /* Chip got too hot and stopped itself (4965 only) */
  4096. if (inta & CSR_INT_BIT_CT_KILL) {
  4097. IWL_ERROR("Microcode CT kill error detected.\n");
  4098. handled |= CSR_INT_BIT_CT_KILL;
  4099. }
  4100. /* Error detected by uCode */
  4101. if (inta & CSR_INT_BIT_SW_ERR) {
  4102. IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n",
  4103. inta);
  4104. iwl3945_irq_handle_error(priv);
  4105. handled |= CSR_INT_BIT_SW_ERR;
  4106. }
  4107. /* uCode wakes up after power-down sleep */
  4108. if (inta & CSR_INT_BIT_WAKEUP) {
  4109. IWL_DEBUG_ISR("Wakeup interrupt\n");
  4110. iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
  4111. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
  4112. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
  4113. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
  4114. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]);
  4115. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]);
  4116. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]);
  4117. handled |= CSR_INT_BIT_WAKEUP;
  4118. }
  4119. /* All uCode command responses, including Tx command responses,
  4120. * Rx "responses" (frame-received notification), and other
  4121. * notifications from uCode come through here*/
  4122. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  4123. iwl3945_rx_handle(priv);
  4124. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  4125. }
  4126. if (inta & CSR_INT_BIT_FH_TX) {
  4127. IWL_DEBUG_ISR("Tx interrupt\n");
  4128. iwl3945_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
  4129. if (!iwl3945_grab_nic_access(priv)) {
  4130. iwl3945_write_direct32(priv,
  4131. FH_TCSR_CREDIT
  4132. (ALM_FH_SRVC_CHNL), 0x0);
  4133. iwl3945_release_nic_access(priv);
  4134. }
  4135. handled |= CSR_INT_BIT_FH_TX;
  4136. }
  4137. if (inta & ~handled)
  4138. IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
  4139. if (inta & ~CSR_INI_SET_MASK) {
  4140. IWL_WARNING("Disabled INTA bits 0x%08x were pending\n",
  4141. inta & ~CSR_INI_SET_MASK);
  4142. IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh);
  4143. }
  4144. /* Re-enable all interrupts */
  4145. iwl3945_enable_interrupts(priv);
  4146. #ifdef CONFIG_IWL3945_DEBUG
  4147. if (iwl3945_debug_level & (IWL_DL_ISR)) {
  4148. inta = iwl3945_read32(priv, CSR_INT);
  4149. inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
  4150. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  4151. IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  4152. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  4153. }
  4154. #endif
  4155. spin_unlock_irqrestore(&priv->lock, flags);
  4156. }
  4157. static irqreturn_t iwl3945_isr(int irq, void *data)
  4158. {
  4159. struct iwl3945_priv *priv = data;
  4160. u32 inta, inta_mask;
  4161. u32 inta_fh;
  4162. if (!priv)
  4163. return IRQ_NONE;
  4164. spin_lock(&priv->lock);
  4165. /* Disable (but don't clear!) interrupts here to avoid
  4166. * back-to-back ISRs and sporadic interrupts from our NIC.
  4167. * If we have something to service, the tasklet will re-enable ints.
  4168. * If we *don't* have something, we'll re-enable before leaving here. */
  4169. inta_mask = iwl3945_read32(priv, CSR_INT_MASK); /* just for debug */
  4170. iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
  4171. /* Discover which interrupts are active/pending */
  4172. inta = iwl3945_read32(priv, CSR_INT);
  4173. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  4174. /* Ignore interrupt if there's nothing in NIC to service.
  4175. * This may be due to IRQ shared with another device,
  4176. * or due to sporadic interrupts thrown from our NIC. */
  4177. if (!inta && !inta_fh) {
  4178. IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
  4179. goto none;
  4180. }
  4181. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  4182. /* Hardware disappeared */
  4183. IWL_WARNING("HARDWARE GONE?? INTA == 0x%080x\n", inta);
  4184. goto unplugged;
  4185. }
  4186. IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  4187. inta, inta_mask, inta_fh);
  4188. /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
  4189. tasklet_schedule(&priv->irq_tasklet);
  4190. unplugged:
  4191. spin_unlock(&priv->lock);
  4192. return IRQ_HANDLED;
  4193. none:
  4194. /* re-enable interrupts here since we don't have anything to service. */
  4195. iwl3945_enable_interrupts(priv);
  4196. spin_unlock(&priv->lock);
  4197. return IRQ_NONE;
  4198. }
  4199. /************************** EEPROM BANDS ****************************
  4200. *
  4201. * The iwl3945_eeprom_band definitions below provide the mapping from the
  4202. * EEPROM contents to the specific channel number supported for each
  4203. * band.
  4204. *
  4205. * For example, iwl3945_priv->eeprom.band_3_channels[4] from the band_3
  4206. * definition below maps to physical channel 42 in the 5.2GHz spectrum.
  4207. * The specific geography and calibration information for that channel
  4208. * is contained in the eeprom map itself.
  4209. *
  4210. * During init, we copy the eeprom information and channel map
  4211. * information into priv->channel_info_24/52 and priv->channel_map_24/52
  4212. *
  4213. * channel_map_24/52 provides the index in the channel_info array for a
  4214. * given channel. We have to have two separate maps as there is channel
  4215. * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
  4216. * band_2
  4217. *
  4218. * A value of 0xff stored in the channel_map indicates that the channel
  4219. * is not supported by the hardware at all.
  4220. *
  4221. * A value of 0xfe in the channel_map indicates that the channel is not
  4222. * valid for Tx with the current hardware. This means that
  4223. * while the system can tune and receive on a given channel, it may not
  4224. * be able to associate or transmit any frames on that
  4225. * channel. There is no corresponding channel information for that
  4226. * entry.
  4227. *
  4228. *********************************************************************/
  4229. /* 2.4 GHz */
  4230. static const u8 iwl3945_eeprom_band_1[14] = {
  4231. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
  4232. };
  4233. /* 5.2 GHz bands */
  4234. static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */
  4235. 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
  4236. };
  4237. static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */
  4238. 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
  4239. };
  4240. static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
  4241. 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
  4242. };
  4243. static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
  4244. 145, 149, 153, 157, 161, 165
  4245. };
  4246. static void iwl3945_init_band_reference(const struct iwl3945_priv *priv, int band,
  4247. int *eeprom_ch_count,
  4248. const struct iwl3945_eeprom_channel
  4249. **eeprom_ch_info,
  4250. const u8 **eeprom_ch_index)
  4251. {
  4252. switch (band) {
  4253. case 1: /* 2.4GHz band */
  4254. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
  4255. *eeprom_ch_info = priv->eeprom.band_1_channels;
  4256. *eeprom_ch_index = iwl3945_eeprom_band_1;
  4257. break;
  4258. case 2: /* 4.9GHz band */
  4259. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
  4260. *eeprom_ch_info = priv->eeprom.band_2_channels;
  4261. *eeprom_ch_index = iwl3945_eeprom_band_2;
  4262. break;
  4263. case 3: /* 5.2GHz band */
  4264. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
  4265. *eeprom_ch_info = priv->eeprom.band_3_channels;
  4266. *eeprom_ch_index = iwl3945_eeprom_band_3;
  4267. break;
  4268. case 4: /* 5.5GHz band */
  4269. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
  4270. *eeprom_ch_info = priv->eeprom.band_4_channels;
  4271. *eeprom_ch_index = iwl3945_eeprom_band_4;
  4272. break;
  4273. case 5: /* 5.7GHz band */
  4274. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
  4275. *eeprom_ch_info = priv->eeprom.band_5_channels;
  4276. *eeprom_ch_index = iwl3945_eeprom_band_5;
  4277. break;
  4278. default:
  4279. BUG();
  4280. return;
  4281. }
  4282. }
  4283. /**
  4284. * iwl3945_get_channel_info - Find driver's private channel info
  4285. *
  4286. * Based on band and channel number.
  4287. */
  4288. const struct iwl3945_channel_info *iwl3945_get_channel_info(const struct iwl3945_priv *priv,
  4289. int phymode, u16 channel)
  4290. {
  4291. int i;
  4292. switch (phymode) {
  4293. case MODE_IEEE80211A:
  4294. for (i = 14; i < priv->channel_count; i++) {
  4295. if (priv->channel_info[i].channel == channel)
  4296. return &priv->channel_info[i];
  4297. }
  4298. break;
  4299. case MODE_IEEE80211B:
  4300. case MODE_IEEE80211G:
  4301. if (channel >= 1 && channel <= 14)
  4302. return &priv->channel_info[channel - 1];
  4303. break;
  4304. }
  4305. return NULL;
  4306. }
  4307. #define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
  4308. ? # x " " : "")
  4309. /**
  4310. * iwl3945_init_channel_map - Set up driver's info for all possible channels
  4311. */
  4312. static int iwl3945_init_channel_map(struct iwl3945_priv *priv)
  4313. {
  4314. int eeprom_ch_count = 0;
  4315. const u8 *eeprom_ch_index = NULL;
  4316. const struct iwl3945_eeprom_channel *eeprom_ch_info = NULL;
  4317. int band, ch;
  4318. struct iwl3945_channel_info *ch_info;
  4319. if (priv->channel_count) {
  4320. IWL_DEBUG_INFO("Channel map already initialized.\n");
  4321. return 0;
  4322. }
  4323. if (priv->eeprom.version < 0x2f) {
  4324. IWL_WARNING("Unsupported EEPROM version: 0x%04X\n",
  4325. priv->eeprom.version);
  4326. return -EINVAL;
  4327. }
  4328. IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
  4329. priv->channel_count =
  4330. ARRAY_SIZE(iwl3945_eeprom_band_1) +
  4331. ARRAY_SIZE(iwl3945_eeprom_band_2) +
  4332. ARRAY_SIZE(iwl3945_eeprom_band_3) +
  4333. ARRAY_SIZE(iwl3945_eeprom_band_4) +
  4334. ARRAY_SIZE(iwl3945_eeprom_band_5);
  4335. IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
  4336. priv->channel_info = kzalloc(sizeof(struct iwl3945_channel_info) *
  4337. priv->channel_count, GFP_KERNEL);
  4338. if (!priv->channel_info) {
  4339. IWL_ERROR("Could not allocate channel_info\n");
  4340. priv->channel_count = 0;
  4341. return -ENOMEM;
  4342. }
  4343. ch_info = priv->channel_info;
  4344. /* Loop through the 5 EEPROM bands adding them in order to the
  4345. * channel map we maintain (that contains additional information than
  4346. * what just in the EEPROM) */
  4347. for (band = 1; band <= 5; band++) {
  4348. iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
  4349. &eeprom_ch_info, &eeprom_ch_index);
  4350. /* Loop through each band adding each of the channels */
  4351. for (ch = 0; ch < eeprom_ch_count; ch++) {
  4352. ch_info->channel = eeprom_ch_index[ch];
  4353. ch_info->phymode = (band == 1) ? MODE_IEEE80211B :
  4354. MODE_IEEE80211A;
  4355. /* permanently store EEPROM's channel regulatory flags
  4356. * and max power in channel info database. */
  4357. ch_info->eeprom = eeprom_ch_info[ch];
  4358. /* Copy the run-time flags so they are there even on
  4359. * invalid channels */
  4360. ch_info->flags = eeprom_ch_info[ch].flags;
  4361. if (!(is_channel_valid(ch_info))) {
  4362. IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
  4363. "No traffic\n",
  4364. ch_info->channel,
  4365. ch_info->flags,
  4366. is_channel_a_band(ch_info) ?
  4367. "5.2" : "2.4");
  4368. ch_info++;
  4369. continue;
  4370. }
  4371. /* Initialize regulatory-based run-time data */
  4372. ch_info->max_power_avg = ch_info->curr_txpow =
  4373. eeprom_ch_info[ch].max_power_avg;
  4374. ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
  4375. ch_info->min_power = 0;
  4376. IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
  4377. " %ddBm): Ad-Hoc %ssupported\n",
  4378. ch_info->channel,
  4379. is_channel_a_band(ch_info) ?
  4380. "5.2" : "2.4",
  4381. CHECK_AND_PRINT(IBSS),
  4382. CHECK_AND_PRINT(ACTIVE),
  4383. CHECK_AND_PRINT(RADAR),
  4384. CHECK_AND_PRINT(WIDE),
  4385. CHECK_AND_PRINT(NARROW),
  4386. CHECK_AND_PRINT(DFS),
  4387. eeprom_ch_info[ch].flags,
  4388. eeprom_ch_info[ch].max_power_avg,
  4389. ((eeprom_ch_info[ch].
  4390. flags & EEPROM_CHANNEL_IBSS)
  4391. && !(eeprom_ch_info[ch].
  4392. flags & EEPROM_CHANNEL_RADAR))
  4393. ? "" : "not ");
  4394. /* Set the user_txpower_limit to the highest power
  4395. * supported by any channel */
  4396. if (eeprom_ch_info[ch].max_power_avg >
  4397. priv->user_txpower_limit)
  4398. priv->user_txpower_limit =
  4399. eeprom_ch_info[ch].max_power_avg;
  4400. ch_info++;
  4401. }
  4402. }
  4403. /* Set up txpower settings in driver for all channels */
  4404. if (iwl3945_txpower_set_from_eeprom(priv))
  4405. return -EIO;
  4406. return 0;
  4407. }
  4408. /* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
  4409. * sending probe req. This should be set long enough to hear probe responses
  4410. * from more than one AP. */
  4411. #define IWL_ACTIVE_DWELL_TIME_24 (20) /* all times in msec */
  4412. #define IWL_ACTIVE_DWELL_TIME_52 (10)
  4413. /* For faster active scanning, scan will move to the next channel if fewer than
  4414. * PLCP_QUIET_THRESH packets are heard on this channel within
  4415. * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
  4416. * time if it's a quiet channel (nothing responded to our probe, and there's
  4417. * no other traffic).
  4418. * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
  4419. #define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
  4420. #define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(5) /* msec */
  4421. /* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
  4422. * Must be set longer than active dwell time.
  4423. * For the most reliable scan, set > AP beacon interval (typically 100msec). */
  4424. #define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
  4425. #define IWL_PASSIVE_DWELL_TIME_52 (10)
  4426. #define IWL_PASSIVE_DWELL_BASE (100)
  4427. #define IWL_CHANNEL_TUNE_TIME 5
  4428. static inline u16 iwl3945_get_active_dwell_time(struct iwl3945_priv *priv, int phymode)
  4429. {
  4430. if (phymode == MODE_IEEE80211A)
  4431. return IWL_ACTIVE_DWELL_TIME_52;
  4432. else
  4433. return IWL_ACTIVE_DWELL_TIME_24;
  4434. }
  4435. static u16 iwl3945_get_passive_dwell_time(struct iwl3945_priv *priv, int phymode)
  4436. {
  4437. u16 active = iwl3945_get_active_dwell_time(priv, phymode);
  4438. u16 passive = (phymode != MODE_IEEE80211A) ?
  4439. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
  4440. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
  4441. if (iwl3945_is_associated(priv)) {
  4442. /* If we're associated, we clamp the maximum passive
  4443. * dwell time to be 98% of the beacon interval (minus
  4444. * 2 * channel tune time) */
  4445. passive = priv->beacon_int;
  4446. if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
  4447. passive = IWL_PASSIVE_DWELL_BASE;
  4448. passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
  4449. }
  4450. if (passive <= active)
  4451. passive = active + 1;
  4452. return passive;
  4453. }
  4454. static int iwl3945_get_channels_for_scan(struct iwl3945_priv *priv, int phymode,
  4455. u8 is_active, u8 direct_mask,
  4456. struct iwl3945_scan_channel *scan_ch)
  4457. {
  4458. const struct ieee80211_channel *channels = NULL;
  4459. const struct ieee80211_hw_mode *hw_mode;
  4460. const struct iwl3945_channel_info *ch_info;
  4461. u16 passive_dwell = 0;
  4462. u16 active_dwell = 0;
  4463. int added, i;
  4464. hw_mode = iwl3945_get_hw_mode(priv, phymode);
  4465. if (!hw_mode)
  4466. return 0;
  4467. channels = hw_mode->channels;
  4468. active_dwell = iwl3945_get_active_dwell_time(priv, phymode);
  4469. passive_dwell = iwl3945_get_passive_dwell_time(priv, phymode);
  4470. for (i = 0, added = 0; i < hw_mode->num_channels; i++) {
  4471. if (channels[i].chan ==
  4472. le16_to_cpu(priv->active_rxon.channel)) {
  4473. if (iwl3945_is_associated(priv)) {
  4474. IWL_DEBUG_SCAN
  4475. ("Skipping current channel %d\n",
  4476. le16_to_cpu(priv->active_rxon.channel));
  4477. continue;
  4478. }
  4479. } else if (priv->only_active_channel)
  4480. continue;
  4481. scan_ch->channel = channels[i].chan;
  4482. ch_info = iwl3945_get_channel_info(priv, phymode, scan_ch->channel);
  4483. if (!is_channel_valid(ch_info)) {
  4484. IWL_DEBUG_SCAN("Channel %d is INVALID for this SKU.\n",
  4485. scan_ch->channel);
  4486. continue;
  4487. }
  4488. if (!is_active || is_channel_passive(ch_info) ||
  4489. !(channels[i].flag & IEEE80211_CHAN_W_ACTIVE_SCAN))
  4490. scan_ch->type = 0; /* passive */
  4491. else
  4492. scan_ch->type = 1; /* active */
  4493. if (scan_ch->type & 1)
  4494. scan_ch->type |= (direct_mask << 1);
  4495. if (is_channel_narrow(ch_info))
  4496. scan_ch->type |= (1 << 7);
  4497. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  4498. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  4499. /* Set txpower levels to defaults */
  4500. scan_ch->tpc.dsp_atten = 110;
  4501. /* scan_pwr_info->tpc.dsp_atten; */
  4502. /*scan_pwr_info->tpc.tx_gain; */
  4503. if (phymode == MODE_IEEE80211A)
  4504. scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
  4505. else {
  4506. scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
  4507. /* NOTE: if we were doing 6Mb OFDM for scans we'd use
  4508. * power level:
  4509. * scan_ch->tpc.tx_gain = ((1<<5) | (2 << 3)) | 3;
  4510. */
  4511. }
  4512. IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
  4513. scan_ch->channel,
  4514. (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
  4515. (scan_ch->type & 1) ?
  4516. active_dwell : passive_dwell);
  4517. scan_ch++;
  4518. added++;
  4519. }
  4520. IWL_DEBUG_SCAN("total channels to scan %d \n", added);
  4521. return added;
  4522. }
  4523. static void iwl3945_reset_channel_flag(struct iwl3945_priv *priv)
  4524. {
  4525. int i, j;
  4526. for (i = 0; i < 3; i++) {
  4527. struct ieee80211_hw_mode *hw_mode = (void *)&priv->modes[i];
  4528. for (j = 0; j < hw_mode->num_channels; j++)
  4529. hw_mode->channels[j].flag = hw_mode->channels[j].val;
  4530. }
  4531. }
  4532. static void iwl3945_init_hw_rates(struct iwl3945_priv *priv,
  4533. struct ieee80211_rate *rates)
  4534. {
  4535. int i;
  4536. for (i = 0; i < IWL_RATE_COUNT; i++) {
  4537. rates[i].rate = iwl3945_rates[i].ieee * 5;
  4538. rates[i].val = i; /* Rate scaling will work on indexes */
  4539. rates[i].val2 = i;
  4540. rates[i].flags = IEEE80211_RATE_SUPPORTED;
  4541. /* Only OFDM have the bits-per-symbol set */
  4542. if ((i <= IWL_LAST_OFDM_RATE) && (i >= IWL_FIRST_OFDM_RATE))
  4543. rates[i].flags |= IEEE80211_RATE_OFDM;
  4544. else {
  4545. /*
  4546. * If CCK 1M then set rate flag to CCK else CCK_2
  4547. * which is CCK | PREAMBLE2
  4548. */
  4549. rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
  4550. IEEE80211_RATE_CCK : IEEE80211_RATE_CCK_2;
  4551. }
  4552. /* Set up which ones are basic rates... */
  4553. if (IWL_BASIC_RATES_MASK & (1 << i))
  4554. rates[i].flags |= IEEE80211_RATE_BASIC;
  4555. }
  4556. }
  4557. /**
  4558. * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
  4559. */
  4560. static int iwl3945_init_geos(struct iwl3945_priv *priv)
  4561. {
  4562. struct iwl3945_channel_info *ch;
  4563. struct ieee80211_hw_mode *modes;
  4564. struct ieee80211_channel *channels;
  4565. struct ieee80211_channel *geo_ch;
  4566. struct ieee80211_rate *rates;
  4567. int i = 0;
  4568. enum {
  4569. A = 0,
  4570. B = 1,
  4571. G = 2,
  4572. };
  4573. int mode_count = 3;
  4574. if (priv->modes) {
  4575. IWL_DEBUG_INFO("Geography modes already initialized.\n");
  4576. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4577. return 0;
  4578. }
  4579. modes = kzalloc(sizeof(struct ieee80211_hw_mode) * mode_count,
  4580. GFP_KERNEL);
  4581. if (!modes)
  4582. return -ENOMEM;
  4583. channels = kzalloc(sizeof(struct ieee80211_channel) *
  4584. priv->channel_count, GFP_KERNEL);
  4585. if (!channels) {
  4586. kfree(modes);
  4587. return -ENOMEM;
  4588. }
  4589. rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_MAX_RATES + 1)),
  4590. GFP_KERNEL);
  4591. if (!rates) {
  4592. kfree(modes);
  4593. kfree(channels);
  4594. return -ENOMEM;
  4595. }
  4596. /* 0 = 802.11a
  4597. * 1 = 802.11b
  4598. * 2 = 802.11g
  4599. */
  4600. /* 5.2GHz channels start after the 2.4GHz channels */
  4601. modes[A].mode = MODE_IEEE80211A;
  4602. modes[A].channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
  4603. modes[A].rates = &rates[4];
  4604. modes[A].num_rates = 8; /* just OFDM */
  4605. modes[A].num_channels = 0;
  4606. modes[B].mode = MODE_IEEE80211B;
  4607. modes[B].channels = channels;
  4608. modes[B].rates = rates;
  4609. modes[B].num_rates = 4; /* just CCK */
  4610. modes[B].num_channels = 0;
  4611. modes[G].mode = MODE_IEEE80211G;
  4612. modes[G].channels = channels;
  4613. modes[G].rates = rates;
  4614. modes[G].num_rates = 12; /* OFDM & CCK */
  4615. modes[G].num_channels = 0;
  4616. priv->ieee_channels = channels;
  4617. priv->ieee_rates = rates;
  4618. iwl3945_init_hw_rates(priv, rates);
  4619. for (i = 0, geo_ch = channels; i < priv->channel_count; i++) {
  4620. ch = &priv->channel_info[i];
  4621. if (!is_channel_valid(ch)) {
  4622. IWL_DEBUG_INFO("Channel %d [%sGHz] is restricted -- "
  4623. "skipping.\n",
  4624. ch->channel, is_channel_a_band(ch) ?
  4625. "5.2" : "2.4");
  4626. continue;
  4627. }
  4628. if (is_channel_a_band(ch))
  4629. geo_ch = &modes[A].channels[modes[A].num_channels++];
  4630. else {
  4631. geo_ch = &modes[B].channels[modes[B].num_channels++];
  4632. modes[G].num_channels++;
  4633. }
  4634. geo_ch->freq = ieee80211chan2mhz(ch->channel);
  4635. geo_ch->chan = ch->channel;
  4636. geo_ch->power_level = ch->max_power_avg;
  4637. geo_ch->antenna_max = 0xff;
  4638. if (is_channel_valid(ch)) {
  4639. geo_ch->flag = IEEE80211_CHAN_W_SCAN;
  4640. if (ch->flags & EEPROM_CHANNEL_IBSS)
  4641. geo_ch->flag |= IEEE80211_CHAN_W_IBSS;
  4642. if (ch->flags & EEPROM_CHANNEL_ACTIVE)
  4643. geo_ch->flag |= IEEE80211_CHAN_W_ACTIVE_SCAN;
  4644. if (ch->flags & EEPROM_CHANNEL_RADAR)
  4645. geo_ch->flag |= IEEE80211_CHAN_W_RADAR_DETECT;
  4646. if (ch->max_power_avg > priv->max_channel_txpower_limit)
  4647. priv->max_channel_txpower_limit =
  4648. ch->max_power_avg;
  4649. }
  4650. geo_ch->val = geo_ch->flag;
  4651. }
  4652. if ((modes[A].num_channels == 0) && priv->is_abg) {
  4653. printk(KERN_INFO DRV_NAME
  4654. ": Incorrectly detected BG card as ABG. Please send "
  4655. "your PCI ID 0x%04X:0x%04X to maintainer.\n",
  4656. priv->pci_dev->device, priv->pci_dev->subsystem_device);
  4657. priv->is_abg = 0;
  4658. }
  4659. printk(KERN_INFO DRV_NAME
  4660. ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
  4661. modes[G].num_channels, modes[A].num_channels);
  4662. /*
  4663. * NOTE: We register these in preference of order -- the
  4664. * stack doesn't currently (as of 7.0.6 / Apr 24 '07) pick
  4665. * a phymode based on rates or AP capabilities but seems to
  4666. * configure it purely on if the channel being configured
  4667. * is supported by a mode -- and the first match is taken
  4668. */
  4669. if (modes[G].num_channels)
  4670. ieee80211_register_hwmode(priv->hw, &modes[G]);
  4671. if (modes[B].num_channels)
  4672. ieee80211_register_hwmode(priv->hw, &modes[B]);
  4673. if (modes[A].num_channels)
  4674. ieee80211_register_hwmode(priv->hw, &modes[A]);
  4675. priv->modes = modes;
  4676. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4677. return 0;
  4678. }
  4679. /******************************************************************************
  4680. *
  4681. * uCode download functions
  4682. *
  4683. ******************************************************************************/
  4684. static void iwl3945_dealloc_ucode_pci(struct iwl3945_priv *priv)
  4685. {
  4686. if (priv->ucode_code.v_addr != NULL) {
  4687. pci_free_consistent(priv->pci_dev,
  4688. priv->ucode_code.len,
  4689. priv->ucode_code.v_addr,
  4690. priv->ucode_code.p_addr);
  4691. priv->ucode_code.v_addr = NULL;
  4692. }
  4693. if (priv->ucode_data.v_addr != NULL) {
  4694. pci_free_consistent(priv->pci_dev,
  4695. priv->ucode_data.len,
  4696. priv->ucode_data.v_addr,
  4697. priv->ucode_data.p_addr);
  4698. priv->ucode_data.v_addr = NULL;
  4699. }
  4700. if (priv->ucode_data_backup.v_addr != NULL) {
  4701. pci_free_consistent(priv->pci_dev,
  4702. priv->ucode_data_backup.len,
  4703. priv->ucode_data_backup.v_addr,
  4704. priv->ucode_data_backup.p_addr);
  4705. priv->ucode_data_backup.v_addr = NULL;
  4706. }
  4707. if (priv->ucode_init.v_addr != NULL) {
  4708. pci_free_consistent(priv->pci_dev,
  4709. priv->ucode_init.len,
  4710. priv->ucode_init.v_addr,
  4711. priv->ucode_init.p_addr);
  4712. priv->ucode_init.v_addr = NULL;
  4713. }
  4714. if (priv->ucode_init_data.v_addr != NULL) {
  4715. pci_free_consistent(priv->pci_dev,
  4716. priv->ucode_init_data.len,
  4717. priv->ucode_init_data.v_addr,
  4718. priv->ucode_init_data.p_addr);
  4719. priv->ucode_init_data.v_addr = NULL;
  4720. }
  4721. if (priv->ucode_boot.v_addr != NULL) {
  4722. pci_free_consistent(priv->pci_dev,
  4723. priv->ucode_boot.len,
  4724. priv->ucode_boot.v_addr,
  4725. priv->ucode_boot.p_addr);
  4726. priv->ucode_boot.v_addr = NULL;
  4727. }
  4728. }
  4729. /**
  4730. * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
  4731. * looking at all data.
  4732. */
  4733. static int iwl3945_verify_inst_full(struct iwl3945_priv *priv, __le32 * image, u32 len)
  4734. {
  4735. u32 val;
  4736. u32 save_len = len;
  4737. int rc = 0;
  4738. u32 errcnt;
  4739. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4740. rc = iwl3945_grab_nic_access(priv);
  4741. if (rc)
  4742. return rc;
  4743. iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
  4744. errcnt = 0;
  4745. for (; len > 0; len -= sizeof(u32), image++) {
  4746. /* read data comes through single port, auto-incr addr */
  4747. /* NOTE: Use the debugless read so we don't flood kernel log
  4748. * if IWL_DL_IO is set */
  4749. val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4750. if (val != le32_to_cpu(*image)) {
  4751. IWL_ERROR("uCode INST section is invalid at "
  4752. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4753. save_len - len, val, le32_to_cpu(*image));
  4754. rc = -EIO;
  4755. errcnt++;
  4756. if (errcnt >= 20)
  4757. break;
  4758. }
  4759. }
  4760. iwl3945_release_nic_access(priv);
  4761. if (!errcnt)
  4762. IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
  4763. return rc;
  4764. }
  4765. /**
  4766. * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
  4767. * using sample data 100 bytes apart. If these sample points are good,
  4768. * it's a pretty good bet that everything between them is good, too.
  4769. */
  4770. static int iwl3945_verify_inst_sparse(struct iwl3945_priv *priv, __le32 *image, u32 len)
  4771. {
  4772. u32 val;
  4773. int rc = 0;
  4774. u32 errcnt = 0;
  4775. u32 i;
  4776. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4777. rc = iwl3945_grab_nic_access(priv);
  4778. if (rc)
  4779. return rc;
  4780. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  4781. /* read data comes through single port, auto-incr addr */
  4782. /* NOTE: Use the debugless read so we don't flood kernel log
  4783. * if IWL_DL_IO is set */
  4784. iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  4785. i + RTC_INST_LOWER_BOUND);
  4786. val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4787. if (val != le32_to_cpu(*image)) {
  4788. #if 0 /* Enable this if you want to see details */
  4789. IWL_ERROR("uCode INST section is invalid at "
  4790. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4791. i, val, *image);
  4792. #endif
  4793. rc = -EIO;
  4794. errcnt++;
  4795. if (errcnt >= 3)
  4796. break;
  4797. }
  4798. }
  4799. iwl3945_release_nic_access(priv);
  4800. return rc;
  4801. }
  4802. /**
  4803. * iwl3945_verify_ucode - determine which instruction image is in SRAM,
  4804. * and verify its contents
  4805. */
  4806. static int iwl3945_verify_ucode(struct iwl3945_priv *priv)
  4807. {
  4808. __le32 *image;
  4809. u32 len;
  4810. int rc = 0;
  4811. /* Try bootstrap */
  4812. image = (__le32 *)priv->ucode_boot.v_addr;
  4813. len = priv->ucode_boot.len;
  4814. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4815. if (rc == 0) {
  4816. IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
  4817. return 0;
  4818. }
  4819. /* Try initialize */
  4820. image = (__le32 *)priv->ucode_init.v_addr;
  4821. len = priv->ucode_init.len;
  4822. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4823. if (rc == 0) {
  4824. IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
  4825. return 0;
  4826. }
  4827. /* Try runtime/protocol */
  4828. image = (__le32 *)priv->ucode_code.v_addr;
  4829. len = priv->ucode_code.len;
  4830. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4831. if (rc == 0) {
  4832. IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
  4833. return 0;
  4834. }
  4835. IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
  4836. /* Since nothing seems to match, show first several data entries in
  4837. * instruction SRAM, so maybe visual inspection will give a clue.
  4838. * Selection of bootstrap image (vs. other images) is arbitrary. */
  4839. image = (__le32 *)priv->ucode_boot.v_addr;
  4840. len = priv->ucode_boot.len;
  4841. rc = iwl3945_verify_inst_full(priv, image, len);
  4842. return rc;
  4843. }
  4844. /* check contents of special bootstrap uCode SRAM */
  4845. static int iwl3945_verify_bsm(struct iwl3945_priv *priv)
  4846. {
  4847. __le32 *image = priv->ucode_boot.v_addr;
  4848. u32 len = priv->ucode_boot.len;
  4849. u32 reg;
  4850. u32 val;
  4851. IWL_DEBUG_INFO("Begin verify bsm\n");
  4852. /* verify BSM SRAM contents */
  4853. val = iwl3945_read_prph(priv, BSM_WR_DWCOUNT_REG);
  4854. for (reg = BSM_SRAM_LOWER_BOUND;
  4855. reg < BSM_SRAM_LOWER_BOUND + len;
  4856. reg += sizeof(u32), image ++) {
  4857. val = iwl3945_read_prph(priv, reg);
  4858. if (val != le32_to_cpu(*image)) {
  4859. IWL_ERROR("BSM uCode verification failed at "
  4860. "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
  4861. BSM_SRAM_LOWER_BOUND,
  4862. reg - BSM_SRAM_LOWER_BOUND, len,
  4863. val, le32_to_cpu(*image));
  4864. return -EIO;
  4865. }
  4866. }
  4867. IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
  4868. return 0;
  4869. }
  4870. /**
  4871. * iwl3945_load_bsm - Load bootstrap instructions
  4872. *
  4873. * BSM operation:
  4874. *
  4875. * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
  4876. * in special SRAM that does not power down during RFKILL. When powering back
  4877. * up after power-saving sleeps (or during initial uCode load), the BSM loads
  4878. * the bootstrap program into the on-board processor, and starts it.
  4879. *
  4880. * The bootstrap program loads (via DMA) instructions and data for a new
  4881. * program from host DRAM locations indicated by the host driver in the
  4882. * BSM_DRAM_* registers. Once the new program is loaded, it starts
  4883. * automatically.
  4884. *
  4885. * When initializing the NIC, the host driver points the BSM to the
  4886. * "initialize" uCode image. This uCode sets up some internal data, then
  4887. * notifies host via "initialize alive" that it is complete.
  4888. *
  4889. * The host then replaces the BSM_DRAM_* pointer values to point to the
  4890. * normal runtime uCode instructions and a backup uCode data cache buffer
  4891. * (filled initially with starting data values for the on-board processor),
  4892. * then triggers the "initialize" uCode to load and launch the runtime uCode,
  4893. * which begins normal operation.
  4894. *
  4895. * When doing a power-save shutdown, runtime uCode saves data SRAM into
  4896. * the backup data cache in DRAM before SRAM is powered down.
  4897. *
  4898. * When powering back up, the BSM loads the bootstrap program. This reloads
  4899. * the runtime uCode instructions and the backup data cache into SRAM,
  4900. * and re-launches the runtime uCode from where it left off.
  4901. */
  4902. static int iwl3945_load_bsm(struct iwl3945_priv *priv)
  4903. {
  4904. __le32 *image = priv->ucode_boot.v_addr;
  4905. u32 len = priv->ucode_boot.len;
  4906. dma_addr_t pinst;
  4907. dma_addr_t pdata;
  4908. u32 inst_len;
  4909. u32 data_len;
  4910. int rc;
  4911. int i;
  4912. u32 done;
  4913. u32 reg_offset;
  4914. IWL_DEBUG_INFO("Begin load bsm\n");
  4915. /* make sure bootstrap program is no larger than BSM's SRAM size */
  4916. if (len > IWL_MAX_BSM_SIZE)
  4917. return -EINVAL;
  4918. /* Tell bootstrap uCode where to find the "Initialize" uCode
  4919. * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
  4920. * NOTE: iwl3945_initialize_alive_start() will replace these values,
  4921. * after the "initialize" uCode has run, to point to
  4922. * runtime/protocol instructions and backup data cache. */
  4923. pinst = priv->ucode_init.p_addr;
  4924. pdata = priv->ucode_init_data.p_addr;
  4925. inst_len = priv->ucode_init.len;
  4926. data_len = priv->ucode_init_data.len;
  4927. rc = iwl3945_grab_nic_access(priv);
  4928. if (rc)
  4929. return rc;
  4930. iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  4931. iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  4932. iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
  4933. iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
  4934. /* Fill BSM memory with bootstrap instructions */
  4935. for (reg_offset = BSM_SRAM_LOWER_BOUND;
  4936. reg_offset < BSM_SRAM_LOWER_BOUND + len;
  4937. reg_offset += sizeof(u32), image++)
  4938. _iwl3945_write_prph(priv, reg_offset,
  4939. le32_to_cpu(*image));
  4940. rc = iwl3945_verify_bsm(priv);
  4941. if (rc) {
  4942. iwl3945_release_nic_access(priv);
  4943. return rc;
  4944. }
  4945. /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
  4946. iwl3945_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
  4947. iwl3945_write_prph(priv, BSM_WR_MEM_DST_REG,
  4948. RTC_INST_LOWER_BOUND);
  4949. iwl3945_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
  4950. /* Load bootstrap code into instruction SRAM now,
  4951. * to prepare to load "initialize" uCode */
  4952. iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
  4953. BSM_WR_CTRL_REG_BIT_START);
  4954. /* Wait for load of bootstrap uCode to finish */
  4955. for (i = 0; i < 100; i++) {
  4956. done = iwl3945_read_prph(priv, BSM_WR_CTRL_REG);
  4957. if (!(done & BSM_WR_CTRL_REG_BIT_START))
  4958. break;
  4959. udelay(10);
  4960. }
  4961. if (i < 100)
  4962. IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
  4963. else {
  4964. IWL_ERROR("BSM write did not complete!\n");
  4965. return -EIO;
  4966. }
  4967. /* Enable future boot loads whenever power management unit triggers it
  4968. * (e.g. when powering back up after power-save shutdown) */
  4969. iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
  4970. BSM_WR_CTRL_REG_BIT_START_EN);
  4971. iwl3945_release_nic_access(priv);
  4972. return 0;
  4973. }
  4974. static void iwl3945_nic_start(struct iwl3945_priv *priv)
  4975. {
  4976. /* Remove all resets to allow NIC to operate */
  4977. iwl3945_write32(priv, CSR_RESET, 0);
  4978. }
  4979. static int iwl3945_alloc_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc)
  4980. {
  4981. desc->v_addr = pci_alloc_consistent(pci_dev, desc->len, &desc->p_addr);
  4982. return (desc->v_addr != NULL) ? 0 : -ENOMEM;
  4983. }
  4984. /**
  4985. * iwl3945_read_ucode - Read uCode images from disk file.
  4986. *
  4987. * Copy into buffers for card to fetch via bus-mastering
  4988. */
  4989. static int iwl3945_read_ucode(struct iwl3945_priv *priv)
  4990. {
  4991. struct iwl3945_ucode *ucode;
  4992. int ret = 0;
  4993. const struct firmware *ucode_raw;
  4994. /* firmware file name contains uCode/driver compatibility version */
  4995. const char *name = "iwlwifi-3945" IWL3945_UCODE_API ".ucode";
  4996. u8 *src;
  4997. size_t len;
  4998. u32 ver, inst_size, data_size, init_size, init_data_size, boot_size;
  4999. /* Ask kernel firmware_class module to get the boot firmware off disk.
  5000. * request_firmware() is synchronous, file is in memory on return. */
  5001. ret = request_firmware(&ucode_raw, name, &priv->pci_dev->dev);
  5002. if (ret < 0) {
  5003. IWL_ERROR("%s firmware file req failed: Reason %d\n",
  5004. name, ret);
  5005. goto error;
  5006. }
  5007. IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
  5008. name, ucode_raw->size);
  5009. /* Make sure that we got at least our header! */
  5010. if (ucode_raw->size < sizeof(*ucode)) {
  5011. IWL_ERROR("File size way too small!\n");
  5012. ret = -EINVAL;
  5013. goto err_release;
  5014. }
  5015. /* Data from ucode file: header followed by uCode images */
  5016. ucode = (void *)ucode_raw->data;
  5017. ver = le32_to_cpu(ucode->ver);
  5018. inst_size = le32_to_cpu(ucode->inst_size);
  5019. data_size = le32_to_cpu(ucode->data_size);
  5020. init_size = le32_to_cpu(ucode->init_size);
  5021. init_data_size = le32_to_cpu(ucode->init_data_size);
  5022. boot_size = le32_to_cpu(ucode->boot_size);
  5023. IWL_DEBUG_INFO("f/w package hdr ucode version = 0x%x\n", ver);
  5024. IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
  5025. IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
  5026. IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
  5027. IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
  5028. IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
  5029. /* Verify size of file vs. image size info in file's header */
  5030. if (ucode_raw->size < sizeof(*ucode) +
  5031. inst_size + data_size + init_size +
  5032. init_data_size + boot_size) {
  5033. IWL_DEBUG_INFO("uCode file size %d too small\n",
  5034. (int)ucode_raw->size);
  5035. ret = -EINVAL;
  5036. goto err_release;
  5037. }
  5038. /* Verify that uCode images will fit in card's SRAM */
  5039. if (inst_size > IWL_MAX_INST_SIZE) {
  5040. IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
  5041. inst_size);
  5042. ret = -EINVAL;
  5043. goto err_release;
  5044. }
  5045. if (data_size > IWL_MAX_DATA_SIZE) {
  5046. IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
  5047. data_size);
  5048. ret = -EINVAL;
  5049. goto err_release;
  5050. }
  5051. if (init_size > IWL_MAX_INST_SIZE) {
  5052. IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
  5053. init_size);
  5054. ret = -EINVAL;
  5055. goto err_release;
  5056. }
  5057. if (init_data_size > IWL_MAX_DATA_SIZE) {
  5058. IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
  5059. init_data_size);
  5060. ret = -EINVAL;
  5061. goto err_release;
  5062. }
  5063. if (boot_size > IWL_MAX_BSM_SIZE) {
  5064. IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
  5065. boot_size);
  5066. ret = -EINVAL;
  5067. goto err_release;
  5068. }
  5069. /* Allocate ucode buffers for card's bus-master loading ... */
  5070. /* Runtime instructions and 2 copies of data:
  5071. * 1) unmodified from disk
  5072. * 2) backup cache for save/restore during power-downs */
  5073. priv->ucode_code.len = inst_size;
  5074. iwl3945_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  5075. priv->ucode_data.len = data_size;
  5076. iwl3945_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  5077. priv->ucode_data_backup.len = data_size;
  5078. iwl3945_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  5079. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  5080. !priv->ucode_data_backup.v_addr)
  5081. goto err_pci_alloc;
  5082. /* Initialization instructions and data */
  5083. if (init_size && init_data_size) {
  5084. priv->ucode_init.len = init_size;
  5085. iwl3945_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  5086. priv->ucode_init_data.len = init_data_size;
  5087. iwl3945_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  5088. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  5089. goto err_pci_alloc;
  5090. }
  5091. /* Bootstrap (instructions only, no data) */
  5092. if (boot_size) {
  5093. priv->ucode_boot.len = boot_size;
  5094. iwl3945_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  5095. if (!priv->ucode_boot.v_addr)
  5096. goto err_pci_alloc;
  5097. }
  5098. /* Copy images into buffers for card's bus-master reads ... */
  5099. /* Runtime instructions (first block of data in file) */
  5100. src = &ucode->data[0];
  5101. len = priv->ucode_code.len;
  5102. IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
  5103. memcpy(priv->ucode_code.v_addr, src, len);
  5104. IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  5105. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  5106. /* Runtime data (2nd block)
  5107. * NOTE: Copy into backup buffer will be done in iwl3945_up() */
  5108. src = &ucode->data[inst_size];
  5109. len = priv->ucode_data.len;
  5110. IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
  5111. memcpy(priv->ucode_data.v_addr, src, len);
  5112. memcpy(priv->ucode_data_backup.v_addr, src, len);
  5113. /* Initialization instructions (3rd block) */
  5114. if (init_size) {
  5115. src = &ucode->data[inst_size + data_size];
  5116. len = priv->ucode_init.len;
  5117. IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
  5118. len);
  5119. memcpy(priv->ucode_init.v_addr, src, len);
  5120. }
  5121. /* Initialization data (4th block) */
  5122. if (init_data_size) {
  5123. src = &ucode->data[inst_size + data_size + init_size];
  5124. len = priv->ucode_init_data.len;
  5125. IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
  5126. (int)len);
  5127. memcpy(priv->ucode_init_data.v_addr, src, len);
  5128. }
  5129. /* Bootstrap instructions (5th block) */
  5130. src = &ucode->data[inst_size + data_size + init_size + init_data_size];
  5131. len = priv->ucode_boot.len;
  5132. IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
  5133. (int)len);
  5134. memcpy(priv->ucode_boot.v_addr, src, len);
  5135. /* We have our copies now, allow OS release its copies */
  5136. release_firmware(ucode_raw);
  5137. return 0;
  5138. err_pci_alloc:
  5139. IWL_ERROR("failed to allocate pci memory\n");
  5140. ret = -ENOMEM;
  5141. iwl3945_dealloc_ucode_pci(priv);
  5142. err_release:
  5143. release_firmware(ucode_raw);
  5144. error:
  5145. return ret;
  5146. }
  5147. /**
  5148. * iwl3945_set_ucode_ptrs - Set uCode address location
  5149. *
  5150. * Tell initialization uCode where to find runtime uCode.
  5151. *
  5152. * BSM registers initially contain pointers to initialization uCode.
  5153. * We need to replace them to load runtime uCode inst and data,
  5154. * and to save runtime data when powering down.
  5155. */
  5156. static int iwl3945_set_ucode_ptrs(struct iwl3945_priv *priv)
  5157. {
  5158. dma_addr_t pinst;
  5159. dma_addr_t pdata;
  5160. int rc = 0;
  5161. unsigned long flags;
  5162. /* bits 31:0 for 3945 */
  5163. pinst = priv->ucode_code.p_addr;
  5164. pdata = priv->ucode_data_backup.p_addr;
  5165. spin_lock_irqsave(&priv->lock, flags);
  5166. rc = iwl3945_grab_nic_access(priv);
  5167. if (rc) {
  5168. spin_unlock_irqrestore(&priv->lock, flags);
  5169. return rc;
  5170. }
  5171. /* Tell bootstrap uCode where to find image to load */
  5172. iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  5173. iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  5174. iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
  5175. priv->ucode_data.len);
  5176. /* Inst bytecount must be last to set up, bit 31 signals uCode
  5177. * that all new ptr/size info is in place */
  5178. iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
  5179. priv->ucode_code.len | BSM_DRAM_INST_LOAD);
  5180. iwl3945_release_nic_access(priv);
  5181. spin_unlock_irqrestore(&priv->lock, flags);
  5182. IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
  5183. return rc;
  5184. }
  5185. /**
  5186. * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
  5187. *
  5188. * Called after REPLY_ALIVE notification received from "initialize" uCode.
  5189. *
  5190. * Tell "initialize" uCode to go ahead and load the runtime uCode.
  5191. */
  5192. static void iwl3945_init_alive_start(struct iwl3945_priv *priv)
  5193. {
  5194. /* Check alive response for "valid" sign from uCode */
  5195. if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
  5196. /* We had an error bringing up the hardware, so take it
  5197. * all the way back down so we can try again */
  5198. IWL_DEBUG_INFO("Initialize Alive failed.\n");
  5199. goto restart;
  5200. }
  5201. /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
  5202. * This is a paranoid check, because we would not have gotten the
  5203. * "initialize" alive if code weren't properly loaded. */
  5204. if (iwl3945_verify_ucode(priv)) {
  5205. /* Runtime instruction load was bad;
  5206. * take it all the way back down so we can try again */
  5207. IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
  5208. goto restart;
  5209. }
  5210. /* Send pointers to protocol/runtime uCode image ... init code will
  5211. * load and launch runtime uCode, which will send us another "Alive"
  5212. * notification. */
  5213. IWL_DEBUG_INFO("Initialization Alive received.\n");
  5214. if (iwl3945_set_ucode_ptrs(priv)) {
  5215. /* Runtime instruction load won't happen;
  5216. * take it all the way back down so we can try again */
  5217. IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
  5218. goto restart;
  5219. }
  5220. return;
  5221. restart:
  5222. queue_work(priv->workqueue, &priv->restart);
  5223. }
  5224. /**
  5225. * iwl3945_alive_start - called after REPLY_ALIVE notification received
  5226. * from protocol/runtime uCode (initialization uCode's
  5227. * Alive gets handled by iwl3945_init_alive_start()).
  5228. */
  5229. static void iwl3945_alive_start(struct iwl3945_priv *priv)
  5230. {
  5231. int rc = 0;
  5232. int thermal_spin = 0;
  5233. u32 rfkill;
  5234. IWL_DEBUG_INFO("Runtime Alive received.\n");
  5235. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  5236. /* We had an error bringing up the hardware, so take it
  5237. * all the way back down so we can try again */
  5238. IWL_DEBUG_INFO("Alive failed.\n");
  5239. goto restart;
  5240. }
  5241. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  5242. * This is a paranoid check, because we would not have gotten the
  5243. * "runtime" alive if code weren't properly loaded. */
  5244. if (iwl3945_verify_ucode(priv)) {
  5245. /* Runtime instruction load was bad;
  5246. * take it all the way back down so we can try again */
  5247. IWL_DEBUG_INFO("Bad runtime uCode load.\n");
  5248. goto restart;
  5249. }
  5250. iwl3945_clear_stations_table(priv);
  5251. rc = iwl3945_grab_nic_access(priv);
  5252. if (rc) {
  5253. IWL_WARNING("Can not read rfkill status from adapter\n");
  5254. return;
  5255. }
  5256. rfkill = iwl3945_read_prph(priv, APMG_RFKILL_REG);
  5257. IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
  5258. iwl3945_release_nic_access(priv);
  5259. if (rfkill & 0x1) {
  5260. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  5261. /* if rfkill is not on, then wait for thermal
  5262. * sensor in adapter to kick in */
  5263. while (iwl3945_hw_get_temperature(priv) == 0) {
  5264. thermal_spin++;
  5265. udelay(10);
  5266. }
  5267. if (thermal_spin)
  5268. IWL_DEBUG_INFO("Thermal calibration took %dus\n",
  5269. thermal_spin * 10);
  5270. } else
  5271. set_bit(STATUS_RF_KILL_HW, &priv->status);
  5272. /* After the ALIVE response, we can send commands to 3945 uCode */
  5273. set_bit(STATUS_ALIVE, &priv->status);
  5274. /* Clear out the uCode error bit if it is set */
  5275. clear_bit(STATUS_FW_ERROR, &priv->status);
  5276. rc = iwl3945_init_channel_map(priv);
  5277. if (rc) {
  5278. IWL_ERROR("initializing regulatory failed: %d\n", rc);
  5279. return;
  5280. }
  5281. iwl3945_init_geos(priv);
  5282. if (iwl3945_is_rfkill(priv))
  5283. return;
  5284. if (!priv->mac80211_registered) {
  5285. /* Unlock so any user space entry points can call back into
  5286. * the driver without a deadlock... */
  5287. mutex_unlock(&priv->mutex);
  5288. iwl3945_rate_control_register(priv->hw);
  5289. rc = ieee80211_register_hw(priv->hw);
  5290. priv->hw->conf.beacon_int = 100;
  5291. mutex_lock(&priv->mutex);
  5292. if (rc) {
  5293. iwl3945_rate_control_unregister(priv->hw);
  5294. IWL_ERROR("Failed to register network "
  5295. "device (error %d)\n", rc);
  5296. return;
  5297. }
  5298. priv->mac80211_registered = 1;
  5299. iwl3945_reset_channel_flag(priv);
  5300. } else
  5301. ieee80211_start_queues(priv->hw);
  5302. priv->active_rate = priv->rates_mask;
  5303. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  5304. iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
  5305. if (iwl3945_is_associated(priv)) {
  5306. struct iwl3945_rxon_cmd *active_rxon =
  5307. (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
  5308. memcpy(&priv->staging_rxon, &priv->active_rxon,
  5309. sizeof(priv->staging_rxon));
  5310. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5311. } else {
  5312. /* Initialize our rx_config data */
  5313. iwl3945_connection_init_rx_config(priv);
  5314. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  5315. }
  5316. /* Configure Bluetooth device coexistence support */
  5317. iwl3945_send_bt_config(priv);
  5318. /* Configure the adapter for unassociated operation */
  5319. iwl3945_commit_rxon(priv);
  5320. /* At this point, the NIC is initialized and operational */
  5321. priv->notif_missed_beacons = 0;
  5322. set_bit(STATUS_READY, &priv->status);
  5323. iwl3945_reg_txpower_periodic(priv);
  5324. IWL_DEBUG_INFO("ALIVE processing complete.\n");
  5325. if (priv->error_recovering)
  5326. iwl3945_error_recovery(priv);
  5327. return;
  5328. restart:
  5329. queue_work(priv->workqueue, &priv->restart);
  5330. }
  5331. static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv);
  5332. static void __iwl3945_down(struct iwl3945_priv *priv)
  5333. {
  5334. unsigned long flags;
  5335. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  5336. struct ieee80211_conf *conf = NULL;
  5337. IWL_DEBUG_INFO(DRV_NAME " is going down\n");
  5338. conf = ieee80211_get_hw_conf(priv->hw);
  5339. if (!exit_pending)
  5340. set_bit(STATUS_EXIT_PENDING, &priv->status);
  5341. iwl3945_clear_stations_table(priv);
  5342. /* Unblock any waiting calls */
  5343. wake_up_interruptible_all(&priv->wait_command_queue);
  5344. /* Wipe out the EXIT_PENDING status bit if we are not actually
  5345. * exiting the module */
  5346. if (!exit_pending)
  5347. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  5348. /* stop and reset the on-board processor */
  5349. iwl3945_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  5350. /* tell the device to stop sending interrupts */
  5351. iwl3945_disable_interrupts(priv);
  5352. if (priv->mac80211_registered)
  5353. ieee80211_stop_queues(priv->hw);
  5354. /* If we have not previously called iwl3945_init() then
  5355. * clear all bits but the RF Kill and SUSPEND bits and return */
  5356. if (!iwl3945_is_init(priv)) {
  5357. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  5358. STATUS_RF_KILL_HW |
  5359. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  5360. STATUS_RF_KILL_SW |
  5361. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  5362. STATUS_IN_SUSPEND;
  5363. goto exit;
  5364. }
  5365. /* ...otherwise clear out all the status bits but the RF Kill and
  5366. * SUSPEND bits and continue taking the NIC down. */
  5367. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  5368. STATUS_RF_KILL_HW |
  5369. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  5370. STATUS_RF_KILL_SW |
  5371. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  5372. STATUS_IN_SUSPEND |
  5373. test_bit(STATUS_FW_ERROR, &priv->status) <<
  5374. STATUS_FW_ERROR;
  5375. spin_lock_irqsave(&priv->lock, flags);
  5376. iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  5377. spin_unlock_irqrestore(&priv->lock, flags);
  5378. iwl3945_hw_txq_ctx_stop(priv);
  5379. iwl3945_hw_rxq_stop(priv);
  5380. spin_lock_irqsave(&priv->lock, flags);
  5381. if (!iwl3945_grab_nic_access(priv)) {
  5382. iwl3945_write_prph(priv, APMG_CLK_DIS_REG,
  5383. APMG_CLK_VAL_DMA_CLK_RQT);
  5384. iwl3945_release_nic_access(priv);
  5385. }
  5386. spin_unlock_irqrestore(&priv->lock, flags);
  5387. udelay(5);
  5388. iwl3945_hw_nic_stop_master(priv);
  5389. iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  5390. iwl3945_hw_nic_reset(priv);
  5391. exit:
  5392. memset(&priv->card_alive, 0, sizeof(struct iwl3945_alive_resp));
  5393. if (priv->ibss_beacon)
  5394. dev_kfree_skb(priv->ibss_beacon);
  5395. priv->ibss_beacon = NULL;
  5396. /* clear out any free frames */
  5397. iwl3945_clear_free_frames(priv);
  5398. }
  5399. static void iwl3945_down(struct iwl3945_priv *priv)
  5400. {
  5401. mutex_lock(&priv->mutex);
  5402. __iwl3945_down(priv);
  5403. mutex_unlock(&priv->mutex);
  5404. iwl3945_cancel_deferred_work(priv);
  5405. }
  5406. #define MAX_HW_RESTARTS 5
  5407. static int __iwl3945_up(struct iwl3945_priv *priv)
  5408. {
  5409. DECLARE_MAC_BUF(mac);
  5410. int rc, i;
  5411. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  5412. IWL_WARNING("Exit pending; will not bring the NIC up\n");
  5413. return -EIO;
  5414. }
  5415. if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
  5416. IWL_WARNING("Radio disabled by SW RF kill (module "
  5417. "parameter)\n");
  5418. return 0;
  5419. }
  5420. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  5421. IWL_ERROR("ucode not available for device bringup\n");
  5422. return -EIO;
  5423. }
  5424. iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
  5425. rc = iwl3945_hw_nic_init(priv);
  5426. if (rc) {
  5427. IWL_ERROR("Unable to int nic\n");
  5428. return rc;
  5429. }
  5430. /* make sure rfkill handshake bits are cleared */
  5431. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  5432. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  5433. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  5434. /* clear (again), then enable host interrupts */
  5435. iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
  5436. iwl3945_enable_interrupts(priv);
  5437. /* really make sure rfkill handshake bits are cleared */
  5438. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  5439. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  5440. /* Copy original ucode data image from disk into backup cache.
  5441. * This will be used to initialize the on-board processor's
  5442. * data SRAM for a clean start when the runtime program first loads. */
  5443. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  5444. priv->ucode_data.len);
  5445. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  5446. iwl3945_clear_stations_table(priv);
  5447. /* load bootstrap state machine,
  5448. * load bootstrap program into processor's memory,
  5449. * prepare to load the "initialize" uCode */
  5450. rc = iwl3945_load_bsm(priv);
  5451. if (rc) {
  5452. IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc);
  5453. continue;
  5454. }
  5455. /* start card; "initialize" will load runtime ucode */
  5456. iwl3945_nic_start(priv);
  5457. /* MAC Address location in EEPROM is same for 3945/4965 */
  5458. get_eeprom_mac(priv, priv->mac_addr);
  5459. IWL_DEBUG_INFO("MAC address: %s\n",
  5460. print_mac(mac, priv->mac_addr));
  5461. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  5462. IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
  5463. return 0;
  5464. }
  5465. set_bit(STATUS_EXIT_PENDING, &priv->status);
  5466. __iwl3945_down(priv);
  5467. /* tried to restart and config the device for as long as our
  5468. * patience could withstand */
  5469. IWL_ERROR("Unable to initialize device after %d attempts.\n", i);
  5470. return -EIO;
  5471. }
  5472. /*****************************************************************************
  5473. *
  5474. * Workqueue callbacks
  5475. *
  5476. *****************************************************************************/
  5477. static void iwl3945_bg_init_alive_start(struct work_struct *data)
  5478. {
  5479. struct iwl3945_priv *priv =
  5480. container_of(data, struct iwl3945_priv, init_alive_start.work);
  5481. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5482. return;
  5483. mutex_lock(&priv->mutex);
  5484. iwl3945_init_alive_start(priv);
  5485. mutex_unlock(&priv->mutex);
  5486. }
  5487. static void iwl3945_bg_alive_start(struct work_struct *data)
  5488. {
  5489. struct iwl3945_priv *priv =
  5490. container_of(data, struct iwl3945_priv, alive_start.work);
  5491. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5492. return;
  5493. mutex_lock(&priv->mutex);
  5494. iwl3945_alive_start(priv);
  5495. mutex_unlock(&priv->mutex);
  5496. }
  5497. static void iwl3945_bg_rf_kill(struct work_struct *work)
  5498. {
  5499. struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, rf_kill);
  5500. wake_up_interruptible(&priv->wait_command_queue);
  5501. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5502. return;
  5503. mutex_lock(&priv->mutex);
  5504. if (!iwl3945_is_rfkill(priv)) {
  5505. IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
  5506. "HW and/or SW RF Kill no longer active, restarting "
  5507. "device\n");
  5508. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  5509. queue_work(priv->workqueue, &priv->restart);
  5510. } else {
  5511. if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
  5512. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  5513. "disabled by SW switch\n");
  5514. else
  5515. IWL_WARNING("Radio Frequency Kill Switch is On:\n"
  5516. "Kill switch must be turned off for "
  5517. "wireless networking to work.\n");
  5518. }
  5519. mutex_unlock(&priv->mutex);
  5520. }
  5521. #define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
  5522. static void iwl3945_bg_scan_check(struct work_struct *data)
  5523. {
  5524. struct iwl3945_priv *priv =
  5525. container_of(data, struct iwl3945_priv, scan_check.work);
  5526. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5527. return;
  5528. mutex_lock(&priv->mutex);
  5529. if (test_bit(STATUS_SCANNING, &priv->status) ||
  5530. test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  5531. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
  5532. "Scan completion watchdog resetting adapter (%dms)\n",
  5533. jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
  5534. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  5535. iwl3945_send_scan_abort(priv);
  5536. }
  5537. mutex_unlock(&priv->mutex);
  5538. }
  5539. static void iwl3945_bg_request_scan(struct work_struct *data)
  5540. {
  5541. struct iwl3945_priv *priv =
  5542. container_of(data, struct iwl3945_priv, request_scan);
  5543. struct iwl3945_host_cmd cmd = {
  5544. .id = REPLY_SCAN_CMD,
  5545. .len = sizeof(struct iwl3945_scan_cmd),
  5546. .meta.flags = CMD_SIZE_HUGE,
  5547. };
  5548. int rc = 0;
  5549. struct iwl3945_scan_cmd *scan;
  5550. struct ieee80211_conf *conf = NULL;
  5551. u8 direct_mask;
  5552. int phymode;
  5553. conf = ieee80211_get_hw_conf(priv->hw);
  5554. mutex_lock(&priv->mutex);
  5555. if (!iwl3945_is_ready(priv)) {
  5556. IWL_WARNING("request scan called when driver not ready.\n");
  5557. goto done;
  5558. }
  5559. /* Make sure the scan wasn't cancelled before this queued work
  5560. * was given the chance to run... */
  5561. if (!test_bit(STATUS_SCANNING, &priv->status))
  5562. goto done;
  5563. /* This should never be called or scheduled if there is currently
  5564. * a scan active in the hardware. */
  5565. if (test_bit(STATUS_SCAN_HW, &priv->status)) {
  5566. IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
  5567. "Ignoring second request.\n");
  5568. rc = -EIO;
  5569. goto done;
  5570. }
  5571. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  5572. IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
  5573. goto done;
  5574. }
  5575. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  5576. IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
  5577. goto done;
  5578. }
  5579. if (iwl3945_is_rfkill(priv)) {
  5580. IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
  5581. goto done;
  5582. }
  5583. if (!test_bit(STATUS_READY, &priv->status)) {
  5584. IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
  5585. goto done;
  5586. }
  5587. if (!priv->scan_bands) {
  5588. IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
  5589. goto done;
  5590. }
  5591. if (!priv->scan) {
  5592. priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
  5593. IWL_MAX_SCAN_SIZE, GFP_KERNEL);
  5594. if (!priv->scan) {
  5595. rc = -ENOMEM;
  5596. goto done;
  5597. }
  5598. }
  5599. scan = priv->scan;
  5600. memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
  5601. scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
  5602. scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
  5603. if (iwl3945_is_associated(priv)) {
  5604. u16 interval = 0;
  5605. u32 extra;
  5606. u32 suspend_time = 100;
  5607. u32 scan_suspend_time = 100;
  5608. unsigned long flags;
  5609. IWL_DEBUG_INFO("Scanning while associated...\n");
  5610. spin_lock_irqsave(&priv->lock, flags);
  5611. interval = priv->beacon_int;
  5612. spin_unlock_irqrestore(&priv->lock, flags);
  5613. scan->suspend_time = 0;
  5614. scan->max_out_time = cpu_to_le32(200 * 1024);
  5615. if (!interval)
  5616. interval = suspend_time;
  5617. /*
  5618. * suspend time format:
  5619. * 0-19: beacon interval in usec (time before exec.)
  5620. * 20-23: 0
  5621. * 24-31: number of beacons (suspend between channels)
  5622. */
  5623. extra = (suspend_time / interval) << 24;
  5624. scan_suspend_time = 0xFF0FFFFF &
  5625. (extra | ((suspend_time % interval) * 1024));
  5626. scan->suspend_time = cpu_to_le32(scan_suspend_time);
  5627. IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
  5628. scan_suspend_time, interval);
  5629. }
  5630. /* We should add the ability for user to lock to PASSIVE ONLY */
  5631. if (priv->one_direct_scan) {
  5632. IWL_DEBUG_SCAN
  5633. ("Kicking off one direct scan for '%s'\n",
  5634. iwl3945_escape_essid(priv->direct_ssid,
  5635. priv->direct_ssid_len));
  5636. scan->direct_scan[0].id = WLAN_EID_SSID;
  5637. scan->direct_scan[0].len = priv->direct_ssid_len;
  5638. memcpy(scan->direct_scan[0].ssid,
  5639. priv->direct_ssid, priv->direct_ssid_len);
  5640. direct_mask = 1;
  5641. } else if (!iwl3945_is_associated(priv) && priv->essid_len) {
  5642. scan->direct_scan[0].id = WLAN_EID_SSID;
  5643. scan->direct_scan[0].len = priv->essid_len;
  5644. memcpy(scan->direct_scan[0].ssid, priv->essid, priv->essid_len);
  5645. direct_mask = 1;
  5646. } else
  5647. direct_mask = 0;
  5648. /* We don't build a direct scan probe request; the uCode will do
  5649. * that based on the direct_mask added to each channel entry */
  5650. scan->tx_cmd.len = cpu_to_le16(
  5651. iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
  5652. IWL_MAX_SCAN_SIZE - sizeof(scan), 0));
  5653. scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
  5654. scan->tx_cmd.sta_id = priv->hw_setting.bcast_sta_id;
  5655. scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  5656. /* flags + rate selection */
  5657. switch (priv->scan_bands) {
  5658. case 2:
  5659. scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
  5660. scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
  5661. scan->good_CRC_th = 0;
  5662. phymode = MODE_IEEE80211G;
  5663. break;
  5664. case 1:
  5665. scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
  5666. scan->good_CRC_th = IWL_GOOD_CRC_TH;
  5667. phymode = MODE_IEEE80211A;
  5668. break;
  5669. default:
  5670. IWL_WARNING("Invalid scan band count\n");
  5671. goto done;
  5672. }
  5673. /* select Rx antennas */
  5674. scan->flags |= iwl3945_get_antenna_flags(priv);
  5675. if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR)
  5676. scan->filter_flags = RXON_FILTER_PROMISC_MSK;
  5677. if (direct_mask)
  5678. IWL_DEBUG_SCAN
  5679. ("Initiating direct scan for %s.\n",
  5680. iwl3945_escape_essid(priv->essid, priv->essid_len));
  5681. else
  5682. IWL_DEBUG_SCAN("Initiating indirect scan.\n");
  5683. scan->channel_count =
  5684. iwl3945_get_channels_for_scan(
  5685. priv, phymode, 1, /* active */
  5686. direct_mask,
  5687. (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
  5688. cmd.len += le16_to_cpu(scan->tx_cmd.len) +
  5689. scan->channel_count * sizeof(struct iwl3945_scan_channel);
  5690. cmd.data = scan;
  5691. scan->len = cpu_to_le16(cmd.len);
  5692. set_bit(STATUS_SCAN_HW, &priv->status);
  5693. rc = iwl3945_send_cmd_sync(priv, &cmd);
  5694. if (rc)
  5695. goto done;
  5696. queue_delayed_work(priv->workqueue, &priv->scan_check,
  5697. IWL_SCAN_CHECK_WATCHDOG);
  5698. mutex_unlock(&priv->mutex);
  5699. return;
  5700. done:
  5701. /* inform mac80211 scan aborted */
  5702. queue_work(priv->workqueue, &priv->scan_completed);
  5703. mutex_unlock(&priv->mutex);
  5704. }
  5705. static void iwl3945_bg_up(struct work_struct *data)
  5706. {
  5707. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, up);
  5708. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5709. return;
  5710. mutex_lock(&priv->mutex);
  5711. __iwl3945_up(priv);
  5712. mutex_unlock(&priv->mutex);
  5713. }
  5714. static void iwl3945_bg_restart(struct work_struct *data)
  5715. {
  5716. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, restart);
  5717. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5718. return;
  5719. iwl3945_down(priv);
  5720. queue_work(priv->workqueue, &priv->up);
  5721. }
  5722. static void iwl3945_bg_rx_replenish(struct work_struct *data)
  5723. {
  5724. struct iwl3945_priv *priv =
  5725. container_of(data, struct iwl3945_priv, rx_replenish);
  5726. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5727. return;
  5728. mutex_lock(&priv->mutex);
  5729. iwl3945_rx_replenish(priv);
  5730. mutex_unlock(&priv->mutex);
  5731. }
  5732. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  5733. static void iwl3945_bg_post_associate(struct work_struct *data)
  5734. {
  5735. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv,
  5736. post_associate.work);
  5737. int rc = 0;
  5738. struct ieee80211_conf *conf = NULL;
  5739. DECLARE_MAC_BUF(mac);
  5740. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  5741. IWL_ERROR("%s Should not be called in AP mode\n", __FUNCTION__);
  5742. return;
  5743. }
  5744. IWL_DEBUG_ASSOC("Associated as %d to: %s\n",
  5745. priv->assoc_id,
  5746. print_mac(mac, priv->active_rxon.bssid_addr));
  5747. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5748. return;
  5749. mutex_lock(&priv->mutex);
  5750. if (!priv->interface_id || !priv->is_open) {
  5751. mutex_unlock(&priv->mutex);
  5752. return;
  5753. }
  5754. iwl3945_scan_cancel_timeout(priv, 200);
  5755. conf = ieee80211_get_hw_conf(priv->hw);
  5756. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5757. iwl3945_commit_rxon(priv);
  5758. memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
  5759. iwl3945_setup_rxon_timing(priv);
  5760. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5761. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5762. if (rc)
  5763. IWL_WARNING("REPLY_RXON_TIMING failed - "
  5764. "Attempting to continue.\n");
  5765. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  5766. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  5767. IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
  5768. priv->assoc_id, priv->beacon_int);
  5769. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  5770. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  5771. else
  5772. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5773. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  5774. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  5775. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  5776. else
  5777. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  5778. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
  5779. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  5780. }
  5781. iwl3945_commit_rxon(priv);
  5782. switch (priv->iw_mode) {
  5783. case IEEE80211_IF_TYPE_STA:
  5784. iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
  5785. break;
  5786. case IEEE80211_IF_TYPE_IBSS:
  5787. /* clear out the station table */
  5788. iwl3945_clear_stations_table(priv);
  5789. iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
  5790. iwl3945_add_station(priv, priv->bssid, 0, 0);
  5791. iwl3945_sync_sta(priv, IWL_STA_ID,
  5792. (priv->phymode == MODE_IEEE80211A)?
  5793. IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
  5794. CMD_ASYNC);
  5795. iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
  5796. iwl3945_send_beacon_cmd(priv);
  5797. break;
  5798. default:
  5799. IWL_ERROR("%s Should not be called in %d mode\n",
  5800. __FUNCTION__, priv->iw_mode);
  5801. break;
  5802. }
  5803. iwl3945_sequence_reset(priv);
  5804. #ifdef CONFIG_IWL3945_QOS
  5805. iwl3945_activate_qos(priv, 0);
  5806. #endif /* CONFIG_IWL3945_QOS */
  5807. /* we have just associated, don't start scan too early */
  5808. priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
  5809. mutex_unlock(&priv->mutex);
  5810. }
  5811. static void iwl3945_bg_abort_scan(struct work_struct *work)
  5812. {
  5813. struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, abort_scan);
  5814. if (!iwl3945_is_ready(priv))
  5815. return;
  5816. mutex_lock(&priv->mutex);
  5817. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  5818. iwl3945_send_scan_abort(priv);
  5819. mutex_unlock(&priv->mutex);
  5820. }
  5821. static void iwl3945_bg_scan_completed(struct work_struct *work)
  5822. {
  5823. struct iwl3945_priv *priv =
  5824. container_of(work, struct iwl3945_priv, scan_completed);
  5825. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
  5826. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5827. return;
  5828. ieee80211_scan_completed(priv->hw);
  5829. /* Since setting the TXPOWER may have been deferred while
  5830. * performing the scan, fire one off */
  5831. mutex_lock(&priv->mutex);
  5832. iwl3945_hw_reg_send_txpower(priv);
  5833. mutex_unlock(&priv->mutex);
  5834. }
  5835. /*****************************************************************************
  5836. *
  5837. * mac80211 entry point functions
  5838. *
  5839. *****************************************************************************/
  5840. static int iwl3945_mac_start(struct ieee80211_hw *hw)
  5841. {
  5842. struct iwl3945_priv *priv = hw->priv;
  5843. IWL_DEBUG_MAC80211("enter\n");
  5844. /* we should be verifying the device is ready to be opened */
  5845. mutex_lock(&priv->mutex);
  5846. priv->is_open = 1;
  5847. if (!iwl3945_is_rfkill(priv))
  5848. ieee80211_start_queues(priv->hw);
  5849. mutex_unlock(&priv->mutex);
  5850. IWL_DEBUG_MAC80211("leave\n");
  5851. return 0;
  5852. }
  5853. static void iwl3945_mac_stop(struct ieee80211_hw *hw)
  5854. {
  5855. struct iwl3945_priv *priv = hw->priv;
  5856. IWL_DEBUG_MAC80211("enter\n");
  5857. mutex_lock(&priv->mutex);
  5858. /* stop mac, cancel any scan request and clear
  5859. * RXON_FILTER_ASSOC_MSK BIT
  5860. */
  5861. priv->is_open = 0;
  5862. iwl3945_scan_cancel_timeout(priv, 100);
  5863. cancel_delayed_work(&priv->post_associate);
  5864. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5865. iwl3945_commit_rxon(priv);
  5866. mutex_unlock(&priv->mutex);
  5867. IWL_DEBUG_MAC80211("leave\n");
  5868. }
  5869. static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
  5870. struct ieee80211_tx_control *ctl)
  5871. {
  5872. struct iwl3945_priv *priv = hw->priv;
  5873. IWL_DEBUG_MAC80211("enter\n");
  5874. if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
  5875. IWL_DEBUG_MAC80211("leave - monitor\n");
  5876. return -1;
  5877. }
  5878. IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  5879. ctl->tx_rate);
  5880. if (iwl3945_tx_skb(priv, skb, ctl))
  5881. dev_kfree_skb_any(skb);
  5882. IWL_DEBUG_MAC80211("leave\n");
  5883. return 0;
  5884. }
  5885. static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
  5886. struct ieee80211_if_init_conf *conf)
  5887. {
  5888. struct iwl3945_priv *priv = hw->priv;
  5889. unsigned long flags;
  5890. DECLARE_MAC_BUF(mac);
  5891. IWL_DEBUG_MAC80211("enter: id %d, type %d\n", conf->if_id, conf->type);
  5892. if (priv->interface_id) {
  5893. IWL_DEBUG_MAC80211("leave - interface_id != 0\n");
  5894. return -EOPNOTSUPP;
  5895. }
  5896. spin_lock_irqsave(&priv->lock, flags);
  5897. priv->interface_id = conf->if_id;
  5898. spin_unlock_irqrestore(&priv->lock, flags);
  5899. mutex_lock(&priv->mutex);
  5900. if (conf->mac_addr) {
  5901. IWL_DEBUG_MAC80211("Set: %s\n", print_mac(mac, conf->mac_addr));
  5902. memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
  5903. }
  5904. iwl3945_set_mode(priv, conf->type);
  5905. IWL_DEBUG_MAC80211("leave\n");
  5906. mutex_unlock(&priv->mutex);
  5907. return 0;
  5908. }
  5909. /**
  5910. * iwl3945_mac_config - mac80211 config callback
  5911. *
  5912. * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
  5913. * be set inappropriately and the driver currently sets the hardware up to
  5914. * use it whenever needed.
  5915. */
  5916. static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
  5917. {
  5918. struct iwl3945_priv *priv = hw->priv;
  5919. const struct iwl3945_channel_info *ch_info;
  5920. unsigned long flags;
  5921. mutex_lock(&priv->mutex);
  5922. IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel);
  5923. if (!iwl3945_is_ready(priv)) {
  5924. IWL_DEBUG_MAC80211("leave - not ready\n");
  5925. mutex_unlock(&priv->mutex);
  5926. return -EIO;
  5927. }
  5928. /* TODO: Figure out how to get ieee80211_local->sta_scanning w/ only
  5929. * what is exposed through include/ declarations */
  5930. if (unlikely(!iwl3945_param_disable_hw_scan &&
  5931. test_bit(STATUS_SCANNING, &priv->status))) {
  5932. IWL_DEBUG_MAC80211("leave - scanning\n");
  5933. mutex_unlock(&priv->mutex);
  5934. return 0;
  5935. }
  5936. spin_lock_irqsave(&priv->lock, flags);
  5937. ch_info = iwl3945_get_channel_info(priv, conf->phymode, conf->channel);
  5938. if (!is_channel_valid(ch_info)) {
  5939. IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this SKU.\n",
  5940. conf->channel, conf->phymode);
  5941. IWL_DEBUG_MAC80211("leave - invalid channel\n");
  5942. spin_unlock_irqrestore(&priv->lock, flags);
  5943. mutex_unlock(&priv->mutex);
  5944. return -EINVAL;
  5945. }
  5946. iwl3945_set_rxon_channel(priv, conf->phymode, conf->channel);
  5947. iwl3945_set_flags_for_phymode(priv, conf->phymode);
  5948. /* The list of supported rates and rate mask can be different
  5949. * for each phymode; since the phymode may have changed, reset
  5950. * the rate mask to what mac80211 lists */
  5951. iwl3945_set_rate(priv);
  5952. spin_unlock_irqrestore(&priv->lock, flags);
  5953. #ifdef IEEE80211_CONF_CHANNEL_SWITCH
  5954. if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
  5955. iwl3945_hw_channel_switch(priv, conf->channel);
  5956. mutex_unlock(&priv->mutex);
  5957. return 0;
  5958. }
  5959. #endif
  5960. iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
  5961. if (!conf->radio_enabled) {
  5962. IWL_DEBUG_MAC80211("leave - radio disabled\n");
  5963. mutex_unlock(&priv->mutex);
  5964. return 0;
  5965. }
  5966. if (iwl3945_is_rfkill(priv)) {
  5967. IWL_DEBUG_MAC80211("leave - RF kill\n");
  5968. mutex_unlock(&priv->mutex);
  5969. return -EIO;
  5970. }
  5971. iwl3945_set_rate(priv);
  5972. if (memcmp(&priv->active_rxon,
  5973. &priv->staging_rxon, sizeof(priv->staging_rxon)))
  5974. iwl3945_commit_rxon(priv);
  5975. else
  5976. IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
  5977. IWL_DEBUG_MAC80211("leave\n");
  5978. mutex_unlock(&priv->mutex);
  5979. return 0;
  5980. }
  5981. static void iwl3945_config_ap(struct iwl3945_priv *priv)
  5982. {
  5983. int rc = 0;
  5984. if (priv->status & STATUS_EXIT_PENDING)
  5985. return;
  5986. /* The following should be done only at AP bring up */
  5987. if ((priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) == 0) {
  5988. /* RXON - unassoc (to set timing command) */
  5989. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5990. iwl3945_commit_rxon(priv);
  5991. /* RXON Timing */
  5992. memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
  5993. iwl3945_setup_rxon_timing(priv);
  5994. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5995. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5996. if (rc)
  5997. IWL_WARNING("REPLY_RXON_TIMING failed - "
  5998. "Attempting to continue.\n");
  5999. /* FIXME: what should be the assoc_id for AP? */
  6000. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  6001. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  6002. priv->staging_rxon.flags |=
  6003. RXON_FLG_SHORT_PREAMBLE_MSK;
  6004. else
  6005. priv->staging_rxon.flags &=
  6006. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  6007. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  6008. if (priv->assoc_capability &
  6009. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  6010. priv->staging_rxon.flags |=
  6011. RXON_FLG_SHORT_SLOT_MSK;
  6012. else
  6013. priv->staging_rxon.flags &=
  6014. ~RXON_FLG_SHORT_SLOT_MSK;
  6015. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
  6016. priv->staging_rxon.flags &=
  6017. ~RXON_FLG_SHORT_SLOT_MSK;
  6018. }
  6019. /* restore RXON assoc */
  6020. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  6021. iwl3945_commit_rxon(priv);
  6022. iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
  6023. }
  6024. iwl3945_send_beacon_cmd(priv);
  6025. /* FIXME - we need to add code here to detect a totally new
  6026. * configuration, reset the AP, unassoc, rxon timing, assoc,
  6027. * clear sta table, add BCAST sta... */
  6028. }
  6029. static int iwl3945_mac_config_interface(struct ieee80211_hw *hw, int if_id,
  6030. struct ieee80211_if_conf *conf)
  6031. {
  6032. struct iwl3945_priv *priv = hw->priv;
  6033. DECLARE_MAC_BUF(mac);
  6034. unsigned long flags;
  6035. int rc;
  6036. if (conf == NULL)
  6037. return -EIO;
  6038. /* XXX: this MUST use conf->mac_addr */
  6039. if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
  6040. (!conf->beacon || !conf->ssid_len)) {
  6041. IWL_DEBUG_MAC80211
  6042. ("Leaving in AP mode because HostAPD is not ready.\n");
  6043. return 0;
  6044. }
  6045. mutex_lock(&priv->mutex);
  6046. IWL_DEBUG_MAC80211("enter: interface id %d\n", if_id);
  6047. if (conf->bssid)
  6048. IWL_DEBUG_MAC80211("bssid: %s\n",
  6049. print_mac(mac, conf->bssid));
  6050. /*
  6051. * very dubious code was here; the probe filtering flag is never set:
  6052. *
  6053. if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
  6054. !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
  6055. */
  6056. if (unlikely(test_bit(STATUS_SCANNING, &priv->status))) {
  6057. IWL_DEBUG_MAC80211("leave - scanning\n");
  6058. mutex_unlock(&priv->mutex);
  6059. return 0;
  6060. }
  6061. if (priv->interface_id != if_id) {
  6062. IWL_DEBUG_MAC80211("leave - interface_id != if_id\n");
  6063. mutex_unlock(&priv->mutex);
  6064. return 0;
  6065. }
  6066. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  6067. if (!conf->bssid) {
  6068. conf->bssid = priv->mac_addr;
  6069. memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
  6070. IWL_DEBUG_MAC80211("bssid was set to: %s\n",
  6071. print_mac(mac, conf->bssid));
  6072. }
  6073. if (priv->ibss_beacon)
  6074. dev_kfree_skb(priv->ibss_beacon);
  6075. priv->ibss_beacon = conf->beacon;
  6076. }
  6077. if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
  6078. !is_multicast_ether_addr(conf->bssid)) {
  6079. /* If there is currently a HW scan going on in the background
  6080. * then we need to cancel it else the RXON below will fail. */
  6081. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  6082. IWL_WARNING("Aborted scan still in progress "
  6083. "after 100ms\n");
  6084. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  6085. mutex_unlock(&priv->mutex);
  6086. return -EAGAIN;
  6087. }
  6088. memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN);
  6089. /* TODO: Audit driver for usage of these members and see
  6090. * if mac80211 deprecates them (priv->bssid looks like it
  6091. * shouldn't be there, but I haven't scanned the IBSS code
  6092. * to verify) - jpk */
  6093. memcpy(priv->bssid, conf->bssid, ETH_ALEN);
  6094. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  6095. iwl3945_config_ap(priv);
  6096. else {
  6097. rc = iwl3945_commit_rxon(priv);
  6098. if ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && rc)
  6099. iwl3945_add_station(priv,
  6100. priv->active_rxon.bssid_addr, 1, 0);
  6101. }
  6102. } else {
  6103. iwl3945_scan_cancel_timeout(priv, 100);
  6104. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  6105. iwl3945_commit_rxon(priv);
  6106. }
  6107. spin_lock_irqsave(&priv->lock, flags);
  6108. if (!conf->ssid_len)
  6109. memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
  6110. else
  6111. memcpy(priv->essid, conf->ssid, conf->ssid_len);
  6112. priv->essid_len = conf->ssid_len;
  6113. spin_unlock_irqrestore(&priv->lock, flags);
  6114. IWL_DEBUG_MAC80211("leave\n");
  6115. mutex_unlock(&priv->mutex);
  6116. return 0;
  6117. }
  6118. static void iwl3945_configure_filter(struct ieee80211_hw *hw,
  6119. unsigned int changed_flags,
  6120. unsigned int *total_flags,
  6121. int mc_count, struct dev_addr_list *mc_list)
  6122. {
  6123. /*
  6124. * XXX: dummy
  6125. * see also iwl3945_connection_init_rx_config
  6126. */
  6127. *total_flags = 0;
  6128. }
  6129. static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
  6130. struct ieee80211_if_init_conf *conf)
  6131. {
  6132. struct iwl3945_priv *priv = hw->priv;
  6133. IWL_DEBUG_MAC80211("enter\n");
  6134. mutex_lock(&priv->mutex);
  6135. iwl3945_scan_cancel_timeout(priv, 100);
  6136. cancel_delayed_work(&priv->post_associate);
  6137. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  6138. iwl3945_commit_rxon(priv);
  6139. if (priv->interface_id == conf->if_id) {
  6140. priv->interface_id = 0;
  6141. memset(priv->bssid, 0, ETH_ALEN);
  6142. memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
  6143. priv->essid_len = 0;
  6144. }
  6145. mutex_unlock(&priv->mutex);
  6146. IWL_DEBUG_MAC80211("leave\n");
  6147. }
  6148. static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
  6149. {
  6150. int rc = 0;
  6151. unsigned long flags;
  6152. struct iwl3945_priv *priv = hw->priv;
  6153. IWL_DEBUG_MAC80211("enter\n");
  6154. mutex_lock(&priv->mutex);
  6155. spin_lock_irqsave(&priv->lock, flags);
  6156. if (!iwl3945_is_ready_rf(priv)) {
  6157. rc = -EIO;
  6158. IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
  6159. goto out_unlock;
  6160. }
  6161. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { /* APs don't scan */
  6162. rc = -EIO;
  6163. IWL_ERROR("ERROR: APs don't scan\n");
  6164. goto out_unlock;
  6165. }
  6166. /* we don't schedule scan within next_scan_jiffies period */
  6167. if (priv->next_scan_jiffies &&
  6168. time_after(priv->next_scan_jiffies, jiffies)) {
  6169. rc = -EAGAIN;
  6170. goto out_unlock;
  6171. }
  6172. /* if we just finished scan ask for delay */
  6173. if (priv->last_scan_jiffies && time_after(priv->last_scan_jiffies +
  6174. IWL_DELAY_NEXT_SCAN, jiffies)) {
  6175. rc = -EAGAIN;
  6176. goto out_unlock;
  6177. }
  6178. if (len) {
  6179. IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
  6180. iwl3945_escape_essid(ssid, len), (int)len);
  6181. priv->one_direct_scan = 1;
  6182. priv->direct_ssid_len = (u8)
  6183. min((u8) len, (u8) IW_ESSID_MAX_SIZE);
  6184. memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
  6185. } else
  6186. priv->one_direct_scan = 0;
  6187. rc = iwl3945_scan_initiate(priv);
  6188. IWL_DEBUG_MAC80211("leave\n");
  6189. out_unlock:
  6190. spin_unlock_irqrestore(&priv->lock, flags);
  6191. mutex_unlock(&priv->mutex);
  6192. return rc;
  6193. }
  6194. static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  6195. const u8 *local_addr, const u8 *addr,
  6196. struct ieee80211_key_conf *key)
  6197. {
  6198. struct iwl3945_priv *priv = hw->priv;
  6199. int rc = 0;
  6200. u8 sta_id;
  6201. IWL_DEBUG_MAC80211("enter\n");
  6202. if (!iwl3945_param_hwcrypto) {
  6203. IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
  6204. return -EOPNOTSUPP;
  6205. }
  6206. if (is_zero_ether_addr(addr))
  6207. /* only support pairwise keys */
  6208. return -EOPNOTSUPP;
  6209. sta_id = iwl3945_hw_find_station(priv, addr);
  6210. if (sta_id == IWL_INVALID_STATION) {
  6211. DECLARE_MAC_BUF(mac);
  6212. IWL_DEBUG_MAC80211("leave - %s not in station map.\n",
  6213. print_mac(mac, addr));
  6214. return -EINVAL;
  6215. }
  6216. mutex_lock(&priv->mutex);
  6217. iwl3945_scan_cancel_timeout(priv, 100);
  6218. switch (cmd) {
  6219. case SET_KEY:
  6220. rc = iwl3945_update_sta_key_info(priv, key, sta_id);
  6221. if (!rc) {
  6222. iwl3945_set_rxon_hwcrypto(priv, 1);
  6223. iwl3945_commit_rxon(priv);
  6224. key->hw_key_idx = sta_id;
  6225. IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
  6226. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  6227. }
  6228. break;
  6229. case DISABLE_KEY:
  6230. rc = iwl3945_clear_sta_key_info(priv, sta_id);
  6231. if (!rc) {
  6232. iwl3945_set_rxon_hwcrypto(priv, 0);
  6233. iwl3945_commit_rxon(priv);
  6234. IWL_DEBUG_MAC80211("disable hwcrypto key\n");
  6235. }
  6236. break;
  6237. default:
  6238. rc = -EINVAL;
  6239. }
  6240. IWL_DEBUG_MAC80211("leave\n");
  6241. mutex_unlock(&priv->mutex);
  6242. return rc;
  6243. }
  6244. static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, int queue,
  6245. const struct ieee80211_tx_queue_params *params)
  6246. {
  6247. struct iwl3945_priv *priv = hw->priv;
  6248. #ifdef CONFIG_IWL3945_QOS
  6249. unsigned long flags;
  6250. int q;
  6251. #endif /* CONFIG_IWL3945_QOS */
  6252. IWL_DEBUG_MAC80211("enter\n");
  6253. if (!iwl3945_is_ready_rf(priv)) {
  6254. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  6255. return -EIO;
  6256. }
  6257. if (queue >= AC_NUM) {
  6258. IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
  6259. return 0;
  6260. }
  6261. #ifdef CONFIG_IWL3945_QOS
  6262. if (!priv->qos_data.qos_enable) {
  6263. priv->qos_data.qos_active = 0;
  6264. IWL_DEBUG_MAC80211("leave - qos not enabled\n");
  6265. return 0;
  6266. }
  6267. q = AC_NUM - 1 - queue;
  6268. spin_lock_irqsave(&priv->lock, flags);
  6269. priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
  6270. priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
  6271. priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
  6272. priv->qos_data.def_qos_parm.ac[q].edca_txop =
  6273. cpu_to_le16((params->burst_time * 100));
  6274. priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
  6275. priv->qos_data.qos_active = 1;
  6276. spin_unlock_irqrestore(&priv->lock, flags);
  6277. mutex_lock(&priv->mutex);
  6278. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  6279. iwl3945_activate_qos(priv, 1);
  6280. else if (priv->assoc_id && iwl3945_is_associated(priv))
  6281. iwl3945_activate_qos(priv, 0);
  6282. mutex_unlock(&priv->mutex);
  6283. #endif /*CONFIG_IWL3945_QOS */
  6284. IWL_DEBUG_MAC80211("leave\n");
  6285. return 0;
  6286. }
  6287. static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
  6288. struct ieee80211_tx_queue_stats *stats)
  6289. {
  6290. struct iwl3945_priv *priv = hw->priv;
  6291. int i, avail;
  6292. struct iwl3945_tx_queue *txq;
  6293. struct iwl3945_queue *q;
  6294. unsigned long flags;
  6295. IWL_DEBUG_MAC80211("enter\n");
  6296. if (!iwl3945_is_ready_rf(priv)) {
  6297. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  6298. return -EIO;
  6299. }
  6300. spin_lock_irqsave(&priv->lock, flags);
  6301. for (i = 0; i < AC_NUM; i++) {
  6302. txq = &priv->txq[i];
  6303. q = &txq->q;
  6304. avail = iwl3945_queue_space(q);
  6305. stats->data[i].len = q->n_window - avail;
  6306. stats->data[i].limit = q->n_window - q->high_mark;
  6307. stats->data[i].count = q->n_window;
  6308. }
  6309. spin_unlock_irqrestore(&priv->lock, flags);
  6310. IWL_DEBUG_MAC80211("leave\n");
  6311. return 0;
  6312. }
  6313. static int iwl3945_mac_get_stats(struct ieee80211_hw *hw,
  6314. struct ieee80211_low_level_stats *stats)
  6315. {
  6316. IWL_DEBUG_MAC80211("enter\n");
  6317. IWL_DEBUG_MAC80211("leave\n");
  6318. return 0;
  6319. }
  6320. static u64 iwl3945_mac_get_tsf(struct ieee80211_hw *hw)
  6321. {
  6322. IWL_DEBUG_MAC80211("enter\n");
  6323. IWL_DEBUG_MAC80211("leave\n");
  6324. return 0;
  6325. }
  6326. static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
  6327. {
  6328. struct iwl3945_priv *priv = hw->priv;
  6329. unsigned long flags;
  6330. mutex_lock(&priv->mutex);
  6331. IWL_DEBUG_MAC80211("enter\n");
  6332. #ifdef CONFIG_IWL3945_QOS
  6333. iwl3945_reset_qos(priv);
  6334. #endif
  6335. cancel_delayed_work(&priv->post_associate);
  6336. spin_lock_irqsave(&priv->lock, flags);
  6337. priv->assoc_id = 0;
  6338. priv->assoc_capability = 0;
  6339. priv->call_post_assoc_from_beacon = 0;
  6340. /* new association get rid of ibss beacon skb */
  6341. if (priv->ibss_beacon)
  6342. dev_kfree_skb(priv->ibss_beacon);
  6343. priv->ibss_beacon = NULL;
  6344. priv->beacon_int = priv->hw->conf.beacon_int;
  6345. priv->timestamp1 = 0;
  6346. priv->timestamp0 = 0;
  6347. if ((priv->iw_mode == IEEE80211_IF_TYPE_STA))
  6348. priv->beacon_int = 0;
  6349. spin_unlock_irqrestore(&priv->lock, flags);
  6350. /* we are restarting association process
  6351. * clear RXON_FILTER_ASSOC_MSK bit
  6352. */
  6353. if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
  6354. iwl3945_scan_cancel_timeout(priv, 100);
  6355. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  6356. iwl3945_commit_rxon(priv);
  6357. }
  6358. /* Per mac80211.h: This is only used in IBSS mode... */
  6359. if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
  6360. IWL_DEBUG_MAC80211("leave - not in IBSS\n");
  6361. mutex_unlock(&priv->mutex);
  6362. return;
  6363. }
  6364. if (!iwl3945_is_ready_rf(priv)) {
  6365. IWL_DEBUG_MAC80211("leave - not ready\n");
  6366. mutex_unlock(&priv->mutex);
  6367. return;
  6368. }
  6369. priv->only_active_channel = 0;
  6370. iwl3945_set_rate(priv);
  6371. mutex_unlock(&priv->mutex);
  6372. IWL_DEBUG_MAC80211("leave\n");
  6373. }
  6374. static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
  6375. struct ieee80211_tx_control *control)
  6376. {
  6377. struct iwl3945_priv *priv = hw->priv;
  6378. unsigned long flags;
  6379. mutex_lock(&priv->mutex);
  6380. IWL_DEBUG_MAC80211("enter\n");
  6381. if (!iwl3945_is_ready_rf(priv)) {
  6382. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  6383. mutex_unlock(&priv->mutex);
  6384. return -EIO;
  6385. }
  6386. if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
  6387. IWL_DEBUG_MAC80211("leave - not IBSS\n");
  6388. mutex_unlock(&priv->mutex);
  6389. return -EIO;
  6390. }
  6391. spin_lock_irqsave(&priv->lock, flags);
  6392. if (priv->ibss_beacon)
  6393. dev_kfree_skb(priv->ibss_beacon);
  6394. priv->ibss_beacon = skb;
  6395. priv->assoc_id = 0;
  6396. IWL_DEBUG_MAC80211("leave\n");
  6397. spin_unlock_irqrestore(&priv->lock, flags);
  6398. #ifdef CONFIG_IWL3945_QOS
  6399. iwl3945_reset_qos(priv);
  6400. #endif
  6401. queue_work(priv->workqueue, &priv->post_associate.work);
  6402. mutex_unlock(&priv->mutex);
  6403. return 0;
  6404. }
  6405. /*****************************************************************************
  6406. *
  6407. * sysfs attributes
  6408. *
  6409. *****************************************************************************/
  6410. #ifdef CONFIG_IWL3945_DEBUG
  6411. /*
  6412. * The following adds a new attribute to the sysfs representation
  6413. * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
  6414. * used for controlling the debug level.
  6415. *
  6416. * See the level definitions in iwl for details.
  6417. */
  6418. static ssize_t show_debug_level(struct device_driver *d, char *buf)
  6419. {
  6420. return sprintf(buf, "0x%08X\n", iwl3945_debug_level);
  6421. }
  6422. static ssize_t store_debug_level(struct device_driver *d,
  6423. const char *buf, size_t count)
  6424. {
  6425. char *p = (char *)buf;
  6426. u32 val;
  6427. val = simple_strtoul(p, &p, 0);
  6428. if (p == buf)
  6429. printk(KERN_INFO DRV_NAME
  6430. ": %s is not in hex or decimal form.\n", buf);
  6431. else
  6432. iwl3945_debug_level = val;
  6433. return strnlen(buf, count);
  6434. }
  6435. static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO,
  6436. show_debug_level, store_debug_level);
  6437. #endif /* CONFIG_IWL3945_DEBUG */
  6438. static ssize_t show_rf_kill(struct device *d,
  6439. struct device_attribute *attr, char *buf)
  6440. {
  6441. /*
  6442. * 0 - RF kill not enabled
  6443. * 1 - SW based RF kill active (sysfs)
  6444. * 2 - HW based RF kill active
  6445. * 3 - Both HW and SW based RF kill active
  6446. */
  6447. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6448. int val = (test_bit(STATUS_RF_KILL_SW, &priv->status) ? 0x1 : 0x0) |
  6449. (test_bit(STATUS_RF_KILL_HW, &priv->status) ? 0x2 : 0x0);
  6450. return sprintf(buf, "%i\n", val);
  6451. }
  6452. static ssize_t store_rf_kill(struct device *d,
  6453. struct device_attribute *attr,
  6454. const char *buf, size_t count)
  6455. {
  6456. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6457. mutex_lock(&priv->mutex);
  6458. iwl3945_radio_kill_sw(priv, buf[0] == '1');
  6459. mutex_unlock(&priv->mutex);
  6460. return count;
  6461. }
  6462. static DEVICE_ATTR(rf_kill, S_IWUSR | S_IRUGO, show_rf_kill, store_rf_kill);
  6463. static ssize_t show_temperature(struct device *d,
  6464. struct device_attribute *attr, char *buf)
  6465. {
  6466. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6467. if (!iwl3945_is_alive(priv))
  6468. return -EAGAIN;
  6469. return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
  6470. }
  6471. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  6472. static ssize_t show_rs_window(struct device *d,
  6473. struct device_attribute *attr,
  6474. char *buf)
  6475. {
  6476. struct iwl3945_priv *priv = d->driver_data;
  6477. return iwl3945_fill_rs_info(priv->hw, buf, IWL_AP_ID);
  6478. }
  6479. static DEVICE_ATTR(rs_window, S_IRUGO, show_rs_window, NULL);
  6480. static ssize_t show_tx_power(struct device *d,
  6481. struct device_attribute *attr, char *buf)
  6482. {
  6483. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6484. return sprintf(buf, "%d\n", priv->user_txpower_limit);
  6485. }
  6486. static ssize_t store_tx_power(struct device *d,
  6487. struct device_attribute *attr,
  6488. const char *buf, size_t count)
  6489. {
  6490. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6491. char *p = (char *)buf;
  6492. u32 val;
  6493. val = simple_strtoul(p, &p, 10);
  6494. if (p == buf)
  6495. printk(KERN_INFO DRV_NAME
  6496. ": %s is not in decimal form.\n", buf);
  6497. else
  6498. iwl3945_hw_reg_set_txpower(priv, val);
  6499. return count;
  6500. }
  6501. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  6502. static ssize_t show_flags(struct device *d,
  6503. struct device_attribute *attr, char *buf)
  6504. {
  6505. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6506. return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
  6507. }
  6508. static ssize_t store_flags(struct device *d,
  6509. struct device_attribute *attr,
  6510. const char *buf, size_t count)
  6511. {
  6512. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6513. u32 flags = simple_strtoul(buf, NULL, 0);
  6514. mutex_lock(&priv->mutex);
  6515. if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
  6516. /* Cancel any currently running scans... */
  6517. if (iwl3945_scan_cancel_timeout(priv, 100))
  6518. IWL_WARNING("Could not cancel scan.\n");
  6519. else {
  6520. IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
  6521. flags);
  6522. priv->staging_rxon.flags = cpu_to_le32(flags);
  6523. iwl3945_commit_rxon(priv);
  6524. }
  6525. }
  6526. mutex_unlock(&priv->mutex);
  6527. return count;
  6528. }
  6529. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  6530. static ssize_t show_filter_flags(struct device *d,
  6531. struct device_attribute *attr, char *buf)
  6532. {
  6533. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6534. return sprintf(buf, "0x%04X\n",
  6535. le32_to_cpu(priv->active_rxon.filter_flags));
  6536. }
  6537. static ssize_t store_filter_flags(struct device *d,
  6538. struct device_attribute *attr,
  6539. const char *buf, size_t count)
  6540. {
  6541. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6542. u32 filter_flags = simple_strtoul(buf, NULL, 0);
  6543. mutex_lock(&priv->mutex);
  6544. if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
  6545. /* Cancel any currently running scans... */
  6546. if (iwl3945_scan_cancel_timeout(priv, 100))
  6547. IWL_WARNING("Could not cancel scan.\n");
  6548. else {
  6549. IWL_DEBUG_INFO("Committing rxon.filter_flags = "
  6550. "0x%04X\n", filter_flags);
  6551. priv->staging_rxon.filter_flags =
  6552. cpu_to_le32(filter_flags);
  6553. iwl3945_commit_rxon(priv);
  6554. }
  6555. }
  6556. mutex_unlock(&priv->mutex);
  6557. return count;
  6558. }
  6559. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  6560. store_filter_flags);
  6561. static ssize_t show_tune(struct device *d,
  6562. struct device_attribute *attr, char *buf)
  6563. {
  6564. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6565. return sprintf(buf, "0x%04X\n",
  6566. (priv->phymode << 8) |
  6567. le16_to_cpu(priv->active_rxon.channel));
  6568. }
  6569. static void iwl3945_set_flags_for_phymode(struct iwl3945_priv *priv, u8 phymode);
  6570. static ssize_t store_tune(struct device *d,
  6571. struct device_attribute *attr,
  6572. const char *buf, size_t count)
  6573. {
  6574. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6575. char *p = (char *)buf;
  6576. u16 tune = simple_strtoul(p, &p, 0);
  6577. u8 phymode = (tune >> 8) & 0xff;
  6578. u16 channel = tune & 0xff;
  6579. IWL_DEBUG_INFO("Tune request to:%d channel:%d\n", phymode, channel);
  6580. mutex_lock(&priv->mutex);
  6581. if ((le16_to_cpu(priv->staging_rxon.channel) != channel) ||
  6582. (priv->phymode != phymode)) {
  6583. const struct iwl3945_channel_info *ch_info;
  6584. ch_info = iwl3945_get_channel_info(priv, phymode, channel);
  6585. if (!ch_info) {
  6586. IWL_WARNING("Requested invalid phymode/channel "
  6587. "combination: %d %d\n", phymode, channel);
  6588. mutex_unlock(&priv->mutex);
  6589. return -EINVAL;
  6590. }
  6591. /* Cancel any currently running scans... */
  6592. if (iwl3945_scan_cancel_timeout(priv, 100))
  6593. IWL_WARNING("Could not cancel scan.\n");
  6594. else {
  6595. IWL_DEBUG_INFO("Committing phymode and "
  6596. "rxon.channel = %d %d\n",
  6597. phymode, channel);
  6598. iwl3945_set_rxon_channel(priv, phymode, channel);
  6599. iwl3945_set_flags_for_phymode(priv, phymode);
  6600. iwl3945_set_rate(priv);
  6601. iwl3945_commit_rxon(priv);
  6602. }
  6603. }
  6604. mutex_unlock(&priv->mutex);
  6605. return count;
  6606. }
  6607. static DEVICE_ATTR(tune, S_IWUSR | S_IRUGO, show_tune, store_tune);
  6608. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  6609. static ssize_t show_measurement(struct device *d,
  6610. struct device_attribute *attr, char *buf)
  6611. {
  6612. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6613. struct iwl3945_spectrum_notification measure_report;
  6614. u32 size = sizeof(measure_report), len = 0, ofs = 0;
  6615. u8 *data = (u8 *) & measure_report;
  6616. unsigned long flags;
  6617. spin_lock_irqsave(&priv->lock, flags);
  6618. if (!(priv->measurement_status & MEASUREMENT_READY)) {
  6619. spin_unlock_irqrestore(&priv->lock, flags);
  6620. return 0;
  6621. }
  6622. memcpy(&measure_report, &priv->measure_report, size);
  6623. priv->measurement_status = 0;
  6624. spin_unlock_irqrestore(&priv->lock, flags);
  6625. while (size && (PAGE_SIZE - len)) {
  6626. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  6627. PAGE_SIZE - len, 1);
  6628. len = strlen(buf);
  6629. if (PAGE_SIZE - len)
  6630. buf[len++] = '\n';
  6631. ofs += 16;
  6632. size -= min(size, 16U);
  6633. }
  6634. return len;
  6635. }
  6636. static ssize_t store_measurement(struct device *d,
  6637. struct device_attribute *attr,
  6638. const char *buf, size_t count)
  6639. {
  6640. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6641. struct ieee80211_measurement_params params = {
  6642. .channel = le16_to_cpu(priv->active_rxon.channel),
  6643. .start_time = cpu_to_le64(priv->last_tsf),
  6644. .duration = cpu_to_le16(1),
  6645. };
  6646. u8 type = IWL_MEASURE_BASIC;
  6647. u8 buffer[32];
  6648. u8 channel;
  6649. if (count) {
  6650. char *p = buffer;
  6651. strncpy(buffer, buf, min(sizeof(buffer), count));
  6652. channel = simple_strtoul(p, NULL, 0);
  6653. if (channel)
  6654. params.channel = channel;
  6655. p = buffer;
  6656. while (*p && *p != ' ')
  6657. p++;
  6658. if (*p)
  6659. type = simple_strtoul(p + 1, NULL, 0);
  6660. }
  6661. IWL_DEBUG_INFO("Invoking measurement of type %d on "
  6662. "channel %d (for '%s')\n", type, params.channel, buf);
  6663. iwl3945_get_measurement(priv, &params, type);
  6664. return count;
  6665. }
  6666. static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
  6667. show_measurement, store_measurement);
  6668. #endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
  6669. static ssize_t show_rate(struct device *d,
  6670. struct device_attribute *attr, char *buf)
  6671. {
  6672. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6673. unsigned long flags;
  6674. int i;
  6675. spin_lock_irqsave(&priv->sta_lock, flags);
  6676. if (priv->iw_mode == IEEE80211_IF_TYPE_STA)
  6677. i = priv->stations[IWL_AP_ID].current_rate.s.rate;
  6678. else
  6679. i = priv->stations[IWL_STA_ID].current_rate.s.rate;
  6680. spin_unlock_irqrestore(&priv->sta_lock, flags);
  6681. i = iwl3945_rate_index_from_plcp(i);
  6682. if (i == -1)
  6683. return sprintf(buf, "0\n");
  6684. return sprintf(buf, "%d%s\n",
  6685. (iwl3945_rates[i].ieee >> 1),
  6686. (iwl3945_rates[i].ieee & 0x1) ? ".5" : "");
  6687. }
  6688. static DEVICE_ATTR(rate, S_IRUSR, show_rate, NULL);
  6689. static ssize_t store_retry_rate(struct device *d,
  6690. struct device_attribute *attr,
  6691. const char *buf, size_t count)
  6692. {
  6693. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6694. priv->retry_rate = simple_strtoul(buf, NULL, 0);
  6695. if (priv->retry_rate <= 0)
  6696. priv->retry_rate = 1;
  6697. return count;
  6698. }
  6699. static ssize_t show_retry_rate(struct device *d,
  6700. struct device_attribute *attr, char *buf)
  6701. {
  6702. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6703. return sprintf(buf, "%d", priv->retry_rate);
  6704. }
  6705. static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
  6706. store_retry_rate);
  6707. static ssize_t store_power_level(struct device *d,
  6708. struct device_attribute *attr,
  6709. const char *buf, size_t count)
  6710. {
  6711. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6712. int rc;
  6713. int mode;
  6714. mode = simple_strtoul(buf, NULL, 0);
  6715. mutex_lock(&priv->mutex);
  6716. if (!iwl3945_is_ready(priv)) {
  6717. rc = -EAGAIN;
  6718. goto out;
  6719. }
  6720. if ((mode < 1) || (mode > IWL_POWER_LIMIT) || (mode == IWL_POWER_AC))
  6721. mode = IWL_POWER_AC;
  6722. else
  6723. mode |= IWL_POWER_ENABLED;
  6724. if (mode != priv->power_mode) {
  6725. rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
  6726. if (rc) {
  6727. IWL_DEBUG_MAC80211("failed setting power mode.\n");
  6728. goto out;
  6729. }
  6730. priv->power_mode = mode;
  6731. }
  6732. rc = count;
  6733. out:
  6734. mutex_unlock(&priv->mutex);
  6735. return rc;
  6736. }
  6737. #define MAX_WX_STRING 80
  6738. /* Values are in microsecond */
  6739. static const s32 timeout_duration[] = {
  6740. 350000,
  6741. 250000,
  6742. 75000,
  6743. 37000,
  6744. 25000,
  6745. };
  6746. static const s32 period_duration[] = {
  6747. 400000,
  6748. 700000,
  6749. 1000000,
  6750. 1000000,
  6751. 1000000
  6752. };
  6753. static ssize_t show_power_level(struct device *d,
  6754. struct device_attribute *attr, char *buf)
  6755. {
  6756. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6757. int level = IWL_POWER_LEVEL(priv->power_mode);
  6758. char *p = buf;
  6759. p += sprintf(p, "%d ", level);
  6760. switch (level) {
  6761. case IWL_POWER_MODE_CAM:
  6762. case IWL_POWER_AC:
  6763. p += sprintf(p, "(AC)");
  6764. break;
  6765. case IWL_POWER_BATTERY:
  6766. p += sprintf(p, "(BATTERY)");
  6767. break;
  6768. default:
  6769. p += sprintf(p,
  6770. "(Timeout %dms, Period %dms)",
  6771. timeout_duration[level - 1] / 1000,
  6772. period_duration[level - 1] / 1000);
  6773. }
  6774. if (!(priv->power_mode & IWL_POWER_ENABLED))
  6775. p += sprintf(p, " OFF\n");
  6776. else
  6777. p += sprintf(p, " \n");
  6778. return (p - buf + 1);
  6779. }
  6780. static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
  6781. store_power_level);
  6782. static ssize_t show_channels(struct device *d,
  6783. struct device_attribute *attr, char *buf)
  6784. {
  6785. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6786. int len = 0, i;
  6787. struct ieee80211_channel *channels = NULL;
  6788. const struct ieee80211_hw_mode *hw_mode = NULL;
  6789. int count = 0;
  6790. if (!iwl3945_is_ready(priv))
  6791. return -EAGAIN;
  6792. hw_mode = iwl3945_get_hw_mode(priv, MODE_IEEE80211G);
  6793. if (!hw_mode)
  6794. hw_mode = iwl3945_get_hw_mode(priv, MODE_IEEE80211B);
  6795. if (hw_mode) {
  6796. channels = hw_mode->channels;
  6797. count = hw_mode->num_channels;
  6798. }
  6799. len +=
  6800. sprintf(&buf[len],
  6801. "Displaying %d channels in 2.4GHz band "
  6802. "(802.11bg):\n", count);
  6803. for (i = 0; i < count; i++)
  6804. len += sprintf(&buf[len], "%d: %ddBm: BSS%s%s, %s.\n",
  6805. channels[i].chan,
  6806. channels[i].power_level,
  6807. channels[i].
  6808. flag & IEEE80211_CHAN_W_RADAR_DETECT ?
  6809. " (IEEE 802.11h required)" : "",
  6810. (!(channels[i].flag & IEEE80211_CHAN_W_IBSS)
  6811. || (channels[i].
  6812. flag &
  6813. IEEE80211_CHAN_W_RADAR_DETECT)) ? "" :
  6814. ", IBSS",
  6815. channels[i].
  6816. flag & IEEE80211_CHAN_W_ACTIVE_SCAN ?
  6817. "active/passive" : "passive only");
  6818. hw_mode = iwl3945_get_hw_mode(priv, MODE_IEEE80211A);
  6819. if (hw_mode) {
  6820. channels = hw_mode->channels;
  6821. count = hw_mode->num_channels;
  6822. } else {
  6823. channels = NULL;
  6824. count = 0;
  6825. }
  6826. len += sprintf(&buf[len], "Displaying %d channels in 5.2GHz band "
  6827. "(802.11a):\n", count);
  6828. for (i = 0; i < count; i++)
  6829. len += sprintf(&buf[len], "%d: %ddBm: BSS%s%s, %s.\n",
  6830. channels[i].chan,
  6831. channels[i].power_level,
  6832. channels[i].
  6833. flag & IEEE80211_CHAN_W_RADAR_DETECT ?
  6834. " (IEEE 802.11h required)" : "",
  6835. (!(channels[i].flag & IEEE80211_CHAN_W_IBSS)
  6836. || (channels[i].
  6837. flag &
  6838. IEEE80211_CHAN_W_RADAR_DETECT)) ? "" :
  6839. ", IBSS",
  6840. channels[i].
  6841. flag & IEEE80211_CHAN_W_ACTIVE_SCAN ?
  6842. "active/passive" : "passive only");
  6843. return len;
  6844. }
  6845. static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
  6846. static ssize_t show_statistics(struct device *d,
  6847. struct device_attribute *attr, char *buf)
  6848. {
  6849. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6850. u32 size = sizeof(struct iwl3945_notif_statistics);
  6851. u32 len = 0, ofs = 0;
  6852. u8 *data = (u8 *) & priv->statistics;
  6853. int rc = 0;
  6854. if (!iwl3945_is_alive(priv))
  6855. return -EAGAIN;
  6856. mutex_lock(&priv->mutex);
  6857. rc = iwl3945_send_statistics_request(priv);
  6858. mutex_unlock(&priv->mutex);
  6859. if (rc) {
  6860. len = sprintf(buf,
  6861. "Error sending statistics request: 0x%08X\n", rc);
  6862. return len;
  6863. }
  6864. while (size && (PAGE_SIZE - len)) {
  6865. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  6866. PAGE_SIZE - len, 1);
  6867. len = strlen(buf);
  6868. if (PAGE_SIZE - len)
  6869. buf[len++] = '\n';
  6870. ofs += 16;
  6871. size -= min(size, 16U);
  6872. }
  6873. return len;
  6874. }
  6875. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  6876. static ssize_t show_antenna(struct device *d,
  6877. struct device_attribute *attr, char *buf)
  6878. {
  6879. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6880. if (!iwl3945_is_alive(priv))
  6881. return -EAGAIN;
  6882. return sprintf(buf, "%d\n", priv->antenna);
  6883. }
  6884. static ssize_t store_antenna(struct device *d,
  6885. struct device_attribute *attr,
  6886. const char *buf, size_t count)
  6887. {
  6888. int ant;
  6889. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6890. if (count == 0)
  6891. return 0;
  6892. if (sscanf(buf, "%1i", &ant) != 1) {
  6893. IWL_DEBUG_INFO("not in hex or decimal form.\n");
  6894. return count;
  6895. }
  6896. if ((ant >= 0) && (ant <= 2)) {
  6897. IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
  6898. priv->antenna = (enum iwl3945_antenna)ant;
  6899. } else
  6900. IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
  6901. return count;
  6902. }
  6903. static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
  6904. static ssize_t show_status(struct device *d,
  6905. struct device_attribute *attr, char *buf)
  6906. {
  6907. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6908. if (!iwl3945_is_alive(priv))
  6909. return -EAGAIN;
  6910. return sprintf(buf, "0x%08x\n", (int)priv->status);
  6911. }
  6912. static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
  6913. static ssize_t dump_error_log(struct device *d,
  6914. struct device_attribute *attr,
  6915. const char *buf, size_t count)
  6916. {
  6917. char *p = (char *)buf;
  6918. if (p[0] == '1')
  6919. iwl3945_dump_nic_error_log((struct iwl3945_priv *)d->driver_data);
  6920. return strnlen(buf, count);
  6921. }
  6922. static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
  6923. static ssize_t dump_event_log(struct device *d,
  6924. struct device_attribute *attr,
  6925. const char *buf, size_t count)
  6926. {
  6927. char *p = (char *)buf;
  6928. if (p[0] == '1')
  6929. iwl3945_dump_nic_event_log((struct iwl3945_priv *)d->driver_data);
  6930. return strnlen(buf, count);
  6931. }
  6932. static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
  6933. /*****************************************************************************
  6934. *
  6935. * driver setup and teardown
  6936. *
  6937. *****************************************************************************/
  6938. static void iwl3945_setup_deferred_work(struct iwl3945_priv *priv)
  6939. {
  6940. priv->workqueue = create_workqueue(DRV_NAME);
  6941. init_waitqueue_head(&priv->wait_command_queue);
  6942. INIT_WORK(&priv->up, iwl3945_bg_up);
  6943. INIT_WORK(&priv->restart, iwl3945_bg_restart);
  6944. INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
  6945. INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed);
  6946. INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
  6947. INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
  6948. INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
  6949. INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
  6950. INIT_DELAYED_WORK(&priv->post_associate, iwl3945_bg_post_associate);
  6951. INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
  6952. INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
  6953. INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check);
  6954. iwl3945_hw_setup_deferred_work(priv);
  6955. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  6956. iwl3945_irq_tasklet, (unsigned long)priv);
  6957. }
  6958. static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv)
  6959. {
  6960. iwl3945_hw_cancel_deferred_work(priv);
  6961. cancel_delayed_work_sync(&priv->init_alive_start);
  6962. cancel_delayed_work(&priv->scan_check);
  6963. cancel_delayed_work(&priv->alive_start);
  6964. cancel_delayed_work(&priv->post_associate);
  6965. cancel_work_sync(&priv->beacon_update);
  6966. }
  6967. static struct attribute *iwl3945_sysfs_entries[] = {
  6968. &dev_attr_antenna.attr,
  6969. &dev_attr_channels.attr,
  6970. &dev_attr_dump_errors.attr,
  6971. &dev_attr_dump_events.attr,
  6972. &dev_attr_flags.attr,
  6973. &dev_attr_filter_flags.attr,
  6974. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  6975. &dev_attr_measurement.attr,
  6976. #endif
  6977. &dev_attr_power_level.attr,
  6978. &dev_attr_rate.attr,
  6979. &dev_attr_retry_rate.attr,
  6980. &dev_attr_rf_kill.attr,
  6981. &dev_attr_rs_window.attr,
  6982. &dev_attr_statistics.attr,
  6983. &dev_attr_status.attr,
  6984. &dev_attr_temperature.attr,
  6985. &dev_attr_tune.attr,
  6986. &dev_attr_tx_power.attr,
  6987. NULL
  6988. };
  6989. static struct attribute_group iwl3945_attribute_group = {
  6990. .name = NULL, /* put in device directory */
  6991. .attrs = iwl3945_sysfs_entries,
  6992. };
  6993. static struct ieee80211_ops iwl3945_hw_ops = {
  6994. .tx = iwl3945_mac_tx,
  6995. .start = iwl3945_mac_start,
  6996. .stop = iwl3945_mac_stop,
  6997. .add_interface = iwl3945_mac_add_interface,
  6998. .remove_interface = iwl3945_mac_remove_interface,
  6999. .config = iwl3945_mac_config,
  7000. .config_interface = iwl3945_mac_config_interface,
  7001. .configure_filter = iwl3945_configure_filter,
  7002. .set_key = iwl3945_mac_set_key,
  7003. .get_stats = iwl3945_mac_get_stats,
  7004. .get_tx_stats = iwl3945_mac_get_tx_stats,
  7005. .conf_tx = iwl3945_mac_conf_tx,
  7006. .get_tsf = iwl3945_mac_get_tsf,
  7007. .reset_tsf = iwl3945_mac_reset_tsf,
  7008. .beacon_update = iwl3945_mac_beacon_update,
  7009. .hw_scan = iwl3945_mac_hw_scan
  7010. };
  7011. static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  7012. {
  7013. int err = 0;
  7014. u32 pci_id;
  7015. struct iwl3945_priv *priv;
  7016. struct ieee80211_hw *hw;
  7017. int i;
  7018. /* Disabling hardware scan means that mac80211 will perform scans
  7019. * "the hard way", rather than using device's scan. */
  7020. if (iwl3945_param_disable_hw_scan) {
  7021. IWL_DEBUG_INFO("Disabling hw_scan\n");
  7022. iwl3945_hw_ops.hw_scan = NULL;
  7023. }
  7024. if ((iwl3945_param_queues_num > IWL_MAX_NUM_QUEUES) ||
  7025. (iwl3945_param_queues_num < IWL_MIN_NUM_QUEUES)) {
  7026. IWL_ERROR("invalid queues_num, should be between %d and %d\n",
  7027. IWL_MIN_NUM_QUEUES, IWL_MAX_NUM_QUEUES);
  7028. err = -EINVAL;
  7029. goto out;
  7030. }
  7031. /* mac80211 allocates memory for this device instance, including
  7032. * space for this driver's private structure */
  7033. hw = ieee80211_alloc_hw(sizeof(struct iwl3945_priv), &iwl3945_hw_ops);
  7034. if (hw == NULL) {
  7035. IWL_ERROR("Can not allocate network device\n");
  7036. err = -ENOMEM;
  7037. goto out;
  7038. }
  7039. SET_IEEE80211_DEV(hw, &pdev->dev);
  7040. hw->rate_control_algorithm = "iwl-3945-rs";
  7041. IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
  7042. priv = hw->priv;
  7043. priv->hw = hw;
  7044. priv->pci_dev = pdev;
  7045. /* Select antenna (may be helpful if only one antenna is connected) */
  7046. priv->antenna = (enum iwl3945_antenna)iwl3945_param_antenna;
  7047. #ifdef CONFIG_IWL3945_DEBUG
  7048. iwl3945_debug_level = iwl3945_param_debug;
  7049. atomic_set(&priv->restrict_refcnt, 0);
  7050. #endif
  7051. priv->retry_rate = 1;
  7052. priv->ibss_beacon = NULL;
  7053. /* Tell mac80211 and its clients (e.g. Wireless Extensions)
  7054. * the range of signal quality values that we'll provide.
  7055. * Negative values for level/noise indicate that we'll provide dBm.
  7056. * For WE, at least, non-0 values here *enable* display of values
  7057. * in app (iwconfig). */
  7058. hw->max_rssi = -20; /* signal level, negative indicates dBm */
  7059. hw->max_noise = -20; /* noise level, negative indicates dBm */
  7060. hw->max_signal = 100; /* link quality indication (%) */
  7061. /* Tell mac80211 our Tx characteristics */
  7062. hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE;
  7063. /* 4 EDCA QOS priorities */
  7064. hw->queues = 4;
  7065. spin_lock_init(&priv->lock);
  7066. spin_lock_init(&priv->power_data.lock);
  7067. spin_lock_init(&priv->sta_lock);
  7068. spin_lock_init(&priv->hcmd_lock);
  7069. for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
  7070. INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
  7071. INIT_LIST_HEAD(&priv->free_frames);
  7072. mutex_init(&priv->mutex);
  7073. if (pci_enable_device(pdev)) {
  7074. err = -ENODEV;
  7075. goto out_ieee80211_free_hw;
  7076. }
  7077. pci_set_master(pdev);
  7078. /* Clear the driver's (not device's) station table */
  7079. iwl3945_clear_stations_table(priv);
  7080. priv->data_retry_limit = -1;
  7081. priv->ieee_channels = NULL;
  7082. priv->ieee_rates = NULL;
  7083. priv->phymode = -1;
  7084. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  7085. if (!err)
  7086. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  7087. if (err) {
  7088. printk(KERN_WARNING DRV_NAME ": No suitable DMA available.\n");
  7089. goto out_pci_disable_device;
  7090. }
  7091. pci_set_drvdata(pdev, priv);
  7092. err = pci_request_regions(pdev, DRV_NAME);
  7093. if (err)
  7094. goto out_pci_disable_device;
  7095. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  7096. * PCI Tx retries from interfering with C3 CPU state */
  7097. pci_write_config_byte(pdev, 0x41, 0x00);
  7098. priv->hw_base = pci_iomap(pdev, 0, 0);
  7099. if (!priv->hw_base) {
  7100. err = -ENODEV;
  7101. goto out_pci_release_regions;
  7102. }
  7103. IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
  7104. (unsigned long long) pci_resource_len(pdev, 0));
  7105. IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
  7106. /* Initialize module parameter values here */
  7107. /* Disable radio (SW RF KILL) via parameter when loading driver */
  7108. if (iwl3945_param_disable) {
  7109. set_bit(STATUS_RF_KILL_SW, &priv->status);
  7110. IWL_DEBUG_INFO("Radio disabled.\n");
  7111. }
  7112. priv->iw_mode = IEEE80211_IF_TYPE_STA;
  7113. pci_id =
  7114. (priv->pci_dev->device << 16) | priv->pci_dev->subsystem_device;
  7115. switch (pci_id) {
  7116. case 0x42221005: /* 0x4222 0x8086 0x1005 is BG SKU */
  7117. case 0x42221034: /* 0x4222 0x8086 0x1034 is BG SKU */
  7118. case 0x42271014: /* 0x4227 0x8086 0x1014 is BG SKU */
  7119. case 0x42221044: /* 0x4222 0x8086 0x1044 is BG SKU */
  7120. priv->is_abg = 0;
  7121. break;
  7122. /*
  7123. * Rest are assumed ABG SKU -- if this is not the
  7124. * case then the card will get the wrong 'Detected'
  7125. * line in the kernel log however the code that
  7126. * initializes the GEO table will detect no A-band
  7127. * channels and remove the is_abg mask.
  7128. */
  7129. default:
  7130. priv->is_abg = 1;
  7131. break;
  7132. }
  7133. printk(KERN_INFO DRV_NAME
  7134. ": Detected Intel PRO/Wireless 3945%sBG Network Connection\n",
  7135. priv->is_abg ? "A" : "");
  7136. /* Device-specific setup */
  7137. if (iwl3945_hw_set_hw_setting(priv)) {
  7138. IWL_ERROR("failed to set hw settings\n");
  7139. mutex_unlock(&priv->mutex);
  7140. goto out_iounmap;
  7141. }
  7142. #ifdef CONFIG_IWL3945_QOS
  7143. if (iwl3945_param_qos_enable)
  7144. priv->qos_data.qos_enable = 1;
  7145. iwl3945_reset_qos(priv);
  7146. priv->qos_data.qos_active = 0;
  7147. priv->qos_data.qos_cap.val = 0;
  7148. #endif /* CONFIG_IWL3945_QOS */
  7149. iwl3945_set_rxon_channel(priv, MODE_IEEE80211G, 6);
  7150. iwl3945_setup_deferred_work(priv);
  7151. iwl3945_setup_rx_handlers(priv);
  7152. priv->rates_mask = IWL_RATES_MASK;
  7153. /* If power management is turned on, default to AC mode */
  7154. priv->power_mode = IWL_POWER_AC;
  7155. priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
  7156. iwl3945_disable_interrupts(priv);
  7157. pci_enable_msi(pdev);
  7158. err = request_irq(pdev->irq, iwl3945_isr, IRQF_SHARED, DRV_NAME, priv);
  7159. if (err) {
  7160. IWL_ERROR("Error allocating IRQ %d\n", pdev->irq);
  7161. goto out_disable_msi;
  7162. }
  7163. mutex_lock(&priv->mutex);
  7164. err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  7165. if (err) {
  7166. IWL_ERROR("failed to create sysfs device attributes\n");
  7167. mutex_unlock(&priv->mutex);
  7168. goto out_release_irq;
  7169. }
  7170. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  7171. * ucode filename and max sizes are card-specific. */
  7172. err = iwl3945_read_ucode(priv);
  7173. if (err) {
  7174. IWL_ERROR("Could not read microcode: %d\n", err);
  7175. mutex_unlock(&priv->mutex);
  7176. goto out_pci_alloc;
  7177. }
  7178. mutex_unlock(&priv->mutex);
  7179. IWL_DEBUG_INFO("Queueing UP work.\n");
  7180. queue_work(priv->workqueue, &priv->up);
  7181. return 0;
  7182. out_pci_alloc:
  7183. iwl3945_dealloc_ucode_pci(priv);
  7184. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  7185. out_release_irq:
  7186. free_irq(pdev->irq, priv);
  7187. out_disable_msi:
  7188. pci_disable_msi(pdev);
  7189. destroy_workqueue(priv->workqueue);
  7190. priv->workqueue = NULL;
  7191. iwl3945_unset_hw_setting(priv);
  7192. out_iounmap:
  7193. pci_iounmap(pdev, priv->hw_base);
  7194. out_pci_release_regions:
  7195. pci_release_regions(pdev);
  7196. out_pci_disable_device:
  7197. pci_disable_device(pdev);
  7198. pci_set_drvdata(pdev, NULL);
  7199. out_ieee80211_free_hw:
  7200. ieee80211_free_hw(priv->hw);
  7201. out:
  7202. return err;
  7203. }
  7204. static void iwl3945_pci_remove(struct pci_dev *pdev)
  7205. {
  7206. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  7207. struct list_head *p, *q;
  7208. int i;
  7209. if (!priv)
  7210. return;
  7211. IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
  7212. set_bit(STATUS_EXIT_PENDING, &priv->status);
  7213. iwl3945_down(priv);
  7214. /* Free MAC hash list for ADHOC */
  7215. for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++) {
  7216. list_for_each_safe(p, q, &priv->ibss_mac_hash[i]) {
  7217. list_del(p);
  7218. kfree(list_entry(p, struct iwl3945_ibss_seq, list));
  7219. }
  7220. }
  7221. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  7222. iwl3945_dealloc_ucode_pci(priv);
  7223. if (priv->rxq.bd)
  7224. iwl3945_rx_queue_free(priv, &priv->rxq);
  7225. iwl3945_hw_txq_ctx_free(priv);
  7226. iwl3945_unset_hw_setting(priv);
  7227. iwl3945_clear_stations_table(priv);
  7228. if (priv->mac80211_registered) {
  7229. ieee80211_unregister_hw(priv->hw);
  7230. iwl3945_rate_control_unregister(priv->hw);
  7231. }
  7232. /*netif_stop_queue(dev); */
  7233. flush_workqueue(priv->workqueue);
  7234. /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
  7235. * priv->workqueue... so we can't take down the workqueue
  7236. * until now... */
  7237. destroy_workqueue(priv->workqueue);
  7238. priv->workqueue = NULL;
  7239. free_irq(pdev->irq, priv);
  7240. pci_disable_msi(pdev);
  7241. pci_iounmap(pdev, priv->hw_base);
  7242. pci_release_regions(pdev);
  7243. pci_disable_device(pdev);
  7244. pci_set_drvdata(pdev, NULL);
  7245. kfree(priv->channel_info);
  7246. kfree(priv->ieee_channels);
  7247. kfree(priv->ieee_rates);
  7248. if (priv->ibss_beacon)
  7249. dev_kfree_skb(priv->ibss_beacon);
  7250. ieee80211_free_hw(priv->hw);
  7251. }
  7252. #ifdef CONFIG_PM
  7253. static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  7254. {
  7255. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  7256. set_bit(STATUS_IN_SUSPEND, &priv->status);
  7257. /* Take down the device; powers it off, etc. */
  7258. iwl3945_down(priv);
  7259. if (priv->mac80211_registered)
  7260. ieee80211_stop_queues(priv->hw);
  7261. pci_save_state(pdev);
  7262. pci_disable_device(pdev);
  7263. pci_set_power_state(pdev, PCI_D3hot);
  7264. return 0;
  7265. }
  7266. static void iwl3945_resume(struct iwl3945_priv *priv)
  7267. {
  7268. unsigned long flags;
  7269. /* The following it a temporary work around due to the
  7270. * suspend / resume not fully initializing the NIC correctly.
  7271. * Without all of the following, resume will not attempt to take
  7272. * down the NIC (it shouldn't really need to) and will just try
  7273. * and bring the NIC back up. However that fails during the
  7274. * ucode verification process. This then causes iwl3945_down to be
  7275. * called *after* iwl3945_hw_nic_init() has succeeded -- which
  7276. * then lets the next init sequence succeed. So, we've
  7277. * replicated all of that NIC init code here... */
  7278. iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
  7279. iwl3945_hw_nic_init(priv);
  7280. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  7281. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  7282. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  7283. iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
  7284. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  7285. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  7286. /* tell the device to stop sending interrupts */
  7287. iwl3945_disable_interrupts(priv);
  7288. spin_lock_irqsave(&priv->lock, flags);
  7289. iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  7290. if (!iwl3945_grab_nic_access(priv)) {
  7291. iwl3945_write_prph(priv, APMG_CLK_DIS_REG,
  7292. APMG_CLK_VAL_DMA_CLK_RQT);
  7293. iwl3945_release_nic_access(priv);
  7294. }
  7295. spin_unlock_irqrestore(&priv->lock, flags);
  7296. udelay(5);
  7297. iwl3945_hw_nic_reset(priv);
  7298. /* Bring the device back up */
  7299. clear_bit(STATUS_IN_SUSPEND, &priv->status);
  7300. queue_work(priv->workqueue, &priv->up);
  7301. }
  7302. static int iwl3945_pci_resume(struct pci_dev *pdev)
  7303. {
  7304. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  7305. int err;
  7306. printk(KERN_INFO "Coming out of suspend...\n");
  7307. pci_set_power_state(pdev, PCI_D0);
  7308. err = pci_enable_device(pdev);
  7309. pci_restore_state(pdev);
  7310. /*
  7311. * Suspend/Resume resets the PCI configuration space, so we have to
  7312. * re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries
  7313. * from interfering with C3 CPU state. pci_restore_state won't help
  7314. * here since it only restores the first 64 bytes pci config header.
  7315. */
  7316. pci_write_config_byte(pdev, 0x41, 0x00);
  7317. iwl3945_resume(priv);
  7318. return 0;
  7319. }
  7320. #endif /* CONFIG_PM */
  7321. /*****************************************************************************
  7322. *
  7323. * driver and module entry point
  7324. *
  7325. *****************************************************************************/
  7326. static struct pci_driver iwl3945_driver = {
  7327. .name = DRV_NAME,
  7328. .id_table = iwl3945_hw_card_ids,
  7329. .probe = iwl3945_pci_probe,
  7330. .remove = __devexit_p(iwl3945_pci_remove),
  7331. #ifdef CONFIG_PM
  7332. .suspend = iwl3945_pci_suspend,
  7333. .resume = iwl3945_pci_resume,
  7334. #endif
  7335. };
  7336. static int __init iwl3945_init(void)
  7337. {
  7338. int ret;
  7339. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  7340. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  7341. ret = pci_register_driver(&iwl3945_driver);
  7342. if (ret) {
  7343. IWL_ERROR("Unable to initialize PCI module\n");
  7344. return ret;
  7345. }
  7346. #ifdef CONFIG_IWL3945_DEBUG
  7347. ret = driver_create_file(&iwl3945_driver.driver, &driver_attr_debug_level);
  7348. if (ret) {
  7349. IWL_ERROR("Unable to create driver sysfs file\n");
  7350. pci_unregister_driver(&iwl3945_driver);
  7351. return ret;
  7352. }
  7353. #endif
  7354. return ret;
  7355. }
  7356. static void __exit iwl3945_exit(void)
  7357. {
  7358. #ifdef CONFIG_IWL3945_DEBUG
  7359. driver_remove_file(&iwl3945_driver.driver, &driver_attr_debug_level);
  7360. #endif
  7361. pci_unregister_driver(&iwl3945_driver);
  7362. }
  7363. module_param_named(antenna, iwl3945_param_antenna, int, 0444);
  7364. MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
  7365. module_param_named(disable, iwl3945_param_disable, int, 0444);
  7366. MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
  7367. module_param_named(hwcrypto, iwl3945_param_hwcrypto, int, 0444);
  7368. MODULE_PARM_DESC(hwcrypto,
  7369. "using hardware crypto engine (default 0 [software])\n");
  7370. module_param_named(debug, iwl3945_param_debug, int, 0444);
  7371. MODULE_PARM_DESC(debug, "debug output mask");
  7372. module_param_named(disable_hw_scan, iwl3945_param_disable_hw_scan, int, 0444);
  7373. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  7374. module_param_named(queues_num, iwl3945_param_queues_num, int, 0444);
  7375. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  7376. /* QoS */
  7377. module_param_named(qos_enable, iwl3945_param_qos_enable, int, 0444);
  7378. MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
  7379. module_exit(iwl3945_exit);
  7380. module_init(iwl3945_init);