main.c 100 KB

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  1. /*
  2. *
  3. * Broadcom B43legacy wireless driver
  4. *
  5. * Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
  6. * Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
  7. * Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
  8. * Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
  9. * Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  10. * Copyright (c) 2007 Larry Finger <Larry.Finger@lwfinger.net>
  11. *
  12. * Some parts of the code in this file are derived from the ipw2200
  13. * driver Copyright(c) 2003 - 2004 Intel Corporation.
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License as published by
  16. * the Free Software Foundation; either version 2 of the License, or
  17. * (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; see the file COPYING. If not, write to
  26. * the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  27. * Boston, MA 02110-1301, USA.
  28. *
  29. */
  30. #include <linux/delay.h>
  31. #include <linux/init.h>
  32. #include <linux/moduleparam.h>
  33. #include <linux/if_arp.h>
  34. #include <linux/etherdevice.h>
  35. #include <linux/version.h>
  36. #include <linux/firmware.h>
  37. #include <linux/wireless.h>
  38. #include <linux/workqueue.h>
  39. #include <linux/skbuff.h>
  40. #include <linux/dma-mapping.h>
  41. #include <net/dst.h>
  42. #include <asm/unaligned.h>
  43. #include "b43legacy.h"
  44. #include "main.h"
  45. #include "debugfs.h"
  46. #include "phy.h"
  47. #include "dma.h"
  48. #include "pio.h"
  49. #include "sysfs.h"
  50. #include "xmit.h"
  51. #include "radio.h"
  52. MODULE_DESCRIPTION("Broadcom B43legacy wireless driver");
  53. MODULE_AUTHOR("Martin Langer");
  54. MODULE_AUTHOR("Stefano Brivio");
  55. MODULE_AUTHOR("Michael Buesch");
  56. MODULE_LICENSE("GPL");
  57. #if defined(CONFIG_B43LEGACY_DMA) && defined(CONFIG_B43LEGACY_PIO)
  58. static int modparam_pio;
  59. module_param_named(pio, modparam_pio, int, 0444);
  60. MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
  61. #elif defined(CONFIG_B43LEGACY_DMA)
  62. # define modparam_pio 0
  63. #elif defined(CONFIG_B43LEGACY_PIO)
  64. # define modparam_pio 1
  65. #endif
  66. static int modparam_bad_frames_preempt;
  67. module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
  68. MODULE_PARM_DESC(bad_frames_preempt, "enable(1) / disable(0) Bad Frames"
  69. " Preemption");
  70. static char modparam_fwpostfix[16];
  71. module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
  72. MODULE_PARM_DESC(fwpostfix, "Postfix for the firmware files to load.");
  73. /* The following table supports BCM4301, BCM4303 and BCM4306/2 devices. */
  74. static const struct ssb_device_id b43legacy_ssb_tbl[] = {
  75. SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 2),
  76. SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 4),
  77. SSB_DEVTABLE_END
  78. };
  79. MODULE_DEVICE_TABLE(ssb, b43legacy_ssb_tbl);
  80. /* Channel and ratetables are shared for all devices.
  81. * They can't be const, because ieee80211 puts some precalculated
  82. * data in there. This data is the same for all devices, so we don't
  83. * get concurrency issues */
  84. #define RATETAB_ENT(_rateid, _flags) \
  85. { \
  86. .rate = B43legacy_RATE_TO_100KBPS(_rateid), \
  87. .val = (_rateid), \
  88. .val2 = (_rateid), \
  89. .flags = (_flags), \
  90. }
  91. static struct ieee80211_rate __b43legacy_ratetable[] = {
  92. RATETAB_ENT(B43legacy_CCK_RATE_1MB, IEEE80211_RATE_CCK),
  93. RATETAB_ENT(B43legacy_CCK_RATE_2MB, IEEE80211_RATE_CCK_2),
  94. RATETAB_ENT(B43legacy_CCK_RATE_5MB, IEEE80211_RATE_CCK_2),
  95. RATETAB_ENT(B43legacy_CCK_RATE_11MB, IEEE80211_RATE_CCK_2),
  96. RATETAB_ENT(B43legacy_OFDM_RATE_6MB, IEEE80211_RATE_OFDM),
  97. RATETAB_ENT(B43legacy_OFDM_RATE_9MB, IEEE80211_RATE_OFDM),
  98. RATETAB_ENT(B43legacy_OFDM_RATE_12MB, IEEE80211_RATE_OFDM),
  99. RATETAB_ENT(B43legacy_OFDM_RATE_18MB, IEEE80211_RATE_OFDM),
  100. RATETAB_ENT(B43legacy_OFDM_RATE_24MB, IEEE80211_RATE_OFDM),
  101. RATETAB_ENT(B43legacy_OFDM_RATE_36MB, IEEE80211_RATE_OFDM),
  102. RATETAB_ENT(B43legacy_OFDM_RATE_48MB, IEEE80211_RATE_OFDM),
  103. RATETAB_ENT(B43legacy_OFDM_RATE_54MB, IEEE80211_RATE_OFDM),
  104. };
  105. #define b43legacy_a_ratetable (__b43legacy_ratetable + 4)
  106. #define b43legacy_a_ratetable_size 8
  107. #define b43legacy_b_ratetable (__b43legacy_ratetable + 0)
  108. #define b43legacy_b_ratetable_size 4
  109. #define b43legacy_g_ratetable (__b43legacy_ratetable + 0)
  110. #define b43legacy_g_ratetable_size 12
  111. #define CHANTAB_ENT(_chanid, _freq) \
  112. { \
  113. .chan = (_chanid), \
  114. .freq = (_freq), \
  115. .val = (_chanid), \
  116. .flag = IEEE80211_CHAN_W_SCAN | \
  117. IEEE80211_CHAN_W_ACTIVE_SCAN | \
  118. IEEE80211_CHAN_W_IBSS, \
  119. .power_level = 0x0A, \
  120. .antenna_max = 0xFF, \
  121. }
  122. static struct ieee80211_channel b43legacy_bg_chantable[] = {
  123. CHANTAB_ENT(1, 2412),
  124. CHANTAB_ENT(2, 2417),
  125. CHANTAB_ENT(3, 2422),
  126. CHANTAB_ENT(4, 2427),
  127. CHANTAB_ENT(5, 2432),
  128. CHANTAB_ENT(6, 2437),
  129. CHANTAB_ENT(7, 2442),
  130. CHANTAB_ENT(8, 2447),
  131. CHANTAB_ENT(9, 2452),
  132. CHANTAB_ENT(10, 2457),
  133. CHANTAB_ENT(11, 2462),
  134. CHANTAB_ENT(12, 2467),
  135. CHANTAB_ENT(13, 2472),
  136. CHANTAB_ENT(14, 2484),
  137. };
  138. #define b43legacy_bg_chantable_size ARRAY_SIZE(b43legacy_bg_chantable)
  139. static void b43legacy_wireless_core_exit(struct b43legacy_wldev *dev);
  140. static int b43legacy_wireless_core_init(struct b43legacy_wldev *dev);
  141. static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev);
  142. static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev);
  143. static int b43legacy_ratelimit(struct b43legacy_wl *wl)
  144. {
  145. if (!wl || !wl->current_dev)
  146. return 1;
  147. if (b43legacy_status(wl->current_dev) < B43legacy_STAT_STARTED)
  148. return 1;
  149. /* We are up and running.
  150. * Ratelimit the messages to avoid DoS over the net. */
  151. return net_ratelimit();
  152. }
  153. void b43legacyinfo(struct b43legacy_wl *wl, const char *fmt, ...)
  154. {
  155. va_list args;
  156. if (!b43legacy_ratelimit(wl))
  157. return;
  158. va_start(args, fmt);
  159. printk(KERN_INFO "b43legacy-%s: ",
  160. (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
  161. vprintk(fmt, args);
  162. va_end(args);
  163. }
  164. void b43legacyerr(struct b43legacy_wl *wl, const char *fmt, ...)
  165. {
  166. va_list args;
  167. if (!b43legacy_ratelimit(wl))
  168. return;
  169. va_start(args, fmt);
  170. printk(KERN_ERR "b43legacy-%s ERROR: ",
  171. (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
  172. vprintk(fmt, args);
  173. va_end(args);
  174. }
  175. void b43legacywarn(struct b43legacy_wl *wl, const char *fmt, ...)
  176. {
  177. va_list args;
  178. if (!b43legacy_ratelimit(wl))
  179. return;
  180. va_start(args, fmt);
  181. printk(KERN_WARNING "b43legacy-%s warning: ",
  182. (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
  183. vprintk(fmt, args);
  184. va_end(args);
  185. }
  186. #if B43legacy_DEBUG
  187. void b43legacydbg(struct b43legacy_wl *wl, const char *fmt, ...)
  188. {
  189. va_list args;
  190. va_start(args, fmt);
  191. printk(KERN_DEBUG "b43legacy-%s debug: ",
  192. (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
  193. vprintk(fmt, args);
  194. va_end(args);
  195. }
  196. #endif /* DEBUG */
  197. static void b43legacy_ram_write(struct b43legacy_wldev *dev, u16 offset,
  198. u32 val)
  199. {
  200. u32 status;
  201. B43legacy_WARN_ON(offset % 4 != 0);
  202. status = b43legacy_read32(dev, B43legacy_MMIO_STATUS_BITFIELD);
  203. if (status & B43legacy_SBF_XFER_REG_BYTESWAP)
  204. val = swab32(val);
  205. b43legacy_write32(dev, B43legacy_MMIO_RAM_CONTROL, offset);
  206. mmiowb();
  207. b43legacy_write32(dev, B43legacy_MMIO_RAM_DATA, val);
  208. }
  209. static inline
  210. void b43legacy_shm_control_word(struct b43legacy_wldev *dev,
  211. u16 routing, u16 offset)
  212. {
  213. u32 control;
  214. /* "offset" is the WORD offset. */
  215. control = routing;
  216. control <<= 16;
  217. control |= offset;
  218. b43legacy_write32(dev, B43legacy_MMIO_SHM_CONTROL, control);
  219. }
  220. u32 b43legacy_shm_read32(struct b43legacy_wldev *dev,
  221. u16 routing, u16 offset)
  222. {
  223. u32 ret;
  224. if (routing == B43legacy_SHM_SHARED) {
  225. B43legacy_WARN_ON((offset & 0x0001) != 0);
  226. if (offset & 0x0003) {
  227. /* Unaligned access */
  228. b43legacy_shm_control_word(dev, routing, offset >> 2);
  229. ret = b43legacy_read16(dev,
  230. B43legacy_MMIO_SHM_DATA_UNALIGNED);
  231. ret <<= 16;
  232. b43legacy_shm_control_word(dev, routing,
  233. (offset >> 2) + 1);
  234. ret |= b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
  235. return ret;
  236. }
  237. offset >>= 2;
  238. }
  239. b43legacy_shm_control_word(dev, routing, offset);
  240. ret = b43legacy_read32(dev, B43legacy_MMIO_SHM_DATA);
  241. return ret;
  242. }
  243. u16 b43legacy_shm_read16(struct b43legacy_wldev *dev,
  244. u16 routing, u16 offset)
  245. {
  246. u16 ret;
  247. if (routing == B43legacy_SHM_SHARED) {
  248. B43legacy_WARN_ON((offset & 0x0001) != 0);
  249. if (offset & 0x0003) {
  250. /* Unaligned access */
  251. b43legacy_shm_control_word(dev, routing, offset >> 2);
  252. ret = b43legacy_read16(dev,
  253. B43legacy_MMIO_SHM_DATA_UNALIGNED);
  254. return ret;
  255. }
  256. offset >>= 2;
  257. }
  258. b43legacy_shm_control_word(dev, routing, offset);
  259. ret = b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
  260. return ret;
  261. }
  262. void b43legacy_shm_write32(struct b43legacy_wldev *dev,
  263. u16 routing, u16 offset,
  264. u32 value)
  265. {
  266. if (routing == B43legacy_SHM_SHARED) {
  267. B43legacy_WARN_ON((offset & 0x0001) != 0);
  268. if (offset & 0x0003) {
  269. /* Unaligned access */
  270. b43legacy_shm_control_word(dev, routing, offset >> 2);
  271. mmiowb();
  272. b43legacy_write16(dev,
  273. B43legacy_MMIO_SHM_DATA_UNALIGNED,
  274. (value >> 16) & 0xffff);
  275. mmiowb();
  276. b43legacy_shm_control_word(dev, routing,
  277. (offset >> 2) + 1);
  278. mmiowb();
  279. b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA,
  280. value & 0xffff);
  281. return;
  282. }
  283. offset >>= 2;
  284. }
  285. b43legacy_shm_control_word(dev, routing, offset);
  286. mmiowb();
  287. b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, value);
  288. }
  289. void b43legacy_shm_write16(struct b43legacy_wldev *dev, u16 routing, u16 offset,
  290. u16 value)
  291. {
  292. if (routing == B43legacy_SHM_SHARED) {
  293. B43legacy_WARN_ON((offset & 0x0001) != 0);
  294. if (offset & 0x0003) {
  295. /* Unaligned access */
  296. b43legacy_shm_control_word(dev, routing, offset >> 2);
  297. mmiowb();
  298. b43legacy_write16(dev,
  299. B43legacy_MMIO_SHM_DATA_UNALIGNED,
  300. value);
  301. return;
  302. }
  303. offset >>= 2;
  304. }
  305. b43legacy_shm_control_word(dev, routing, offset);
  306. mmiowb();
  307. b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA, value);
  308. }
  309. /* Read HostFlags */
  310. u32 b43legacy_hf_read(struct b43legacy_wldev *dev)
  311. {
  312. u32 ret;
  313. ret = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  314. B43legacy_SHM_SH_HOSTFHI);
  315. ret <<= 16;
  316. ret |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  317. B43legacy_SHM_SH_HOSTFLO);
  318. return ret;
  319. }
  320. /* Write HostFlags */
  321. void b43legacy_hf_write(struct b43legacy_wldev *dev, u32 value)
  322. {
  323. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  324. B43legacy_SHM_SH_HOSTFLO,
  325. (value & 0x0000FFFF));
  326. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  327. B43legacy_SHM_SH_HOSTFHI,
  328. ((value & 0xFFFF0000) >> 16));
  329. }
  330. void b43legacy_tsf_read(struct b43legacy_wldev *dev, u64 *tsf)
  331. {
  332. /* We need to be careful. As we read the TSF from multiple
  333. * registers, we should take care of register overflows.
  334. * In theory, the whole tsf read process should be atomic.
  335. * We try to be atomic here, by restaring the read process,
  336. * if any of the high registers changed (overflew).
  337. */
  338. if (dev->dev->id.revision >= 3) {
  339. u32 low;
  340. u32 high;
  341. u32 high2;
  342. do {
  343. high = b43legacy_read32(dev,
  344. B43legacy_MMIO_REV3PLUS_TSF_HIGH);
  345. low = b43legacy_read32(dev,
  346. B43legacy_MMIO_REV3PLUS_TSF_LOW);
  347. high2 = b43legacy_read32(dev,
  348. B43legacy_MMIO_REV3PLUS_TSF_HIGH);
  349. } while (unlikely(high != high2));
  350. *tsf = high;
  351. *tsf <<= 32;
  352. *tsf |= low;
  353. } else {
  354. u64 tmp;
  355. u16 v0;
  356. u16 v1;
  357. u16 v2;
  358. u16 v3;
  359. u16 test1;
  360. u16 test2;
  361. u16 test3;
  362. do {
  363. v3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
  364. v2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
  365. v1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
  366. v0 = b43legacy_read16(dev, B43legacy_MMIO_TSF_0);
  367. test3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
  368. test2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
  369. test1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
  370. } while (v3 != test3 || v2 != test2 || v1 != test1);
  371. *tsf = v3;
  372. *tsf <<= 48;
  373. tmp = v2;
  374. tmp <<= 32;
  375. *tsf |= tmp;
  376. tmp = v1;
  377. tmp <<= 16;
  378. *tsf |= tmp;
  379. *tsf |= v0;
  380. }
  381. }
  382. static void b43legacy_time_lock(struct b43legacy_wldev *dev)
  383. {
  384. u32 status;
  385. status = b43legacy_read32(dev, B43legacy_MMIO_STATUS_BITFIELD);
  386. status |= B43legacy_SBF_TIME_UPDATE;
  387. b43legacy_write32(dev, B43legacy_MMIO_STATUS_BITFIELD, status);
  388. mmiowb();
  389. }
  390. static void b43legacy_time_unlock(struct b43legacy_wldev *dev)
  391. {
  392. u32 status;
  393. status = b43legacy_read32(dev, B43legacy_MMIO_STATUS_BITFIELD);
  394. status &= ~B43legacy_SBF_TIME_UPDATE;
  395. b43legacy_write32(dev, B43legacy_MMIO_STATUS_BITFIELD, status);
  396. }
  397. static void b43legacy_tsf_write_locked(struct b43legacy_wldev *dev, u64 tsf)
  398. {
  399. /* Be careful with the in-progress timer.
  400. * First zero out the low register, so we have a full
  401. * register-overflow duration to complete the operation.
  402. */
  403. if (dev->dev->id.revision >= 3) {
  404. u32 lo = (tsf & 0x00000000FFFFFFFFULL);
  405. u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
  406. b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW, 0);
  407. mmiowb();
  408. b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_HIGH,
  409. hi);
  410. mmiowb();
  411. b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW,
  412. lo);
  413. } else {
  414. u16 v0 = (tsf & 0x000000000000FFFFULL);
  415. u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
  416. u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
  417. u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
  418. b43legacy_write16(dev, B43legacy_MMIO_TSF_0, 0);
  419. mmiowb();
  420. b43legacy_write16(dev, B43legacy_MMIO_TSF_3, v3);
  421. mmiowb();
  422. b43legacy_write16(dev, B43legacy_MMIO_TSF_2, v2);
  423. mmiowb();
  424. b43legacy_write16(dev, B43legacy_MMIO_TSF_1, v1);
  425. mmiowb();
  426. b43legacy_write16(dev, B43legacy_MMIO_TSF_0, v0);
  427. }
  428. }
  429. void b43legacy_tsf_write(struct b43legacy_wldev *dev, u64 tsf)
  430. {
  431. b43legacy_time_lock(dev);
  432. b43legacy_tsf_write_locked(dev, tsf);
  433. b43legacy_time_unlock(dev);
  434. }
  435. static
  436. void b43legacy_macfilter_set(struct b43legacy_wldev *dev,
  437. u16 offset, const u8 *mac)
  438. {
  439. static const u8 zero_addr[ETH_ALEN] = { 0 };
  440. u16 data;
  441. if (!mac)
  442. mac = zero_addr;
  443. offset |= 0x0020;
  444. b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_CONTROL, offset);
  445. data = mac[0];
  446. data |= mac[1] << 8;
  447. b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
  448. data = mac[2];
  449. data |= mac[3] << 8;
  450. b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
  451. data = mac[4];
  452. data |= mac[5] << 8;
  453. b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
  454. }
  455. static void b43legacy_write_mac_bssid_templates(struct b43legacy_wldev *dev)
  456. {
  457. static const u8 zero_addr[ETH_ALEN] = { 0 };
  458. const u8 *mac = dev->wl->mac_addr;
  459. const u8 *bssid = dev->wl->bssid;
  460. u8 mac_bssid[ETH_ALEN * 2];
  461. int i;
  462. u32 tmp;
  463. if (!bssid)
  464. bssid = zero_addr;
  465. if (!mac)
  466. mac = zero_addr;
  467. b43legacy_macfilter_set(dev, B43legacy_MACFILTER_BSSID, bssid);
  468. memcpy(mac_bssid, mac, ETH_ALEN);
  469. memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
  470. /* Write our MAC address and BSSID to template ram */
  471. for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
  472. tmp = (u32)(mac_bssid[i + 0]);
  473. tmp |= (u32)(mac_bssid[i + 1]) << 8;
  474. tmp |= (u32)(mac_bssid[i + 2]) << 16;
  475. tmp |= (u32)(mac_bssid[i + 3]) << 24;
  476. b43legacy_ram_write(dev, 0x20 + i, tmp);
  477. b43legacy_ram_write(dev, 0x78 + i, tmp);
  478. b43legacy_ram_write(dev, 0x478 + i, tmp);
  479. }
  480. }
  481. static void b43legacy_upload_card_macaddress(struct b43legacy_wldev *dev)
  482. {
  483. b43legacy_write_mac_bssid_templates(dev);
  484. b43legacy_macfilter_set(dev, B43legacy_MACFILTER_SELF,
  485. dev->wl->mac_addr);
  486. }
  487. static void b43legacy_set_slot_time(struct b43legacy_wldev *dev,
  488. u16 slot_time)
  489. {
  490. /* slot_time is in usec. */
  491. if (dev->phy.type != B43legacy_PHYTYPE_G)
  492. return;
  493. b43legacy_write16(dev, 0x684, 510 + slot_time);
  494. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0010,
  495. slot_time);
  496. }
  497. static void b43legacy_short_slot_timing_enable(struct b43legacy_wldev *dev)
  498. {
  499. b43legacy_set_slot_time(dev, 9);
  500. dev->short_slot = 1;
  501. }
  502. static void b43legacy_short_slot_timing_disable(struct b43legacy_wldev *dev)
  503. {
  504. b43legacy_set_slot_time(dev, 20);
  505. dev->short_slot = 0;
  506. }
  507. /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
  508. * Returns the _previously_ enabled IRQ mask.
  509. */
  510. static inline u32 b43legacy_interrupt_enable(struct b43legacy_wldev *dev,
  511. u32 mask)
  512. {
  513. u32 old_mask;
  514. old_mask = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK);
  515. b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, old_mask |
  516. mask);
  517. return old_mask;
  518. }
  519. /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
  520. * Returns the _previously_ enabled IRQ mask.
  521. */
  522. static inline u32 b43legacy_interrupt_disable(struct b43legacy_wldev *dev,
  523. u32 mask)
  524. {
  525. u32 old_mask;
  526. old_mask = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK);
  527. b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
  528. return old_mask;
  529. }
  530. /* Synchronize IRQ top- and bottom-half.
  531. * IRQs must be masked before calling this.
  532. * This must not be called with the irq_lock held.
  533. */
  534. static void b43legacy_synchronize_irq(struct b43legacy_wldev *dev)
  535. {
  536. synchronize_irq(dev->dev->irq);
  537. tasklet_kill(&dev->isr_tasklet);
  538. }
  539. /* DummyTransmission function, as documented on
  540. * http://bcm-specs.sipsolutions.net/DummyTransmission
  541. */
  542. void b43legacy_dummy_transmission(struct b43legacy_wldev *dev)
  543. {
  544. struct b43legacy_phy *phy = &dev->phy;
  545. unsigned int i;
  546. unsigned int max_loop;
  547. u16 value;
  548. u32 buffer[5] = {
  549. 0x00000000,
  550. 0x00D40000,
  551. 0x00000000,
  552. 0x01000000,
  553. 0x00000000,
  554. };
  555. switch (phy->type) {
  556. case B43legacy_PHYTYPE_B:
  557. case B43legacy_PHYTYPE_G:
  558. max_loop = 0xFA;
  559. buffer[0] = 0x000B846E;
  560. break;
  561. default:
  562. B43legacy_BUG_ON(1);
  563. return;
  564. }
  565. for (i = 0; i < 5; i++)
  566. b43legacy_ram_write(dev, i * 4, buffer[i]);
  567. /* dummy read follows */
  568. b43legacy_read32(dev, B43legacy_MMIO_STATUS_BITFIELD);
  569. b43legacy_write16(dev, 0x0568, 0x0000);
  570. b43legacy_write16(dev, 0x07C0, 0x0000);
  571. b43legacy_write16(dev, 0x050C, 0x0000);
  572. b43legacy_write16(dev, 0x0508, 0x0000);
  573. b43legacy_write16(dev, 0x050A, 0x0000);
  574. b43legacy_write16(dev, 0x054C, 0x0000);
  575. b43legacy_write16(dev, 0x056A, 0x0014);
  576. b43legacy_write16(dev, 0x0568, 0x0826);
  577. b43legacy_write16(dev, 0x0500, 0x0000);
  578. b43legacy_write16(dev, 0x0502, 0x0030);
  579. if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
  580. b43legacy_radio_write16(dev, 0x0051, 0x0017);
  581. for (i = 0x00; i < max_loop; i++) {
  582. value = b43legacy_read16(dev, 0x050E);
  583. if (value & 0x0080)
  584. break;
  585. udelay(10);
  586. }
  587. for (i = 0x00; i < 0x0A; i++) {
  588. value = b43legacy_read16(dev, 0x050E);
  589. if (value & 0x0400)
  590. break;
  591. udelay(10);
  592. }
  593. for (i = 0x00; i < 0x0A; i++) {
  594. value = b43legacy_read16(dev, 0x0690);
  595. if (!(value & 0x0100))
  596. break;
  597. udelay(10);
  598. }
  599. if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
  600. b43legacy_radio_write16(dev, 0x0051, 0x0037);
  601. }
  602. /* Turn the Analog ON/OFF */
  603. static void b43legacy_switch_analog(struct b43legacy_wldev *dev, int on)
  604. {
  605. b43legacy_write16(dev, B43legacy_MMIO_PHY0, on ? 0 : 0xF4);
  606. }
  607. void b43legacy_wireless_core_reset(struct b43legacy_wldev *dev, u32 flags)
  608. {
  609. u32 tmslow;
  610. u32 macctl;
  611. flags |= B43legacy_TMSLOW_PHYCLKEN;
  612. flags |= B43legacy_TMSLOW_PHYRESET;
  613. ssb_device_enable(dev->dev, flags);
  614. msleep(2); /* Wait for the PLL to turn on. */
  615. /* Now take the PHY out of Reset again */
  616. tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
  617. tmslow |= SSB_TMSLOW_FGC;
  618. tmslow &= ~B43legacy_TMSLOW_PHYRESET;
  619. ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
  620. ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
  621. msleep(1);
  622. tmslow &= ~SSB_TMSLOW_FGC;
  623. ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
  624. ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
  625. msleep(1);
  626. /* Turn Analog ON */
  627. b43legacy_switch_analog(dev, 1);
  628. macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  629. macctl &= ~B43legacy_MACCTL_GMODE;
  630. if (flags & B43legacy_TMSLOW_GMODE) {
  631. macctl |= B43legacy_MACCTL_GMODE;
  632. dev->phy.gmode = 1;
  633. } else
  634. dev->phy.gmode = 0;
  635. macctl |= B43legacy_MACCTL_IHR_ENABLED;
  636. b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
  637. }
  638. static void handle_irq_transmit_status(struct b43legacy_wldev *dev)
  639. {
  640. u32 v0;
  641. u32 v1;
  642. u16 tmp;
  643. struct b43legacy_txstatus stat;
  644. while (1) {
  645. v0 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
  646. if (!(v0 & 0x00000001))
  647. break;
  648. v1 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
  649. stat.cookie = (v0 >> 16);
  650. stat.seq = (v1 & 0x0000FFFF);
  651. stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
  652. tmp = (v0 & 0x0000FFFF);
  653. stat.frame_count = ((tmp & 0xF000) >> 12);
  654. stat.rts_count = ((tmp & 0x0F00) >> 8);
  655. stat.supp_reason = ((tmp & 0x001C) >> 2);
  656. stat.pm_indicated = !!(tmp & 0x0080);
  657. stat.intermediate = !!(tmp & 0x0040);
  658. stat.for_ampdu = !!(tmp & 0x0020);
  659. stat.acked = !!(tmp & 0x0002);
  660. b43legacy_handle_txstatus(dev, &stat);
  661. }
  662. }
  663. static void drain_txstatus_queue(struct b43legacy_wldev *dev)
  664. {
  665. u32 dummy;
  666. if (dev->dev->id.revision < 5)
  667. return;
  668. /* Read all entries from the microcode TXstatus FIFO
  669. * and throw them away.
  670. */
  671. while (1) {
  672. dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
  673. if (!(dummy & 0x00000001))
  674. break;
  675. dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
  676. }
  677. }
  678. static u32 b43legacy_jssi_read(struct b43legacy_wldev *dev)
  679. {
  680. u32 val = 0;
  681. val = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x40A);
  682. val <<= 16;
  683. val |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x408);
  684. return val;
  685. }
  686. static void b43legacy_jssi_write(struct b43legacy_wldev *dev, u32 jssi)
  687. {
  688. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x408,
  689. (jssi & 0x0000FFFF));
  690. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x40A,
  691. (jssi & 0xFFFF0000) >> 16);
  692. }
  693. static void b43legacy_generate_noise_sample(struct b43legacy_wldev *dev)
  694. {
  695. b43legacy_jssi_write(dev, 0x7F7F7F7F);
  696. b43legacy_write32(dev, B43legacy_MMIO_STATUS2_BITFIELD,
  697. b43legacy_read32(dev,
  698. B43legacy_MMIO_STATUS2_BITFIELD)
  699. | (1 << 4));
  700. B43legacy_WARN_ON(dev->noisecalc.channel_at_start !=
  701. dev->phy.channel);
  702. }
  703. static void b43legacy_calculate_link_quality(struct b43legacy_wldev *dev)
  704. {
  705. /* Top half of Link Quality calculation. */
  706. if (dev->noisecalc.calculation_running)
  707. return;
  708. dev->noisecalc.channel_at_start = dev->phy.channel;
  709. dev->noisecalc.calculation_running = 1;
  710. dev->noisecalc.nr_samples = 0;
  711. b43legacy_generate_noise_sample(dev);
  712. }
  713. static void handle_irq_noise(struct b43legacy_wldev *dev)
  714. {
  715. struct b43legacy_phy *phy = &dev->phy;
  716. u16 tmp;
  717. u8 noise[4];
  718. u8 i;
  719. u8 j;
  720. s32 average;
  721. /* Bottom half of Link Quality calculation. */
  722. B43legacy_WARN_ON(!dev->noisecalc.calculation_running);
  723. if (dev->noisecalc.channel_at_start != phy->channel)
  724. goto drop_calculation;
  725. *((__le32 *)noise) = cpu_to_le32(b43legacy_jssi_read(dev));
  726. if (noise[0] == 0x7F || noise[1] == 0x7F ||
  727. noise[2] == 0x7F || noise[3] == 0x7F)
  728. goto generate_new;
  729. /* Get the noise samples. */
  730. B43legacy_WARN_ON(dev->noisecalc.nr_samples >= 8);
  731. i = dev->noisecalc.nr_samples;
  732. noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
  733. noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
  734. noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
  735. noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
  736. dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
  737. dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
  738. dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
  739. dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
  740. dev->noisecalc.nr_samples++;
  741. if (dev->noisecalc.nr_samples == 8) {
  742. /* Calculate the Link Quality by the noise samples. */
  743. average = 0;
  744. for (i = 0; i < 8; i++) {
  745. for (j = 0; j < 4; j++)
  746. average += dev->noisecalc.samples[i][j];
  747. }
  748. average /= (8 * 4);
  749. average *= 125;
  750. average += 64;
  751. average /= 128;
  752. tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  753. 0x40C);
  754. tmp = (tmp / 128) & 0x1F;
  755. if (tmp >= 8)
  756. average += 2;
  757. else
  758. average -= 25;
  759. if (tmp == 8)
  760. average -= 72;
  761. else
  762. average -= 48;
  763. dev->stats.link_noise = average;
  764. drop_calculation:
  765. dev->noisecalc.calculation_running = 0;
  766. return;
  767. }
  768. generate_new:
  769. b43legacy_generate_noise_sample(dev);
  770. }
  771. static void handle_irq_tbtt_indication(struct b43legacy_wldev *dev)
  772. {
  773. if (b43legacy_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
  774. /* TODO: PS TBTT */
  775. } else {
  776. if (1/*FIXME: the last PSpoll frame was sent successfully */)
  777. b43legacy_power_saving_ctl_bits(dev, -1, -1);
  778. }
  779. dev->reg124_set_0x4 = 0;
  780. if (b43legacy_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
  781. dev->reg124_set_0x4 = 1;
  782. }
  783. static void handle_irq_atim_end(struct b43legacy_wldev *dev)
  784. {
  785. if (!dev->reg124_set_0x4) /*FIXME rename this variable*/
  786. return;
  787. b43legacy_write32(dev, B43legacy_MMIO_STATUS2_BITFIELD,
  788. b43legacy_read32(dev, B43legacy_MMIO_STATUS2_BITFIELD)
  789. | 0x4);
  790. }
  791. static void handle_irq_pmq(struct b43legacy_wldev *dev)
  792. {
  793. u32 tmp;
  794. /* TODO: AP mode. */
  795. while (1) {
  796. tmp = b43legacy_read32(dev, B43legacy_MMIO_PS_STATUS);
  797. if (!(tmp & 0x00000008))
  798. break;
  799. }
  800. /* 16bit write is odd, but correct. */
  801. b43legacy_write16(dev, B43legacy_MMIO_PS_STATUS, 0x0002);
  802. }
  803. static void b43legacy_write_template_common(struct b43legacy_wldev *dev,
  804. const u8 *data, u16 size,
  805. u16 ram_offset,
  806. u16 shm_size_offset, u8 rate)
  807. {
  808. u32 i;
  809. u32 tmp;
  810. struct b43legacy_plcp_hdr4 plcp;
  811. plcp.data = 0;
  812. b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
  813. b43legacy_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
  814. ram_offset += sizeof(u32);
  815. /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
  816. * So leave the first two bytes of the next write blank.
  817. */
  818. tmp = (u32)(data[0]) << 16;
  819. tmp |= (u32)(data[1]) << 24;
  820. b43legacy_ram_write(dev, ram_offset, tmp);
  821. ram_offset += sizeof(u32);
  822. for (i = 2; i < size; i += sizeof(u32)) {
  823. tmp = (u32)(data[i + 0]);
  824. if (i + 1 < size)
  825. tmp |= (u32)(data[i + 1]) << 8;
  826. if (i + 2 < size)
  827. tmp |= (u32)(data[i + 2]) << 16;
  828. if (i + 3 < size)
  829. tmp |= (u32)(data[i + 3]) << 24;
  830. b43legacy_ram_write(dev, ram_offset + i - 2, tmp);
  831. }
  832. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_size_offset,
  833. size + sizeof(struct b43legacy_plcp_hdr6));
  834. }
  835. static void b43legacy_write_beacon_template(struct b43legacy_wldev *dev,
  836. u16 ram_offset,
  837. u16 shm_size_offset, u8 rate)
  838. {
  839. int len;
  840. const u8 *data;
  841. B43legacy_WARN_ON(!dev->cached_beacon);
  842. len = min((size_t)dev->cached_beacon->len,
  843. 0x200 - sizeof(struct b43legacy_plcp_hdr6));
  844. data = (const u8 *)(dev->cached_beacon->data);
  845. b43legacy_write_template_common(dev, data,
  846. len, ram_offset,
  847. shm_size_offset, rate);
  848. }
  849. static void b43legacy_write_probe_resp_plcp(struct b43legacy_wldev *dev,
  850. u16 shm_offset, u16 size,
  851. u8 rate)
  852. {
  853. struct b43legacy_plcp_hdr4 plcp;
  854. u32 tmp;
  855. __le16 dur;
  856. plcp.data = 0;
  857. b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
  858. dur = ieee80211_generic_frame_duration(dev->wl->hw,
  859. dev->wl->if_id,
  860. size,
  861. B43legacy_RATE_TO_100KBPS(rate));
  862. /* Write PLCP in two parts and timing for packet transfer */
  863. tmp = le32_to_cpu(plcp.data);
  864. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset,
  865. tmp & 0xFFFF);
  866. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 2,
  867. tmp >> 16);
  868. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 6,
  869. le16_to_cpu(dur));
  870. }
  871. /* Instead of using custom probe response template, this function
  872. * just patches custom beacon template by:
  873. * 1) Changing packet type
  874. * 2) Patching duration field
  875. * 3) Stripping TIM
  876. */
  877. static u8 *b43legacy_generate_probe_resp(struct b43legacy_wldev *dev,
  878. u16 *dest_size, u8 rate)
  879. {
  880. const u8 *src_data;
  881. u8 *dest_data;
  882. u16 src_size;
  883. u16 elem_size;
  884. u16 src_pos;
  885. u16 dest_pos;
  886. __le16 dur;
  887. struct ieee80211_hdr *hdr;
  888. B43legacy_WARN_ON(!dev->cached_beacon);
  889. src_size = dev->cached_beacon->len;
  890. src_data = (const u8 *)dev->cached_beacon->data;
  891. if (unlikely(src_size < 0x24)) {
  892. b43legacydbg(dev->wl, "b43legacy_generate_probe_resp: "
  893. "invalid beacon\n");
  894. return NULL;
  895. }
  896. dest_data = kmalloc(src_size, GFP_ATOMIC);
  897. if (unlikely(!dest_data))
  898. return NULL;
  899. /* 0x24 is offset of first variable-len Information-Element
  900. * in beacon frame.
  901. */
  902. memcpy(dest_data, src_data, 0x24);
  903. src_pos = 0x24;
  904. dest_pos = 0x24;
  905. for (; src_pos < src_size - 2; src_pos += elem_size) {
  906. elem_size = src_data[src_pos + 1] + 2;
  907. if (src_data[src_pos] != 0x05) { /* TIM */
  908. memcpy(dest_data + dest_pos, src_data + src_pos,
  909. elem_size);
  910. dest_pos += elem_size;
  911. }
  912. }
  913. *dest_size = dest_pos;
  914. hdr = (struct ieee80211_hdr *)dest_data;
  915. /* Set the frame control. */
  916. hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
  917. IEEE80211_STYPE_PROBE_RESP);
  918. dur = ieee80211_generic_frame_duration(dev->wl->hw,
  919. dev->wl->if_id,
  920. *dest_size,
  921. B43legacy_RATE_TO_100KBPS(rate));
  922. hdr->duration_id = dur;
  923. return dest_data;
  924. }
  925. static void b43legacy_write_probe_resp_template(struct b43legacy_wldev *dev,
  926. u16 ram_offset,
  927. u16 shm_size_offset, u8 rate)
  928. {
  929. u8 *probe_resp_data;
  930. u16 size;
  931. B43legacy_WARN_ON(!dev->cached_beacon);
  932. size = dev->cached_beacon->len;
  933. probe_resp_data = b43legacy_generate_probe_resp(dev, &size, rate);
  934. if (unlikely(!probe_resp_data))
  935. return;
  936. /* Looks like PLCP headers plus packet timings are stored for
  937. * all possible basic rates
  938. */
  939. b43legacy_write_probe_resp_plcp(dev, 0x31A, size,
  940. B43legacy_CCK_RATE_1MB);
  941. b43legacy_write_probe_resp_plcp(dev, 0x32C, size,
  942. B43legacy_CCK_RATE_2MB);
  943. b43legacy_write_probe_resp_plcp(dev, 0x33E, size,
  944. B43legacy_CCK_RATE_5MB);
  945. b43legacy_write_probe_resp_plcp(dev, 0x350, size,
  946. B43legacy_CCK_RATE_11MB);
  947. size = min((size_t)size,
  948. 0x200 - sizeof(struct b43legacy_plcp_hdr6));
  949. b43legacy_write_template_common(dev, probe_resp_data,
  950. size, ram_offset,
  951. shm_size_offset, rate);
  952. kfree(probe_resp_data);
  953. }
  954. static int b43legacy_refresh_cached_beacon(struct b43legacy_wldev *dev,
  955. struct sk_buff *beacon)
  956. {
  957. if (dev->cached_beacon)
  958. kfree_skb(dev->cached_beacon);
  959. dev->cached_beacon = beacon;
  960. return 0;
  961. }
  962. static void b43legacy_update_templates(struct b43legacy_wldev *dev)
  963. {
  964. u32 status;
  965. B43legacy_WARN_ON(!dev->cached_beacon);
  966. b43legacy_write_beacon_template(dev, 0x68, 0x18,
  967. B43legacy_CCK_RATE_1MB);
  968. b43legacy_write_beacon_template(dev, 0x468, 0x1A,
  969. B43legacy_CCK_RATE_1MB);
  970. b43legacy_write_probe_resp_template(dev, 0x268, 0x4A,
  971. B43legacy_CCK_RATE_11MB);
  972. status = b43legacy_read32(dev, B43legacy_MMIO_STATUS2_BITFIELD);
  973. status |= 0x03;
  974. b43legacy_write32(dev, B43legacy_MMIO_STATUS2_BITFIELD, status);
  975. }
  976. static void b43legacy_refresh_templates(struct b43legacy_wldev *dev,
  977. struct sk_buff *beacon)
  978. {
  979. int err;
  980. err = b43legacy_refresh_cached_beacon(dev, beacon);
  981. if (unlikely(err))
  982. return;
  983. b43legacy_update_templates(dev);
  984. }
  985. static void b43legacy_set_ssid(struct b43legacy_wldev *dev,
  986. const u8 *ssid, u8 ssid_len)
  987. {
  988. u32 tmp;
  989. u16 i;
  990. u16 len;
  991. len = min((u16)ssid_len, (u16)0x100);
  992. for (i = 0; i < len; i += sizeof(u32)) {
  993. tmp = (u32)(ssid[i + 0]);
  994. if (i + 1 < len)
  995. tmp |= (u32)(ssid[i + 1]) << 8;
  996. if (i + 2 < len)
  997. tmp |= (u32)(ssid[i + 2]) << 16;
  998. if (i + 3 < len)
  999. tmp |= (u32)(ssid[i + 3]) << 24;
  1000. b43legacy_shm_write32(dev, B43legacy_SHM_SHARED,
  1001. 0x380 + i, tmp);
  1002. }
  1003. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  1004. 0x48, len);
  1005. }
  1006. static void b43legacy_set_beacon_int(struct b43legacy_wldev *dev,
  1007. u16 beacon_int)
  1008. {
  1009. b43legacy_time_lock(dev);
  1010. if (dev->dev->id.revision >= 3)
  1011. b43legacy_write32(dev, 0x188, (beacon_int << 16));
  1012. else {
  1013. b43legacy_write16(dev, 0x606, (beacon_int >> 6));
  1014. b43legacy_write16(dev, 0x610, beacon_int);
  1015. }
  1016. b43legacy_time_unlock(dev);
  1017. }
  1018. static void handle_irq_beacon(struct b43legacy_wldev *dev)
  1019. {
  1020. u32 status;
  1021. if (!b43legacy_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
  1022. return;
  1023. dev->irq_savedstate &= ~B43legacy_IRQ_BEACON;
  1024. status = b43legacy_read32(dev, B43legacy_MMIO_STATUS2_BITFIELD);
  1025. if (!dev->cached_beacon || ((status & 0x1) && (status & 0x2))) {
  1026. /* ACK beacon IRQ. */
  1027. b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
  1028. B43legacy_IRQ_BEACON);
  1029. dev->irq_savedstate |= B43legacy_IRQ_BEACON;
  1030. if (dev->cached_beacon)
  1031. kfree_skb(dev->cached_beacon);
  1032. dev->cached_beacon = NULL;
  1033. return;
  1034. }
  1035. if (!(status & 0x1)) {
  1036. b43legacy_write_beacon_template(dev, 0x68, 0x18,
  1037. B43legacy_CCK_RATE_1MB);
  1038. status |= 0x1;
  1039. b43legacy_write32(dev, B43legacy_MMIO_STATUS2_BITFIELD,
  1040. status);
  1041. }
  1042. if (!(status & 0x2)) {
  1043. b43legacy_write_beacon_template(dev, 0x468, 0x1A,
  1044. B43legacy_CCK_RATE_1MB);
  1045. status |= 0x2;
  1046. b43legacy_write32(dev, B43legacy_MMIO_STATUS2_BITFIELD,
  1047. status);
  1048. }
  1049. }
  1050. static void handle_irq_ucode_debug(struct b43legacy_wldev *dev)
  1051. {
  1052. }
  1053. /* Interrupt handler bottom-half */
  1054. static void b43legacy_interrupt_tasklet(struct b43legacy_wldev *dev)
  1055. {
  1056. u32 reason;
  1057. u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
  1058. u32 merged_dma_reason = 0;
  1059. int i;
  1060. unsigned long flags;
  1061. spin_lock_irqsave(&dev->wl->irq_lock, flags);
  1062. B43legacy_WARN_ON(b43legacy_status(dev) <
  1063. B43legacy_STAT_INITIALIZED);
  1064. reason = dev->irq_reason;
  1065. for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
  1066. dma_reason[i] = dev->dma_reason[i];
  1067. merged_dma_reason |= dma_reason[i];
  1068. }
  1069. if (unlikely(reason & B43legacy_IRQ_MAC_TXERR))
  1070. b43legacyerr(dev->wl, "MAC transmission error\n");
  1071. if (unlikely(reason & B43legacy_IRQ_PHY_TXERR))
  1072. b43legacyerr(dev->wl, "PHY transmission error\n");
  1073. if (unlikely(merged_dma_reason & (B43legacy_DMAIRQ_FATALMASK |
  1074. B43legacy_DMAIRQ_NONFATALMASK))) {
  1075. if (merged_dma_reason & B43legacy_DMAIRQ_FATALMASK) {
  1076. b43legacyerr(dev->wl, "Fatal DMA error: "
  1077. "0x%08X, 0x%08X, 0x%08X, "
  1078. "0x%08X, 0x%08X, 0x%08X\n",
  1079. dma_reason[0], dma_reason[1],
  1080. dma_reason[2], dma_reason[3],
  1081. dma_reason[4], dma_reason[5]);
  1082. b43legacy_controller_restart(dev, "DMA error");
  1083. mmiowb();
  1084. spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
  1085. return;
  1086. }
  1087. if (merged_dma_reason & B43legacy_DMAIRQ_NONFATALMASK)
  1088. b43legacyerr(dev->wl, "DMA error: "
  1089. "0x%08X, 0x%08X, 0x%08X, "
  1090. "0x%08X, 0x%08X, 0x%08X\n",
  1091. dma_reason[0], dma_reason[1],
  1092. dma_reason[2], dma_reason[3],
  1093. dma_reason[4], dma_reason[5]);
  1094. }
  1095. if (unlikely(reason & B43legacy_IRQ_UCODE_DEBUG))
  1096. handle_irq_ucode_debug(dev);
  1097. if (reason & B43legacy_IRQ_TBTT_INDI)
  1098. handle_irq_tbtt_indication(dev);
  1099. if (reason & B43legacy_IRQ_ATIM_END)
  1100. handle_irq_atim_end(dev);
  1101. if (reason & B43legacy_IRQ_BEACON)
  1102. handle_irq_beacon(dev);
  1103. if (reason & B43legacy_IRQ_PMQ)
  1104. handle_irq_pmq(dev);
  1105. if (reason & B43legacy_IRQ_TXFIFO_FLUSH_OK)
  1106. ;/*TODO*/
  1107. if (reason & B43legacy_IRQ_NOISESAMPLE_OK)
  1108. handle_irq_noise(dev);
  1109. /* Check the DMA reason registers for received data. */
  1110. if (dma_reason[0] & B43legacy_DMAIRQ_RX_DONE) {
  1111. if (b43legacy_using_pio(dev))
  1112. b43legacy_pio_rx(dev->pio.queue0);
  1113. else
  1114. b43legacy_dma_rx(dev->dma.rx_ring0);
  1115. }
  1116. B43legacy_WARN_ON(dma_reason[1] & B43legacy_DMAIRQ_RX_DONE);
  1117. B43legacy_WARN_ON(dma_reason[2] & B43legacy_DMAIRQ_RX_DONE);
  1118. if (dma_reason[3] & B43legacy_DMAIRQ_RX_DONE) {
  1119. if (b43legacy_using_pio(dev))
  1120. b43legacy_pio_rx(dev->pio.queue3);
  1121. else
  1122. b43legacy_dma_rx(dev->dma.rx_ring3);
  1123. }
  1124. B43legacy_WARN_ON(dma_reason[4] & B43legacy_DMAIRQ_RX_DONE);
  1125. B43legacy_WARN_ON(dma_reason[5] & B43legacy_DMAIRQ_RX_DONE);
  1126. if (reason & B43legacy_IRQ_TX_OK)
  1127. handle_irq_transmit_status(dev);
  1128. b43legacy_interrupt_enable(dev, dev->irq_savedstate);
  1129. mmiowb();
  1130. spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
  1131. }
  1132. static void pio_irq_workaround(struct b43legacy_wldev *dev,
  1133. u16 base, int queueidx)
  1134. {
  1135. u16 rxctl;
  1136. rxctl = b43legacy_read16(dev, base + B43legacy_PIO_RXCTL);
  1137. if (rxctl & B43legacy_PIO_RXCTL_DATAAVAILABLE)
  1138. dev->dma_reason[queueidx] |= B43legacy_DMAIRQ_RX_DONE;
  1139. else
  1140. dev->dma_reason[queueidx] &= ~B43legacy_DMAIRQ_RX_DONE;
  1141. }
  1142. static void b43legacy_interrupt_ack(struct b43legacy_wldev *dev, u32 reason)
  1143. {
  1144. if (b43legacy_using_pio(dev) &&
  1145. (dev->dev->id.revision < 3) &&
  1146. (!(reason & B43legacy_IRQ_PIO_WORKAROUND))) {
  1147. /* Apply a PIO specific workaround to the dma_reasons */
  1148. pio_irq_workaround(dev, B43legacy_MMIO_PIO1_BASE, 0);
  1149. pio_irq_workaround(dev, B43legacy_MMIO_PIO2_BASE, 1);
  1150. pio_irq_workaround(dev, B43legacy_MMIO_PIO3_BASE, 2);
  1151. pio_irq_workaround(dev, B43legacy_MMIO_PIO4_BASE, 3);
  1152. }
  1153. b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, reason);
  1154. b43legacy_write32(dev, B43legacy_MMIO_DMA0_REASON,
  1155. dev->dma_reason[0]);
  1156. b43legacy_write32(dev, B43legacy_MMIO_DMA1_REASON,
  1157. dev->dma_reason[1]);
  1158. b43legacy_write32(dev, B43legacy_MMIO_DMA2_REASON,
  1159. dev->dma_reason[2]);
  1160. b43legacy_write32(dev, B43legacy_MMIO_DMA3_REASON,
  1161. dev->dma_reason[3]);
  1162. b43legacy_write32(dev, B43legacy_MMIO_DMA4_REASON,
  1163. dev->dma_reason[4]);
  1164. b43legacy_write32(dev, B43legacy_MMIO_DMA5_REASON,
  1165. dev->dma_reason[5]);
  1166. }
  1167. /* Interrupt handler top-half */
  1168. static irqreturn_t b43legacy_interrupt_handler(int irq, void *dev_id)
  1169. {
  1170. irqreturn_t ret = IRQ_NONE;
  1171. struct b43legacy_wldev *dev = dev_id;
  1172. u32 reason;
  1173. if (!dev)
  1174. return IRQ_NONE;
  1175. spin_lock(&dev->wl->irq_lock);
  1176. if (b43legacy_status(dev) < B43legacy_STAT_STARTED)
  1177. goto out;
  1178. reason = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
  1179. if (reason == 0xffffffff) /* shared IRQ */
  1180. goto out;
  1181. ret = IRQ_HANDLED;
  1182. reason &= b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK);
  1183. if (!reason)
  1184. goto out;
  1185. dev->dma_reason[0] = b43legacy_read32(dev,
  1186. B43legacy_MMIO_DMA0_REASON)
  1187. & 0x0001DC00;
  1188. dev->dma_reason[1] = b43legacy_read32(dev,
  1189. B43legacy_MMIO_DMA1_REASON)
  1190. & 0x0000DC00;
  1191. dev->dma_reason[2] = b43legacy_read32(dev,
  1192. B43legacy_MMIO_DMA2_REASON)
  1193. & 0x0000DC00;
  1194. dev->dma_reason[3] = b43legacy_read32(dev,
  1195. B43legacy_MMIO_DMA3_REASON)
  1196. & 0x0001DC00;
  1197. dev->dma_reason[4] = b43legacy_read32(dev,
  1198. B43legacy_MMIO_DMA4_REASON)
  1199. & 0x0000DC00;
  1200. dev->dma_reason[5] = b43legacy_read32(dev,
  1201. B43legacy_MMIO_DMA5_REASON)
  1202. & 0x0000DC00;
  1203. b43legacy_interrupt_ack(dev, reason);
  1204. /* disable all IRQs. They are enabled again in the bottom half. */
  1205. dev->irq_savedstate = b43legacy_interrupt_disable(dev,
  1206. B43legacy_IRQ_ALL);
  1207. /* save the reason code and call our bottom half. */
  1208. dev->irq_reason = reason;
  1209. tasklet_schedule(&dev->isr_tasklet);
  1210. out:
  1211. mmiowb();
  1212. spin_unlock(&dev->wl->irq_lock);
  1213. return ret;
  1214. }
  1215. static void b43legacy_release_firmware(struct b43legacy_wldev *dev)
  1216. {
  1217. release_firmware(dev->fw.ucode);
  1218. dev->fw.ucode = NULL;
  1219. release_firmware(dev->fw.pcm);
  1220. dev->fw.pcm = NULL;
  1221. release_firmware(dev->fw.initvals);
  1222. dev->fw.initvals = NULL;
  1223. release_firmware(dev->fw.initvals_band);
  1224. dev->fw.initvals_band = NULL;
  1225. }
  1226. static void b43legacy_print_fw_helptext(struct b43legacy_wl *wl)
  1227. {
  1228. b43legacyerr(wl, "You must go to http://linuxwireless.org/en/users/"
  1229. "Drivers/b43#devicefirmware "
  1230. "and download the correct firmware (version 3).\n");
  1231. }
  1232. static int do_request_fw(struct b43legacy_wldev *dev,
  1233. const char *name,
  1234. const struct firmware **fw)
  1235. {
  1236. char path[sizeof(modparam_fwpostfix) + 32];
  1237. struct b43legacy_fw_header *hdr;
  1238. u32 size;
  1239. int err;
  1240. if (!name)
  1241. return 0;
  1242. snprintf(path, ARRAY_SIZE(path),
  1243. "b43legacy%s/%s.fw",
  1244. modparam_fwpostfix, name);
  1245. err = request_firmware(fw, path, dev->dev->dev);
  1246. if (err) {
  1247. b43legacyerr(dev->wl, "Firmware file \"%s\" not found "
  1248. "or load failed.\n", path);
  1249. return err;
  1250. }
  1251. if ((*fw)->size < sizeof(struct b43legacy_fw_header))
  1252. goto err_format;
  1253. hdr = (struct b43legacy_fw_header *)((*fw)->data);
  1254. switch (hdr->type) {
  1255. case B43legacy_FW_TYPE_UCODE:
  1256. case B43legacy_FW_TYPE_PCM:
  1257. size = be32_to_cpu(hdr->size);
  1258. if (size != (*fw)->size - sizeof(struct b43legacy_fw_header))
  1259. goto err_format;
  1260. /* fallthrough */
  1261. case B43legacy_FW_TYPE_IV:
  1262. if (hdr->ver != 1)
  1263. goto err_format;
  1264. break;
  1265. default:
  1266. goto err_format;
  1267. }
  1268. return err;
  1269. err_format:
  1270. b43legacyerr(dev->wl, "Firmware file \"%s\" format error.\n", path);
  1271. return -EPROTO;
  1272. }
  1273. static int b43legacy_request_firmware(struct b43legacy_wldev *dev)
  1274. {
  1275. struct b43legacy_firmware *fw = &dev->fw;
  1276. const u8 rev = dev->dev->id.revision;
  1277. const char *filename;
  1278. u32 tmshigh;
  1279. int err;
  1280. tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
  1281. if (!fw->ucode) {
  1282. if (rev == 2)
  1283. filename = "ucode2";
  1284. else if (rev == 4)
  1285. filename = "ucode4";
  1286. else
  1287. filename = "ucode5";
  1288. err = do_request_fw(dev, filename, &fw->ucode);
  1289. if (err)
  1290. goto err_load;
  1291. }
  1292. if (!fw->pcm) {
  1293. if (rev < 5)
  1294. filename = "pcm4";
  1295. else
  1296. filename = "pcm5";
  1297. err = do_request_fw(dev, filename, &fw->pcm);
  1298. if (err)
  1299. goto err_load;
  1300. }
  1301. if (!fw->initvals) {
  1302. switch (dev->phy.type) {
  1303. case B43legacy_PHYTYPE_G:
  1304. if ((rev >= 5) && (rev <= 10))
  1305. filename = "b0g0initvals5";
  1306. else if (rev == 2 || rev == 4)
  1307. filename = "b0g0initvals2";
  1308. else
  1309. goto err_no_initvals;
  1310. break;
  1311. default:
  1312. goto err_no_initvals;
  1313. }
  1314. err = do_request_fw(dev, filename, &fw->initvals);
  1315. if (err)
  1316. goto err_load;
  1317. }
  1318. if (!fw->initvals_band) {
  1319. switch (dev->phy.type) {
  1320. case B43legacy_PHYTYPE_G:
  1321. if ((rev >= 5) && (rev <= 10))
  1322. filename = "b0g0bsinitvals5";
  1323. else if (rev >= 11)
  1324. filename = NULL;
  1325. else if (rev == 2 || rev == 4)
  1326. filename = NULL;
  1327. else
  1328. goto err_no_initvals;
  1329. break;
  1330. default:
  1331. goto err_no_initvals;
  1332. }
  1333. err = do_request_fw(dev, filename, &fw->initvals_band);
  1334. if (err)
  1335. goto err_load;
  1336. }
  1337. return 0;
  1338. err_load:
  1339. b43legacy_print_fw_helptext(dev->wl);
  1340. goto error;
  1341. err_no_initvals:
  1342. err = -ENODEV;
  1343. b43legacyerr(dev->wl, "No Initial Values firmware file for PHY %u, "
  1344. "core rev %u\n", dev->phy.type, rev);
  1345. goto error;
  1346. error:
  1347. b43legacy_release_firmware(dev);
  1348. return err;
  1349. }
  1350. static int b43legacy_upload_microcode(struct b43legacy_wldev *dev)
  1351. {
  1352. const size_t hdr_len = sizeof(struct b43legacy_fw_header);
  1353. const __be32 *data;
  1354. unsigned int i;
  1355. unsigned int len;
  1356. u16 fwrev;
  1357. u16 fwpatch;
  1358. u16 fwdate;
  1359. u16 fwtime;
  1360. u32 tmp;
  1361. int err = 0;
  1362. /* Upload Microcode. */
  1363. data = (__be32 *) (dev->fw.ucode->data + hdr_len);
  1364. len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
  1365. b43legacy_shm_control_word(dev,
  1366. B43legacy_SHM_UCODE |
  1367. B43legacy_SHM_AUTOINC_W,
  1368. 0x0000);
  1369. for (i = 0; i < len; i++) {
  1370. b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
  1371. be32_to_cpu(data[i]));
  1372. udelay(10);
  1373. }
  1374. if (dev->fw.pcm) {
  1375. /* Upload PCM data. */
  1376. data = (__be32 *) (dev->fw.pcm->data + hdr_len);
  1377. len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
  1378. b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EA);
  1379. b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, 0x00004000);
  1380. /* No need for autoinc bit in SHM_HW */
  1381. b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EB);
  1382. for (i = 0; i < len; i++) {
  1383. b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
  1384. be32_to_cpu(data[i]));
  1385. udelay(10);
  1386. }
  1387. }
  1388. b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
  1389. B43legacy_IRQ_ALL);
  1390. b43legacy_write32(dev, B43legacy_MMIO_STATUS_BITFIELD, 0x00020402);
  1391. /* Wait for the microcode to load and respond */
  1392. i = 0;
  1393. while (1) {
  1394. tmp = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
  1395. if (tmp == B43legacy_IRQ_MAC_SUSPENDED)
  1396. break;
  1397. i++;
  1398. if (i >= B43legacy_IRQWAIT_MAX_RETRIES) {
  1399. b43legacyerr(dev->wl, "Microcode not responding\n");
  1400. b43legacy_print_fw_helptext(dev->wl);
  1401. err = -ENODEV;
  1402. goto out;
  1403. }
  1404. udelay(10);
  1405. }
  1406. /* dummy read follows */
  1407. b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
  1408. /* Get and check the revisions. */
  1409. fwrev = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1410. B43legacy_SHM_SH_UCODEREV);
  1411. fwpatch = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1412. B43legacy_SHM_SH_UCODEPATCH);
  1413. fwdate = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1414. B43legacy_SHM_SH_UCODEDATE);
  1415. fwtime = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1416. B43legacy_SHM_SH_UCODETIME);
  1417. if (fwrev > 0x128) {
  1418. b43legacyerr(dev->wl, "YOU ARE TRYING TO LOAD V4 FIRMWARE."
  1419. " Only firmware from binary drivers version 3.x"
  1420. " is supported. You must change your firmware"
  1421. " files.\n");
  1422. b43legacy_print_fw_helptext(dev->wl);
  1423. b43legacy_write32(dev, B43legacy_MMIO_STATUS_BITFIELD, 0);
  1424. err = -EOPNOTSUPP;
  1425. goto out;
  1426. }
  1427. b43legacydbg(dev->wl, "Loading firmware version 0x%X, patch level %u "
  1428. "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n", fwrev, fwpatch,
  1429. (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
  1430. (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
  1431. dev->fw.rev = fwrev;
  1432. dev->fw.patch = fwpatch;
  1433. out:
  1434. return err;
  1435. }
  1436. static int b43legacy_write_initvals(struct b43legacy_wldev *dev,
  1437. const struct b43legacy_iv *ivals,
  1438. size_t count,
  1439. size_t array_size)
  1440. {
  1441. const struct b43legacy_iv *iv;
  1442. u16 offset;
  1443. size_t i;
  1444. bool bit32;
  1445. BUILD_BUG_ON(sizeof(struct b43legacy_iv) != 6);
  1446. iv = ivals;
  1447. for (i = 0; i < count; i++) {
  1448. if (array_size < sizeof(iv->offset_size))
  1449. goto err_format;
  1450. array_size -= sizeof(iv->offset_size);
  1451. offset = be16_to_cpu(iv->offset_size);
  1452. bit32 = !!(offset & B43legacy_IV_32BIT);
  1453. offset &= B43legacy_IV_OFFSET_MASK;
  1454. if (offset >= 0x1000)
  1455. goto err_format;
  1456. if (bit32) {
  1457. u32 value;
  1458. if (array_size < sizeof(iv->data.d32))
  1459. goto err_format;
  1460. array_size -= sizeof(iv->data.d32);
  1461. value = be32_to_cpu(get_unaligned(&iv->data.d32));
  1462. b43legacy_write32(dev, offset, value);
  1463. iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
  1464. sizeof(__be16) +
  1465. sizeof(__be32));
  1466. } else {
  1467. u16 value;
  1468. if (array_size < sizeof(iv->data.d16))
  1469. goto err_format;
  1470. array_size -= sizeof(iv->data.d16);
  1471. value = be16_to_cpu(iv->data.d16);
  1472. b43legacy_write16(dev, offset, value);
  1473. iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
  1474. sizeof(__be16) +
  1475. sizeof(__be16));
  1476. }
  1477. }
  1478. if (array_size)
  1479. goto err_format;
  1480. return 0;
  1481. err_format:
  1482. b43legacyerr(dev->wl, "Initial Values Firmware file-format error.\n");
  1483. b43legacy_print_fw_helptext(dev->wl);
  1484. return -EPROTO;
  1485. }
  1486. static int b43legacy_upload_initvals(struct b43legacy_wldev *dev)
  1487. {
  1488. const size_t hdr_len = sizeof(struct b43legacy_fw_header);
  1489. const struct b43legacy_fw_header *hdr;
  1490. struct b43legacy_firmware *fw = &dev->fw;
  1491. const struct b43legacy_iv *ivals;
  1492. size_t count;
  1493. int err;
  1494. hdr = (const struct b43legacy_fw_header *)(fw->initvals->data);
  1495. ivals = (const struct b43legacy_iv *)(fw->initvals->data + hdr_len);
  1496. count = be32_to_cpu(hdr->size);
  1497. err = b43legacy_write_initvals(dev, ivals, count,
  1498. fw->initvals->size - hdr_len);
  1499. if (err)
  1500. goto out;
  1501. if (fw->initvals_band) {
  1502. hdr = (const struct b43legacy_fw_header *)
  1503. (fw->initvals_band->data);
  1504. ivals = (const struct b43legacy_iv *)(fw->initvals_band->data
  1505. + hdr_len);
  1506. count = be32_to_cpu(hdr->size);
  1507. err = b43legacy_write_initvals(dev, ivals, count,
  1508. fw->initvals_band->size - hdr_len);
  1509. if (err)
  1510. goto out;
  1511. }
  1512. out:
  1513. return err;
  1514. }
  1515. /* Initialize the GPIOs
  1516. * http://bcm-specs.sipsolutions.net/GPIO
  1517. */
  1518. static int b43legacy_gpio_init(struct b43legacy_wldev *dev)
  1519. {
  1520. struct ssb_bus *bus = dev->dev->bus;
  1521. struct ssb_device *gpiodev, *pcidev = NULL;
  1522. u32 mask;
  1523. u32 set;
  1524. b43legacy_write32(dev, B43legacy_MMIO_STATUS_BITFIELD,
  1525. b43legacy_read32(dev,
  1526. B43legacy_MMIO_STATUS_BITFIELD)
  1527. & 0xFFFF3FFF);
  1528. b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
  1529. b43legacy_read16(dev,
  1530. B43legacy_MMIO_GPIO_MASK)
  1531. | 0x000F);
  1532. mask = 0x0000001F;
  1533. set = 0x0000000F;
  1534. if (dev->dev->bus->chip_id == 0x4301) {
  1535. mask |= 0x0060;
  1536. set |= 0x0060;
  1537. }
  1538. if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_PACTRL) {
  1539. b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
  1540. b43legacy_read16(dev,
  1541. B43legacy_MMIO_GPIO_MASK)
  1542. | 0x0200);
  1543. mask |= 0x0200;
  1544. set |= 0x0200;
  1545. }
  1546. if (dev->dev->id.revision >= 2)
  1547. mask |= 0x0010; /* FIXME: This is redundant. */
  1548. #ifdef CONFIG_SSB_DRIVER_PCICORE
  1549. pcidev = bus->pcicore.dev;
  1550. #endif
  1551. gpiodev = bus->chipco.dev ? : pcidev;
  1552. if (!gpiodev)
  1553. return 0;
  1554. ssb_write32(gpiodev, B43legacy_GPIO_CONTROL,
  1555. (ssb_read32(gpiodev, B43legacy_GPIO_CONTROL)
  1556. & mask) | set);
  1557. return 0;
  1558. }
  1559. /* Turn off all GPIO stuff. Call this on module unload, for example. */
  1560. static void b43legacy_gpio_cleanup(struct b43legacy_wldev *dev)
  1561. {
  1562. struct ssb_bus *bus = dev->dev->bus;
  1563. struct ssb_device *gpiodev, *pcidev = NULL;
  1564. #ifdef CONFIG_SSB_DRIVER_PCICORE
  1565. pcidev = bus->pcicore.dev;
  1566. #endif
  1567. gpiodev = bus->chipco.dev ? : pcidev;
  1568. if (!gpiodev)
  1569. return;
  1570. ssb_write32(gpiodev, B43legacy_GPIO_CONTROL, 0);
  1571. }
  1572. /* http://bcm-specs.sipsolutions.net/EnableMac */
  1573. void b43legacy_mac_enable(struct b43legacy_wldev *dev)
  1574. {
  1575. dev->mac_suspended--;
  1576. B43legacy_WARN_ON(dev->mac_suspended < 0);
  1577. B43legacy_WARN_ON(irqs_disabled());
  1578. if (dev->mac_suspended == 0) {
  1579. b43legacy_write32(dev, B43legacy_MMIO_STATUS_BITFIELD,
  1580. b43legacy_read32(dev,
  1581. B43legacy_MMIO_STATUS_BITFIELD)
  1582. | B43legacy_SBF_MAC_ENABLED);
  1583. b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
  1584. B43legacy_IRQ_MAC_SUSPENDED);
  1585. /* the next two are dummy reads */
  1586. b43legacy_read32(dev, B43legacy_MMIO_STATUS_BITFIELD);
  1587. b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
  1588. b43legacy_power_saving_ctl_bits(dev, -1, -1);
  1589. /* Re-enable IRQs. */
  1590. spin_lock_irq(&dev->wl->irq_lock);
  1591. b43legacy_interrupt_enable(dev, dev->irq_savedstate);
  1592. spin_unlock_irq(&dev->wl->irq_lock);
  1593. }
  1594. }
  1595. /* http://bcm-specs.sipsolutions.net/SuspendMAC */
  1596. void b43legacy_mac_suspend(struct b43legacy_wldev *dev)
  1597. {
  1598. int i;
  1599. u32 tmp;
  1600. might_sleep();
  1601. B43legacy_WARN_ON(irqs_disabled());
  1602. B43legacy_WARN_ON(dev->mac_suspended < 0);
  1603. if (dev->mac_suspended == 0) {
  1604. /* Mask IRQs before suspending MAC. Otherwise
  1605. * the MAC stays busy and won't suspend. */
  1606. spin_lock_irq(&dev->wl->irq_lock);
  1607. tmp = b43legacy_interrupt_disable(dev, B43legacy_IRQ_ALL);
  1608. spin_unlock_irq(&dev->wl->irq_lock);
  1609. b43legacy_synchronize_irq(dev);
  1610. dev->irq_savedstate = tmp;
  1611. b43legacy_power_saving_ctl_bits(dev, -1, 1);
  1612. b43legacy_write32(dev, B43legacy_MMIO_STATUS_BITFIELD,
  1613. b43legacy_read32(dev,
  1614. B43legacy_MMIO_STATUS_BITFIELD)
  1615. & ~B43legacy_SBF_MAC_ENABLED);
  1616. b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
  1617. for (i = 40; i; i--) {
  1618. tmp = b43legacy_read32(dev,
  1619. B43legacy_MMIO_GEN_IRQ_REASON);
  1620. if (tmp & B43legacy_IRQ_MAC_SUSPENDED)
  1621. goto out;
  1622. msleep(1);
  1623. }
  1624. b43legacyerr(dev->wl, "MAC suspend failed\n");
  1625. }
  1626. out:
  1627. dev->mac_suspended++;
  1628. }
  1629. static void b43legacy_adjust_opmode(struct b43legacy_wldev *dev)
  1630. {
  1631. struct b43legacy_wl *wl = dev->wl;
  1632. u32 ctl;
  1633. u16 cfp_pretbtt;
  1634. ctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  1635. /* Reset status to STA infrastructure mode. */
  1636. ctl &= ~B43legacy_MACCTL_AP;
  1637. ctl &= ~B43legacy_MACCTL_KEEP_CTL;
  1638. ctl &= ~B43legacy_MACCTL_KEEP_BADPLCP;
  1639. ctl &= ~B43legacy_MACCTL_KEEP_BAD;
  1640. ctl &= ~B43legacy_MACCTL_PROMISC;
  1641. ctl &= ~B43legacy_MACCTL_BEACPROMISC;
  1642. ctl |= B43legacy_MACCTL_INFRA;
  1643. if (b43legacy_is_mode(wl, IEEE80211_IF_TYPE_AP))
  1644. ctl |= B43legacy_MACCTL_AP;
  1645. else if (b43legacy_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
  1646. ctl &= ~B43legacy_MACCTL_INFRA;
  1647. if (wl->filter_flags & FIF_CONTROL)
  1648. ctl |= B43legacy_MACCTL_KEEP_CTL;
  1649. if (wl->filter_flags & FIF_FCSFAIL)
  1650. ctl |= B43legacy_MACCTL_KEEP_BAD;
  1651. if (wl->filter_flags & FIF_PLCPFAIL)
  1652. ctl |= B43legacy_MACCTL_KEEP_BADPLCP;
  1653. if (wl->filter_flags & FIF_PROMISC_IN_BSS)
  1654. ctl |= B43legacy_MACCTL_PROMISC;
  1655. if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
  1656. ctl |= B43legacy_MACCTL_BEACPROMISC;
  1657. /* Workaround: On old hardware the HW-MAC-address-filter
  1658. * doesn't work properly, so always run promisc in filter
  1659. * it in software. */
  1660. if (dev->dev->id.revision <= 4)
  1661. ctl |= B43legacy_MACCTL_PROMISC;
  1662. b43legacy_write32(dev, B43legacy_MMIO_MACCTL, ctl);
  1663. cfp_pretbtt = 2;
  1664. if ((ctl & B43legacy_MACCTL_INFRA) &&
  1665. !(ctl & B43legacy_MACCTL_AP)) {
  1666. if (dev->dev->bus->chip_id == 0x4306 &&
  1667. dev->dev->bus->chip_rev == 3)
  1668. cfp_pretbtt = 100;
  1669. else
  1670. cfp_pretbtt = 50;
  1671. }
  1672. b43legacy_write16(dev, 0x612, cfp_pretbtt);
  1673. }
  1674. static void b43legacy_rate_memory_write(struct b43legacy_wldev *dev,
  1675. u16 rate,
  1676. int is_ofdm)
  1677. {
  1678. u16 offset;
  1679. if (is_ofdm) {
  1680. offset = 0x480;
  1681. offset += (b43legacy_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
  1682. } else {
  1683. offset = 0x4C0;
  1684. offset += (b43legacy_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
  1685. }
  1686. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, offset + 0x20,
  1687. b43legacy_shm_read16(dev,
  1688. B43legacy_SHM_SHARED, offset));
  1689. }
  1690. static void b43legacy_rate_memory_init(struct b43legacy_wldev *dev)
  1691. {
  1692. switch (dev->phy.type) {
  1693. case B43legacy_PHYTYPE_G:
  1694. b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_6MB, 1);
  1695. b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_12MB, 1);
  1696. b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_18MB, 1);
  1697. b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_24MB, 1);
  1698. b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_36MB, 1);
  1699. b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_48MB, 1);
  1700. b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_54MB, 1);
  1701. /* fallthrough */
  1702. case B43legacy_PHYTYPE_B:
  1703. b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_1MB, 0);
  1704. b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_2MB, 0);
  1705. b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_5MB, 0);
  1706. b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_11MB, 0);
  1707. break;
  1708. default:
  1709. B43legacy_BUG_ON(1);
  1710. }
  1711. }
  1712. /* Set the TX-Antenna for management frames sent by firmware. */
  1713. static void b43legacy_mgmtframe_txantenna(struct b43legacy_wldev *dev,
  1714. int antenna)
  1715. {
  1716. u16 ant = 0;
  1717. u16 tmp;
  1718. switch (antenna) {
  1719. case B43legacy_ANTENNA0:
  1720. ant |= B43legacy_TX4_PHY_ANT0;
  1721. break;
  1722. case B43legacy_ANTENNA1:
  1723. ant |= B43legacy_TX4_PHY_ANT1;
  1724. break;
  1725. case B43legacy_ANTENNA_AUTO:
  1726. ant |= B43legacy_TX4_PHY_ANTLAST;
  1727. break;
  1728. default:
  1729. B43legacy_BUG_ON(1);
  1730. }
  1731. /* FIXME We also need to set the other flags of the PHY control
  1732. * field somewhere. */
  1733. /* For Beacons */
  1734. tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1735. B43legacy_SHM_SH_BEACPHYCTL);
  1736. tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
  1737. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  1738. B43legacy_SHM_SH_BEACPHYCTL, tmp);
  1739. /* For ACK/CTS */
  1740. tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1741. B43legacy_SHM_SH_ACKCTSPHYCTL);
  1742. tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
  1743. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  1744. B43legacy_SHM_SH_ACKCTSPHYCTL, tmp);
  1745. /* For Probe Resposes */
  1746. tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1747. B43legacy_SHM_SH_PRPHYCTL);
  1748. tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
  1749. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  1750. B43legacy_SHM_SH_PRPHYCTL, tmp);
  1751. }
  1752. /* This is the opposite of b43legacy_chip_init() */
  1753. static void b43legacy_chip_exit(struct b43legacy_wldev *dev)
  1754. {
  1755. b43legacy_radio_turn_off(dev, 1);
  1756. b43legacy_leds_exit(dev);
  1757. b43legacy_gpio_cleanup(dev);
  1758. /* firmware is released later */
  1759. }
  1760. /* Initialize the chip
  1761. * http://bcm-specs.sipsolutions.net/ChipInit
  1762. */
  1763. static int b43legacy_chip_init(struct b43legacy_wldev *dev)
  1764. {
  1765. struct b43legacy_phy *phy = &dev->phy;
  1766. int err;
  1767. int tmp;
  1768. u32 value32;
  1769. u16 value16;
  1770. b43legacy_write32(dev, B43legacy_MMIO_STATUS_BITFIELD,
  1771. B43legacy_SBF_CORE_READY
  1772. | B43legacy_SBF_400);
  1773. err = b43legacy_request_firmware(dev);
  1774. if (err)
  1775. goto out;
  1776. err = b43legacy_upload_microcode(dev);
  1777. if (err)
  1778. goto out; /* firmware is released later */
  1779. err = b43legacy_gpio_init(dev);
  1780. if (err)
  1781. goto out; /* firmware is released later */
  1782. b43legacy_leds_init(dev);
  1783. err = b43legacy_upload_initvals(dev);
  1784. if (err)
  1785. goto err_leds_exit;
  1786. b43legacy_radio_turn_on(dev);
  1787. b43legacy_write16(dev, 0x03E6, 0x0000);
  1788. err = b43legacy_phy_init(dev);
  1789. if (err)
  1790. goto err_radio_off;
  1791. /* Select initial Interference Mitigation. */
  1792. tmp = phy->interfmode;
  1793. phy->interfmode = B43legacy_INTERFMODE_NONE;
  1794. b43legacy_radio_set_interference_mitigation(dev, tmp);
  1795. b43legacy_phy_set_antenna_diversity(dev);
  1796. b43legacy_mgmtframe_txantenna(dev, B43legacy_ANTENNA_DEFAULT);
  1797. if (phy->type == B43legacy_PHYTYPE_B) {
  1798. value16 = b43legacy_read16(dev, 0x005E);
  1799. value16 |= 0x0004;
  1800. b43legacy_write16(dev, 0x005E, value16);
  1801. }
  1802. b43legacy_write32(dev, 0x0100, 0x01000000);
  1803. if (dev->dev->id.revision < 5)
  1804. b43legacy_write32(dev, 0x010C, 0x01000000);
  1805. value32 = b43legacy_read32(dev, B43legacy_MMIO_STATUS_BITFIELD);
  1806. value32 &= ~B43legacy_SBF_MODE_NOTADHOC;
  1807. b43legacy_write32(dev, B43legacy_MMIO_STATUS_BITFIELD, value32);
  1808. value32 = b43legacy_read32(dev, B43legacy_MMIO_STATUS_BITFIELD);
  1809. value32 |= B43legacy_SBF_MODE_NOTADHOC;
  1810. b43legacy_write32(dev, B43legacy_MMIO_STATUS_BITFIELD, value32);
  1811. if (b43legacy_using_pio(dev)) {
  1812. b43legacy_write32(dev, 0x0210, 0x00000100);
  1813. b43legacy_write32(dev, 0x0230, 0x00000100);
  1814. b43legacy_write32(dev, 0x0250, 0x00000100);
  1815. b43legacy_write32(dev, 0x0270, 0x00000100);
  1816. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0034,
  1817. 0x0000);
  1818. }
  1819. /* Probe Response Timeout value */
  1820. /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
  1821. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0074, 0x0000);
  1822. /* Initially set the wireless operation mode. */
  1823. b43legacy_adjust_opmode(dev);
  1824. if (dev->dev->id.revision < 3) {
  1825. b43legacy_write16(dev, 0x060E, 0x0000);
  1826. b43legacy_write16(dev, 0x0610, 0x8000);
  1827. b43legacy_write16(dev, 0x0604, 0x0000);
  1828. b43legacy_write16(dev, 0x0606, 0x0200);
  1829. } else {
  1830. b43legacy_write32(dev, 0x0188, 0x80000000);
  1831. b43legacy_write32(dev, 0x018C, 0x02000000);
  1832. }
  1833. b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, 0x00004000);
  1834. b43legacy_write32(dev, B43legacy_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
  1835. b43legacy_write32(dev, B43legacy_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
  1836. b43legacy_write32(dev, B43legacy_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
  1837. b43legacy_write32(dev, B43legacy_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
  1838. b43legacy_write32(dev, B43legacy_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
  1839. b43legacy_write32(dev, B43legacy_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
  1840. value32 = ssb_read32(dev->dev, SSB_TMSLOW);
  1841. value32 |= 0x00100000;
  1842. ssb_write32(dev->dev, SSB_TMSLOW, value32);
  1843. b43legacy_write16(dev, B43legacy_MMIO_POWERUP_DELAY,
  1844. dev->dev->bus->chipco.fast_pwrup_delay);
  1845. B43legacy_WARN_ON(err != 0);
  1846. b43legacydbg(dev->wl, "Chip initialized\n");
  1847. out:
  1848. return err;
  1849. err_radio_off:
  1850. b43legacy_radio_turn_off(dev, 1);
  1851. err_leds_exit:
  1852. b43legacy_leds_exit(dev);
  1853. b43legacy_gpio_cleanup(dev);
  1854. goto out;
  1855. }
  1856. static void b43legacy_periodic_every120sec(struct b43legacy_wldev *dev)
  1857. {
  1858. struct b43legacy_phy *phy = &dev->phy;
  1859. if (phy->type != B43legacy_PHYTYPE_G || phy->rev < 2)
  1860. return;
  1861. b43legacy_mac_suspend(dev);
  1862. b43legacy_phy_lo_g_measure(dev);
  1863. b43legacy_mac_enable(dev);
  1864. }
  1865. static void b43legacy_periodic_every60sec(struct b43legacy_wldev *dev)
  1866. {
  1867. b43legacy_phy_lo_mark_all_unused(dev);
  1868. if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_RSSI) {
  1869. b43legacy_mac_suspend(dev);
  1870. b43legacy_calc_nrssi_slope(dev);
  1871. b43legacy_mac_enable(dev);
  1872. }
  1873. }
  1874. static void b43legacy_periodic_every30sec(struct b43legacy_wldev *dev)
  1875. {
  1876. /* Update device statistics. */
  1877. b43legacy_calculate_link_quality(dev);
  1878. }
  1879. static void b43legacy_periodic_every15sec(struct b43legacy_wldev *dev)
  1880. {
  1881. b43legacy_phy_xmitpower(dev); /* FIXME: unless scanning? */
  1882. }
  1883. static void do_periodic_work(struct b43legacy_wldev *dev)
  1884. {
  1885. unsigned int state;
  1886. state = dev->periodic_state;
  1887. if (state % 8 == 0)
  1888. b43legacy_periodic_every120sec(dev);
  1889. if (state % 4 == 0)
  1890. b43legacy_periodic_every60sec(dev);
  1891. if (state % 2 == 0)
  1892. b43legacy_periodic_every30sec(dev);
  1893. b43legacy_periodic_every15sec(dev);
  1894. }
  1895. /* Periodic work locking policy:
  1896. * The whole periodic work handler is protected by
  1897. * wl->mutex. If another lock is needed somewhere in the
  1898. * pwork callchain, it's aquired in-place, where it's needed.
  1899. */
  1900. static void b43legacy_periodic_work_handler(struct work_struct *work)
  1901. {
  1902. struct b43legacy_wldev *dev = container_of(work, struct b43legacy_wldev,
  1903. periodic_work.work);
  1904. struct b43legacy_wl *wl = dev->wl;
  1905. unsigned long delay;
  1906. mutex_lock(&wl->mutex);
  1907. if (unlikely(b43legacy_status(dev) != B43legacy_STAT_STARTED))
  1908. goto out;
  1909. if (b43legacy_debug(dev, B43legacy_DBG_PWORK_STOP))
  1910. goto out_requeue;
  1911. do_periodic_work(dev);
  1912. dev->periodic_state++;
  1913. out_requeue:
  1914. if (b43legacy_debug(dev, B43legacy_DBG_PWORK_FAST))
  1915. delay = msecs_to_jiffies(50);
  1916. else
  1917. delay = round_jiffies_relative(HZ * 15);
  1918. queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
  1919. out:
  1920. mutex_unlock(&wl->mutex);
  1921. }
  1922. static void b43legacy_periodic_tasks_setup(struct b43legacy_wldev *dev)
  1923. {
  1924. struct delayed_work *work = &dev->periodic_work;
  1925. dev->periodic_state = 0;
  1926. INIT_DELAYED_WORK(work, b43legacy_periodic_work_handler);
  1927. queue_delayed_work(dev->wl->hw->workqueue, work, 0);
  1928. }
  1929. /* Validate access to the chip (SHM) */
  1930. static int b43legacy_validate_chipaccess(struct b43legacy_wldev *dev)
  1931. {
  1932. u32 value;
  1933. u32 shm_backup;
  1934. shm_backup = b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0);
  1935. b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0xAA5555AA);
  1936. if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
  1937. 0xAA5555AA)
  1938. goto error;
  1939. b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0x55AAAA55);
  1940. if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
  1941. 0x55AAAA55)
  1942. goto error;
  1943. b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, shm_backup);
  1944. value = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
  1945. if ((value | B43legacy_MACCTL_GMODE) !=
  1946. (B43legacy_MACCTL_GMODE | B43legacy_MACCTL_IHR_ENABLED))
  1947. goto error;
  1948. value = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
  1949. if (value)
  1950. goto error;
  1951. return 0;
  1952. error:
  1953. b43legacyerr(dev->wl, "Failed to validate the chipaccess\n");
  1954. return -ENODEV;
  1955. }
  1956. static void b43legacy_security_init(struct b43legacy_wldev *dev)
  1957. {
  1958. dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
  1959. B43legacy_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
  1960. dev->ktp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
  1961. 0x0056);
  1962. /* KTP is a word address, but we address SHM bytewise.
  1963. * So multiply by two.
  1964. */
  1965. dev->ktp *= 2;
  1966. if (dev->dev->id.revision >= 5)
  1967. /* Number of RCMTA address slots */
  1968. b43legacy_write16(dev, B43legacy_MMIO_RCMTA_COUNT,
  1969. dev->max_nr_keys - 8);
  1970. }
  1971. static int b43legacy_rng_read(struct hwrng *rng, u32 *data)
  1972. {
  1973. struct b43legacy_wl *wl = (struct b43legacy_wl *)rng->priv;
  1974. unsigned long flags;
  1975. /* Don't take wl->mutex here, as it could deadlock with
  1976. * hwrng internal locking. It's not needed to take
  1977. * wl->mutex here, anyway. */
  1978. spin_lock_irqsave(&wl->irq_lock, flags);
  1979. *data = b43legacy_read16(wl->current_dev, B43legacy_MMIO_RNG);
  1980. spin_unlock_irqrestore(&wl->irq_lock, flags);
  1981. return (sizeof(u16));
  1982. }
  1983. static void b43legacy_rng_exit(struct b43legacy_wl *wl)
  1984. {
  1985. if (wl->rng_initialized)
  1986. hwrng_unregister(&wl->rng);
  1987. }
  1988. static int b43legacy_rng_init(struct b43legacy_wl *wl)
  1989. {
  1990. int err;
  1991. snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
  1992. "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
  1993. wl->rng.name = wl->rng_name;
  1994. wl->rng.data_read = b43legacy_rng_read;
  1995. wl->rng.priv = (unsigned long)wl;
  1996. wl->rng_initialized = 1;
  1997. err = hwrng_register(&wl->rng);
  1998. if (err) {
  1999. wl->rng_initialized = 0;
  2000. b43legacyerr(wl, "Failed to register the random "
  2001. "number generator (%d)\n", err);
  2002. }
  2003. return err;
  2004. }
  2005. static int b43legacy_op_tx(struct ieee80211_hw *hw,
  2006. struct sk_buff *skb,
  2007. struct ieee80211_tx_control *ctl)
  2008. {
  2009. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2010. struct b43legacy_wldev *dev = wl->current_dev;
  2011. int err = -ENODEV;
  2012. unsigned long flags;
  2013. if (unlikely(!dev))
  2014. goto out;
  2015. if (unlikely(b43legacy_status(dev) < B43legacy_STAT_STARTED))
  2016. goto out;
  2017. /* DMA-TX is done without a global lock. */
  2018. if (b43legacy_using_pio(dev)) {
  2019. spin_lock_irqsave(&wl->irq_lock, flags);
  2020. err = b43legacy_pio_tx(dev, skb, ctl);
  2021. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2022. } else
  2023. err = b43legacy_dma_tx(dev, skb, ctl);
  2024. out:
  2025. if (unlikely(err))
  2026. return NETDEV_TX_BUSY;
  2027. return NETDEV_TX_OK;
  2028. }
  2029. static int b43legacy_op_conf_tx(struct ieee80211_hw *hw,
  2030. int queue,
  2031. const struct ieee80211_tx_queue_params *params)
  2032. {
  2033. return 0;
  2034. }
  2035. static int b43legacy_op_get_tx_stats(struct ieee80211_hw *hw,
  2036. struct ieee80211_tx_queue_stats *stats)
  2037. {
  2038. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2039. struct b43legacy_wldev *dev = wl->current_dev;
  2040. unsigned long flags;
  2041. int err = -ENODEV;
  2042. if (!dev)
  2043. goto out;
  2044. spin_lock_irqsave(&wl->irq_lock, flags);
  2045. if (likely(b43legacy_status(dev) >= B43legacy_STAT_STARTED)) {
  2046. if (b43legacy_using_pio(dev))
  2047. b43legacy_pio_get_tx_stats(dev, stats);
  2048. else
  2049. b43legacy_dma_get_tx_stats(dev, stats);
  2050. err = 0;
  2051. }
  2052. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2053. out:
  2054. return err;
  2055. }
  2056. static int b43legacy_op_get_stats(struct ieee80211_hw *hw,
  2057. struct ieee80211_low_level_stats *stats)
  2058. {
  2059. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2060. unsigned long flags;
  2061. spin_lock_irqsave(&wl->irq_lock, flags);
  2062. memcpy(stats, &wl->ieee_stats, sizeof(*stats));
  2063. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2064. return 0;
  2065. }
  2066. static const char *phymode_to_string(unsigned int phymode)
  2067. {
  2068. switch (phymode) {
  2069. case B43legacy_PHYMODE_B:
  2070. return "B";
  2071. case B43legacy_PHYMODE_G:
  2072. return "G";
  2073. default:
  2074. B43legacy_BUG_ON(1);
  2075. }
  2076. return "";
  2077. }
  2078. static int find_wldev_for_phymode(struct b43legacy_wl *wl,
  2079. unsigned int phymode,
  2080. struct b43legacy_wldev **dev,
  2081. bool *gmode)
  2082. {
  2083. struct b43legacy_wldev *d;
  2084. list_for_each_entry(d, &wl->devlist, list) {
  2085. if (d->phy.possible_phymodes & phymode) {
  2086. /* Ok, this device supports the PHY-mode.
  2087. * Set the gmode bit. */
  2088. *gmode = 1;
  2089. *dev = d;
  2090. return 0;
  2091. }
  2092. }
  2093. return -ESRCH;
  2094. }
  2095. static void b43legacy_put_phy_into_reset(struct b43legacy_wldev *dev)
  2096. {
  2097. struct ssb_device *sdev = dev->dev;
  2098. u32 tmslow;
  2099. tmslow = ssb_read32(sdev, SSB_TMSLOW);
  2100. tmslow &= ~B43legacy_TMSLOW_GMODE;
  2101. tmslow |= B43legacy_TMSLOW_PHYRESET;
  2102. tmslow |= SSB_TMSLOW_FGC;
  2103. ssb_write32(sdev, SSB_TMSLOW, tmslow);
  2104. msleep(1);
  2105. tmslow = ssb_read32(sdev, SSB_TMSLOW);
  2106. tmslow &= ~SSB_TMSLOW_FGC;
  2107. tmslow |= B43legacy_TMSLOW_PHYRESET;
  2108. ssb_write32(sdev, SSB_TMSLOW, tmslow);
  2109. msleep(1);
  2110. }
  2111. /* Expects wl->mutex locked */
  2112. static int b43legacy_switch_phymode(struct b43legacy_wl *wl,
  2113. unsigned int new_mode)
  2114. {
  2115. struct b43legacy_wldev *up_dev;
  2116. struct b43legacy_wldev *down_dev;
  2117. int err;
  2118. bool gmode = 0;
  2119. int prev_status;
  2120. err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
  2121. if (err) {
  2122. b43legacyerr(wl, "Could not find a device for %s-PHY mode\n",
  2123. phymode_to_string(new_mode));
  2124. return err;
  2125. }
  2126. if ((up_dev == wl->current_dev) &&
  2127. (!!wl->current_dev->phy.gmode == !!gmode))
  2128. /* This device is already running. */
  2129. return 0;
  2130. b43legacydbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
  2131. phymode_to_string(new_mode));
  2132. down_dev = wl->current_dev;
  2133. prev_status = b43legacy_status(down_dev);
  2134. /* Shutdown the currently running core. */
  2135. if (prev_status >= B43legacy_STAT_STARTED)
  2136. b43legacy_wireless_core_stop(down_dev);
  2137. if (prev_status >= B43legacy_STAT_INITIALIZED)
  2138. b43legacy_wireless_core_exit(down_dev);
  2139. if (down_dev != up_dev)
  2140. /* We switch to a different core, so we put PHY into
  2141. * RESET on the old core. */
  2142. b43legacy_put_phy_into_reset(down_dev);
  2143. /* Now start the new core. */
  2144. up_dev->phy.gmode = gmode;
  2145. if (prev_status >= B43legacy_STAT_INITIALIZED) {
  2146. err = b43legacy_wireless_core_init(up_dev);
  2147. if (err) {
  2148. b43legacyerr(wl, "Fatal: Could not initialize device"
  2149. " for newly selected %s-PHY mode\n",
  2150. phymode_to_string(new_mode));
  2151. goto init_failure;
  2152. }
  2153. }
  2154. if (prev_status >= B43legacy_STAT_STARTED) {
  2155. err = b43legacy_wireless_core_start(up_dev);
  2156. if (err) {
  2157. b43legacyerr(wl, "Fatal: Coult not start device for "
  2158. "newly selected %s-PHY mode\n",
  2159. phymode_to_string(new_mode));
  2160. b43legacy_wireless_core_exit(up_dev);
  2161. goto init_failure;
  2162. }
  2163. }
  2164. B43legacy_WARN_ON(b43legacy_status(up_dev) != prev_status);
  2165. b43legacy_shm_write32(up_dev, B43legacy_SHM_SHARED, 0x003E, 0);
  2166. wl->current_dev = up_dev;
  2167. return 0;
  2168. init_failure:
  2169. /* Whoops, failed to init the new core. No core is operating now. */
  2170. wl->current_dev = NULL;
  2171. return err;
  2172. }
  2173. static int b43legacy_antenna_from_ieee80211(u8 antenna)
  2174. {
  2175. switch (antenna) {
  2176. case 0: /* default/diversity */
  2177. return B43legacy_ANTENNA_DEFAULT;
  2178. case 1: /* Antenna 0 */
  2179. return B43legacy_ANTENNA0;
  2180. case 2: /* Antenna 1 */
  2181. return B43legacy_ANTENNA1;
  2182. default:
  2183. return B43legacy_ANTENNA_DEFAULT;
  2184. }
  2185. }
  2186. static int b43legacy_op_dev_config(struct ieee80211_hw *hw,
  2187. struct ieee80211_conf *conf)
  2188. {
  2189. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2190. struct b43legacy_wldev *dev;
  2191. struct b43legacy_phy *phy;
  2192. unsigned long flags;
  2193. unsigned int new_phymode = 0xFFFF;
  2194. int antenna_tx;
  2195. int antenna_rx;
  2196. int err = 0;
  2197. u32 savedirqs;
  2198. antenna_tx = b43legacy_antenna_from_ieee80211(conf->antenna_sel_tx);
  2199. antenna_rx = b43legacy_antenna_from_ieee80211(conf->antenna_sel_rx);
  2200. mutex_lock(&wl->mutex);
  2201. /* Switch the PHY mode (if necessary). */
  2202. switch (conf->phymode) {
  2203. case MODE_IEEE80211B:
  2204. new_phymode = B43legacy_PHYMODE_B;
  2205. break;
  2206. case MODE_IEEE80211G:
  2207. new_phymode = B43legacy_PHYMODE_G;
  2208. break;
  2209. default:
  2210. B43legacy_WARN_ON(1);
  2211. }
  2212. err = b43legacy_switch_phymode(wl, new_phymode);
  2213. if (err)
  2214. goto out_unlock_mutex;
  2215. dev = wl->current_dev;
  2216. phy = &dev->phy;
  2217. /* Disable IRQs while reconfiguring the device.
  2218. * This makes it possible to drop the spinlock throughout
  2219. * the reconfiguration process. */
  2220. spin_lock_irqsave(&wl->irq_lock, flags);
  2221. if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
  2222. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2223. goto out_unlock_mutex;
  2224. }
  2225. savedirqs = b43legacy_interrupt_disable(dev, B43legacy_IRQ_ALL);
  2226. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2227. b43legacy_synchronize_irq(dev);
  2228. /* Switch to the requested channel.
  2229. * The firmware takes care of races with the TX handler. */
  2230. if (conf->channel_val != phy->channel)
  2231. b43legacy_radio_selectchannel(dev, conf->channel_val, 0);
  2232. /* Enable/Disable ShortSlot timing. */
  2233. if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME))
  2234. != dev->short_slot) {
  2235. B43legacy_WARN_ON(phy->type != B43legacy_PHYTYPE_G);
  2236. if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
  2237. b43legacy_short_slot_timing_enable(dev);
  2238. else
  2239. b43legacy_short_slot_timing_disable(dev);
  2240. }
  2241. dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
  2242. /* Adjust the desired TX power level. */
  2243. if (conf->power_level != 0) {
  2244. if (conf->power_level != phy->power_level) {
  2245. phy->power_level = conf->power_level;
  2246. b43legacy_phy_xmitpower(dev);
  2247. }
  2248. }
  2249. /* Antennas for RX and management frame TX. */
  2250. b43legacy_mgmtframe_txantenna(dev, antenna_tx);
  2251. /* Update templates for AP mode. */
  2252. if (b43legacy_is_mode(wl, IEEE80211_IF_TYPE_AP))
  2253. b43legacy_set_beacon_int(dev, conf->beacon_int);
  2254. if (!!conf->radio_enabled != phy->radio_on) {
  2255. if (conf->radio_enabled) {
  2256. b43legacy_radio_turn_on(dev);
  2257. b43legacyinfo(dev->wl, "Radio turned on by software\n");
  2258. if (!dev->radio_hw_enable)
  2259. b43legacyinfo(dev->wl, "The hardware RF-kill"
  2260. " button still turns the radio"
  2261. " physically off. Press the"
  2262. " button to turn it on.\n");
  2263. } else {
  2264. b43legacy_radio_turn_off(dev, 0);
  2265. b43legacyinfo(dev->wl, "Radio turned off by"
  2266. " software\n");
  2267. }
  2268. }
  2269. spin_lock_irqsave(&wl->irq_lock, flags);
  2270. b43legacy_interrupt_enable(dev, savedirqs);
  2271. mmiowb();
  2272. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2273. out_unlock_mutex:
  2274. mutex_unlock(&wl->mutex);
  2275. return err;
  2276. }
  2277. static void b43legacy_op_configure_filter(struct ieee80211_hw *hw,
  2278. unsigned int changed,
  2279. unsigned int *fflags,
  2280. int mc_count,
  2281. struct dev_addr_list *mc_list)
  2282. {
  2283. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2284. struct b43legacy_wldev *dev = wl->current_dev;
  2285. unsigned long flags;
  2286. if (!dev) {
  2287. *fflags = 0;
  2288. return;
  2289. }
  2290. spin_lock_irqsave(&wl->irq_lock, flags);
  2291. *fflags &= FIF_PROMISC_IN_BSS |
  2292. FIF_ALLMULTI |
  2293. FIF_FCSFAIL |
  2294. FIF_PLCPFAIL |
  2295. FIF_CONTROL |
  2296. FIF_OTHER_BSS |
  2297. FIF_BCN_PRBRESP_PROMISC;
  2298. changed &= FIF_PROMISC_IN_BSS |
  2299. FIF_ALLMULTI |
  2300. FIF_FCSFAIL |
  2301. FIF_PLCPFAIL |
  2302. FIF_CONTROL |
  2303. FIF_OTHER_BSS |
  2304. FIF_BCN_PRBRESP_PROMISC;
  2305. wl->filter_flags = *fflags;
  2306. if (changed && b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED)
  2307. b43legacy_adjust_opmode(dev);
  2308. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2309. }
  2310. static int b43legacy_op_config_interface(struct ieee80211_hw *hw,
  2311. int if_id,
  2312. struct ieee80211_if_conf *conf)
  2313. {
  2314. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2315. struct b43legacy_wldev *dev = wl->current_dev;
  2316. unsigned long flags;
  2317. if (!dev)
  2318. return -ENODEV;
  2319. mutex_lock(&wl->mutex);
  2320. spin_lock_irqsave(&wl->irq_lock, flags);
  2321. B43legacy_WARN_ON(wl->if_id != if_id);
  2322. if (conf->bssid)
  2323. memcpy(wl->bssid, conf->bssid, ETH_ALEN);
  2324. else
  2325. memset(wl->bssid, 0, ETH_ALEN);
  2326. if (b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED) {
  2327. if (b43legacy_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
  2328. B43legacy_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
  2329. b43legacy_set_ssid(dev, conf->ssid, conf->ssid_len);
  2330. if (conf->beacon)
  2331. b43legacy_refresh_templates(dev, conf->beacon);
  2332. }
  2333. b43legacy_write_mac_bssid_templates(dev);
  2334. }
  2335. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2336. mutex_unlock(&wl->mutex);
  2337. return 0;
  2338. }
  2339. /* Locking: wl->mutex */
  2340. static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev)
  2341. {
  2342. struct b43legacy_wl *wl = dev->wl;
  2343. unsigned long flags;
  2344. if (b43legacy_status(dev) < B43legacy_STAT_STARTED)
  2345. return;
  2346. /* Disable and sync interrupts. We must do this before than
  2347. * setting the status to INITIALIZED, as the interrupt handler
  2348. * won't care about IRQs then. */
  2349. spin_lock_irqsave(&wl->irq_lock, flags);
  2350. dev->irq_savedstate = b43legacy_interrupt_disable(dev,
  2351. B43legacy_IRQ_ALL);
  2352. b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK); /* flush */
  2353. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2354. b43legacy_synchronize_irq(dev);
  2355. b43legacy_set_status(dev, B43legacy_STAT_INITIALIZED);
  2356. mutex_unlock(&wl->mutex);
  2357. /* Must unlock as it would otherwise deadlock. No races here.
  2358. * Cancel the possibly running self-rearming periodic work. */
  2359. cancel_delayed_work_sync(&dev->periodic_work);
  2360. mutex_lock(&wl->mutex);
  2361. ieee80211_stop_queues(wl->hw); /* FIXME this could cause a deadlock */
  2362. b43legacy_mac_suspend(dev);
  2363. free_irq(dev->dev->irq, dev);
  2364. b43legacydbg(wl, "Wireless interface stopped\n");
  2365. }
  2366. /* Locking: wl->mutex */
  2367. static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev)
  2368. {
  2369. int err;
  2370. B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_INITIALIZED);
  2371. drain_txstatus_queue(dev);
  2372. err = request_irq(dev->dev->irq, b43legacy_interrupt_handler,
  2373. IRQF_SHARED, KBUILD_MODNAME, dev);
  2374. if (err) {
  2375. b43legacyerr(dev->wl, "Cannot request IRQ-%d\n",
  2376. dev->dev->irq);
  2377. goto out;
  2378. }
  2379. /* We are ready to run. */
  2380. b43legacy_set_status(dev, B43legacy_STAT_STARTED);
  2381. /* Start data flow (TX/RX) */
  2382. b43legacy_mac_enable(dev);
  2383. b43legacy_interrupt_enable(dev, dev->irq_savedstate);
  2384. ieee80211_start_queues(dev->wl->hw);
  2385. /* Start maintenance work */
  2386. b43legacy_periodic_tasks_setup(dev);
  2387. b43legacydbg(dev->wl, "Wireless interface started\n");
  2388. out:
  2389. return err;
  2390. }
  2391. /* Get PHY and RADIO versioning numbers */
  2392. static int b43legacy_phy_versioning(struct b43legacy_wldev *dev)
  2393. {
  2394. struct b43legacy_phy *phy = &dev->phy;
  2395. u32 tmp;
  2396. u8 analog_type;
  2397. u8 phy_type;
  2398. u8 phy_rev;
  2399. u16 radio_manuf;
  2400. u16 radio_ver;
  2401. u16 radio_rev;
  2402. int unsupported = 0;
  2403. /* Get PHY versioning */
  2404. tmp = b43legacy_read16(dev, B43legacy_MMIO_PHY_VER);
  2405. analog_type = (tmp & B43legacy_PHYVER_ANALOG)
  2406. >> B43legacy_PHYVER_ANALOG_SHIFT;
  2407. phy_type = (tmp & B43legacy_PHYVER_TYPE) >> B43legacy_PHYVER_TYPE_SHIFT;
  2408. phy_rev = (tmp & B43legacy_PHYVER_VERSION);
  2409. switch (phy_type) {
  2410. case B43legacy_PHYTYPE_B:
  2411. if (phy_rev != 2 && phy_rev != 4
  2412. && phy_rev != 6 && phy_rev != 7)
  2413. unsupported = 1;
  2414. break;
  2415. case B43legacy_PHYTYPE_G:
  2416. if (phy_rev > 8)
  2417. unsupported = 1;
  2418. break;
  2419. default:
  2420. unsupported = 1;
  2421. };
  2422. if (unsupported) {
  2423. b43legacyerr(dev->wl, "FOUND UNSUPPORTED PHY "
  2424. "(Analog %u, Type %u, Revision %u)\n",
  2425. analog_type, phy_type, phy_rev);
  2426. return -EOPNOTSUPP;
  2427. }
  2428. b43legacydbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
  2429. analog_type, phy_type, phy_rev);
  2430. /* Get RADIO versioning */
  2431. if (dev->dev->bus->chip_id == 0x4317) {
  2432. if (dev->dev->bus->chip_rev == 0)
  2433. tmp = 0x3205017F;
  2434. else if (dev->dev->bus->chip_rev == 1)
  2435. tmp = 0x4205017F;
  2436. else
  2437. tmp = 0x5205017F;
  2438. } else {
  2439. b43legacy_write16(dev, B43legacy_MMIO_RADIO_CONTROL,
  2440. B43legacy_RADIOCTL_ID);
  2441. tmp = b43legacy_read16(dev, B43legacy_MMIO_RADIO_DATA_HIGH);
  2442. tmp <<= 16;
  2443. b43legacy_write16(dev, B43legacy_MMIO_RADIO_CONTROL,
  2444. B43legacy_RADIOCTL_ID);
  2445. tmp |= b43legacy_read16(dev, B43legacy_MMIO_RADIO_DATA_LOW);
  2446. }
  2447. radio_manuf = (tmp & 0x00000FFF);
  2448. radio_ver = (tmp & 0x0FFFF000) >> 12;
  2449. radio_rev = (tmp & 0xF0000000) >> 28;
  2450. switch (phy_type) {
  2451. case B43legacy_PHYTYPE_B:
  2452. if ((radio_ver & 0xFFF0) != 0x2050)
  2453. unsupported = 1;
  2454. break;
  2455. case B43legacy_PHYTYPE_G:
  2456. if (radio_ver != 0x2050)
  2457. unsupported = 1;
  2458. break;
  2459. default:
  2460. B43legacy_BUG_ON(1);
  2461. }
  2462. if (unsupported) {
  2463. b43legacyerr(dev->wl, "FOUND UNSUPPORTED RADIO "
  2464. "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
  2465. radio_manuf, radio_ver, radio_rev);
  2466. return -EOPNOTSUPP;
  2467. }
  2468. b43legacydbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X,"
  2469. " Revision %u\n", radio_manuf, radio_ver, radio_rev);
  2470. phy->radio_manuf = radio_manuf;
  2471. phy->radio_ver = radio_ver;
  2472. phy->radio_rev = radio_rev;
  2473. phy->analog = analog_type;
  2474. phy->type = phy_type;
  2475. phy->rev = phy_rev;
  2476. return 0;
  2477. }
  2478. static void setup_struct_phy_for_init(struct b43legacy_wldev *dev,
  2479. struct b43legacy_phy *phy)
  2480. {
  2481. struct b43legacy_lopair *lo;
  2482. int i;
  2483. memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
  2484. memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
  2485. /* Flags */
  2486. phy->locked = 0;
  2487. /* Assume the radio is enabled. If it's not enabled, the state will
  2488. * immediately get fixed on the first periodic work run. */
  2489. dev->radio_hw_enable = 1;
  2490. phy->savedpctlreg = 0xFFFF;
  2491. phy->aci_enable = 0;
  2492. phy->aci_wlan_automatic = 0;
  2493. phy->aci_hw_rssi = 0;
  2494. lo = phy->_lo_pairs;
  2495. if (lo)
  2496. memset(lo, 0, sizeof(struct b43legacy_lopair) *
  2497. B43legacy_LO_COUNT);
  2498. phy->max_lb_gain = 0;
  2499. phy->trsw_rx_gain = 0;
  2500. /* Set default attenuation values. */
  2501. phy->bbatt = b43legacy_default_baseband_attenuation(dev);
  2502. phy->rfatt = b43legacy_default_radio_attenuation(dev);
  2503. phy->txctl1 = b43legacy_default_txctl1(dev);
  2504. phy->txpwr_offset = 0;
  2505. /* NRSSI */
  2506. phy->nrssislope = 0;
  2507. for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
  2508. phy->nrssi[i] = -1000;
  2509. for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
  2510. phy->nrssi_lt[i] = i;
  2511. phy->lofcal = 0xFFFF;
  2512. phy->initval = 0xFFFF;
  2513. spin_lock_init(&phy->lock);
  2514. phy->interfmode = B43legacy_INTERFMODE_NONE;
  2515. phy->channel = 0xFF;
  2516. }
  2517. static void setup_struct_wldev_for_init(struct b43legacy_wldev *dev)
  2518. {
  2519. /* Flags */
  2520. dev->reg124_set_0x4 = 0;
  2521. /* Stats */
  2522. memset(&dev->stats, 0, sizeof(dev->stats));
  2523. setup_struct_phy_for_init(dev, &dev->phy);
  2524. /* IRQ related flags */
  2525. dev->irq_reason = 0;
  2526. memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
  2527. dev->irq_savedstate = B43legacy_IRQ_MASKTEMPLATE;
  2528. dev->mac_suspended = 1;
  2529. /* Noise calculation context */
  2530. memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
  2531. }
  2532. static void b43legacy_imcfglo_timeouts_workaround(struct b43legacy_wldev *dev)
  2533. {
  2534. #ifdef CONFIG_SSB_DRIVER_PCICORE
  2535. struct ssb_bus *bus = dev->dev->bus;
  2536. u32 tmp;
  2537. if (bus->pcicore.dev &&
  2538. bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
  2539. bus->pcicore.dev->id.revision <= 5) {
  2540. /* IMCFGLO timeouts workaround. */
  2541. tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
  2542. tmp &= ~SSB_IMCFGLO_REQTO;
  2543. tmp &= ~SSB_IMCFGLO_SERTO;
  2544. switch (bus->bustype) {
  2545. case SSB_BUSTYPE_PCI:
  2546. case SSB_BUSTYPE_PCMCIA:
  2547. tmp |= 0x32;
  2548. break;
  2549. case SSB_BUSTYPE_SSB:
  2550. tmp |= 0x53;
  2551. break;
  2552. }
  2553. ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
  2554. }
  2555. #endif /* CONFIG_SSB_DRIVER_PCICORE */
  2556. }
  2557. /* Write the short and long frame retry limit values. */
  2558. static void b43legacy_set_retry_limits(struct b43legacy_wldev *dev,
  2559. unsigned int short_retry,
  2560. unsigned int long_retry)
  2561. {
  2562. /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
  2563. * the chip-internal counter. */
  2564. short_retry = min(short_retry, (unsigned int)0xF);
  2565. long_retry = min(long_retry, (unsigned int)0xF);
  2566. b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 0x0006, short_retry);
  2567. b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 0x0007, long_retry);
  2568. }
  2569. /* Shutdown a wireless core */
  2570. /* Locking: wl->mutex */
  2571. static void b43legacy_wireless_core_exit(struct b43legacy_wldev *dev)
  2572. {
  2573. struct b43legacy_wl *wl = dev->wl;
  2574. struct b43legacy_phy *phy = &dev->phy;
  2575. B43legacy_WARN_ON(b43legacy_status(dev) > B43legacy_STAT_INITIALIZED);
  2576. if (b43legacy_status(dev) != B43legacy_STAT_INITIALIZED)
  2577. return;
  2578. b43legacy_set_status(dev, B43legacy_STAT_UNINIT);
  2579. mutex_unlock(&wl->mutex);
  2580. /* Must unlock as it would otherwise deadlock. No races here.
  2581. * Cancel possibly pending workqueues. */
  2582. cancel_work_sync(&dev->restart_work);
  2583. mutex_lock(&wl->mutex);
  2584. mutex_unlock(&dev->wl->mutex);
  2585. b43legacy_rfkill_exit(dev);
  2586. mutex_lock(&dev->wl->mutex);
  2587. b43legacy_rng_exit(dev->wl);
  2588. b43legacy_pio_free(dev);
  2589. b43legacy_dma_free(dev);
  2590. b43legacy_chip_exit(dev);
  2591. b43legacy_radio_turn_off(dev, 1);
  2592. b43legacy_switch_analog(dev, 0);
  2593. if (phy->dyn_tssi_tbl)
  2594. kfree(phy->tssi2dbm);
  2595. kfree(phy->lo_control);
  2596. phy->lo_control = NULL;
  2597. ssb_device_disable(dev->dev, 0);
  2598. ssb_bus_may_powerdown(dev->dev->bus);
  2599. }
  2600. static void prepare_phy_data_for_init(struct b43legacy_wldev *dev)
  2601. {
  2602. struct b43legacy_phy *phy = &dev->phy;
  2603. int i;
  2604. /* Set default attenuation values. */
  2605. phy->bbatt = b43legacy_default_baseband_attenuation(dev);
  2606. phy->rfatt = b43legacy_default_radio_attenuation(dev);
  2607. phy->txctl1 = b43legacy_default_txctl1(dev);
  2608. phy->txctl2 = 0xFFFF;
  2609. phy->txpwr_offset = 0;
  2610. /* NRSSI */
  2611. phy->nrssislope = 0;
  2612. for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
  2613. phy->nrssi[i] = -1000;
  2614. for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
  2615. phy->nrssi_lt[i] = i;
  2616. phy->lofcal = 0xFFFF;
  2617. phy->initval = 0xFFFF;
  2618. phy->aci_enable = 0;
  2619. phy->aci_wlan_automatic = 0;
  2620. phy->aci_hw_rssi = 0;
  2621. phy->antenna_diversity = 0xFFFF;
  2622. memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
  2623. memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
  2624. /* Flags */
  2625. phy->calibrated = 0;
  2626. phy->locked = 0;
  2627. if (phy->_lo_pairs)
  2628. memset(phy->_lo_pairs, 0,
  2629. sizeof(struct b43legacy_lopair) * B43legacy_LO_COUNT);
  2630. memset(phy->loopback_gain, 0, sizeof(phy->loopback_gain));
  2631. }
  2632. /* Initialize a wireless core */
  2633. static int b43legacy_wireless_core_init(struct b43legacy_wldev *dev)
  2634. {
  2635. struct b43legacy_wl *wl = dev->wl;
  2636. struct ssb_bus *bus = dev->dev->bus;
  2637. struct b43legacy_phy *phy = &dev->phy;
  2638. struct ssb_sprom *sprom = &dev->dev->bus->sprom;
  2639. int err;
  2640. u32 hf;
  2641. u32 tmp;
  2642. B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_UNINIT);
  2643. err = ssb_bus_powerup(bus, 0);
  2644. if (err)
  2645. goto out;
  2646. if (!ssb_device_is_enabled(dev->dev)) {
  2647. tmp = phy->gmode ? B43legacy_TMSLOW_GMODE : 0;
  2648. b43legacy_wireless_core_reset(dev, tmp);
  2649. }
  2650. if ((phy->type == B43legacy_PHYTYPE_B) ||
  2651. (phy->type == B43legacy_PHYTYPE_G)) {
  2652. phy->_lo_pairs = kzalloc(sizeof(struct b43legacy_lopair)
  2653. * B43legacy_LO_COUNT,
  2654. GFP_KERNEL);
  2655. if (!phy->_lo_pairs)
  2656. return -ENOMEM;
  2657. }
  2658. setup_struct_wldev_for_init(dev);
  2659. err = b43legacy_phy_init_tssi2dbm_table(dev);
  2660. if (err)
  2661. goto err_kfree_lo_control;
  2662. /* Enable IRQ routing to this device. */
  2663. ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
  2664. b43legacy_imcfglo_timeouts_workaround(dev);
  2665. prepare_phy_data_for_init(dev);
  2666. b43legacy_phy_calibrate(dev);
  2667. err = b43legacy_chip_init(dev);
  2668. if (err)
  2669. goto err_kfree_tssitbl;
  2670. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  2671. B43legacy_SHM_SH_WLCOREREV,
  2672. dev->dev->id.revision);
  2673. hf = b43legacy_hf_read(dev);
  2674. if (phy->type == B43legacy_PHYTYPE_G) {
  2675. hf |= B43legacy_HF_SYMW;
  2676. if (phy->rev == 1)
  2677. hf |= B43legacy_HF_GDCW;
  2678. if (sprom->boardflags_lo & B43legacy_BFL_PACTRL)
  2679. hf |= B43legacy_HF_OFDMPABOOST;
  2680. } else if (phy->type == B43legacy_PHYTYPE_B) {
  2681. hf |= B43legacy_HF_SYMW;
  2682. if (phy->rev >= 2 && phy->radio_ver == 0x2050)
  2683. hf &= ~B43legacy_HF_GDCW;
  2684. }
  2685. b43legacy_hf_write(dev, hf);
  2686. b43legacy_set_retry_limits(dev,
  2687. B43legacy_DEFAULT_SHORT_RETRY_LIMIT,
  2688. B43legacy_DEFAULT_LONG_RETRY_LIMIT);
  2689. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  2690. 0x0044, 3);
  2691. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  2692. 0x0046, 2);
  2693. /* Disable sending probe responses from firmware.
  2694. * Setting the MaxTime to one usec will always trigger
  2695. * a timeout, so we never send any probe resp.
  2696. * A timeout of zero is infinite. */
  2697. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
  2698. B43legacy_SHM_SH_PRMAXTIME, 1);
  2699. b43legacy_rate_memory_init(dev);
  2700. /* Minimum Contention Window */
  2701. if (phy->type == B43legacy_PHYTYPE_B)
  2702. b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
  2703. 0x0003, 31);
  2704. else
  2705. b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
  2706. 0x0003, 15);
  2707. /* Maximum Contention Window */
  2708. b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
  2709. 0x0004, 1023);
  2710. do {
  2711. if (b43legacy_using_pio(dev))
  2712. err = b43legacy_pio_init(dev);
  2713. else {
  2714. err = b43legacy_dma_init(dev);
  2715. if (!err)
  2716. b43legacy_qos_init(dev);
  2717. }
  2718. } while (err == -EAGAIN);
  2719. if (err)
  2720. goto err_chip_exit;
  2721. b43legacy_write16(dev, 0x0612, 0x0050);
  2722. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0416, 0x0050);
  2723. b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0414, 0x01F4);
  2724. ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
  2725. memset(wl->bssid, 0, ETH_ALEN);
  2726. memset(wl->mac_addr, 0, ETH_ALEN);
  2727. b43legacy_upload_card_macaddress(dev);
  2728. b43legacy_security_init(dev);
  2729. b43legacy_rfkill_init(dev);
  2730. b43legacy_rng_init(wl);
  2731. b43legacy_set_status(dev, B43legacy_STAT_INITIALIZED);
  2732. out:
  2733. return err;
  2734. err_chip_exit:
  2735. b43legacy_chip_exit(dev);
  2736. err_kfree_tssitbl:
  2737. if (phy->dyn_tssi_tbl)
  2738. kfree(phy->tssi2dbm);
  2739. err_kfree_lo_control:
  2740. kfree(phy->lo_control);
  2741. phy->lo_control = NULL;
  2742. ssb_bus_may_powerdown(bus);
  2743. B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_UNINIT);
  2744. return err;
  2745. }
  2746. static int b43legacy_op_add_interface(struct ieee80211_hw *hw,
  2747. struct ieee80211_if_init_conf *conf)
  2748. {
  2749. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2750. struct b43legacy_wldev *dev;
  2751. unsigned long flags;
  2752. int err = -EOPNOTSUPP;
  2753. /* TODO: allow WDS/AP devices to coexist */
  2754. if (conf->type != IEEE80211_IF_TYPE_AP &&
  2755. conf->type != IEEE80211_IF_TYPE_STA &&
  2756. conf->type != IEEE80211_IF_TYPE_WDS &&
  2757. conf->type != IEEE80211_IF_TYPE_IBSS)
  2758. return -EOPNOTSUPP;
  2759. mutex_lock(&wl->mutex);
  2760. if (wl->operating)
  2761. goto out_mutex_unlock;
  2762. b43legacydbg(wl, "Adding Interface type %d\n", conf->type);
  2763. dev = wl->current_dev;
  2764. wl->operating = 1;
  2765. wl->if_id = conf->if_id;
  2766. wl->if_type = conf->type;
  2767. memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
  2768. spin_lock_irqsave(&wl->irq_lock, flags);
  2769. b43legacy_adjust_opmode(dev);
  2770. b43legacy_upload_card_macaddress(dev);
  2771. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2772. err = 0;
  2773. out_mutex_unlock:
  2774. mutex_unlock(&wl->mutex);
  2775. return err;
  2776. }
  2777. static void b43legacy_op_remove_interface(struct ieee80211_hw *hw,
  2778. struct ieee80211_if_init_conf *conf)
  2779. {
  2780. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2781. struct b43legacy_wldev *dev = wl->current_dev;
  2782. unsigned long flags;
  2783. b43legacydbg(wl, "Removing Interface type %d\n", conf->type);
  2784. mutex_lock(&wl->mutex);
  2785. B43legacy_WARN_ON(!wl->operating);
  2786. B43legacy_WARN_ON(wl->if_id != conf->if_id);
  2787. wl->operating = 0;
  2788. spin_lock_irqsave(&wl->irq_lock, flags);
  2789. b43legacy_adjust_opmode(dev);
  2790. memset(wl->mac_addr, 0, ETH_ALEN);
  2791. b43legacy_upload_card_macaddress(dev);
  2792. spin_unlock_irqrestore(&wl->irq_lock, flags);
  2793. mutex_unlock(&wl->mutex);
  2794. }
  2795. static int b43legacy_op_start(struct ieee80211_hw *hw)
  2796. {
  2797. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2798. struct b43legacy_wldev *dev = wl->current_dev;
  2799. int did_init = 0;
  2800. int err = 0;
  2801. mutex_lock(&wl->mutex);
  2802. if (b43legacy_status(dev) < B43legacy_STAT_INITIALIZED) {
  2803. err = b43legacy_wireless_core_init(dev);
  2804. if (err)
  2805. goto out_mutex_unlock;
  2806. did_init = 1;
  2807. }
  2808. if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
  2809. err = b43legacy_wireless_core_start(dev);
  2810. if (err) {
  2811. if (did_init)
  2812. b43legacy_wireless_core_exit(dev);
  2813. goto out_mutex_unlock;
  2814. }
  2815. }
  2816. out_mutex_unlock:
  2817. mutex_unlock(&wl->mutex);
  2818. return err;
  2819. }
  2820. static void b43legacy_op_stop(struct ieee80211_hw *hw)
  2821. {
  2822. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2823. struct b43legacy_wldev *dev = wl->current_dev;
  2824. mutex_lock(&wl->mutex);
  2825. if (b43legacy_status(dev) >= B43legacy_STAT_STARTED)
  2826. b43legacy_wireless_core_stop(dev);
  2827. b43legacy_wireless_core_exit(dev);
  2828. mutex_unlock(&wl->mutex);
  2829. }
  2830. static int b43legacy_op_set_retry_limit(struct ieee80211_hw *hw,
  2831. u32 short_retry_limit,
  2832. u32 long_retry_limit)
  2833. {
  2834. struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
  2835. struct b43legacy_wldev *dev;
  2836. int err = 0;
  2837. mutex_lock(&wl->mutex);
  2838. dev = wl->current_dev;
  2839. if (unlikely(!dev ||
  2840. (b43legacy_status(dev) < B43legacy_STAT_INITIALIZED))) {
  2841. err = -ENODEV;
  2842. goto out_unlock;
  2843. }
  2844. b43legacy_set_retry_limits(dev, short_retry_limit, long_retry_limit);
  2845. out_unlock:
  2846. mutex_unlock(&wl->mutex);
  2847. return err;
  2848. }
  2849. static const struct ieee80211_ops b43legacy_hw_ops = {
  2850. .tx = b43legacy_op_tx,
  2851. .conf_tx = b43legacy_op_conf_tx,
  2852. .add_interface = b43legacy_op_add_interface,
  2853. .remove_interface = b43legacy_op_remove_interface,
  2854. .config = b43legacy_op_dev_config,
  2855. .config_interface = b43legacy_op_config_interface,
  2856. .configure_filter = b43legacy_op_configure_filter,
  2857. .get_stats = b43legacy_op_get_stats,
  2858. .get_tx_stats = b43legacy_op_get_tx_stats,
  2859. .start = b43legacy_op_start,
  2860. .stop = b43legacy_op_stop,
  2861. .set_retry_limit = b43legacy_op_set_retry_limit,
  2862. };
  2863. /* Hard-reset the chip. Do not call this directly.
  2864. * Use b43legacy_controller_restart()
  2865. */
  2866. static void b43legacy_chip_reset(struct work_struct *work)
  2867. {
  2868. struct b43legacy_wldev *dev =
  2869. container_of(work, struct b43legacy_wldev, restart_work);
  2870. struct b43legacy_wl *wl = dev->wl;
  2871. int err = 0;
  2872. int prev_status;
  2873. mutex_lock(&wl->mutex);
  2874. prev_status = b43legacy_status(dev);
  2875. /* Bring the device down... */
  2876. if (prev_status >= B43legacy_STAT_STARTED)
  2877. b43legacy_wireless_core_stop(dev);
  2878. if (prev_status >= B43legacy_STAT_INITIALIZED)
  2879. b43legacy_wireless_core_exit(dev);
  2880. /* ...and up again. */
  2881. if (prev_status >= B43legacy_STAT_INITIALIZED) {
  2882. err = b43legacy_wireless_core_init(dev);
  2883. if (err)
  2884. goto out;
  2885. }
  2886. if (prev_status >= B43legacy_STAT_STARTED) {
  2887. err = b43legacy_wireless_core_start(dev);
  2888. if (err) {
  2889. b43legacy_wireless_core_exit(dev);
  2890. goto out;
  2891. }
  2892. }
  2893. out:
  2894. mutex_unlock(&wl->mutex);
  2895. if (err)
  2896. b43legacyerr(wl, "Controller restart FAILED\n");
  2897. else
  2898. b43legacyinfo(wl, "Controller restarted\n");
  2899. }
  2900. static int b43legacy_setup_modes(struct b43legacy_wldev *dev,
  2901. int have_bphy,
  2902. int have_gphy)
  2903. {
  2904. struct ieee80211_hw *hw = dev->wl->hw;
  2905. struct ieee80211_hw_mode *mode;
  2906. struct b43legacy_phy *phy = &dev->phy;
  2907. int cnt = 0;
  2908. int err;
  2909. phy->possible_phymodes = 0;
  2910. for (; 1; cnt++) {
  2911. if (have_bphy) {
  2912. B43legacy_WARN_ON(cnt >= B43legacy_MAX_PHYHWMODES);
  2913. mode = &phy->hwmodes[cnt];
  2914. mode->mode = MODE_IEEE80211B;
  2915. mode->num_channels = b43legacy_bg_chantable_size;
  2916. mode->channels = b43legacy_bg_chantable;
  2917. mode->num_rates = b43legacy_b_ratetable_size;
  2918. mode->rates = b43legacy_b_ratetable;
  2919. err = ieee80211_register_hwmode(hw, mode);
  2920. if (err)
  2921. return err;
  2922. phy->possible_phymodes |= B43legacy_PHYMODE_B;
  2923. have_bphy = 0;
  2924. continue;
  2925. }
  2926. if (have_gphy) {
  2927. B43legacy_WARN_ON(cnt >= B43legacy_MAX_PHYHWMODES);
  2928. mode = &phy->hwmodes[cnt];
  2929. mode->mode = MODE_IEEE80211G;
  2930. mode->num_channels = b43legacy_bg_chantable_size;
  2931. mode->channels = b43legacy_bg_chantable;
  2932. mode->num_rates = b43legacy_g_ratetable_size;
  2933. mode->rates = b43legacy_g_ratetable;
  2934. err = ieee80211_register_hwmode(hw, mode);
  2935. if (err)
  2936. return err;
  2937. phy->possible_phymodes |= B43legacy_PHYMODE_G;
  2938. have_gphy = 0;
  2939. continue;
  2940. }
  2941. break;
  2942. }
  2943. return 0;
  2944. }
  2945. static void b43legacy_wireless_core_detach(struct b43legacy_wldev *dev)
  2946. {
  2947. /* We release firmware that late to not be required to re-request
  2948. * is all the time when we reinit the core. */
  2949. b43legacy_release_firmware(dev);
  2950. }
  2951. static int b43legacy_wireless_core_attach(struct b43legacy_wldev *dev)
  2952. {
  2953. struct b43legacy_wl *wl = dev->wl;
  2954. struct ssb_bus *bus = dev->dev->bus;
  2955. struct pci_dev *pdev = bus->host_pci;
  2956. int err;
  2957. int have_bphy = 0;
  2958. int have_gphy = 0;
  2959. u32 tmp;
  2960. /* Do NOT do any device initialization here.
  2961. * Do it in wireless_core_init() instead.
  2962. * This function is for gathering basic information about the HW, only.
  2963. * Also some structs may be set up here. But most likely you want to
  2964. * have that in core_init(), too.
  2965. */
  2966. err = ssb_bus_powerup(bus, 0);
  2967. if (err) {
  2968. b43legacyerr(wl, "Bus powerup failed\n");
  2969. goto out;
  2970. }
  2971. /* Get the PHY type. */
  2972. if (dev->dev->id.revision >= 5) {
  2973. u32 tmshigh;
  2974. tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
  2975. have_gphy = !!(tmshigh & B43legacy_TMSHIGH_GPHY);
  2976. if (!have_gphy)
  2977. have_bphy = 1;
  2978. } else if (dev->dev->id.revision == 4)
  2979. have_gphy = 1;
  2980. else
  2981. have_bphy = 1;
  2982. dev->phy.gmode = (have_gphy || have_bphy);
  2983. tmp = dev->phy.gmode ? B43legacy_TMSLOW_GMODE : 0;
  2984. b43legacy_wireless_core_reset(dev, tmp);
  2985. err = b43legacy_phy_versioning(dev);
  2986. if (err)
  2987. goto err_powerdown;
  2988. /* Check if this device supports multiband. */
  2989. if (!pdev ||
  2990. (pdev->device != 0x4312 &&
  2991. pdev->device != 0x4319 &&
  2992. pdev->device != 0x4324)) {
  2993. /* No multiband support. */
  2994. have_bphy = 0;
  2995. have_gphy = 0;
  2996. switch (dev->phy.type) {
  2997. case B43legacy_PHYTYPE_B:
  2998. have_bphy = 1;
  2999. break;
  3000. case B43legacy_PHYTYPE_G:
  3001. have_gphy = 1;
  3002. break;
  3003. default:
  3004. B43legacy_BUG_ON(1);
  3005. }
  3006. }
  3007. dev->phy.gmode = (have_gphy || have_bphy);
  3008. tmp = dev->phy.gmode ? B43legacy_TMSLOW_GMODE : 0;
  3009. b43legacy_wireless_core_reset(dev, tmp);
  3010. err = b43legacy_validate_chipaccess(dev);
  3011. if (err)
  3012. goto err_powerdown;
  3013. err = b43legacy_setup_modes(dev, have_bphy, have_gphy);
  3014. if (err)
  3015. goto err_powerdown;
  3016. /* Now set some default "current_dev" */
  3017. if (!wl->current_dev)
  3018. wl->current_dev = dev;
  3019. INIT_WORK(&dev->restart_work, b43legacy_chip_reset);
  3020. b43legacy_radio_turn_off(dev, 1);
  3021. b43legacy_switch_analog(dev, 0);
  3022. ssb_device_disable(dev->dev, 0);
  3023. ssb_bus_may_powerdown(bus);
  3024. out:
  3025. return err;
  3026. err_powerdown:
  3027. ssb_bus_may_powerdown(bus);
  3028. return err;
  3029. }
  3030. static void b43legacy_one_core_detach(struct ssb_device *dev)
  3031. {
  3032. struct b43legacy_wldev *wldev;
  3033. struct b43legacy_wl *wl;
  3034. wldev = ssb_get_drvdata(dev);
  3035. wl = wldev->wl;
  3036. cancel_work_sync(&wldev->restart_work);
  3037. b43legacy_debugfs_remove_device(wldev);
  3038. b43legacy_wireless_core_detach(wldev);
  3039. list_del(&wldev->list);
  3040. wl->nr_devs--;
  3041. ssb_set_drvdata(dev, NULL);
  3042. kfree(wldev);
  3043. }
  3044. static int b43legacy_one_core_attach(struct ssb_device *dev,
  3045. struct b43legacy_wl *wl)
  3046. {
  3047. struct b43legacy_wldev *wldev;
  3048. struct pci_dev *pdev;
  3049. int err = -ENOMEM;
  3050. if (!list_empty(&wl->devlist)) {
  3051. /* We are not the first core on this chip. */
  3052. pdev = dev->bus->host_pci;
  3053. /* Only special chips support more than one wireless
  3054. * core, although some of the other chips have more than
  3055. * one wireless core as well. Check for this and
  3056. * bail out early.
  3057. */
  3058. if (!pdev ||
  3059. ((pdev->device != 0x4321) &&
  3060. (pdev->device != 0x4313) &&
  3061. (pdev->device != 0x431A))) {
  3062. b43legacydbg(wl, "Ignoring unconnected 802.11 core\n");
  3063. return -ENODEV;
  3064. }
  3065. }
  3066. wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
  3067. if (!wldev)
  3068. goto out;
  3069. wldev->dev = dev;
  3070. wldev->wl = wl;
  3071. b43legacy_set_status(wldev, B43legacy_STAT_UNINIT);
  3072. wldev->bad_frames_preempt = modparam_bad_frames_preempt;
  3073. tasklet_init(&wldev->isr_tasklet,
  3074. (void (*)(unsigned long))b43legacy_interrupt_tasklet,
  3075. (unsigned long)wldev);
  3076. if (modparam_pio)
  3077. wldev->__using_pio = 1;
  3078. INIT_LIST_HEAD(&wldev->list);
  3079. err = b43legacy_wireless_core_attach(wldev);
  3080. if (err)
  3081. goto err_kfree_wldev;
  3082. list_add(&wldev->list, &wl->devlist);
  3083. wl->nr_devs++;
  3084. ssb_set_drvdata(dev, wldev);
  3085. b43legacy_debugfs_add_device(wldev);
  3086. out:
  3087. return err;
  3088. err_kfree_wldev:
  3089. kfree(wldev);
  3090. return err;
  3091. }
  3092. static void b43legacy_sprom_fixup(struct ssb_bus *bus)
  3093. {
  3094. /* boardflags workarounds */
  3095. if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
  3096. bus->boardinfo.type == 0x4E &&
  3097. bus->boardinfo.rev > 0x40)
  3098. bus->sprom.boardflags_lo |= B43legacy_BFL_PACTRL;
  3099. /* Convert Antennagain values to Q5.2 */
  3100. if (bus->sprom.antenna_gain_bg == 0xFF)
  3101. bus->sprom.antenna_gain_bg = 2; /* if unset, use 2 dBm */
  3102. bus->sprom.antenna_gain_bg <<= 2;
  3103. }
  3104. static void b43legacy_wireless_exit(struct ssb_device *dev,
  3105. struct b43legacy_wl *wl)
  3106. {
  3107. struct ieee80211_hw *hw = wl->hw;
  3108. ssb_set_devtypedata(dev, NULL);
  3109. ieee80211_free_hw(hw);
  3110. }
  3111. static int b43legacy_wireless_init(struct ssb_device *dev)
  3112. {
  3113. struct ssb_sprom *sprom = &dev->bus->sprom;
  3114. struct ieee80211_hw *hw;
  3115. struct b43legacy_wl *wl;
  3116. int err = -ENOMEM;
  3117. b43legacy_sprom_fixup(dev->bus);
  3118. hw = ieee80211_alloc_hw(sizeof(*wl), &b43legacy_hw_ops);
  3119. if (!hw) {
  3120. b43legacyerr(NULL, "Could not allocate ieee80211 device\n");
  3121. goto out;
  3122. }
  3123. /* fill hw info */
  3124. hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
  3125. IEEE80211_HW_RX_INCLUDES_FCS;
  3126. hw->max_signal = 100;
  3127. hw->max_rssi = -110;
  3128. hw->max_noise = -110;
  3129. hw->queues = 1; /* FIXME: hardware has more queues */
  3130. SET_IEEE80211_DEV(hw, dev->dev);
  3131. if (is_valid_ether_addr(sprom->et1mac))
  3132. SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
  3133. else
  3134. SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
  3135. /* Get and initialize struct b43legacy_wl */
  3136. wl = hw_to_b43legacy_wl(hw);
  3137. memset(wl, 0, sizeof(*wl));
  3138. wl->hw = hw;
  3139. spin_lock_init(&wl->irq_lock);
  3140. spin_lock_init(&wl->leds_lock);
  3141. mutex_init(&wl->mutex);
  3142. INIT_LIST_HEAD(&wl->devlist);
  3143. ssb_set_devtypedata(dev, wl);
  3144. b43legacyinfo(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
  3145. err = 0;
  3146. out:
  3147. return err;
  3148. }
  3149. static int b43legacy_probe(struct ssb_device *dev,
  3150. const struct ssb_device_id *id)
  3151. {
  3152. struct b43legacy_wl *wl;
  3153. int err;
  3154. int first = 0;
  3155. wl = ssb_get_devtypedata(dev);
  3156. if (!wl) {
  3157. /* Probing the first core - setup common struct b43legacy_wl */
  3158. first = 1;
  3159. err = b43legacy_wireless_init(dev);
  3160. if (err)
  3161. goto out;
  3162. wl = ssb_get_devtypedata(dev);
  3163. B43legacy_WARN_ON(!wl);
  3164. }
  3165. err = b43legacy_one_core_attach(dev, wl);
  3166. if (err)
  3167. goto err_wireless_exit;
  3168. if (first) {
  3169. err = ieee80211_register_hw(wl->hw);
  3170. if (err)
  3171. goto err_one_core_detach;
  3172. }
  3173. out:
  3174. return err;
  3175. err_one_core_detach:
  3176. b43legacy_one_core_detach(dev);
  3177. err_wireless_exit:
  3178. if (first)
  3179. b43legacy_wireless_exit(dev, wl);
  3180. return err;
  3181. }
  3182. static void b43legacy_remove(struct ssb_device *dev)
  3183. {
  3184. struct b43legacy_wl *wl = ssb_get_devtypedata(dev);
  3185. struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
  3186. B43legacy_WARN_ON(!wl);
  3187. if (wl->current_dev == wldev)
  3188. ieee80211_unregister_hw(wl->hw);
  3189. b43legacy_one_core_detach(dev);
  3190. if (list_empty(&wl->devlist))
  3191. /* Last core on the chip unregistered.
  3192. * We can destroy common struct b43legacy_wl.
  3193. */
  3194. b43legacy_wireless_exit(dev, wl);
  3195. }
  3196. /* Perform a hardware reset. This can be called from any context. */
  3197. void b43legacy_controller_restart(struct b43legacy_wldev *dev,
  3198. const char *reason)
  3199. {
  3200. /* Must avoid requeueing, if we are in shutdown. */
  3201. if (b43legacy_status(dev) < B43legacy_STAT_INITIALIZED)
  3202. return;
  3203. b43legacyinfo(dev->wl, "Controller RESET (%s) ...\n", reason);
  3204. queue_work(dev->wl->hw->workqueue, &dev->restart_work);
  3205. }
  3206. #ifdef CONFIG_PM
  3207. static int b43legacy_suspend(struct ssb_device *dev, pm_message_t state)
  3208. {
  3209. struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
  3210. struct b43legacy_wl *wl = wldev->wl;
  3211. b43legacydbg(wl, "Suspending...\n");
  3212. mutex_lock(&wl->mutex);
  3213. wldev->suspend_init_status = b43legacy_status(wldev);
  3214. if (wldev->suspend_init_status >= B43legacy_STAT_STARTED)
  3215. b43legacy_wireless_core_stop(wldev);
  3216. if (wldev->suspend_init_status >= B43legacy_STAT_INITIALIZED)
  3217. b43legacy_wireless_core_exit(wldev);
  3218. mutex_unlock(&wl->mutex);
  3219. b43legacydbg(wl, "Device suspended.\n");
  3220. return 0;
  3221. }
  3222. static int b43legacy_resume(struct ssb_device *dev)
  3223. {
  3224. struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
  3225. struct b43legacy_wl *wl = wldev->wl;
  3226. int err = 0;
  3227. b43legacydbg(wl, "Resuming...\n");
  3228. mutex_lock(&wl->mutex);
  3229. if (wldev->suspend_init_status >= B43legacy_STAT_INITIALIZED) {
  3230. err = b43legacy_wireless_core_init(wldev);
  3231. if (err) {
  3232. b43legacyerr(wl, "Resume failed at core init\n");
  3233. goto out;
  3234. }
  3235. }
  3236. if (wldev->suspend_init_status >= B43legacy_STAT_STARTED) {
  3237. err = b43legacy_wireless_core_start(wldev);
  3238. if (err) {
  3239. b43legacy_wireless_core_exit(wldev);
  3240. b43legacyerr(wl, "Resume failed at core start\n");
  3241. goto out;
  3242. }
  3243. }
  3244. mutex_unlock(&wl->mutex);
  3245. b43legacydbg(wl, "Device resumed.\n");
  3246. out:
  3247. return err;
  3248. }
  3249. #else /* CONFIG_PM */
  3250. # define b43legacy_suspend NULL
  3251. # define b43legacy_resume NULL
  3252. #endif /* CONFIG_PM */
  3253. static struct ssb_driver b43legacy_ssb_driver = {
  3254. .name = KBUILD_MODNAME,
  3255. .id_table = b43legacy_ssb_tbl,
  3256. .probe = b43legacy_probe,
  3257. .remove = b43legacy_remove,
  3258. .suspend = b43legacy_suspend,
  3259. .resume = b43legacy_resume,
  3260. };
  3261. static int __init b43legacy_init(void)
  3262. {
  3263. int err;
  3264. b43legacy_debugfs_init();
  3265. err = ssb_driver_register(&b43legacy_ssb_driver);
  3266. if (err)
  3267. goto err_dfs_exit;
  3268. return err;
  3269. err_dfs_exit:
  3270. b43legacy_debugfs_exit();
  3271. return err;
  3272. }
  3273. static void __exit b43legacy_exit(void)
  3274. {
  3275. ssb_driver_unregister(&b43legacy_ssb_driver);
  3276. b43legacy_debugfs_exit();
  3277. }
  3278. module_init(b43legacy_init)
  3279. module_exit(b43legacy_exit)