r8152.c 49 KB

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  1. /*
  2. * Copyright (c) 2013 Realtek Semiconductor Corp. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * version 2 as published by the Free Software Foundation.
  7. *
  8. */
  9. #include <linux/init.h>
  10. #include <linux/signal.h>
  11. #include <linux/slab.h>
  12. #include <linux/module.h>
  13. #include <linux/netdevice.h>
  14. #include <linux/etherdevice.h>
  15. #include <linux/mii.h>
  16. #include <linux/ethtool.h>
  17. #include <linux/usb.h>
  18. #include <linux/crc32.h>
  19. #include <linux/if_vlan.h>
  20. #include <linux/uaccess.h>
  21. #include <linux/list.h>
  22. #include <linux/ip.h>
  23. #include <linux/ipv6.h>
  24. /* Version Information */
  25. #define DRIVER_VERSION "v1.01.0 (2013/08/12)"
  26. #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
  27. #define DRIVER_DESC "Realtek RTL8152 Based USB 2.0 Ethernet Adapters"
  28. #define MODULENAME "r8152"
  29. #define R8152_PHY_ID 32
  30. #define PLA_IDR 0xc000
  31. #define PLA_RCR 0xc010
  32. #define PLA_RMS 0xc016
  33. #define PLA_RXFIFO_CTRL0 0xc0a0
  34. #define PLA_RXFIFO_CTRL1 0xc0a4
  35. #define PLA_RXFIFO_CTRL2 0xc0a8
  36. #define PLA_FMC 0xc0b4
  37. #define PLA_CFG_WOL 0xc0b6
  38. #define PLA_MAR 0xcd00
  39. #define PAL_BDC_CR 0xd1a0
  40. #define PLA_LEDSEL 0xdd90
  41. #define PLA_LED_FEATURE 0xdd92
  42. #define PLA_PHYAR 0xde00
  43. #define PLA_GPHY_INTR_IMR 0xe022
  44. #define PLA_EEE_CR 0xe040
  45. #define PLA_EEEP_CR 0xe080
  46. #define PLA_MAC_PWR_CTRL 0xe0c0
  47. #define PLA_TCR0 0xe610
  48. #define PLA_TCR1 0xe612
  49. #define PLA_TXFIFO_CTRL 0xe618
  50. #define PLA_RSTTELLY 0xe800
  51. #define PLA_CR 0xe813
  52. #define PLA_CRWECR 0xe81c
  53. #define PLA_CONFIG5 0xe822
  54. #define PLA_PHY_PWR 0xe84c
  55. #define PLA_OOB_CTRL 0xe84f
  56. #define PLA_CPCR 0xe854
  57. #define PLA_MISC_0 0xe858
  58. #define PLA_MISC_1 0xe85a
  59. #define PLA_OCP_GPHY_BASE 0xe86c
  60. #define PLA_TELLYCNT 0xe890
  61. #define PLA_SFF_STS_7 0xe8de
  62. #define PLA_PHYSTATUS 0xe908
  63. #define PLA_BP_BA 0xfc26
  64. #define PLA_BP_0 0xfc28
  65. #define PLA_BP_1 0xfc2a
  66. #define PLA_BP_2 0xfc2c
  67. #define PLA_BP_3 0xfc2e
  68. #define PLA_BP_4 0xfc30
  69. #define PLA_BP_5 0xfc32
  70. #define PLA_BP_6 0xfc34
  71. #define PLA_BP_7 0xfc36
  72. #define USB_DEV_STAT 0xb808
  73. #define USB_USB_CTRL 0xd406
  74. #define USB_PHY_CTRL 0xd408
  75. #define USB_TX_AGG 0xd40a
  76. #define USB_RX_BUF_TH 0xd40c
  77. #define USB_USB_TIMER 0xd428
  78. #define USB_PM_CTRL_STATUS 0xd432
  79. #define USB_TX_DMA 0xd434
  80. #define USB_UPS_CTRL 0xd800
  81. #define USB_BP_BA 0xfc26
  82. #define USB_BP_0 0xfc28
  83. #define USB_BP_1 0xfc2a
  84. #define USB_BP_2 0xfc2c
  85. #define USB_BP_3 0xfc2e
  86. #define USB_BP_4 0xfc30
  87. #define USB_BP_5 0xfc32
  88. #define USB_BP_6 0xfc34
  89. #define USB_BP_7 0xfc36
  90. /* OCP Registers */
  91. #define OCP_ALDPS_CONFIG 0x2010
  92. #define OCP_EEE_CONFIG1 0x2080
  93. #define OCP_EEE_CONFIG2 0x2092
  94. #define OCP_EEE_CONFIG3 0x2094
  95. #define OCP_EEE_AR 0xa41a
  96. #define OCP_EEE_DATA 0xa41c
  97. /* PLA_RCR */
  98. #define RCR_AAP 0x00000001
  99. #define RCR_APM 0x00000002
  100. #define RCR_AM 0x00000004
  101. #define RCR_AB 0x00000008
  102. #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
  103. /* PLA_RXFIFO_CTRL0 */
  104. #define RXFIFO_THR1_NORMAL 0x00080002
  105. #define RXFIFO_THR1_OOB 0x01800003
  106. /* PLA_RXFIFO_CTRL1 */
  107. #define RXFIFO_THR2_FULL 0x00000060
  108. #define RXFIFO_THR2_HIGH 0x00000038
  109. #define RXFIFO_THR2_OOB 0x0000004a
  110. /* PLA_RXFIFO_CTRL2 */
  111. #define RXFIFO_THR3_FULL 0x00000078
  112. #define RXFIFO_THR3_HIGH 0x00000048
  113. #define RXFIFO_THR3_OOB 0x0000005a
  114. /* PLA_TXFIFO_CTRL */
  115. #define TXFIFO_THR_NORMAL 0x00400008
  116. /* PLA_FMC */
  117. #define FMC_FCR_MCU_EN 0x0001
  118. /* PLA_EEEP_CR */
  119. #define EEEP_CR_EEEP_TX 0x0002
  120. /* PLA_TCR0 */
  121. #define TCR0_TX_EMPTY 0x0800
  122. #define TCR0_AUTO_FIFO 0x0080
  123. /* PLA_TCR1 */
  124. #define VERSION_MASK 0x7cf0
  125. /* PLA_CR */
  126. #define CR_RST 0x10
  127. #define CR_RE 0x08
  128. #define CR_TE 0x04
  129. /* PLA_CRWECR */
  130. #define CRWECR_NORAML 0x00
  131. #define CRWECR_CONFIG 0xc0
  132. /* PLA_OOB_CTRL */
  133. #define NOW_IS_OOB 0x80
  134. #define TXFIFO_EMPTY 0x20
  135. #define RXFIFO_EMPTY 0x10
  136. #define LINK_LIST_READY 0x02
  137. #define DIS_MCU_CLROOB 0x01
  138. #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
  139. /* PLA_MISC_1 */
  140. #define RXDY_GATED_EN 0x0008
  141. /* PLA_SFF_STS_7 */
  142. #define RE_INIT_LL 0x8000
  143. #define MCU_BORW_EN 0x4000
  144. /* PLA_CPCR */
  145. #define CPCR_RX_VLAN 0x0040
  146. /* PLA_CFG_WOL */
  147. #define MAGIC_EN 0x0001
  148. /* PAL_BDC_CR */
  149. #define ALDPS_PROXY_MODE 0x0001
  150. /* PLA_CONFIG5 */
  151. #define LAN_WAKE_EN 0x0002
  152. /* PLA_LED_FEATURE */
  153. #define LED_MODE_MASK 0x0700
  154. /* PLA_PHY_PWR */
  155. #define TX_10M_IDLE_EN 0x0080
  156. #define PFM_PWM_SWITCH 0x0040
  157. /* PLA_MAC_PWR_CTRL */
  158. #define D3_CLK_GATED_EN 0x00004000
  159. #define MCU_CLK_RATIO 0x07010f07
  160. #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
  161. /* PLA_GPHY_INTR_IMR */
  162. #define GPHY_STS_MSK 0x0001
  163. #define SPEED_DOWN_MSK 0x0002
  164. #define SPDWN_RXDV_MSK 0x0004
  165. #define SPDWN_LINKCHG_MSK 0x0008
  166. /* PLA_PHYAR */
  167. #define PHYAR_FLAG 0x80000000
  168. /* PLA_EEE_CR */
  169. #define EEE_RX_EN 0x0001
  170. #define EEE_TX_EN 0x0002
  171. /* USB_DEV_STAT */
  172. #define STAT_SPEED_MASK 0x0006
  173. #define STAT_SPEED_HIGH 0x0000
  174. #define STAT_SPEED_FULL 0x0001
  175. /* USB_TX_AGG */
  176. #define TX_AGG_MAX_THRESHOLD 0x03
  177. /* USB_RX_BUF_TH */
  178. #define RX_BUF_THR 0x7a120180
  179. /* USB_TX_DMA */
  180. #define TEST_MODE_DISABLE 0x00000001
  181. #define TX_SIZE_ADJUST1 0x00000100
  182. /* USB_UPS_CTRL */
  183. #define POWER_CUT 0x0100
  184. /* USB_PM_CTRL_STATUS */
  185. #define RWSUME_INDICATE 0x0001
  186. /* USB_USB_CTRL */
  187. #define RX_AGG_DISABLE 0x0010
  188. /* OCP_ALDPS_CONFIG */
  189. #define ENPWRSAVE 0x8000
  190. #define ENPDNPS 0x0200
  191. #define LINKENA 0x0100
  192. #define DIS_SDSAVE 0x0010
  193. /* OCP_EEE_CONFIG1 */
  194. #define RG_TXLPI_MSK_HFDUP 0x8000
  195. #define RG_MATCLR_EN 0x4000
  196. #define EEE_10_CAP 0x2000
  197. #define EEE_NWAY_EN 0x1000
  198. #define TX_QUIET_EN 0x0200
  199. #define RX_QUIET_EN 0x0100
  200. #define SDRISETIME 0x0010 /* bit 4 ~ 6 */
  201. #define RG_RXLPI_MSK_HFDUP 0x0008
  202. #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
  203. /* OCP_EEE_CONFIG2 */
  204. #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
  205. #define RG_DACQUIET_EN 0x0400
  206. #define RG_LDVQUIET_EN 0x0200
  207. #define RG_CKRSEL 0x0020
  208. #define RG_EEEPRG_EN 0x0010
  209. /* OCP_EEE_CONFIG3 */
  210. #define FST_SNR_EYE_R 0x1500 /* bit 7 ~ 15 */
  211. #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
  212. #define MSK_PH 0x0006 /* bit 0 ~ 3 */
  213. /* OCP_EEE_AR */
  214. /* bit[15:14] function */
  215. #define FUN_ADDR 0x0000
  216. #define FUN_DATA 0x4000
  217. /* bit[4:0] device addr */
  218. #define DEVICE_ADDR 0x0007
  219. /* OCP_EEE_DATA */
  220. #define EEE_ADDR 0x003C
  221. #define EEE_DATA 0x0002
  222. enum rtl_register_content {
  223. _100bps = 0x08,
  224. _10bps = 0x04,
  225. LINK_STATUS = 0x02,
  226. FULL_DUP = 0x01,
  227. };
  228. #define RTL8152_MAX_TX 10
  229. #define RTL8152_MAX_RX 10
  230. #define RTL8152_REQT_READ 0xc0
  231. #define RTL8152_REQT_WRITE 0x40
  232. #define RTL8152_REQ_GET_REGS 0x05
  233. #define RTL8152_REQ_SET_REGS 0x05
  234. #define BYTE_EN_DWORD 0xff
  235. #define BYTE_EN_WORD 0x33
  236. #define BYTE_EN_BYTE 0x11
  237. #define BYTE_EN_SIX_BYTES 0x3f
  238. #define BYTE_EN_START_MASK 0x0f
  239. #define BYTE_EN_END_MASK 0xf0
  240. #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
  241. #define RTL8152_TX_TIMEOUT (HZ)
  242. /* rtl8152 flags */
  243. enum rtl8152_flags {
  244. RTL8152_UNPLUG = 0,
  245. RTL8152_SET_RX_MODE,
  246. WORK_ENABLE
  247. };
  248. /* Define these values to match your device */
  249. #define VENDOR_ID_REALTEK 0x0bda
  250. #define PRODUCT_ID_RTL8152 0x8152
  251. #define MCU_TYPE_PLA 0x0100
  252. #define MCU_TYPE_USB 0x0000
  253. struct rx_desc {
  254. u32 opts1;
  255. #define RX_LEN_MASK 0x7fff
  256. u32 opts2;
  257. u32 opts3;
  258. u32 opts4;
  259. u32 opts5;
  260. u32 opts6;
  261. };
  262. struct tx_desc {
  263. u32 opts1;
  264. #define TX_FS (1 << 31) /* First segment of a packet */
  265. #define TX_LS (1 << 30) /* Final segment of a packet */
  266. #define TX_LEN_MASK 0x3ffff
  267. u32 opts2;
  268. #define UDP_CS (1 << 31) /* Calculate UDP/IP checksum */
  269. #define TCP_CS (1 << 30) /* Calculate TCP/IP checksum */
  270. #define IPV4_CS (1 << 29) /* Calculate IPv4 checksum */
  271. #define IPV6_CS (1 << 28) /* Calculate IPv6 checksum */
  272. };
  273. struct rx_agg {
  274. struct list_head list;
  275. struct urb *urb;
  276. void *context;
  277. void *buffer;
  278. void *head;
  279. };
  280. struct tx_agg {
  281. struct list_head list;
  282. struct urb *urb;
  283. void *context;
  284. void *buffer;
  285. void *head;
  286. u32 skb_num;
  287. u32 skb_len;
  288. };
  289. struct r8152 {
  290. unsigned long flags;
  291. struct usb_device *udev;
  292. struct tasklet_struct tl;
  293. struct net_device *netdev;
  294. struct tx_agg tx_info[RTL8152_MAX_TX];
  295. struct rx_agg rx_info[RTL8152_MAX_RX];
  296. struct list_head rx_done, tx_free;
  297. struct sk_buff_head tx_queue;
  298. spinlock_t rx_lock, tx_lock;
  299. struct delayed_work schedule;
  300. struct mii_if_info mii;
  301. u32 msg_enable;
  302. u16 ocp_base;
  303. u8 version;
  304. u8 speed;
  305. };
  306. enum rtl_version {
  307. RTL_VER_UNKNOWN = 0,
  308. RTL_VER_01,
  309. RTL_VER_02
  310. };
  311. /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  312. * The RTL chips use a 64 element hash table based on the Ethernet CRC.
  313. */
  314. static const int multicast_filter_limit = 32;
  315. static unsigned int rx_buf_sz = 16384;
  316. static
  317. int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  318. {
  319. int ret;
  320. void *tmp;
  321. tmp = kmalloc(size, GFP_KERNEL);
  322. if (!tmp)
  323. return -ENOMEM;
  324. ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
  325. RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
  326. value, index, tmp, size, 500);
  327. memcpy(data, tmp, size);
  328. kfree(tmp);
  329. return ret;
  330. }
  331. static
  332. int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  333. {
  334. int ret;
  335. void *tmp;
  336. tmp = kmalloc(size, GFP_KERNEL);
  337. if (!tmp)
  338. return -ENOMEM;
  339. memcpy(tmp, data, size);
  340. ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
  341. RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
  342. value, index, tmp, size, 500);
  343. kfree(tmp);
  344. return ret;
  345. }
  346. static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
  347. void *data, u16 type)
  348. {
  349. u16 limit = 64;
  350. int ret = 0;
  351. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  352. return -ENODEV;
  353. /* both size and indix must be 4 bytes align */
  354. if ((size & 3) || !size || (index & 3) || !data)
  355. return -EPERM;
  356. if ((u32)index + (u32)size > 0xffff)
  357. return -EPERM;
  358. while (size) {
  359. if (size > limit) {
  360. ret = get_registers(tp, index, type, limit, data);
  361. if (ret < 0)
  362. break;
  363. index += limit;
  364. data += limit;
  365. size -= limit;
  366. } else {
  367. ret = get_registers(tp, index, type, size, data);
  368. if (ret < 0)
  369. break;
  370. index += size;
  371. data += size;
  372. size = 0;
  373. break;
  374. }
  375. }
  376. return ret;
  377. }
  378. static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
  379. u16 size, void *data, u16 type)
  380. {
  381. int ret;
  382. u16 byteen_start, byteen_end, byen;
  383. u16 limit = 512;
  384. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  385. return -ENODEV;
  386. /* both size and indix must be 4 bytes align */
  387. if ((size & 3) || !size || (index & 3) || !data)
  388. return -EPERM;
  389. if ((u32)index + (u32)size > 0xffff)
  390. return -EPERM;
  391. byteen_start = byteen & BYTE_EN_START_MASK;
  392. byteen_end = byteen & BYTE_EN_END_MASK;
  393. byen = byteen_start | (byteen_start << 4);
  394. ret = set_registers(tp, index, type | byen, 4, data);
  395. if (ret < 0)
  396. goto error1;
  397. index += 4;
  398. data += 4;
  399. size -= 4;
  400. if (size) {
  401. size -= 4;
  402. while (size) {
  403. if (size > limit) {
  404. ret = set_registers(tp, index,
  405. type | BYTE_EN_DWORD,
  406. limit, data);
  407. if (ret < 0)
  408. goto error1;
  409. index += limit;
  410. data += limit;
  411. size -= limit;
  412. } else {
  413. ret = set_registers(tp, index,
  414. type | BYTE_EN_DWORD,
  415. size, data);
  416. if (ret < 0)
  417. goto error1;
  418. index += size;
  419. data += size;
  420. size = 0;
  421. break;
  422. }
  423. }
  424. byen = byteen_end | (byteen_end >> 4);
  425. ret = set_registers(tp, index, type | byen, 4, data);
  426. if (ret < 0)
  427. goto error1;
  428. }
  429. error1:
  430. return ret;
  431. }
  432. static inline
  433. int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
  434. {
  435. return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
  436. }
  437. static inline
  438. int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
  439. {
  440. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
  441. }
  442. static inline
  443. int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
  444. {
  445. return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
  446. }
  447. static inline
  448. int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
  449. {
  450. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
  451. }
  452. static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
  453. {
  454. __le32 data;
  455. generic_ocp_read(tp, index, sizeof(data), &data, type);
  456. return __le32_to_cpu(data);
  457. }
  458. static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
  459. {
  460. __le32 tmp = __cpu_to_le32(data);
  461. generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
  462. }
  463. static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
  464. {
  465. u32 data;
  466. __le32 tmp;
  467. u8 shift = index & 2;
  468. index &= ~3;
  469. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  470. data = __le32_to_cpu(tmp);
  471. data >>= (shift * 8);
  472. data &= 0xffff;
  473. return (u16)data;
  474. }
  475. static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
  476. {
  477. u32 mask = 0xffff;
  478. __le32 tmp;
  479. u16 byen = BYTE_EN_WORD;
  480. u8 shift = index & 2;
  481. data &= mask;
  482. if (index & 2) {
  483. byen <<= shift;
  484. mask <<= (shift * 8);
  485. data <<= (shift * 8);
  486. index &= ~3;
  487. }
  488. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  489. data |= __le32_to_cpu(tmp) & ~mask;
  490. tmp = __cpu_to_le32(data);
  491. generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
  492. }
  493. static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
  494. {
  495. u32 data;
  496. __le32 tmp;
  497. u8 shift = index & 3;
  498. index &= ~3;
  499. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  500. data = __le32_to_cpu(tmp);
  501. data >>= (shift * 8);
  502. data &= 0xff;
  503. return (u8)data;
  504. }
  505. static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
  506. {
  507. u32 mask = 0xff;
  508. __le32 tmp;
  509. u16 byen = BYTE_EN_BYTE;
  510. u8 shift = index & 3;
  511. data &= mask;
  512. if (index & 3) {
  513. byen <<= shift;
  514. mask <<= (shift * 8);
  515. data <<= (shift * 8);
  516. index &= ~3;
  517. }
  518. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  519. data |= __le32_to_cpu(tmp) & ~mask;
  520. tmp = __cpu_to_le32(data);
  521. generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
  522. }
  523. static void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
  524. {
  525. u32 ocp_data;
  526. int i;
  527. ocp_data = PHYAR_FLAG | ((reg_addr & 0x1f) << 16) |
  528. (value & 0xffff);
  529. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_PHYAR, ocp_data);
  530. for (i = 20; i > 0; i--) {
  531. udelay(25);
  532. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_PHYAR);
  533. if (!(ocp_data & PHYAR_FLAG))
  534. break;
  535. }
  536. udelay(20);
  537. }
  538. static int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
  539. {
  540. u32 ocp_data;
  541. int i;
  542. ocp_data = (reg_addr & 0x1f) << 16;
  543. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_PHYAR, ocp_data);
  544. for (i = 20; i > 0; i--) {
  545. udelay(25);
  546. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_PHYAR);
  547. if (ocp_data & PHYAR_FLAG)
  548. break;
  549. }
  550. udelay(20);
  551. if (!(ocp_data & PHYAR_FLAG))
  552. return -EAGAIN;
  553. return (u16)(ocp_data & 0xffff);
  554. }
  555. static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
  556. {
  557. struct r8152 *tp = netdev_priv(netdev);
  558. if (phy_id != R8152_PHY_ID)
  559. return -EINVAL;
  560. return r8152_mdio_read(tp, reg);
  561. }
  562. static
  563. void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
  564. {
  565. struct r8152 *tp = netdev_priv(netdev);
  566. if (phy_id != R8152_PHY_ID)
  567. return;
  568. r8152_mdio_write(tp, reg, val);
  569. }
  570. static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
  571. {
  572. u16 ocp_base, ocp_index;
  573. ocp_base = addr & 0xf000;
  574. if (ocp_base != tp->ocp_base) {
  575. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
  576. tp->ocp_base = ocp_base;
  577. }
  578. ocp_index = (addr & 0x0fff) | 0xb000;
  579. ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
  580. }
  581. static
  582. int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
  583. static inline void set_ethernet_addr(struct r8152 *tp)
  584. {
  585. struct net_device *dev = tp->netdev;
  586. u8 node_id[8] = {0};
  587. if (pla_ocp_read(tp, PLA_IDR, sizeof(node_id), node_id) < 0)
  588. netif_notice(tp, probe, dev, "inet addr fail\n");
  589. else {
  590. memcpy(dev->dev_addr, node_id, dev->addr_len);
  591. memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
  592. }
  593. }
  594. static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
  595. {
  596. struct r8152 *tp = netdev_priv(netdev);
  597. struct sockaddr *addr = p;
  598. if (!is_valid_ether_addr(addr->sa_data))
  599. return -EADDRNOTAVAIL;
  600. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  601. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  602. pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
  603. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  604. return 0;
  605. }
  606. static struct net_device_stats *rtl8152_get_stats(struct net_device *dev)
  607. {
  608. return &dev->stats;
  609. }
  610. static void read_bulk_callback(struct urb *urb)
  611. {
  612. struct net_device *netdev;
  613. unsigned long lockflags;
  614. int status = urb->status;
  615. struct rx_agg *agg;
  616. struct r8152 *tp;
  617. int result;
  618. agg = urb->context;
  619. if (!agg)
  620. return;
  621. tp = agg->context;
  622. if (!tp)
  623. return;
  624. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  625. return;
  626. if (!test_bit(WORK_ENABLE, &tp->flags))
  627. return;
  628. netdev = tp->netdev;
  629. if (!netif_carrier_ok(netdev))
  630. return;
  631. switch (status) {
  632. case 0:
  633. if (urb->actual_length < ETH_ZLEN)
  634. break;
  635. spin_lock_irqsave(&tp->rx_lock, lockflags);
  636. list_add_tail(&agg->list, &tp->rx_done);
  637. spin_unlock_irqrestore(&tp->rx_lock, lockflags);
  638. tasklet_schedule(&tp->tl);
  639. return;
  640. case -ESHUTDOWN:
  641. set_bit(RTL8152_UNPLUG, &tp->flags);
  642. netif_device_detach(tp->netdev);
  643. return;
  644. case -ENOENT:
  645. return; /* the urb is in unlink state */
  646. case -ETIME:
  647. pr_warn_ratelimited("may be reset is needed?..\n");
  648. break;
  649. default:
  650. pr_warn_ratelimited("Rx status %d\n", status);
  651. break;
  652. }
  653. result = r8152_submit_rx(tp, agg, GFP_ATOMIC);
  654. if (result == -ENODEV) {
  655. netif_device_detach(tp->netdev);
  656. } else if (result) {
  657. spin_lock_irqsave(&tp->rx_lock, lockflags);
  658. list_add_tail(&agg->list, &tp->rx_done);
  659. spin_unlock_irqrestore(&tp->rx_lock, lockflags);
  660. tasklet_schedule(&tp->tl);
  661. }
  662. }
  663. static void write_bulk_callback(struct urb *urb)
  664. {
  665. struct net_device_stats *stats;
  666. unsigned long lockflags;
  667. struct tx_agg *agg;
  668. struct r8152 *tp;
  669. int status = urb->status;
  670. agg = urb->context;
  671. if (!agg)
  672. return;
  673. tp = agg->context;
  674. if (!tp)
  675. return;
  676. stats = rtl8152_get_stats(tp->netdev);
  677. if (status) {
  678. pr_warn_ratelimited("Tx status %d\n", status);
  679. stats->tx_errors += agg->skb_num;
  680. } else {
  681. stats->tx_packets += agg->skb_num;
  682. stats->tx_bytes += agg->skb_len;
  683. }
  684. spin_lock_irqsave(&tp->tx_lock, lockflags);
  685. list_add_tail(&agg->list, &tp->tx_free);
  686. spin_unlock_irqrestore(&tp->tx_lock, lockflags);
  687. if (!netif_carrier_ok(tp->netdev))
  688. return;
  689. if (!test_bit(WORK_ENABLE, &tp->flags))
  690. return;
  691. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  692. return;
  693. if (!skb_queue_empty(&tp->tx_queue))
  694. tasklet_schedule(&tp->tl);
  695. }
  696. static inline void *rx_agg_align(void *data)
  697. {
  698. return (void *)ALIGN((uintptr_t)data, 8);
  699. }
  700. static inline void *tx_agg_align(void *data)
  701. {
  702. return (void *)ALIGN((uintptr_t)data, 4);
  703. }
  704. static void free_all_mem(struct r8152 *tp)
  705. {
  706. int i;
  707. for (i = 0; i < RTL8152_MAX_RX; i++) {
  708. if (tp->rx_info[i].urb) {
  709. usb_free_urb(tp->rx_info[i].urb);
  710. tp->rx_info[i].urb = NULL;
  711. }
  712. if (tp->rx_info[i].buffer) {
  713. kfree(tp->rx_info[i].buffer);
  714. tp->rx_info[i].buffer = NULL;
  715. tp->rx_info[i].head = NULL;
  716. }
  717. }
  718. for (i = 0; i < RTL8152_MAX_TX; i++) {
  719. if (tp->tx_info[i].urb) {
  720. usb_free_urb(tp->tx_info[i].urb);
  721. tp->tx_info[i].urb = NULL;
  722. }
  723. if (tp->tx_info[i].buffer) {
  724. kfree(tp->tx_info[i].buffer);
  725. tp->tx_info[i].buffer = NULL;
  726. tp->tx_info[i].head = NULL;
  727. }
  728. }
  729. }
  730. static int alloc_all_mem(struct r8152 *tp)
  731. {
  732. struct net_device *netdev = tp->netdev;
  733. struct urb *urb;
  734. int node, i;
  735. u8 *buf;
  736. node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
  737. spin_lock_init(&tp->rx_lock);
  738. spin_lock_init(&tp->tx_lock);
  739. INIT_LIST_HEAD(&tp->rx_done);
  740. INIT_LIST_HEAD(&tp->tx_free);
  741. skb_queue_head_init(&tp->tx_queue);
  742. for (i = 0; i < RTL8152_MAX_RX; i++) {
  743. buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
  744. if (!buf)
  745. goto err1;
  746. if (buf != rx_agg_align(buf)) {
  747. kfree(buf);
  748. buf = kmalloc_node(rx_buf_sz + 8, GFP_KERNEL, node);
  749. if (!buf)
  750. goto err1;
  751. }
  752. urb = usb_alloc_urb(0, GFP_KERNEL);
  753. if (!urb) {
  754. kfree(buf);
  755. goto err1;
  756. }
  757. INIT_LIST_HEAD(&tp->rx_info[i].list);
  758. tp->rx_info[i].context = tp;
  759. tp->rx_info[i].urb = urb;
  760. tp->rx_info[i].buffer = buf;
  761. tp->rx_info[i].head = rx_agg_align(buf);
  762. }
  763. for (i = 0; i < RTL8152_MAX_TX; i++) {
  764. buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
  765. if (!buf)
  766. goto err1;
  767. if (buf != tx_agg_align(buf)) {
  768. kfree(buf);
  769. buf = kmalloc_node(rx_buf_sz + 4, GFP_KERNEL, node);
  770. if (!buf)
  771. goto err1;
  772. }
  773. urb = usb_alloc_urb(0, GFP_KERNEL);
  774. if (!urb) {
  775. kfree(buf);
  776. goto err1;
  777. }
  778. INIT_LIST_HEAD(&tp->tx_info[i].list);
  779. tp->tx_info[i].context = tp;
  780. tp->tx_info[i].urb = urb;
  781. tp->tx_info[i].buffer = buf;
  782. tp->tx_info[i].head = tx_agg_align(buf);
  783. list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
  784. }
  785. return 0;
  786. err1:
  787. free_all_mem(tp);
  788. return -ENOMEM;
  789. }
  790. static void
  791. r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, struct sk_buff *skb)
  792. {
  793. memset(desc, 0, sizeof(*desc));
  794. desc->opts1 = cpu_to_le32((skb->len & TX_LEN_MASK) | TX_FS | TX_LS);
  795. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  796. __be16 protocol;
  797. u8 ip_protocol;
  798. u32 opts2 = 0;
  799. if (skb->protocol == htons(ETH_P_8021Q))
  800. protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
  801. else
  802. protocol = skb->protocol;
  803. switch (protocol) {
  804. case htons(ETH_P_IP):
  805. opts2 |= IPV4_CS;
  806. ip_protocol = ip_hdr(skb)->protocol;
  807. break;
  808. case htons(ETH_P_IPV6):
  809. opts2 |= IPV6_CS;
  810. ip_protocol = ipv6_hdr(skb)->nexthdr;
  811. break;
  812. default:
  813. ip_protocol = IPPROTO_RAW;
  814. break;
  815. }
  816. if (ip_protocol == IPPROTO_TCP) {
  817. opts2 |= TCP_CS;
  818. opts2 |= (skb_transport_offset(skb) & 0x7fff) << 17;
  819. } else if (ip_protocol == IPPROTO_UDP) {
  820. opts2 |= UDP_CS;
  821. } else {
  822. WARN_ON_ONCE(1);
  823. }
  824. desc->opts2 = cpu_to_le32(opts2);
  825. }
  826. }
  827. static void rx_bottom(struct r8152 *tp)
  828. {
  829. struct net_device_stats *stats;
  830. struct net_device *netdev;
  831. struct rx_agg *agg;
  832. struct rx_desc *rx_desc;
  833. unsigned long lockflags;
  834. struct list_head *cursor, *next;
  835. struct sk_buff *skb;
  836. struct urb *urb;
  837. unsigned pkt_len;
  838. int len_used;
  839. u8 *rx_data;
  840. int ret;
  841. netdev = tp->netdev;
  842. stats = rtl8152_get_stats(netdev);
  843. spin_lock_irqsave(&tp->rx_lock, lockflags);
  844. list_for_each_safe(cursor, next, &tp->rx_done) {
  845. list_del_init(cursor);
  846. spin_unlock_irqrestore(&tp->rx_lock, lockflags);
  847. agg = list_entry(cursor, struct rx_agg, list);
  848. urb = agg->urb;
  849. if (urb->actual_length < ETH_ZLEN) {
  850. ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
  851. spin_lock_irqsave(&tp->rx_lock, lockflags);
  852. if (ret && ret != -ENODEV) {
  853. list_add_tail(&agg->list, next);
  854. tasklet_schedule(&tp->tl);
  855. }
  856. continue;
  857. }
  858. len_used = 0;
  859. rx_desc = agg->head;
  860. rx_data = agg->head;
  861. pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
  862. len_used += sizeof(struct rx_desc) + pkt_len;
  863. while (urb->actual_length >= len_used) {
  864. if (pkt_len < ETH_ZLEN)
  865. break;
  866. pkt_len -= 4; /* CRC */
  867. rx_data += sizeof(struct rx_desc);
  868. skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
  869. if (!skb) {
  870. stats->rx_dropped++;
  871. break;
  872. }
  873. memcpy(skb->data, rx_data, pkt_len);
  874. skb_put(skb, pkt_len);
  875. skb->protocol = eth_type_trans(skb, netdev);
  876. netif_rx(skb);
  877. stats->rx_packets++;
  878. stats->rx_bytes += pkt_len;
  879. rx_data = rx_agg_align(rx_data + pkt_len + 4);
  880. rx_desc = (struct rx_desc *)rx_data;
  881. pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
  882. len_used = (int)(rx_data - (u8 *)agg->head);
  883. len_used += sizeof(struct rx_desc) + pkt_len;
  884. }
  885. ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
  886. spin_lock_irqsave(&tp->rx_lock, lockflags);
  887. if (ret && ret != -ENODEV) {
  888. list_add_tail(&agg->list, next);
  889. tasklet_schedule(&tp->tl);
  890. }
  891. }
  892. spin_unlock_irqrestore(&tp->rx_lock, lockflags);
  893. }
  894. static void tx_bottom(struct r8152 *tp)
  895. {
  896. struct net_device_stats *stats;
  897. struct net_device *netdev;
  898. struct tx_agg *agg;
  899. unsigned long lockflags;
  900. u32 remain, total;
  901. u8 *tx_data;
  902. int res;
  903. netdev = tp->netdev;
  904. next_agg:
  905. agg = NULL;
  906. spin_lock_irqsave(&tp->tx_lock, lockflags);
  907. if (!skb_queue_empty(&tp->tx_queue) && !list_empty(&tp->tx_free)) {
  908. struct list_head *cursor;
  909. cursor = tp->tx_free.next;
  910. list_del_init(cursor);
  911. agg = list_entry(cursor, struct tx_agg, list);
  912. }
  913. spin_unlock_irqrestore(&tp->tx_lock, lockflags);
  914. if (!agg)
  915. return;
  916. tx_data = agg->head;
  917. agg->skb_num = agg->skb_len = 0;
  918. remain = rx_buf_sz - sizeof(struct tx_desc);
  919. total = 0;
  920. while (remain >= ETH_ZLEN) {
  921. struct tx_desc *tx_desc;
  922. struct sk_buff *skb;
  923. unsigned int len;
  924. skb = skb_dequeue(&tp->tx_queue);
  925. if (!skb)
  926. break;
  927. len = skb->len;
  928. if (remain < len) {
  929. skb_queue_head(&tp->tx_queue, skb);
  930. break;
  931. }
  932. tx_data = tx_agg_align(tx_data);
  933. tx_desc = (struct tx_desc *)tx_data;
  934. tx_data += sizeof(*tx_desc);
  935. r8152_tx_csum(tp, tx_desc, skb);
  936. memcpy(tx_data, skb->data, len);
  937. agg->skb_num++;
  938. agg->skb_len += len;
  939. dev_kfree_skb_any(skb);
  940. tx_data += len;
  941. remain = rx_buf_sz - sizeof(*tx_desc) -
  942. (u32)(tx_agg_align(tx_data) - agg->head);
  943. }
  944. usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
  945. agg->head, (int)(tx_data - (u8 *)agg->head),
  946. (usb_complete_t)write_bulk_callback, agg);
  947. res = usb_submit_urb(agg->urb, GFP_ATOMIC);
  948. stats = rtl8152_get_stats(netdev);
  949. if (res) {
  950. /* Can we get/handle EPIPE here? */
  951. if (res == -ENODEV) {
  952. netif_device_detach(netdev);
  953. } else {
  954. netif_warn(tp, tx_err, netdev,
  955. "failed tx_urb %d\n", res);
  956. stats->tx_dropped += agg->skb_num;
  957. spin_lock_irqsave(&tp->tx_lock, lockflags);
  958. list_add_tail(&agg->list, &tp->tx_free);
  959. spin_unlock_irqrestore(&tp->tx_lock, lockflags);
  960. }
  961. return;
  962. }
  963. goto next_agg;
  964. }
  965. static void bottom_half(unsigned long data)
  966. {
  967. struct r8152 *tp;
  968. tp = (struct r8152 *)data;
  969. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  970. return;
  971. if (!test_bit(WORK_ENABLE, &tp->flags))
  972. return;
  973. if (!netif_carrier_ok(tp->netdev))
  974. return;
  975. rx_bottom(tp);
  976. tx_bottom(tp);
  977. }
  978. static
  979. int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
  980. {
  981. usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
  982. agg->head, rx_buf_sz,
  983. (usb_complete_t)read_bulk_callback, agg);
  984. return usb_submit_urb(agg->urb, mem_flags);
  985. }
  986. static void rtl8152_tx_timeout(struct net_device *netdev)
  987. {
  988. struct r8152 *tp = netdev_priv(netdev);
  989. int i;
  990. netif_warn(tp, tx_err, netdev, "Tx timeout.\n");
  991. for (i = 0; i < RTL8152_MAX_TX; i++)
  992. usb_unlink_urb(tp->tx_info[i].urb);
  993. }
  994. static void rtl8152_set_rx_mode(struct net_device *netdev)
  995. {
  996. struct r8152 *tp = netdev_priv(netdev);
  997. if (tp->speed & LINK_STATUS)
  998. set_bit(RTL8152_SET_RX_MODE, &tp->flags);
  999. }
  1000. static void _rtl8152_set_rx_mode(struct net_device *netdev)
  1001. {
  1002. struct r8152 *tp = netdev_priv(netdev);
  1003. u32 mc_filter[2]; /* Multicast hash filter */
  1004. __le32 tmp[2];
  1005. u32 ocp_data;
  1006. clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
  1007. netif_stop_queue(netdev);
  1008. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1009. ocp_data &= ~RCR_ACPT_ALL;
  1010. ocp_data |= RCR_AB | RCR_APM;
  1011. if (netdev->flags & IFF_PROMISC) {
  1012. /* Unconditionally log net taps. */
  1013. netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
  1014. ocp_data |= RCR_AM | RCR_AAP;
  1015. mc_filter[1] = mc_filter[0] = 0xffffffff;
  1016. } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
  1017. (netdev->flags & IFF_ALLMULTI)) {
  1018. /* Too many to filter perfectly -- accept all multicasts. */
  1019. ocp_data |= RCR_AM;
  1020. mc_filter[1] = mc_filter[0] = 0xffffffff;
  1021. } else {
  1022. struct netdev_hw_addr *ha;
  1023. mc_filter[1] = mc_filter[0] = 0;
  1024. netdev_for_each_mc_addr(ha, netdev) {
  1025. int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
  1026. mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
  1027. ocp_data |= RCR_AM;
  1028. }
  1029. }
  1030. tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
  1031. tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
  1032. pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
  1033. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1034. netif_wake_queue(netdev);
  1035. }
  1036. static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
  1037. struct net_device *netdev)
  1038. {
  1039. struct r8152 *tp = netdev_priv(netdev);
  1040. struct net_device_stats *stats = rtl8152_get_stats(netdev);
  1041. unsigned long lockflags;
  1042. struct tx_agg *agg = NULL;
  1043. struct tx_desc *tx_desc;
  1044. unsigned int len;
  1045. u8 *tx_data;
  1046. int res;
  1047. skb_tx_timestamp(skb);
  1048. spin_lock_irqsave(&tp->tx_lock, lockflags);
  1049. if (!list_empty(&tp->tx_free) && skb_queue_empty(&tp->tx_queue)) {
  1050. struct list_head *cursor;
  1051. cursor = tp->tx_free.next;
  1052. list_del_init(cursor);
  1053. agg = list_entry(cursor, struct tx_agg, list);
  1054. }
  1055. spin_unlock_irqrestore(&tp->tx_lock, lockflags);
  1056. if (!agg) {
  1057. skb_queue_tail(&tp->tx_queue, skb);
  1058. return NETDEV_TX_OK;
  1059. }
  1060. tx_desc = (struct tx_desc *)agg->head;
  1061. tx_data = agg->head + sizeof(*tx_desc);
  1062. agg->skb_num = agg->skb_len = 0;
  1063. len = skb->len;
  1064. r8152_tx_csum(tp, tx_desc, skb);
  1065. memcpy(tx_data, skb->data, len);
  1066. dev_kfree_skb_any(skb);
  1067. agg->skb_num++;
  1068. agg->skb_len += len;
  1069. usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
  1070. agg->head, len + sizeof(*tx_desc),
  1071. (usb_complete_t)write_bulk_callback, agg);
  1072. res = usb_submit_urb(agg->urb, GFP_ATOMIC);
  1073. if (res) {
  1074. /* Can we get/handle EPIPE here? */
  1075. if (res == -ENODEV) {
  1076. netif_device_detach(tp->netdev);
  1077. } else {
  1078. netif_warn(tp, tx_err, netdev,
  1079. "failed tx_urb %d\n", res);
  1080. stats->tx_dropped++;
  1081. spin_lock_irqsave(&tp->tx_lock, lockflags);
  1082. list_add_tail(&agg->list, &tp->tx_free);
  1083. spin_unlock_irqrestore(&tp->tx_lock, lockflags);
  1084. }
  1085. }
  1086. return NETDEV_TX_OK;
  1087. }
  1088. static void r8152b_reset_packet_filter(struct r8152 *tp)
  1089. {
  1090. u32 ocp_data;
  1091. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
  1092. ocp_data &= ~FMC_FCR_MCU_EN;
  1093. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  1094. ocp_data |= FMC_FCR_MCU_EN;
  1095. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  1096. }
  1097. static void rtl8152_nic_reset(struct r8152 *tp)
  1098. {
  1099. int i;
  1100. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
  1101. for (i = 0; i < 1000; i++) {
  1102. if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
  1103. break;
  1104. udelay(100);
  1105. }
  1106. }
  1107. static inline u8 rtl8152_get_speed(struct r8152 *tp)
  1108. {
  1109. return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
  1110. }
  1111. static int rtl8152_enable(struct r8152 *tp)
  1112. {
  1113. u32 ocp_data;
  1114. int i, ret;
  1115. u8 speed;
  1116. speed = rtl8152_get_speed(tp);
  1117. if (speed & _10bps) {
  1118. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
  1119. ocp_data |= EEEP_CR_EEEP_TX;
  1120. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
  1121. } else {
  1122. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
  1123. ocp_data &= ~EEEP_CR_EEEP_TX;
  1124. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
  1125. }
  1126. r8152b_reset_packet_filter(tp);
  1127. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
  1128. ocp_data |= CR_RE | CR_TE;
  1129. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
  1130. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
  1131. ocp_data &= ~RXDY_GATED_EN;
  1132. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
  1133. INIT_LIST_HEAD(&tp->rx_done);
  1134. ret = 0;
  1135. for (i = 0; i < RTL8152_MAX_RX; i++) {
  1136. INIT_LIST_HEAD(&tp->rx_info[i].list);
  1137. ret |= r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
  1138. }
  1139. return ret;
  1140. }
  1141. static void rtl8152_disable(struct r8152 *tp)
  1142. {
  1143. struct net_device_stats *stats = rtl8152_get_stats(tp->netdev);
  1144. struct sk_buff *skb;
  1145. u32 ocp_data;
  1146. int i;
  1147. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1148. ocp_data &= ~RCR_ACPT_ALL;
  1149. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1150. while ((skb = skb_dequeue(&tp->tx_queue))) {
  1151. dev_kfree_skb(skb);
  1152. stats->tx_dropped++;
  1153. }
  1154. for (i = 0; i < RTL8152_MAX_TX; i++)
  1155. usb_kill_urb(tp->tx_info[i].urb);
  1156. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
  1157. ocp_data |= RXDY_GATED_EN;
  1158. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
  1159. for (i = 0; i < 1000; i++) {
  1160. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1161. if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
  1162. break;
  1163. mdelay(1);
  1164. }
  1165. for (i = 0; i < 1000; i++) {
  1166. if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
  1167. break;
  1168. mdelay(1);
  1169. }
  1170. for (i = 0; i < RTL8152_MAX_RX; i++)
  1171. usb_kill_urb(tp->rx_info[i].urb);
  1172. rtl8152_nic_reset(tp);
  1173. }
  1174. static void r8152b_exit_oob(struct r8152 *tp)
  1175. {
  1176. u32 ocp_data;
  1177. int i;
  1178. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1179. ocp_data &= ~RCR_ACPT_ALL;
  1180. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1181. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
  1182. ocp_data |= RXDY_GATED_EN;
  1183. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
  1184. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  1185. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
  1186. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1187. ocp_data &= ~NOW_IS_OOB;
  1188. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  1189. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  1190. ocp_data &= ~MCU_BORW_EN;
  1191. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  1192. for (i = 0; i < 1000; i++) {
  1193. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1194. if (ocp_data & LINK_LIST_READY)
  1195. break;
  1196. mdelay(1);
  1197. }
  1198. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  1199. ocp_data |= RE_INIT_LL;
  1200. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  1201. for (i = 0; i < 1000; i++) {
  1202. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1203. if (ocp_data & LINK_LIST_READY)
  1204. break;
  1205. mdelay(1);
  1206. }
  1207. rtl8152_nic_reset(tp);
  1208. /* rx share fifo credit full threshold */
  1209. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
  1210. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_DEV_STAT);
  1211. ocp_data &= STAT_SPEED_MASK;
  1212. if (ocp_data == STAT_SPEED_FULL) {
  1213. /* rx share fifo credit near full threshold */
  1214. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  1215. RXFIFO_THR2_FULL);
  1216. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  1217. RXFIFO_THR3_FULL);
  1218. } else {
  1219. /* rx share fifo credit near full threshold */
  1220. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  1221. RXFIFO_THR2_HIGH);
  1222. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  1223. RXFIFO_THR3_HIGH);
  1224. }
  1225. /* TX share fifo free credit full threshold */
  1226. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
  1227. ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
  1228. ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_BUF_THR);
  1229. ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
  1230. TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
  1231. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
  1232. ocp_data &= ~CPCR_RX_VLAN;
  1233. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
  1234. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  1235. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
  1236. ocp_data |= TCR0_AUTO_FIFO;
  1237. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
  1238. }
  1239. static void r8152b_enter_oob(struct r8152 *tp)
  1240. {
  1241. u32 ocp_data;
  1242. int i;
  1243. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1244. ocp_data &= ~NOW_IS_OOB;
  1245. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  1246. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
  1247. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
  1248. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
  1249. rtl8152_disable(tp);
  1250. for (i = 0; i < 1000; i++) {
  1251. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1252. if (ocp_data & LINK_LIST_READY)
  1253. break;
  1254. mdelay(1);
  1255. }
  1256. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  1257. ocp_data |= RE_INIT_LL;
  1258. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  1259. for (i = 0; i < 1000; i++) {
  1260. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1261. if (ocp_data & LINK_LIST_READY)
  1262. break;
  1263. mdelay(1);
  1264. }
  1265. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  1266. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
  1267. ocp_data |= MAGIC_EN;
  1268. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
  1269. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
  1270. ocp_data |= CPCR_RX_VLAN;
  1271. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
  1272. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
  1273. ocp_data |= ALDPS_PROXY_MODE;
  1274. ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
  1275. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1276. ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
  1277. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  1278. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5, LAN_WAKE_EN);
  1279. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
  1280. ocp_data &= ~RXDY_GATED_EN;
  1281. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
  1282. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1283. ocp_data |= RCR_APM | RCR_AM | RCR_AB;
  1284. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1285. }
  1286. static void r8152b_disable_aldps(struct r8152 *tp)
  1287. {
  1288. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
  1289. msleep(20);
  1290. }
  1291. static inline void r8152b_enable_aldps(struct r8152 *tp)
  1292. {
  1293. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
  1294. LINKENA | DIS_SDSAVE);
  1295. }
  1296. static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
  1297. {
  1298. u16 bmcr, anar;
  1299. int ret = 0;
  1300. cancel_delayed_work_sync(&tp->schedule);
  1301. anar = r8152_mdio_read(tp, MII_ADVERTISE);
  1302. anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
  1303. ADVERTISE_100HALF | ADVERTISE_100FULL);
  1304. if (autoneg == AUTONEG_DISABLE) {
  1305. if (speed == SPEED_10) {
  1306. bmcr = 0;
  1307. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  1308. } else if (speed == SPEED_100) {
  1309. bmcr = BMCR_SPEED100;
  1310. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  1311. } else {
  1312. ret = -EINVAL;
  1313. goto out;
  1314. }
  1315. if (duplex == DUPLEX_FULL)
  1316. bmcr |= BMCR_FULLDPLX;
  1317. } else {
  1318. if (speed == SPEED_10) {
  1319. if (duplex == DUPLEX_FULL)
  1320. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  1321. else
  1322. anar |= ADVERTISE_10HALF;
  1323. } else if (speed == SPEED_100) {
  1324. if (duplex == DUPLEX_FULL) {
  1325. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  1326. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  1327. } else {
  1328. anar |= ADVERTISE_10HALF;
  1329. anar |= ADVERTISE_100HALF;
  1330. }
  1331. } else {
  1332. ret = -EINVAL;
  1333. goto out;
  1334. }
  1335. bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
  1336. }
  1337. r8152_mdio_write(tp, MII_ADVERTISE, anar);
  1338. r8152_mdio_write(tp, MII_BMCR, bmcr);
  1339. out:
  1340. schedule_delayed_work(&tp->schedule, 5 * HZ);
  1341. return ret;
  1342. }
  1343. static void rtl8152_down(struct r8152 *tp)
  1344. {
  1345. u32 ocp_data;
  1346. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
  1347. ocp_data &= ~POWER_CUT;
  1348. ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
  1349. r8152b_disable_aldps(tp);
  1350. r8152b_enter_oob(tp);
  1351. r8152b_enable_aldps(tp);
  1352. }
  1353. static void set_carrier(struct r8152 *tp)
  1354. {
  1355. struct net_device *netdev = tp->netdev;
  1356. u8 speed;
  1357. speed = rtl8152_get_speed(tp);
  1358. if (speed & LINK_STATUS) {
  1359. if (!(tp->speed & LINK_STATUS)) {
  1360. rtl8152_enable(tp);
  1361. set_bit(RTL8152_SET_RX_MODE, &tp->flags);
  1362. netif_carrier_on(netdev);
  1363. }
  1364. } else {
  1365. if (tp->speed & LINK_STATUS) {
  1366. netif_carrier_off(netdev);
  1367. tasklet_disable(&tp->tl);
  1368. rtl8152_disable(tp);
  1369. tasklet_enable(&tp->tl);
  1370. }
  1371. }
  1372. tp->speed = speed;
  1373. }
  1374. static void rtl_work_func_t(struct work_struct *work)
  1375. {
  1376. struct r8152 *tp = container_of(work, struct r8152, schedule.work);
  1377. if (!test_bit(WORK_ENABLE, &tp->flags))
  1378. goto out1;
  1379. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1380. goto out1;
  1381. set_carrier(tp);
  1382. if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
  1383. _rtl8152_set_rx_mode(tp->netdev);
  1384. schedule_delayed_work(&tp->schedule, HZ);
  1385. out1:
  1386. return;
  1387. }
  1388. static int rtl8152_open(struct net_device *netdev)
  1389. {
  1390. struct r8152 *tp = netdev_priv(netdev);
  1391. int res = 0;
  1392. tp->speed = rtl8152_get_speed(tp);
  1393. if (tp->speed & LINK_STATUS) {
  1394. res = rtl8152_enable(tp);
  1395. if (res) {
  1396. if (res == -ENODEV)
  1397. netif_device_detach(tp->netdev);
  1398. netif_err(tp, ifup, netdev,
  1399. "rtl8152_open failed: %d\n", res);
  1400. return res;
  1401. }
  1402. netif_carrier_on(netdev);
  1403. } else {
  1404. netif_stop_queue(netdev);
  1405. netif_carrier_off(netdev);
  1406. }
  1407. rtl8152_set_speed(tp, AUTONEG_ENABLE, SPEED_100, DUPLEX_FULL);
  1408. netif_start_queue(netdev);
  1409. set_bit(WORK_ENABLE, &tp->flags);
  1410. schedule_delayed_work(&tp->schedule, 0);
  1411. return res;
  1412. }
  1413. static int rtl8152_close(struct net_device *netdev)
  1414. {
  1415. struct r8152 *tp = netdev_priv(netdev);
  1416. int res = 0;
  1417. clear_bit(WORK_ENABLE, &tp->flags);
  1418. cancel_delayed_work_sync(&tp->schedule);
  1419. netif_stop_queue(netdev);
  1420. tasklet_disable(&tp->tl);
  1421. rtl8152_disable(tp);
  1422. tasklet_enable(&tp->tl);
  1423. return res;
  1424. }
  1425. static void rtl_clear_bp(struct r8152 *tp)
  1426. {
  1427. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_0, 0);
  1428. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_2, 0);
  1429. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_4, 0);
  1430. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_6, 0);
  1431. ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_0, 0);
  1432. ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_2, 0);
  1433. ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_4, 0);
  1434. ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_6, 0);
  1435. mdelay(3);
  1436. ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_BA, 0);
  1437. ocp_write_word(tp, MCU_TYPE_USB, USB_BP_BA, 0);
  1438. }
  1439. static void r8152b_enable_eee(struct r8152 *tp)
  1440. {
  1441. u32 ocp_data;
  1442. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  1443. ocp_data |= EEE_RX_EN | EEE_TX_EN;
  1444. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
  1445. ocp_reg_write(tp, OCP_EEE_CONFIG1, RG_TXLPI_MSK_HFDUP | RG_MATCLR_EN |
  1446. EEE_10_CAP | EEE_NWAY_EN |
  1447. TX_QUIET_EN | RX_QUIET_EN |
  1448. SDRISETIME | RG_RXLPI_MSK_HFDUP |
  1449. SDFALLTIME);
  1450. ocp_reg_write(tp, OCP_EEE_CONFIG2, RG_LPIHYS_NUM | RG_DACQUIET_EN |
  1451. RG_LDVQUIET_EN | RG_CKRSEL |
  1452. RG_EEEPRG_EN);
  1453. ocp_reg_write(tp, OCP_EEE_CONFIG3, FST_SNR_EYE_R | RG_LFS_SEL | MSK_PH);
  1454. ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | DEVICE_ADDR);
  1455. ocp_reg_write(tp, OCP_EEE_DATA, EEE_ADDR);
  1456. ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | DEVICE_ADDR);
  1457. ocp_reg_write(tp, OCP_EEE_DATA, EEE_DATA);
  1458. ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
  1459. }
  1460. static void r8152b_enable_fc(struct r8152 *tp)
  1461. {
  1462. u16 anar;
  1463. anar = r8152_mdio_read(tp, MII_ADVERTISE);
  1464. anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  1465. r8152_mdio_write(tp, MII_ADVERTISE, anar);
  1466. }
  1467. static void r8152b_hw_phy_cfg(struct r8152 *tp)
  1468. {
  1469. r8152_mdio_write(tp, MII_BMCR, BMCR_ANENABLE);
  1470. r8152b_disable_aldps(tp);
  1471. }
  1472. static void r8152b_init(struct r8152 *tp)
  1473. {
  1474. u32 ocp_data;
  1475. int i;
  1476. rtl_clear_bp(tp);
  1477. if (tp->version == RTL_VER_01) {
  1478. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
  1479. ocp_data &= ~LED_MODE_MASK;
  1480. ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
  1481. }
  1482. r8152b_hw_phy_cfg(tp);
  1483. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
  1484. ocp_data &= ~POWER_CUT;
  1485. ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
  1486. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
  1487. ocp_data &= ~RWSUME_INDICATE;
  1488. ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
  1489. r8152b_exit_oob(tp);
  1490. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  1491. ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
  1492. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  1493. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
  1494. ocp_data &= ~MCU_CLK_RATIO_MASK;
  1495. ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
  1496. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
  1497. ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
  1498. SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
  1499. ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
  1500. r8152b_enable_eee(tp);
  1501. r8152b_enable_aldps(tp);
  1502. r8152b_enable_fc(tp);
  1503. r8152_mdio_write(tp, MII_BMCR, BMCR_RESET | BMCR_ANENABLE |
  1504. BMCR_ANRESTART);
  1505. for (i = 0; i < 100; i++) {
  1506. udelay(100);
  1507. if (!(r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET))
  1508. break;
  1509. }
  1510. /* enable rx aggregation */
  1511. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  1512. ocp_data &= ~RX_AGG_DISABLE;
  1513. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  1514. }
  1515. static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
  1516. {
  1517. struct r8152 *tp = usb_get_intfdata(intf);
  1518. netif_device_detach(tp->netdev);
  1519. if (netif_running(tp->netdev)) {
  1520. clear_bit(WORK_ENABLE, &tp->flags);
  1521. cancel_delayed_work_sync(&tp->schedule);
  1522. tasklet_disable(&tp->tl);
  1523. }
  1524. rtl8152_down(tp);
  1525. return 0;
  1526. }
  1527. static int rtl8152_resume(struct usb_interface *intf)
  1528. {
  1529. struct r8152 *tp = usb_get_intfdata(intf);
  1530. r8152b_init(tp);
  1531. netif_device_attach(tp->netdev);
  1532. if (netif_running(tp->netdev)) {
  1533. rtl8152_enable(tp);
  1534. set_bit(WORK_ENABLE, &tp->flags);
  1535. set_bit(RTL8152_SET_RX_MODE, &tp->flags);
  1536. schedule_delayed_work(&tp->schedule, 0);
  1537. tasklet_enable(&tp->tl);
  1538. }
  1539. return 0;
  1540. }
  1541. static void rtl8152_get_drvinfo(struct net_device *netdev,
  1542. struct ethtool_drvinfo *info)
  1543. {
  1544. struct r8152 *tp = netdev_priv(netdev);
  1545. strncpy(info->driver, MODULENAME, ETHTOOL_BUSINFO_LEN);
  1546. strncpy(info->version, DRIVER_VERSION, ETHTOOL_BUSINFO_LEN);
  1547. usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
  1548. }
  1549. static
  1550. int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
  1551. {
  1552. struct r8152 *tp = netdev_priv(netdev);
  1553. if (!tp->mii.mdio_read)
  1554. return -EOPNOTSUPP;
  1555. return mii_ethtool_gset(&tp->mii, cmd);
  1556. }
  1557. static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1558. {
  1559. struct r8152 *tp = netdev_priv(dev);
  1560. return rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
  1561. }
  1562. static struct ethtool_ops ops = {
  1563. .get_drvinfo = rtl8152_get_drvinfo,
  1564. .get_settings = rtl8152_get_settings,
  1565. .set_settings = rtl8152_set_settings,
  1566. .get_link = ethtool_op_get_link,
  1567. };
  1568. static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
  1569. {
  1570. struct r8152 *tp = netdev_priv(netdev);
  1571. struct mii_ioctl_data *data = if_mii(rq);
  1572. int res = 0;
  1573. switch (cmd) {
  1574. case SIOCGMIIPHY:
  1575. data->phy_id = R8152_PHY_ID; /* Internal PHY */
  1576. break;
  1577. case SIOCGMIIREG:
  1578. data->val_out = r8152_mdio_read(tp, data->reg_num);
  1579. break;
  1580. case SIOCSMIIREG:
  1581. if (!capable(CAP_NET_ADMIN)) {
  1582. res = -EPERM;
  1583. break;
  1584. }
  1585. r8152_mdio_write(tp, data->reg_num, data->val_in);
  1586. break;
  1587. default:
  1588. res = -EOPNOTSUPP;
  1589. }
  1590. return res;
  1591. }
  1592. static const struct net_device_ops rtl8152_netdev_ops = {
  1593. .ndo_open = rtl8152_open,
  1594. .ndo_stop = rtl8152_close,
  1595. .ndo_do_ioctl = rtl8152_ioctl,
  1596. .ndo_start_xmit = rtl8152_start_xmit,
  1597. .ndo_tx_timeout = rtl8152_tx_timeout,
  1598. .ndo_set_rx_mode = rtl8152_set_rx_mode,
  1599. .ndo_set_mac_address = rtl8152_set_mac_address,
  1600. .ndo_change_mtu = eth_change_mtu,
  1601. .ndo_validate_addr = eth_validate_addr,
  1602. };
  1603. static void r8152b_get_version(struct r8152 *tp)
  1604. {
  1605. u32 ocp_data;
  1606. u16 version;
  1607. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
  1608. version = (u16)(ocp_data & VERSION_MASK);
  1609. switch (version) {
  1610. case 0x4c00:
  1611. tp->version = RTL_VER_01;
  1612. break;
  1613. case 0x4c10:
  1614. tp->version = RTL_VER_02;
  1615. break;
  1616. default:
  1617. netif_info(tp, probe, tp->netdev,
  1618. "Unknown version 0x%04x\n", version);
  1619. break;
  1620. }
  1621. }
  1622. static int rtl8152_probe(struct usb_interface *intf,
  1623. const struct usb_device_id *id)
  1624. {
  1625. struct usb_device *udev = interface_to_usbdev(intf);
  1626. struct r8152 *tp;
  1627. struct net_device *netdev;
  1628. int ret;
  1629. if (udev->actconfig->desc.bConfigurationValue != 1) {
  1630. usb_driver_set_configuration(udev, 1);
  1631. return -ENODEV;
  1632. }
  1633. netdev = alloc_etherdev(sizeof(struct r8152));
  1634. if (!netdev) {
  1635. dev_err(&intf->dev, "Out of memory");
  1636. return -ENOMEM;
  1637. }
  1638. SET_NETDEV_DEV(netdev, &intf->dev);
  1639. tp = netdev_priv(netdev);
  1640. memset(tp, 0, sizeof(*tp));
  1641. tp->msg_enable = 0x7FFF;
  1642. tasklet_init(&tp->tl, bottom_half, (unsigned long)tp);
  1643. INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
  1644. tp->udev = udev;
  1645. tp->netdev = netdev;
  1646. netdev->netdev_ops = &rtl8152_netdev_ops;
  1647. netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
  1648. netdev->features |= NETIF_F_IP_CSUM;
  1649. netdev->hw_features = NETIF_F_IP_CSUM;
  1650. SET_ETHTOOL_OPS(netdev, &ops);
  1651. tp->speed = 0;
  1652. tp->mii.dev = netdev;
  1653. tp->mii.mdio_read = read_mii_word;
  1654. tp->mii.mdio_write = write_mii_word;
  1655. tp->mii.phy_id_mask = 0x3f;
  1656. tp->mii.reg_num_mask = 0x1f;
  1657. tp->mii.phy_id = R8152_PHY_ID;
  1658. tp->mii.supports_gmii = 0;
  1659. r8152b_get_version(tp);
  1660. r8152b_init(tp);
  1661. set_ethernet_addr(tp);
  1662. ret = alloc_all_mem(tp);
  1663. if (ret)
  1664. goto out;
  1665. usb_set_intfdata(intf, tp);
  1666. ret = register_netdev(netdev);
  1667. if (ret != 0) {
  1668. netif_err(tp, probe, netdev, "couldn't register the device");
  1669. goto out1;
  1670. }
  1671. netif_info(tp, probe, netdev, "%s", DRIVER_VERSION);
  1672. return 0;
  1673. out1:
  1674. usb_set_intfdata(intf, NULL);
  1675. out:
  1676. free_netdev(netdev);
  1677. return ret;
  1678. }
  1679. static void rtl8152_unload(struct r8152 *tp)
  1680. {
  1681. u32 ocp_data;
  1682. if (tp->version != RTL_VER_01) {
  1683. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
  1684. ocp_data |= POWER_CUT;
  1685. ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
  1686. }
  1687. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
  1688. ocp_data &= ~RWSUME_INDICATE;
  1689. ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
  1690. }
  1691. static void rtl8152_disconnect(struct usb_interface *intf)
  1692. {
  1693. struct r8152 *tp = usb_get_intfdata(intf);
  1694. usb_set_intfdata(intf, NULL);
  1695. if (tp) {
  1696. set_bit(RTL8152_UNPLUG, &tp->flags);
  1697. tasklet_kill(&tp->tl);
  1698. unregister_netdev(tp->netdev);
  1699. rtl8152_unload(tp);
  1700. free_all_mem(tp);
  1701. free_netdev(tp->netdev);
  1702. }
  1703. }
  1704. /* table of devices that work with this driver */
  1705. static struct usb_device_id rtl8152_table[] = {
  1706. {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)},
  1707. {}
  1708. };
  1709. MODULE_DEVICE_TABLE(usb, rtl8152_table);
  1710. static struct usb_driver rtl8152_driver = {
  1711. .name = MODULENAME,
  1712. .id_table = rtl8152_table,
  1713. .probe = rtl8152_probe,
  1714. .disconnect = rtl8152_disconnect,
  1715. .suspend = rtl8152_suspend,
  1716. .resume = rtl8152_resume,
  1717. .reset_resume = rtl8152_resume,
  1718. };
  1719. module_usb_driver(rtl8152_driver);
  1720. MODULE_AUTHOR(DRIVER_AUTHOR);
  1721. MODULE_DESCRIPTION(DRIVER_DESC);
  1722. MODULE_LICENSE("GPL");