Kconfig 27 KB

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  1. #
  2. # For a description of the syntax of this configuration file,
  3. # see Documentation/kbuild/kconfig-language.txt.
  4. #
  5. mainmenu "Blackfin Kernel Configuration"
  6. config MMU
  7. bool
  8. default n
  9. config FPU
  10. bool
  11. default n
  12. config RWSEM_GENERIC_SPINLOCK
  13. bool
  14. default y
  15. config RWSEM_XCHGADD_ALGORITHM
  16. bool
  17. default n
  18. config BLACKFIN
  19. bool
  20. default y
  21. select HAVE_IDE
  22. select HAVE_OPROFILE
  23. select ARCH_WANT_OPTIONAL_GPIOLIB
  24. config ZONE_DMA
  25. bool
  26. default y
  27. config GENERIC_FIND_NEXT_BIT
  28. bool
  29. default y
  30. config GENERIC_HWEIGHT
  31. bool
  32. default y
  33. config GENERIC_HARDIRQS
  34. bool
  35. default y
  36. config GENERIC_IRQ_PROBE
  37. bool
  38. default y
  39. config GENERIC_GPIO
  40. bool
  41. default y
  42. config FORCE_MAX_ZONEORDER
  43. int
  44. default "14"
  45. config GENERIC_CALIBRATE_DELAY
  46. bool
  47. default y
  48. source "init/Kconfig"
  49. source "kernel/Kconfig.preempt"
  50. source "kernel/Kconfig.freezer"
  51. menu "Blackfin Processor Options"
  52. comment "Processor and Board Settings"
  53. choice
  54. prompt "CPU"
  55. default BF533
  56. config BF512
  57. bool "BF512"
  58. help
  59. BF512 Processor Support.
  60. config BF514
  61. bool "BF514"
  62. help
  63. BF514 Processor Support.
  64. config BF516
  65. bool "BF516"
  66. help
  67. BF516 Processor Support.
  68. config BF518
  69. bool "BF518"
  70. help
  71. BF518 Processor Support.
  72. config BF522
  73. bool "BF522"
  74. help
  75. BF522 Processor Support.
  76. config BF523
  77. bool "BF523"
  78. help
  79. BF523 Processor Support.
  80. config BF524
  81. bool "BF524"
  82. help
  83. BF524 Processor Support.
  84. config BF525
  85. bool "BF525"
  86. help
  87. BF525 Processor Support.
  88. config BF526
  89. bool "BF526"
  90. help
  91. BF526 Processor Support.
  92. config BF527
  93. bool "BF527"
  94. help
  95. BF527 Processor Support.
  96. config BF531
  97. bool "BF531"
  98. help
  99. BF531 Processor Support.
  100. config BF532
  101. bool "BF532"
  102. help
  103. BF532 Processor Support.
  104. config BF533
  105. bool "BF533"
  106. help
  107. BF533 Processor Support.
  108. config BF534
  109. bool "BF534"
  110. help
  111. BF534 Processor Support.
  112. config BF536
  113. bool "BF536"
  114. help
  115. BF536 Processor Support.
  116. config BF537
  117. bool "BF537"
  118. help
  119. BF537 Processor Support.
  120. config BF538
  121. bool "BF538"
  122. help
  123. BF538 Processor Support.
  124. config BF539
  125. bool "BF539"
  126. help
  127. BF539 Processor Support.
  128. config BF542
  129. bool "BF542"
  130. help
  131. BF542 Processor Support.
  132. config BF544
  133. bool "BF544"
  134. help
  135. BF544 Processor Support.
  136. config BF547
  137. bool "BF547"
  138. help
  139. BF547 Processor Support.
  140. config BF548
  141. bool "BF548"
  142. help
  143. BF548 Processor Support.
  144. config BF549
  145. bool "BF549"
  146. help
  147. BF549 Processor Support.
  148. config BF561
  149. bool "BF561"
  150. help
  151. BF561 Processor Support.
  152. endchoice
  153. config SMP
  154. depends on BF561
  155. bool "Symmetric multi-processing support"
  156. ---help---
  157. This enables support for systems with more than one CPU,
  158. like the dual core BF561. If you have a system with only one
  159. CPU, say N. If you have a system with more than one CPU, say Y.
  160. If you don't know what to do here, say N.
  161. config NR_CPUS
  162. int
  163. depends on SMP
  164. default 2 if BF561
  165. config IRQ_PER_CPU
  166. bool
  167. depends on SMP
  168. default y
  169. config TICK_SOURCE_SYSTMR0
  170. bool
  171. select BFIN_GPTIMERS
  172. depends on SMP
  173. default y
  174. config BF_REV_MIN
  175. int
  176. default 0 if (BF51x || BF52x || BF54x)
  177. default 2 if (BF537 || BF536 || BF534)
  178. default 3 if (BF561 ||BF533 || BF532 || BF531)
  179. default 4 if (BF538 || BF539)
  180. config BF_REV_MAX
  181. int
  182. default 2 if (BF51x || BF52x || BF54x)
  183. default 3 if (BF537 || BF536 || BF534)
  184. default 5 if (BF561 || BF538 || BF539)
  185. default 6 if (BF533 || BF532 || BF531)
  186. choice
  187. prompt "Silicon Rev"
  188. default BF_REV_0_1 if (BF51x || BF52x || BF54x)
  189. default BF_REV_0_2 if (BF534 || BF536 || BF537)
  190. default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF561)
  191. config BF_REV_0_0
  192. bool "0.0"
  193. depends on (BF51x || BF52x || BF54x)
  194. config BF_REV_0_1
  195. bool "0.1"
  196. depends on (BF52x || BF54x)
  197. config BF_REV_0_2
  198. bool "0.2"
  199. depends on (BF52x || BF537 || BF536 || BF534 || BF54x)
  200. config BF_REV_0_3
  201. bool "0.3"
  202. depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
  203. config BF_REV_0_4
  204. bool "0.4"
  205. depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
  206. config BF_REV_0_5
  207. bool "0.5"
  208. depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
  209. config BF_REV_0_6
  210. bool "0.6"
  211. depends on (BF533 || BF532 || BF531)
  212. config BF_REV_ANY
  213. bool "any"
  214. config BF_REV_NONE
  215. bool "none"
  216. endchoice
  217. config BF51x
  218. bool
  219. depends on (BF512 || BF514 || BF516 || BF518)
  220. default y
  221. config BF52x
  222. bool
  223. depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
  224. default y
  225. config BF53x
  226. bool
  227. depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
  228. default y
  229. config BF54x
  230. bool
  231. depends on (BF542 || BF544 || BF547 || BF548 || BF549)
  232. default y
  233. config MEM_GENERIC_BOARD
  234. bool
  235. depends on GENERIC_BOARD
  236. default y
  237. config MEM_MT48LC64M4A2FB_7E
  238. bool
  239. depends on (BFIN533_STAMP)
  240. default y
  241. config MEM_MT48LC16M16A2TG_75
  242. bool
  243. depends on (BFIN533_EZKIT || BFIN561_EZKIT \
  244. || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
  245. || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM)
  246. default y
  247. config MEM_MT48LC32M8A2_75
  248. bool
  249. depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
  250. default y
  251. config MEM_MT48LC8M32B2B5_7
  252. bool
  253. depends on (BFIN561_BLUETECHNIX_CM)
  254. default y
  255. config MEM_MT48LC32M16A2TG_75
  256. bool
  257. depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
  258. default y
  259. config MEM_MT48LC32M8A2_75
  260. bool
  261. depends on (BFIN518F_EZBRD)
  262. default y
  263. source "arch/blackfin/mach-bf518/Kconfig"
  264. source "arch/blackfin/mach-bf527/Kconfig"
  265. source "arch/blackfin/mach-bf533/Kconfig"
  266. source "arch/blackfin/mach-bf561/Kconfig"
  267. source "arch/blackfin/mach-bf537/Kconfig"
  268. source "arch/blackfin/mach-bf538/Kconfig"
  269. source "arch/blackfin/mach-bf548/Kconfig"
  270. menu "Board customizations"
  271. config CMDLINE_BOOL
  272. bool "Default bootloader kernel arguments"
  273. config CMDLINE
  274. string "Initial kernel command string"
  275. depends on CMDLINE_BOOL
  276. default "console=ttyBF0,57600"
  277. help
  278. If you don't have a boot loader capable of passing a command line string
  279. to the kernel, you may specify one here. As a minimum, you should specify
  280. the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
  281. config BOOT_LOAD
  282. hex "Kernel load address for booting"
  283. default "0x1000"
  284. range 0x1000 0x20000000
  285. help
  286. This option allows you to set the load address of the kernel.
  287. This can be useful if you are on a board which has a small amount
  288. of memory or you wish to reserve some memory at the beginning of
  289. the address space.
  290. Note that you need to keep this value above 4k (0x1000) as this
  291. memory region is used to capture NULL pointer references as well
  292. as some core kernel functions.
  293. config ROM_BASE
  294. hex "Kernel ROM Base"
  295. depends on ROMKERNEL
  296. default "0x20040000"
  297. range 0x20000000 0x20400000 if !(BF54x || BF561)
  298. range 0x20000000 0x30000000 if (BF54x || BF561)
  299. help
  300. comment "Clock/PLL Setup"
  301. config CLKIN_HZ
  302. int "Frequency of the crystal on the board in Hz"
  303. default "11059200" if BFIN533_STAMP
  304. default "27000000" if BFIN533_EZKIT
  305. default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN538_EZKIT || BFIN518F-EZBRD)
  306. default "30000000" if BFIN561_EZKIT
  307. default "24576000" if PNAV10
  308. default "10000000" if BFIN532_IP0X
  309. help
  310. The frequency of CLKIN crystal oscillator on the board in Hz.
  311. Warning: This value should match the crystal on the board. Otherwise,
  312. peripherals won't work properly.
  313. config BFIN_KERNEL_CLOCK
  314. bool "Re-program Clocks while Kernel boots?"
  315. default n
  316. help
  317. This option decides if kernel clocks are re-programed from the
  318. bootloader settings. If the clocks are not set, the SDRAM settings
  319. are also not changed, and the Bootloader does 100% of the hardware
  320. configuration.
  321. config PLL_BYPASS
  322. bool "Bypass PLL"
  323. depends on BFIN_KERNEL_CLOCK
  324. default n
  325. config CLKIN_HALF
  326. bool "Half Clock In"
  327. depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
  328. default n
  329. help
  330. If this is set the clock will be divided by 2, before it goes to the PLL.
  331. config VCO_MULT
  332. int "VCO Multiplier"
  333. depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
  334. range 1 64
  335. default "22" if BFIN533_EZKIT
  336. default "45" if BFIN533_STAMP
  337. default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
  338. default "22" if BFIN533_BLUETECHNIX_CM
  339. default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
  340. default "20" if BFIN561_EZKIT
  341. default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
  342. help
  343. This controls the frequency of the on-chip PLL. This can be between 1 and 64.
  344. PLL Frequency = (Crystal Frequency) * (this setting)
  345. choice
  346. prompt "Core Clock Divider"
  347. depends on BFIN_KERNEL_CLOCK
  348. default CCLK_DIV_1
  349. help
  350. This sets the frequency of the core. It can be 1, 2, 4 or 8
  351. Core Frequency = (PLL frequency) / (this setting)
  352. config CCLK_DIV_1
  353. bool "1"
  354. config CCLK_DIV_2
  355. bool "2"
  356. config CCLK_DIV_4
  357. bool "4"
  358. config CCLK_DIV_8
  359. bool "8"
  360. endchoice
  361. config SCLK_DIV
  362. int "System Clock Divider"
  363. depends on BFIN_KERNEL_CLOCK
  364. range 1 15
  365. default 5
  366. help
  367. This sets the frequency of the system clock (including SDRAM or DDR).
  368. This can be between 1 and 15
  369. System Clock = (PLL frequency) / (this setting)
  370. choice
  371. prompt "DDR SDRAM Chip Type"
  372. depends on BFIN_KERNEL_CLOCK
  373. depends on BF54x
  374. default MEM_MT46V32M16_5B
  375. config MEM_MT46V32M16_6T
  376. bool "MT46V32M16_6T"
  377. config MEM_MT46V32M16_5B
  378. bool "MT46V32M16_5B"
  379. endchoice
  380. choice
  381. prompt "DDR/SDRAM Timing"
  382. depends on BFIN_KERNEL_CLOCK
  383. default BFIN_KERNEL_CLOCK_MEMINIT_CALC
  384. help
  385. This option allows you to specify Blackfin SDRAM/DDR Timing parameters
  386. The calculated SDRAM timing parameters may not be 100%
  387. accurate - This option is therefore marked experimental.
  388. config BFIN_KERNEL_CLOCK_MEMINIT_CALC
  389. bool "Calculate Timings (EXPERIMENTAL)"
  390. depends on EXPERIMENTAL
  391. config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
  392. bool "Provide accurate Timings based on target SCLK"
  393. help
  394. Please consult the Blackfin Hardware Reference Manuals as well
  395. as the memory device datasheet.
  396. http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
  397. endchoice
  398. menu "Memory Init Control"
  399. depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
  400. config MEM_DDRCTL0
  401. depends on BF54x
  402. hex "DDRCTL0"
  403. default 0x0
  404. config MEM_DDRCTL1
  405. depends on BF54x
  406. hex "DDRCTL1"
  407. default 0x0
  408. config MEM_DDRCTL2
  409. depends on BF54x
  410. hex "DDRCTL2"
  411. default 0x0
  412. config MEM_EBIU_DDRQUE
  413. depends on BF54x
  414. hex "DDRQUE"
  415. default 0x0
  416. config MEM_SDRRC
  417. depends on !BF54x
  418. hex "SDRRC"
  419. default 0x0
  420. config MEM_SDGCTL
  421. depends on !BF54x
  422. hex "SDGCTL"
  423. default 0x0
  424. endmenu
  425. #
  426. # Max & Min Speeds for various Chips
  427. #
  428. config MAX_VCO_HZ
  429. int
  430. default 400000000 if BF512
  431. default 400000000 if BF514
  432. default 400000000 if BF516
  433. default 400000000 if BF518
  434. default 600000000 if BF522
  435. default 400000000 if BF523
  436. default 400000000 if BF524
  437. default 600000000 if BF525
  438. default 400000000 if BF526
  439. default 600000000 if BF527
  440. default 400000000 if BF531
  441. default 400000000 if BF532
  442. default 750000000 if BF533
  443. default 500000000 if BF534
  444. default 400000000 if BF536
  445. default 600000000 if BF537
  446. default 533333333 if BF538
  447. default 533333333 if BF539
  448. default 600000000 if BF542
  449. default 533333333 if BF544
  450. default 600000000 if BF547
  451. default 600000000 if BF548
  452. default 533333333 if BF549
  453. default 600000000 if BF561
  454. config MIN_VCO_HZ
  455. int
  456. default 50000000
  457. config MAX_SCLK_HZ
  458. int
  459. default 133333333
  460. config MIN_SCLK_HZ
  461. int
  462. default 27000000
  463. comment "Kernel Timer/Scheduler"
  464. source kernel/Kconfig.hz
  465. config GENERIC_TIME
  466. bool "Generic time"
  467. depends on !SMP
  468. default y
  469. config GENERIC_CLOCKEVENTS
  470. bool "Generic clock events"
  471. depends on GENERIC_TIME
  472. default y
  473. config CYCLES_CLOCKSOURCE
  474. bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)"
  475. depends on EXPERIMENTAL
  476. depends on GENERIC_CLOCKEVENTS
  477. depends on !BFIN_SCRATCH_REG_CYCLES
  478. default n
  479. help
  480. If you say Y here, you will enable support for using the 'cycles'
  481. registers as a clock source. Doing so means you will be unable to
  482. safely write to the 'cycles' register during runtime. You will
  483. still be able to read it (such as for performance monitoring), but
  484. writing the registers will most likely crash the kernel.
  485. source kernel/time/Kconfig
  486. comment "Misc"
  487. choice
  488. prompt "Blackfin Exception Scratch Register"
  489. default BFIN_SCRATCH_REG_RETN
  490. help
  491. Select the resource to reserve for the Exception handler:
  492. - RETN: Non-Maskable Interrupt (NMI)
  493. - RETE: Exception Return (JTAG/ICE)
  494. - CYCLES: Performance counter
  495. If you are unsure, please select "RETN".
  496. config BFIN_SCRATCH_REG_RETN
  497. bool "RETN"
  498. help
  499. Use the RETN register in the Blackfin exception handler
  500. as a stack scratch register. This means you cannot
  501. safely use NMI on the Blackfin while running Linux, but
  502. you can debug the system with a JTAG ICE and use the
  503. CYCLES performance registers.
  504. If you are unsure, please select "RETN".
  505. config BFIN_SCRATCH_REG_RETE
  506. bool "RETE"
  507. help
  508. Use the RETE register in the Blackfin exception handler
  509. as a stack scratch register. This means you cannot
  510. safely use a JTAG ICE while debugging a Blackfin board,
  511. but you can safely use the CYCLES performance registers
  512. and the NMI.
  513. If you are unsure, please select "RETN".
  514. config BFIN_SCRATCH_REG_CYCLES
  515. bool "CYCLES"
  516. help
  517. Use the CYCLES register in the Blackfin exception handler
  518. as a stack scratch register. This means you cannot
  519. safely use the CYCLES performance registers on a Blackfin
  520. board at anytime, but you can debug the system with a JTAG
  521. ICE and use the NMI.
  522. If you are unsure, please select "RETN".
  523. endchoice
  524. endmenu
  525. menu "Blackfin Kernel Optimizations"
  526. depends on !SMP
  527. comment "Memory Optimizations"
  528. config I_ENTRY_L1
  529. bool "Locate interrupt entry code in L1 Memory"
  530. default y
  531. help
  532. If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
  533. into L1 instruction memory. (less latency)
  534. config EXCPT_IRQ_SYSC_L1
  535. bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
  536. default y
  537. help
  538. If enabled, the entire ASM lowlevel exception and interrupt entry code
  539. (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
  540. (less latency)
  541. config DO_IRQ_L1
  542. bool "Locate frequently called do_irq dispatcher function in L1 Memory"
  543. default y
  544. help
  545. If enabled, the frequently called do_irq dispatcher function is linked
  546. into L1 instruction memory. (less latency)
  547. config CORE_TIMER_IRQ_L1
  548. bool "Locate frequently called timer_interrupt() function in L1 Memory"
  549. default y
  550. help
  551. If enabled, the frequently called timer_interrupt() function is linked
  552. into L1 instruction memory. (less latency)
  553. config IDLE_L1
  554. bool "Locate frequently idle function in L1 Memory"
  555. default y
  556. help
  557. If enabled, the frequently called idle function is linked
  558. into L1 instruction memory. (less latency)
  559. config SCHEDULE_L1
  560. bool "Locate kernel schedule function in L1 Memory"
  561. default y
  562. help
  563. If enabled, the frequently called kernel schedule is linked
  564. into L1 instruction memory. (less latency)
  565. config ARITHMETIC_OPS_L1
  566. bool "Locate kernel owned arithmetic functions in L1 Memory"
  567. default y
  568. help
  569. If enabled, arithmetic functions are linked
  570. into L1 instruction memory. (less latency)
  571. config ACCESS_OK_L1
  572. bool "Locate access_ok function in L1 Memory"
  573. default y
  574. help
  575. If enabled, the access_ok function is linked
  576. into L1 instruction memory. (less latency)
  577. config MEMSET_L1
  578. bool "Locate memset function in L1 Memory"
  579. default y
  580. help
  581. If enabled, the memset function is linked
  582. into L1 instruction memory. (less latency)
  583. config MEMCPY_L1
  584. bool "Locate memcpy function in L1 Memory"
  585. default y
  586. help
  587. If enabled, the memcpy function is linked
  588. into L1 instruction memory. (less latency)
  589. config SYS_BFIN_SPINLOCK_L1
  590. bool "Locate sys_bfin_spinlock function in L1 Memory"
  591. default y
  592. help
  593. If enabled, sys_bfin_spinlock function is linked
  594. into L1 instruction memory. (less latency)
  595. config IP_CHECKSUM_L1
  596. bool "Locate IP Checksum function in L1 Memory"
  597. default n
  598. help
  599. If enabled, the IP Checksum function is linked
  600. into L1 instruction memory. (less latency)
  601. config CACHELINE_ALIGNED_L1
  602. bool "Locate cacheline_aligned data to L1 Data Memory"
  603. default y if !BF54x
  604. default n if BF54x
  605. depends on !BF531
  606. help
  607. If enabled, cacheline_anligned data is linked
  608. into L1 data memory. (less latency)
  609. config SYSCALL_TAB_L1
  610. bool "Locate Syscall Table L1 Data Memory"
  611. default n
  612. depends on !BF531
  613. help
  614. If enabled, the Syscall LUT is linked
  615. into L1 data memory. (less latency)
  616. config CPLB_SWITCH_TAB_L1
  617. bool "Locate CPLB Switch Tables L1 Data Memory"
  618. default n
  619. depends on !BF531
  620. help
  621. If enabled, the CPLB Switch Tables are linked
  622. into L1 data memory. (less latency)
  623. config APP_STACK_L1
  624. bool "Support locating application stack in L1 Scratch Memory"
  625. default y
  626. help
  627. If enabled the application stack can be located in L1
  628. scratch memory (less latency).
  629. Currently only works with FLAT binaries.
  630. config EXCEPTION_L1_SCRATCH
  631. bool "Locate exception stack in L1 Scratch Memory"
  632. default n
  633. depends on !APP_STACK_L1 && !SYSCALL_TAB_L1
  634. help
  635. Whenever an exception occurs, use the L1 Scratch memory for
  636. stack storage. You cannot place the stacks of FLAT binaries
  637. in L1 when using this option.
  638. If you don't use L1 Scratch, then you should say Y here.
  639. comment "Speed Optimizations"
  640. config BFIN_INS_LOWOVERHEAD
  641. bool "ins[bwl] low overhead, higher interrupt latency"
  642. default y
  643. help
  644. Reads on the Blackfin are speculative. In Blackfin terms, this means
  645. they can be interrupted at any time (even after they have been issued
  646. on to the external bus), and re-issued after the interrupt occurs.
  647. For memory - this is not a big deal, since memory does not change if
  648. it sees a read.
  649. If a FIFO is sitting on the end of the read, it will see two reads,
  650. when the core only sees one since the FIFO receives both the read
  651. which is cancelled (and not delivered to the core) and the one which
  652. is re-issued (which is delivered to the core).
  653. To solve this, interrupts are turned off before reads occur to
  654. I/O space. This option controls which the overhead/latency of
  655. controlling interrupts during this time
  656. "n" turns interrupts off every read
  657. (higher overhead, but lower interrupt latency)
  658. "y" turns interrupts off every loop
  659. (low overhead, but longer interrupt latency)
  660. default behavior is to leave this set to on (type "Y"). If you are experiencing
  661. interrupt latency issues, it is safe and OK to turn this off.
  662. endmenu
  663. choice
  664. prompt "Kernel executes from"
  665. help
  666. Choose the memory type that the kernel will be running in.
  667. config RAMKERNEL
  668. bool "RAM"
  669. help
  670. The kernel will be resident in RAM when running.
  671. config ROMKERNEL
  672. bool "ROM"
  673. help
  674. The kernel will be resident in FLASH/ROM when running.
  675. endchoice
  676. source "mm/Kconfig"
  677. config BFIN_GPTIMERS
  678. tristate "Enable Blackfin General Purpose Timers API"
  679. default n
  680. help
  681. Enable support for the General Purpose Timers API. If you
  682. are unsure, say N.
  683. To compile this driver as a module, choose M here: the module
  684. will be called gptimers.ko.
  685. choice
  686. prompt "Uncached DMA region"
  687. default DMA_UNCACHED_1M
  688. config DMA_UNCACHED_4M
  689. bool "Enable 4M DMA region"
  690. config DMA_UNCACHED_2M
  691. bool "Enable 2M DMA region"
  692. config DMA_UNCACHED_1M
  693. bool "Enable 1M DMA region"
  694. config DMA_UNCACHED_NONE
  695. bool "Disable DMA region"
  696. endchoice
  697. comment "Cache Support"
  698. config BFIN_ICACHE
  699. bool "Enable ICACHE"
  700. config BFIN_DCACHE
  701. bool "Enable DCACHE"
  702. config BFIN_DCACHE_BANKA
  703. bool "Enable only 16k BankA DCACHE - BankB is SRAM"
  704. depends on BFIN_DCACHE && !BF531
  705. default n
  706. config BFIN_ICACHE_LOCK
  707. bool "Enable Instruction Cache Locking"
  708. choice
  709. prompt "Policy"
  710. depends on BFIN_DCACHE
  711. default BFIN_WB if !SMP
  712. default BFIN_WT if SMP
  713. config BFIN_WB
  714. bool "Write back"
  715. depends on !SMP
  716. help
  717. Write Back Policy:
  718. Cached data will be written back to SDRAM only when needed.
  719. This can give a nice increase in performance, but beware of
  720. broken drivers that do not properly invalidate/flush their
  721. cache.
  722. Write Through Policy:
  723. Cached data will always be written back to SDRAM when the
  724. cache is updated. This is a completely safe setting, but
  725. performance is worse than Write Back.
  726. If you are unsure of the options and you want to be safe,
  727. then go with Write Through.
  728. config BFIN_WT
  729. bool "Write through"
  730. help
  731. Write Back Policy:
  732. Cached data will be written back to SDRAM only when needed.
  733. This can give a nice increase in performance, but beware of
  734. broken drivers that do not properly invalidate/flush their
  735. cache.
  736. Write Through Policy:
  737. Cached data will always be written back to SDRAM when the
  738. cache is updated. This is a completely safe setting, but
  739. performance is worse than Write Back.
  740. If you are unsure of the options and you want to be safe,
  741. then go with Write Through.
  742. endchoice
  743. config BFIN_L2_CACHEABLE
  744. bool "Cache L2 SRAM"
  745. depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || (BF561 && !SMP))
  746. default n
  747. help
  748. Select to make L2 SRAM cacheable in L1 data and instruction cache.
  749. config MPU
  750. bool "Enable the memory protection unit (EXPERIMENTAL)"
  751. default n
  752. help
  753. Use the processor's MPU to protect applications from accessing
  754. memory they do not own. This comes at a performance penalty
  755. and is recommended only for debugging.
  756. comment "Asynchonous Memory Configuration"
  757. menu "EBIU_AMGCTL Global Control"
  758. config C_AMCKEN
  759. bool "Enable CLKOUT"
  760. default y
  761. config C_CDPRIO
  762. bool "DMA has priority over core for ext. accesses"
  763. default n
  764. config C_B0PEN
  765. depends on BF561
  766. bool "Bank 0 16 bit packing enable"
  767. default y
  768. config C_B1PEN
  769. depends on BF561
  770. bool "Bank 1 16 bit packing enable"
  771. default y
  772. config C_B2PEN
  773. depends on BF561
  774. bool "Bank 2 16 bit packing enable"
  775. default y
  776. config C_B3PEN
  777. depends on BF561
  778. bool "Bank 3 16 bit packing enable"
  779. default n
  780. choice
  781. prompt"Enable Asynchonous Memory Banks"
  782. default C_AMBEN_ALL
  783. config C_AMBEN
  784. bool "Disable All Banks"
  785. config C_AMBEN_B0
  786. bool "Enable Bank 0"
  787. config C_AMBEN_B0_B1
  788. bool "Enable Bank 0 & 1"
  789. config C_AMBEN_B0_B1_B2
  790. bool "Enable Bank 0 & 1 & 2"
  791. config C_AMBEN_ALL
  792. bool "Enable All Banks"
  793. endchoice
  794. endmenu
  795. menu "EBIU_AMBCTL Control"
  796. config BANK_0
  797. hex "Bank 0"
  798. default 0x7BB0
  799. config BANK_1
  800. hex "Bank 1"
  801. default 0x7BB0
  802. default 0x5558 if BF54x
  803. config BANK_2
  804. hex "Bank 2"
  805. default 0x7BB0
  806. config BANK_3
  807. hex "Bank 3"
  808. default 0x99B3
  809. endmenu
  810. config EBIU_MBSCTLVAL
  811. hex "EBIU Bank Select Control Register"
  812. depends on BF54x
  813. default 0
  814. config EBIU_MODEVAL
  815. hex "Flash Memory Mode Control Register"
  816. depends on BF54x
  817. default 1
  818. config EBIU_FCTLVAL
  819. hex "Flash Memory Bank Control Register"
  820. depends on BF54x
  821. default 6
  822. endmenu
  823. #############################################################################
  824. menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
  825. config PCI
  826. bool "PCI support"
  827. depends on BROKEN
  828. help
  829. Support for PCI bus.
  830. source "drivers/pci/Kconfig"
  831. config HOTPLUG
  832. bool "Support for hot-pluggable device"
  833. help
  834. Say Y here if you want to plug devices into your computer while
  835. the system is running, and be able to use them quickly. In many
  836. cases, the devices can likewise be unplugged at any time too.
  837. One well known example of this is PCMCIA- or PC-cards, credit-card
  838. size devices such as network cards, modems or hard drives which are
  839. plugged into slots found on all modern laptop computers. Another
  840. example, used on modern desktops as well as laptops, is USB.
  841. Enable HOTPLUG and build a modular kernel. Get agent software
  842. (from <http://linux-hotplug.sourceforge.net/>) and install it.
  843. Then your kernel will automatically call out to a user mode "policy
  844. agent" (/sbin/hotplug) to load modules and set up software needed
  845. to use devices as you hotplug them.
  846. source "drivers/pcmcia/Kconfig"
  847. source "drivers/pci/hotplug/Kconfig"
  848. endmenu
  849. menu "Executable file formats"
  850. source "fs/Kconfig.binfmt"
  851. endmenu
  852. menu "Power management options"
  853. source "kernel/power/Kconfig"
  854. config ARCH_SUSPEND_POSSIBLE
  855. def_bool y
  856. depends on !SMP
  857. choice
  858. prompt "Standby Power Saving Mode"
  859. depends on PM
  860. default PM_BFIN_SLEEP_DEEPER
  861. config PM_BFIN_SLEEP_DEEPER
  862. bool "Sleep Deeper"
  863. help
  864. Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
  865. power dissipation by disabling the clock to the processor core (CCLK).
  866. Furthermore, Standby sets the internal power supply voltage (VDDINT)
  867. to 0.85 V to provide the greatest power savings, while preserving the
  868. processor state.
  869. The PLL and system clock (SCLK) continue to operate at a very low
  870. frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
  871. the SDRAM is put into Self Refresh Mode. Typically an external event
  872. such as GPIO interrupt or RTC activity wakes up the processor.
  873. Various Peripherals such as UART, SPORT, PPI may not function as
  874. normal during Sleep Deeper, due to the reduced SCLK frequency.
  875. When in the sleep mode, system DMA access to L1 memory is not supported.
  876. If unsure, select "Sleep Deeper".
  877. config PM_BFIN_SLEEP
  878. bool "Sleep"
  879. help
  880. Sleep Mode (High Power Savings) - The sleep mode reduces power
  881. dissipation by disabling the clock to the processor core (CCLK).
  882. The PLL and system clock (SCLK), however, continue to operate in
  883. this mode. Typically an external event or RTC activity will wake
  884. up the processor. When in the sleep mode, system DMA access to L1
  885. memory is not supported.
  886. If unsure, select "Sleep Deeper".
  887. endchoice
  888. config PM_WAKEUP_BY_GPIO
  889. bool "Allow Wakeup from Standby by GPIO"
  890. config PM_WAKEUP_GPIO_NUMBER
  891. int "GPIO number"
  892. range 0 47
  893. depends on PM_WAKEUP_BY_GPIO
  894. default 2
  895. choice
  896. prompt "GPIO Polarity"
  897. depends on PM_WAKEUP_BY_GPIO
  898. default PM_WAKEUP_GPIO_POLAR_H
  899. config PM_WAKEUP_GPIO_POLAR_H
  900. bool "Active High"
  901. config PM_WAKEUP_GPIO_POLAR_L
  902. bool "Active Low"
  903. config PM_WAKEUP_GPIO_POLAR_EDGE_F
  904. bool "Falling EDGE"
  905. config PM_WAKEUP_GPIO_POLAR_EDGE_R
  906. bool "Rising EDGE"
  907. config PM_WAKEUP_GPIO_POLAR_EDGE_B
  908. bool "Both EDGE"
  909. endchoice
  910. comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
  911. depends on PM
  912. config PM_BFIN_WAKE_PH6
  913. bool "Allow Wake-Up from on-chip PHY or PH6 GP"
  914. depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
  915. default n
  916. help
  917. Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
  918. config PM_BFIN_WAKE_GP
  919. bool "Allow Wake-Up from GPIOs"
  920. depends on PM && BF54x
  921. default n
  922. help
  923. Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
  924. endmenu
  925. menu "CPU Frequency scaling"
  926. source "drivers/cpufreq/Kconfig"
  927. config BFIN_CPU_FREQ
  928. bool
  929. depends on CPU_FREQ
  930. select CPU_FREQ_TABLE
  931. default y
  932. config CPU_VOLTAGE
  933. bool "CPU Voltage scaling"
  934. depends on EXPERIMENTAL
  935. depends on CPU_FREQ
  936. default n
  937. help
  938. Say Y here if you want CPU voltage scaling according to the CPU frequency.
  939. This option violates the PLL BYPASS recommendation in the Blackfin Processor
  940. manuals. There is a theoretical risk that during VDDINT transitions
  941. the PLL may unlock.
  942. endmenu
  943. source "net/Kconfig"
  944. source "drivers/Kconfig"
  945. source "fs/Kconfig"
  946. source "arch/blackfin/Kconfig.debug"
  947. source "security/Kconfig"
  948. source "crypto/Kconfig"
  949. source "lib/Kconfig"