cdce949.c 6.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289
  1. /*
  2. * TI CDCE949 clock synthesizer driver
  3. *
  4. * Note: This implementation assumes an input of 27MHz to the CDCE.
  5. * This is by no means constrained by CDCE hardware although the datasheet
  6. * does use this as an example for all illustrations and more importantly:
  7. * that is the crystal input on boards it is currently used on.
  8. *
  9. * Copyright (C) 2009 Texas Instruments Incorporated. http://www.ti.com/
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. *
  15. */
  16. #include <linux/kernel.h>
  17. #include <linux/clk.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/i2c.h>
  20. #include <mach/clock.h>
  21. #include "clock.h"
  22. static struct i2c_client *cdce_i2c_client;
  23. /* CDCE register descriptor */
  24. struct cdce_reg {
  25. u8 addr;
  26. u8 val;
  27. };
  28. /* Per-Output (Y1, Y2 etc.) frequency descriptor */
  29. struct cdce_freq {
  30. /* Frequency in KHz */
  31. unsigned long frequency;
  32. /*
  33. * List of registers to program to obtain a particular frequency.
  34. * 0x0 in register address and value is the end of list marker.
  35. */
  36. struct cdce_reg *reglist;
  37. };
  38. #define CDCE_FREQ_TABLE_ENTRY(line, out) \
  39. { \
  40. .reglist = cdce_y ##line## _ ##out, \
  41. .frequency = out, \
  42. }
  43. /* List of CDCE outputs */
  44. struct cdce_output {
  45. /* List of frequencies on this output */
  46. struct cdce_freq *freq_table;
  47. /* Number of possible frequencies */
  48. int size;
  49. };
  50. /*
  51. * Finding out the values to program into CDCE949 registers for a particular
  52. * frequency output is not a simple calculation. Have a look at the datasheet
  53. * for the details. There is desktop software available to help users with
  54. * the calculations. Here, we just depend on the output of that software
  55. * (or hand calculations) instead trying to runtime calculate the register
  56. * values and inflicting misery on ourselves.
  57. */
  58. static struct cdce_reg cdce_y1_148500[] = {
  59. { 0x13, 0x00 },
  60. /* program PLL1_0 multiplier */
  61. { 0x18, 0xaf },
  62. { 0x19, 0x50 },
  63. { 0x1a, 0x02 },
  64. { 0x1b, 0xc9 },
  65. /* program PLL1_11 multiplier */
  66. { 0x1c, 0x00 },
  67. { 0x1d, 0x40 },
  68. { 0x1e, 0x02 },
  69. { 0x1f, 0xc9 },
  70. /* output state selection */
  71. { 0x15, 0x00 },
  72. { 0x14, 0xef },
  73. /* switch MUX to PLL1 output */
  74. { 0x14, 0x6f },
  75. { 0x16, 0x06 },
  76. /* set P2DIV divider, P3DIV and input crystal */
  77. { 0x17, 0x06 },
  78. { 0x01, 0x00 },
  79. { 0x05, 0x48 },
  80. { 0x02, 0x80 },
  81. /* enable and disable PLL */
  82. { 0x02, 0xbc },
  83. { 0x03, 0x01 },
  84. { },
  85. };
  86. static struct cdce_reg cdce_y1_74250[] = {
  87. { 0x13, 0x00 },
  88. { 0x18, 0xaf },
  89. { 0x19, 0x50 },
  90. { 0x1a, 0x02 },
  91. { 0x1b, 0xc9 },
  92. { 0x1c, 0x00 },
  93. { 0x1d, 0x40 },
  94. { 0x1e, 0x02 },
  95. { 0x1f, 0xc9 },
  96. /* output state selection */
  97. { 0x15, 0x00 },
  98. { 0x14, 0xef },
  99. /* switch MUX to PLL1 output */
  100. { 0x14, 0x6f },
  101. { 0x16, 0x06 },
  102. /* set P2DIV divider, P3DIV and input crystal */
  103. { 0x17, 0x06 },
  104. { 0x01, 0x00 },
  105. { 0x05, 0x48 },
  106. { 0x02, 0x80 },
  107. /* enable and disable PLL */
  108. { 0x02, 0xbc },
  109. { 0x03, 0x02 },
  110. { },
  111. };
  112. static struct cdce_reg cdce_y1_27000[] = {
  113. { 0x13, 0x00 },
  114. { 0x18, 0x00 },
  115. { 0x19, 0x40 },
  116. { 0x1a, 0x02 },
  117. { 0x1b, 0x08 },
  118. { 0x1c, 0x00 },
  119. { 0x1d, 0x40 },
  120. { 0x1e, 0x02 },
  121. { 0x1f, 0x08 },
  122. { 0x15, 0x02 },
  123. { 0x14, 0xed },
  124. { 0x16, 0x01 },
  125. { 0x17, 0x01 },
  126. { 0x01, 0x00 },
  127. { 0x05, 0x50 },
  128. { 0x02, 0xb4 },
  129. { 0x03, 0x01 },
  130. { },
  131. };
  132. static struct cdce_freq cdce_y1_freqs[] = {
  133. CDCE_FREQ_TABLE_ENTRY(1, 148500),
  134. CDCE_FREQ_TABLE_ENTRY(1, 74250),
  135. CDCE_FREQ_TABLE_ENTRY(1, 27000),
  136. };
  137. static struct cdce_reg cdce_y5_13500[] = {
  138. { 0x27, 0x08 },
  139. { 0x28, 0x00 },
  140. { 0x29, 0x40 },
  141. { 0x2a, 0x02 },
  142. { 0x2b, 0x08 },
  143. { 0x24, 0x6f },
  144. { },
  145. };
  146. static struct cdce_reg cdce_y5_16875[] = {
  147. { 0x27, 0x08 },
  148. { 0x28, 0x9f },
  149. { 0x29, 0xb0 },
  150. { 0x2a, 0x02 },
  151. { 0x2b, 0x89 },
  152. { 0x24, 0x6f },
  153. { },
  154. };
  155. static struct cdce_reg cdce_y5_27000[] = {
  156. { 0x27, 0x04 },
  157. { 0x28, 0x00 },
  158. { 0x29, 0x40 },
  159. { 0x2a, 0x02 },
  160. { 0x2b, 0x08 },
  161. { 0x24, 0x6f },
  162. { },
  163. };
  164. static struct cdce_reg cdce_y5_54000[] = {
  165. { 0x27, 0x04 },
  166. { 0x28, 0xff },
  167. { 0x29, 0x80 },
  168. { 0x2a, 0x02 },
  169. { 0x2b, 0x07 },
  170. { 0x24, 0x6f },
  171. { },
  172. };
  173. static struct cdce_reg cdce_y5_81000[] = {
  174. { 0x27, 0x02 },
  175. { 0x28, 0xbf },
  176. { 0x29, 0xa0 },
  177. { 0x2a, 0x03 },
  178. { 0x2b, 0x0a },
  179. { 0x24, 0x6f },
  180. { },
  181. };
  182. static struct cdce_freq cdce_y5_freqs[] = {
  183. CDCE_FREQ_TABLE_ENTRY(5, 13500),
  184. CDCE_FREQ_TABLE_ENTRY(5, 16875),
  185. CDCE_FREQ_TABLE_ENTRY(5, 27000),
  186. CDCE_FREQ_TABLE_ENTRY(5, 54000),
  187. CDCE_FREQ_TABLE_ENTRY(5, 81000),
  188. };
  189. static struct cdce_output output_list[] = {
  190. [1] = { cdce_y1_freqs, ARRAY_SIZE(cdce_y1_freqs) },
  191. [5] = { cdce_y5_freqs, ARRAY_SIZE(cdce_y5_freqs) },
  192. };
  193. int cdce_set_rate(struct clk *clk, unsigned long rate)
  194. {
  195. int i, ret = 0;
  196. struct cdce_freq *freq_table = output_list[clk->lpsc].freq_table;
  197. struct cdce_reg *regs = NULL;
  198. if (!cdce_i2c_client)
  199. return -ENODEV;
  200. if (!freq_table)
  201. return -EINVAL;
  202. for (i = 0; i < output_list[clk->lpsc].size; i++) {
  203. if (freq_table[i].frequency == rate / 1000) {
  204. regs = freq_table[i].reglist;
  205. break;
  206. }
  207. }
  208. if (!regs)
  209. return -EINVAL;
  210. for (i = 0; regs[i].addr; i++) {
  211. ret = i2c_smbus_write_byte_data(cdce_i2c_client,
  212. regs[i].addr | 0x80, regs[i].val);
  213. if (ret)
  214. return ret;
  215. }
  216. clk->rate = rate;
  217. return 0;
  218. }
  219. static int cdce_probe(struct i2c_client *client,
  220. const struct i2c_device_id *id)
  221. {
  222. cdce_i2c_client = client;
  223. return 0;
  224. }
  225. static int __devexit cdce_remove(struct i2c_client *client)
  226. {
  227. cdce_i2c_client = NULL;
  228. return 0;
  229. }
  230. static const struct i2c_device_id cdce_id[] = {
  231. {"cdce949", 0},
  232. {},
  233. };
  234. MODULE_DEVICE_TABLE(i2c, cdce_id);
  235. static struct i2c_driver cdce_driver = {
  236. .driver = {
  237. .owner = THIS_MODULE,
  238. .name = "cdce949",
  239. },
  240. .probe = cdce_probe,
  241. .remove = __devexit_p(cdce_remove),
  242. .id_table = cdce_id,
  243. };
  244. static int __init cdce_init(void)
  245. {
  246. return i2c_add_driver(&cdce_driver);
  247. }
  248. subsys_initcall(cdce_init);
  249. static void __exit cdce_exit(void)
  250. {
  251. i2c_del_driver(&cdce_driver);
  252. }
  253. module_exit(cdce_exit);
  254. MODULE_AUTHOR("Texas Instruments");
  255. MODULE_DESCRIPTION("CDCE949 clock synthesizer driver");
  256. MODULE_LICENSE("GPL v2");