apic.c 53 KB

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  1. /*
  2. * Local APIC handling, local APIC timers
  3. *
  4. * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
  5. *
  6. * Fixes
  7. * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
  8. * thanks to Eric Gilmore
  9. * and Rolf G. Tews
  10. * for testing these extensively.
  11. * Maciej W. Rozycki : Various updates and fixes.
  12. * Mikael Pettersson : Power Management for UP-APIC.
  13. * Pavel Machek and
  14. * Mikael Pettersson : PM converted to driver model.
  15. */
  16. #include <linux/init.h>
  17. #include <linux/mm.h>
  18. #include <linux/delay.h>
  19. #include <linux/bootmem.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/mc146818rtc.h>
  22. #include <linux/kernel_stat.h>
  23. #include <linux/sysdev.h>
  24. #include <linux/ioport.h>
  25. #include <linux/cpu.h>
  26. #include <linux/clockchips.h>
  27. #include <linux/acpi_pmtmr.h>
  28. #include <linux/module.h>
  29. #include <linux/dmi.h>
  30. #include <linux/dmar.h>
  31. #include <linux/ftrace.h>
  32. #include <linux/smp.h>
  33. #include <linux/nmi.h>
  34. #include <linux/timex.h>
  35. #include <asm/atomic.h>
  36. #include <asm/mtrr.h>
  37. #include <asm/mpspec.h>
  38. #include <asm/desc.h>
  39. #include <asm/arch_hooks.h>
  40. #include <asm/hpet.h>
  41. #include <asm/pgalloc.h>
  42. #include <asm/i8253.h>
  43. #include <asm/idle.h>
  44. #include <asm/proto.h>
  45. #include <asm/apic.h>
  46. #include <asm/i8259.h>
  47. #include <asm/smp.h>
  48. #include <mach_apic.h>
  49. #include <mach_apicdef.h>
  50. #include <mach_ipi.h>
  51. /*
  52. * Sanity check
  53. */
  54. #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
  55. # error SPURIOUS_APIC_VECTOR definition error
  56. #endif
  57. unsigned int num_processors;
  58. unsigned disabled_cpus __cpuinitdata;
  59. /* Processor that is doing the boot up */
  60. unsigned int boot_cpu_physical_apicid = -1U;
  61. EXPORT_SYMBOL(boot_cpu_physical_apicid);
  62. unsigned int max_physical_apicid;
  63. /* Bitmask of physically existing CPUs */
  64. physid_mask_t phys_cpu_present_map;
  65. /*
  66. * Map cpu index to physical APIC ID
  67. */
  68. DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID);
  69. DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID);
  70. EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
  71. EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
  72. #ifdef CONFIG_X86_32
  73. /*
  74. * Knob to control our willingness to enable the local APIC.
  75. *
  76. * +1=force-enable
  77. */
  78. static int force_enable_local_apic;
  79. /*
  80. * APIC command line parameters
  81. */
  82. static int __init parse_lapic(char *arg)
  83. {
  84. force_enable_local_apic = 1;
  85. return 0;
  86. }
  87. early_param("lapic", parse_lapic);
  88. /* Local APIC was disabled by the BIOS and enabled by the kernel */
  89. static int enabled_via_apicbase;
  90. #endif
  91. #ifdef CONFIG_X86_64
  92. static int apic_calibrate_pmtmr __initdata;
  93. static __init int setup_apicpmtimer(char *s)
  94. {
  95. apic_calibrate_pmtmr = 1;
  96. notsc_setup(NULL);
  97. return 0;
  98. }
  99. __setup("apicpmtimer", setup_apicpmtimer);
  100. #endif
  101. #ifdef CONFIG_X86_64
  102. #define HAVE_X2APIC
  103. #endif
  104. #ifdef HAVE_X2APIC
  105. int x2apic;
  106. /* x2apic enabled before OS handover */
  107. static int x2apic_preenabled;
  108. static int disable_x2apic;
  109. static __init int setup_nox2apic(char *str)
  110. {
  111. disable_x2apic = 1;
  112. setup_clear_cpu_cap(X86_FEATURE_X2APIC);
  113. return 0;
  114. }
  115. early_param("nox2apic", setup_nox2apic);
  116. #endif
  117. unsigned long mp_lapic_addr;
  118. int disable_apic;
  119. /* Disable local APIC timer from the kernel commandline or via dmi quirk */
  120. static int disable_apic_timer __cpuinitdata;
  121. /* Local APIC timer works in C2 */
  122. int local_apic_timer_c2_ok;
  123. EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
  124. int first_system_vector = 0xfe;
  125. /*
  126. * Debug level, exported for io_apic.c
  127. */
  128. unsigned int apic_verbosity;
  129. int pic_mode;
  130. /* Have we found an MP table */
  131. int smp_found_config;
  132. static struct resource lapic_resource = {
  133. .name = "Local APIC",
  134. .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
  135. };
  136. static unsigned int calibration_result;
  137. static int lapic_next_event(unsigned long delta,
  138. struct clock_event_device *evt);
  139. static void lapic_timer_setup(enum clock_event_mode mode,
  140. struct clock_event_device *evt);
  141. static void lapic_timer_broadcast(const struct cpumask *mask);
  142. static void apic_pm_activate(void);
  143. /*
  144. * The local apic timer can be used for any function which is CPU local.
  145. */
  146. static struct clock_event_device lapic_clockevent = {
  147. .name = "lapic",
  148. .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
  149. | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
  150. .shift = 32,
  151. .set_mode = lapic_timer_setup,
  152. .set_next_event = lapic_next_event,
  153. .broadcast = lapic_timer_broadcast,
  154. .rating = 100,
  155. .irq = -1,
  156. };
  157. static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
  158. static unsigned long apic_phys;
  159. /*
  160. * Get the LAPIC version
  161. */
  162. static inline int lapic_get_version(void)
  163. {
  164. return GET_APIC_VERSION(apic_read(APIC_LVR));
  165. }
  166. /*
  167. * Check, if the APIC is integrated or a separate chip
  168. */
  169. static inline int lapic_is_integrated(void)
  170. {
  171. #ifdef CONFIG_X86_64
  172. return 1;
  173. #else
  174. return APIC_INTEGRATED(lapic_get_version());
  175. #endif
  176. }
  177. /*
  178. * Check, whether this is a modern or a first generation APIC
  179. */
  180. static int modern_apic(void)
  181. {
  182. /* AMD systems use old APIC versions, so check the CPU */
  183. if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
  184. boot_cpu_data.x86 >= 0xf)
  185. return 1;
  186. return lapic_get_version() >= 0x14;
  187. }
  188. /*
  189. * Paravirt kernels also might be using these below ops. So we still
  190. * use generic apic_read()/apic_write(), which might be pointing to different
  191. * ops in PARAVIRT case.
  192. */
  193. void xapic_wait_icr_idle(void)
  194. {
  195. while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
  196. cpu_relax();
  197. }
  198. u32 safe_xapic_wait_icr_idle(void)
  199. {
  200. u32 send_status;
  201. int timeout;
  202. timeout = 0;
  203. do {
  204. send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
  205. if (!send_status)
  206. break;
  207. udelay(100);
  208. } while (timeout++ < 1000);
  209. return send_status;
  210. }
  211. void xapic_icr_write(u32 low, u32 id)
  212. {
  213. apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
  214. apic_write(APIC_ICR, low);
  215. }
  216. static u64 xapic_icr_read(void)
  217. {
  218. u32 icr1, icr2;
  219. icr2 = apic_read(APIC_ICR2);
  220. icr1 = apic_read(APIC_ICR);
  221. return icr1 | ((u64)icr2 << 32);
  222. }
  223. static struct apic_ops xapic_ops = {
  224. .read = native_apic_mem_read,
  225. .write = native_apic_mem_write,
  226. .icr_read = xapic_icr_read,
  227. .icr_write = xapic_icr_write,
  228. .wait_icr_idle = xapic_wait_icr_idle,
  229. .safe_wait_icr_idle = safe_xapic_wait_icr_idle,
  230. };
  231. struct apic_ops __read_mostly *apic_ops = &xapic_ops;
  232. EXPORT_SYMBOL_GPL(apic_ops);
  233. #ifdef HAVE_X2APIC
  234. static void x2apic_wait_icr_idle(void)
  235. {
  236. /* no need to wait for icr idle in x2apic */
  237. return;
  238. }
  239. static u32 safe_x2apic_wait_icr_idle(void)
  240. {
  241. /* no need to wait for icr idle in x2apic */
  242. return 0;
  243. }
  244. void x2apic_icr_write(u32 low, u32 id)
  245. {
  246. wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
  247. }
  248. static u64 x2apic_icr_read(void)
  249. {
  250. unsigned long val;
  251. rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
  252. return val;
  253. }
  254. static struct apic_ops x2apic_ops = {
  255. .read = native_apic_msr_read,
  256. .write = native_apic_msr_write,
  257. .icr_read = x2apic_icr_read,
  258. .icr_write = x2apic_icr_write,
  259. .wait_icr_idle = x2apic_wait_icr_idle,
  260. .safe_wait_icr_idle = safe_x2apic_wait_icr_idle,
  261. };
  262. #endif
  263. /**
  264. * enable_NMI_through_LVT0 - enable NMI through local vector table 0
  265. */
  266. void __cpuinit enable_NMI_through_LVT0(void)
  267. {
  268. unsigned int v;
  269. /* unmask and set to NMI */
  270. v = APIC_DM_NMI;
  271. /* Level triggered for 82489DX (32bit mode) */
  272. if (!lapic_is_integrated())
  273. v |= APIC_LVT_LEVEL_TRIGGER;
  274. apic_write(APIC_LVT0, v);
  275. }
  276. #ifdef CONFIG_X86_32
  277. /**
  278. * get_physical_broadcast - Get number of physical broadcast IDs
  279. */
  280. int get_physical_broadcast(void)
  281. {
  282. return modern_apic() ? 0xff : 0xf;
  283. }
  284. #endif
  285. /**
  286. * lapic_get_maxlvt - get the maximum number of local vector table entries
  287. */
  288. int lapic_get_maxlvt(void)
  289. {
  290. unsigned int v;
  291. v = apic_read(APIC_LVR);
  292. /*
  293. * - we always have APIC integrated on 64bit mode
  294. * - 82489DXs do not report # of LVT entries
  295. */
  296. return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
  297. }
  298. /*
  299. * Local APIC timer
  300. */
  301. /* Clock divisor */
  302. #define APIC_DIVISOR 16
  303. /*
  304. * This function sets up the local APIC timer, with a timeout of
  305. * 'clocks' APIC bus clock. During calibration we actually call
  306. * this function twice on the boot CPU, once with a bogus timeout
  307. * value, second time for real. The other (noncalibrating) CPUs
  308. * call this function only once, with the real, calibrated value.
  309. *
  310. * We do reads before writes even if unnecessary, to get around the
  311. * P5 APIC double write bug.
  312. */
  313. static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
  314. {
  315. unsigned int lvtt_value, tmp_value;
  316. lvtt_value = LOCAL_TIMER_VECTOR;
  317. if (!oneshot)
  318. lvtt_value |= APIC_LVT_TIMER_PERIODIC;
  319. if (!lapic_is_integrated())
  320. lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
  321. if (!irqen)
  322. lvtt_value |= APIC_LVT_MASKED;
  323. apic_write(APIC_LVTT, lvtt_value);
  324. /*
  325. * Divide PICLK by 16
  326. */
  327. tmp_value = apic_read(APIC_TDCR);
  328. apic_write(APIC_TDCR,
  329. (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
  330. APIC_TDR_DIV_16);
  331. if (!oneshot)
  332. apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
  333. }
  334. /*
  335. * Setup extended LVT, AMD specific (K8, family 10h)
  336. *
  337. * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
  338. * MCE interrupts are supported. Thus MCE offset must be set to 0.
  339. *
  340. * If mask=1, the LVT entry does not generate interrupts while mask=0
  341. * enables the vector. See also the BKDGs.
  342. */
  343. #define APIC_EILVT_LVTOFF_MCE 0
  344. #define APIC_EILVT_LVTOFF_IBS 1
  345. static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
  346. {
  347. unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
  348. unsigned int v = (mask << 16) | (msg_type << 8) | vector;
  349. apic_write(reg, v);
  350. }
  351. u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
  352. {
  353. setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
  354. return APIC_EILVT_LVTOFF_MCE;
  355. }
  356. u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
  357. {
  358. setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
  359. return APIC_EILVT_LVTOFF_IBS;
  360. }
  361. EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs);
  362. /*
  363. * Program the next event, relative to now
  364. */
  365. static int lapic_next_event(unsigned long delta,
  366. struct clock_event_device *evt)
  367. {
  368. apic_write(APIC_TMICT, delta);
  369. return 0;
  370. }
  371. /*
  372. * Setup the lapic timer in periodic or oneshot mode
  373. */
  374. static void lapic_timer_setup(enum clock_event_mode mode,
  375. struct clock_event_device *evt)
  376. {
  377. unsigned long flags;
  378. unsigned int v;
  379. /* Lapic used as dummy for broadcast ? */
  380. if (evt->features & CLOCK_EVT_FEAT_DUMMY)
  381. return;
  382. local_irq_save(flags);
  383. switch (mode) {
  384. case CLOCK_EVT_MODE_PERIODIC:
  385. case CLOCK_EVT_MODE_ONESHOT:
  386. __setup_APIC_LVTT(calibration_result,
  387. mode != CLOCK_EVT_MODE_PERIODIC, 1);
  388. break;
  389. case CLOCK_EVT_MODE_UNUSED:
  390. case CLOCK_EVT_MODE_SHUTDOWN:
  391. v = apic_read(APIC_LVTT);
  392. v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
  393. apic_write(APIC_LVTT, v);
  394. apic_write(APIC_TMICT, 0xffffffff);
  395. break;
  396. case CLOCK_EVT_MODE_RESUME:
  397. /* Nothing to do here */
  398. break;
  399. }
  400. local_irq_restore(flags);
  401. }
  402. /*
  403. * Local APIC timer broadcast function
  404. */
  405. static void lapic_timer_broadcast(const struct cpumask *mask)
  406. {
  407. #ifdef CONFIG_SMP
  408. send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
  409. #endif
  410. }
  411. /*
  412. * Setup the local APIC timer for this CPU. Copy the initilized values
  413. * of the boot CPU and register the clock event in the framework.
  414. */
  415. static void __cpuinit setup_APIC_timer(void)
  416. {
  417. struct clock_event_device *levt = &__get_cpu_var(lapic_events);
  418. memcpy(levt, &lapic_clockevent, sizeof(*levt));
  419. levt->cpumask = cpumask_of(smp_processor_id());
  420. clockevents_register_device(levt);
  421. }
  422. /*
  423. * In this functions we calibrate APIC bus clocks to the external timer.
  424. *
  425. * We want to do the calibration only once since we want to have local timer
  426. * irqs syncron. CPUs connected by the same APIC bus have the very same bus
  427. * frequency.
  428. *
  429. * This was previously done by reading the PIT/HPET and waiting for a wrap
  430. * around to find out, that a tick has elapsed. I have a box, where the PIT
  431. * readout is broken, so it never gets out of the wait loop again. This was
  432. * also reported by others.
  433. *
  434. * Monitoring the jiffies value is inaccurate and the clockevents
  435. * infrastructure allows us to do a simple substitution of the interrupt
  436. * handler.
  437. *
  438. * The calibration routine also uses the pm_timer when possible, as the PIT
  439. * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
  440. * back to normal later in the boot process).
  441. */
  442. #define LAPIC_CAL_LOOPS (HZ/10)
  443. static __initdata int lapic_cal_loops = -1;
  444. static __initdata long lapic_cal_t1, lapic_cal_t2;
  445. static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
  446. static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
  447. static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
  448. /*
  449. * Temporary interrupt handler.
  450. */
  451. static void __init lapic_cal_handler(struct clock_event_device *dev)
  452. {
  453. unsigned long long tsc = 0;
  454. long tapic = apic_read(APIC_TMCCT);
  455. unsigned long pm = acpi_pm_read_early();
  456. if (cpu_has_tsc)
  457. rdtscll(tsc);
  458. switch (lapic_cal_loops++) {
  459. case 0:
  460. lapic_cal_t1 = tapic;
  461. lapic_cal_tsc1 = tsc;
  462. lapic_cal_pm1 = pm;
  463. lapic_cal_j1 = jiffies;
  464. break;
  465. case LAPIC_CAL_LOOPS:
  466. lapic_cal_t2 = tapic;
  467. lapic_cal_tsc2 = tsc;
  468. if (pm < lapic_cal_pm1)
  469. pm += ACPI_PM_OVRRUN;
  470. lapic_cal_pm2 = pm;
  471. lapic_cal_j2 = jiffies;
  472. break;
  473. }
  474. }
  475. static int __init calibrate_by_pmtimer(long deltapm, long *delta)
  476. {
  477. const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
  478. const long pm_thresh = pm_100ms / 100;
  479. unsigned long mult;
  480. u64 res;
  481. #ifndef CONFIG_X86_PM_TIMER
  482. return -1;
  483. #endif
  484. apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm);
  485. /* Check, if the PM timer is available */
  486. if (!deltapm)
  487. return -1;
  488. mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
  489. if (deltapm > (pm_100ms - pm_thresh) &&
  490. deltapm < (pm_100ms + pm_thresh)) {
  491. apic_printk(APIC_VERBOSE, "... PM timer result ok\n");
  492. } else {
  493. res = (((u64)deltapm) * mult) >> 22;
  494. do_div(res, 1000000);
  495. pr_warning("APIC calibration not consistent "
  496. "with PM Timer: %ldms instead of 100ms\n",
  497. (long)res);
  498. /* Correct the lapic counter value */
  499. res = (((u64)(*delta)) * pm_100ms);
  500. do_div(res, deltapm);
  501. pr_info("APIC delta adjusted to PM-Timer: "
  502. "%lu (%ld)\n", (unsigned long)res, *delta);
  503. *delta = (long)res;
  504. }
  505. return 0;
  506. }
  507. static int __init calibrate_APIC_clock(void)
  508. {
  509. struct clock_event_device *levt = &__get_cpu_var(lapic_events);
  510. void (*real_handler)(struct clock_event_device *dev);
  511. unsigned long deltaj;
  512. long delta;
  513. int pm_referenced = 0;
  514. local_irq_disable();
  515. /* Replace the global interrupt handler */
  516. real_handler = global_clock_event->event_handler;
  517. global_clock_event->event_handler = lapic_cal_handler;
  518. /*
  519. * Setup the APIC counter to maximum. There is no way the lapic
  520. * can underflow in the 100ms detection time frame
  521. */
  522. __setup_APIC_LVTT(0xffffffff, 0, 0);
  523. /* Let the interrupts run */
  524. local_irq_enable();
  525. while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
  526. cpu_relax();
  527. local_irq_disable();
  528. /* Restore the real event handler */
  529. global_clock_event->event_handler = real_handler;
  530. /* Build delta t1-t2 as apic timer counts down */
  531. delta = lapic_cal_t1 - lapic_cal_t2;
  532. apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
  533. /* we trust the PM based calibration if possible */
  534. pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
  535. &delta);
  536. /* Calculate the scaled math multiplication factor */
  537. lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
  538. lapic_clockevent.shift);
  539. lapic_clockevent.max_delta_ns =
  540. clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
  541. lapic_clockevent.min_delta_ns =
  542. clockevent_delta2ns(0xF, &lapic_clockevent);
  543. calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
  544. apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
  545. apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult);
  546. apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
  547. calibration_result);
  548. if (cpu_has_tsc) {
  549. delta = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
  550. apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
  551. "%ld.%04ld MHz.\n",
  552. (delta / LAPIC_CAL_LOOPS) / (1000000 / HZ),
  553. (delta / LAPIC_CAL_LOOPS) % (1000000 / HZ));
  554. }
  555. apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
  556. "%u.%04u MHz.\n",
  557. calibration_result / (1000000 / HZ),
  558. calibration_result % (1000000 / HZ));
  559. /*
  560. * Do a sanity check on the APIC calibration result
  561. */
  562. if (calibration_result < (1000000 / HZ)) {
  563. local_irq_enable();
  564. pr_warning("APIC frequency too slow, disabling apic timer\n");
  565. return -1;
  566. }
  567. levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
  568. /*
  569. * PM timer calibration failed or not turned on
  570. * so lets try APIC timer based calibration
  571. */
  572. if (!pm_referenced) {
  573. apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
  574. /*
  575. * Setup the apic timer manually
  576. */
  577. levt->event_handler = lapic_cal_handler;
  578. lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
  579. lapic_cal_loops = -1;
  580. /* Let the interrupts run */
  581. local_irq_enable();
  582. while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
  583. cpu_relax();
  584. /* Stop the lapic timer */
  585. lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
  586. /* Jiffies delta */
  587. deltaj = lapic_cal_j2 - lapic_cal_j1;
  588. apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
  589. /* Check, if the jiffies result is consistent */
  590. if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
  591. apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
  592. else
  593. levt->features |= CLOCK_EVT_FEAT_DUMMY;
  594. } else
  595. local_irq_enable();
  596. if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
  597. pr_warning("APIC timer disabled due to verification failure\n");
  598. return -1;
  599. }
  600. return 0;
  601. }
  602. /*
  603. * Setup the boot APIC
  604. *
  605. * Calibrate and verify the result.
  606. */
  607. void __init setup_boot_APIC_clock(void)
  608. {
  609. /*
  610. * The local apic timer can be disabled via the kernel
  611. * commandline or from the CPU detection code. Register the lapic
  612. * timer as a dummy clock event source on SMP systems, so the
  613. * broadcast mechanism is used. On UP systems simply ignore it.
  614. */
  615. if (disable_apic_timer) {
  616. pr_info("Disabling APIC timer\n");
  617. /* No broadcast on UP ! */
  618. if (num_possible_cpus() > 1) {
  619. lapic_clockevent.mult = 1;
  620. setup_APIC_timer();
  621. }
  622. return;
  623. }
  624. apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
  625. "calibrating APIC timer ...\n");
  626. if (calibrate_APIC_clock()) {
  627. /* No broadcast on UP ! */
  628. if (num_possible_cpus() > 1)
  629. setup_APIC_timer();
  630. return;
  631. }
  632. /*
  633. * If nmi_watchdog is set to IO_APIC, we need the
  634. * PIT/HPET going. Otherwise register lapic as a dummy
  635. * device.
  636. */
  637. if (nmi_watchdog != NMI_IO_APIC)
  638. lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
  639. else
  640. pr_warning("APIC timer registered as dummy,"
  641. " due to nmi_watchdog=%d!\n", nmi_watchdog);
  642. /* Setup the lapic or request the broadcast */
  643. setup_APIC_timer();
  644. }
  645. void __cpuinit setup_secondary_APIC_clock(void)
  646. {
  647. setup_APIC_timer();
  648. }
  649. /*
  650. * The guts of the apic timer interrupt
  651. */
  652. static void local_apic_timer_interrupt(void)
  653. {
  654. int cpu = smp_processor_id();
  655. struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
  656. /*
  657. * Normally we should not be here till LAPIC has been initialized but
  658. * in some cases like kdump, its possible that there is a pending LAPIC
  659. * timer interrupt from previous kernel's context and is delivered in
  660. * new kernel the moment interrupts are enabled.
  661. *
  662. * Interrupts are enabled early and LAPIC is setup much later, hence
  663. * its possible that when we get here evt->event_handler is NULL.
  664. * Check for event_handler being NULL and discard the interrupt as
  665. * spurious.
  666. */
  667. if (!evt->event_handler) {
  668. pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu);
  669. /* Switch it off */
  670. lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
  671. return;
  672. }
  673. /*
  674. * the NMI deadlock-detector uses this.
  675. */
  676. inc_irq_stat(apic_timer_irqs);
  677. evt->event_handler(evt);
  678. }
  679. /*
  680. * Local APIC timer interrupt. This is the most natural way for doing
  681. * local interrupts, but local timer interrupts can be emulated by
  682. * broadcast interrupts too. [in case the hw doesn't support APIC timers]
  683. *
  684. * [ if a single-CPU system runs an SMP kernel then we call the local
  685. * interrupt as well. Thus we cannot inline the local irq ... ]
  686. */
  687. void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
  688. {
  689. struct pt_regs *old_regs = set_irq_regs(regs);
  690. /*
  691. * NOTE! We'd better ACK the irq immediately,
  692. * because timer handling can be slow.
  693. */
  694. ack_APIC_irq();
  695. /*
  696. * update_process_times() expects us to have done irq_enter().
  697. * Besides, if we don't timer interrupts ignore the global
  698. * interrupt lock, which is the WrongThing (tm) to do.
  699. */
  700. exit_idle();
  701. irq_enter();
  702. local_apic_timer_interrupt();
  703. irq_exit();
  704. set_irq_regs(old_regs);
  705. }
  706. int setup_profiling_timer(unsigned int multiplier)
  707. {
  708. return -EINVAL;
  709. }
  710. /*
  711. * Local APIC start and shutdown
  712. */
  713. /**
  714. * clear_local_APIC - shutdown the local APIC
  715. *
  716. * This is called, when a CPU is disabled and before rebooting, so the state of
  717. * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
  718. * leftovers during boot.
  719. */
  720. void clear_local_APIC(void)
  721. {
  722. int maxlvt;
  723. u32 v;
  724. /* APIC hasn't been mapped yet */
  725. if (!apic_phys)
  726. return;
  727. maxlvt = lapic_get_maxlvt();
  728. /*
  729. * Masking an LVT entry can trigger a local APIC error
  730. * if the vector is zero. Mask LVTERR first to prevent this.
  731. */
  732. if (maxlvt >= 3) {
  733. v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
  734. apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
  735. }
  736. /*
  737. * Careful: we have to set masks only first to deassert
  738. * any level-triggered sources.
  739. */
  740. v = apic_read(APIC_LVTT);
  741. apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
  742. v = apic_read(APIC_LVT0);
  743. apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
  744. v = apic_read(APIC_LVT1);
  745. apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
  746. if (maxlvt >= 4) {
  747. v = apic_read(APIC_LVTPC);
  748. apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
  749. }
  750. /* lets not touch this if we didn't frob it */
  751. #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
  752. if (maxlvt >= 5) {
  753. v = apic_read(APIC_LVTTHMR);
  754. apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
  755. }
  756. #endif
  757. /*
  758. * Clean APIC state for other OSs:
  759. */
  760. apic_write(APIC_LVTT, APIC_LVT_MASKED);
  761. apic_write(APIC_LVT0, APIC_LVT_MASKED);
  762. apic_write(APIC_LVT1, APIC_LVT_MASKED);
  763. if (maxlvt >= 3)
  764. apic_write(APIC_LVTERR, APIC_LVT_MASKED);
  765. if (maxlvt >= 4)
  766. apic_write(APIC_LVTPC, APIC_LVT_MASKED);
  767. /* Integrated APIC (!82489DX) ? */
  768. if (lapic_is_integrated()) {
  769. if (maxlvt > 3)
  770. /* Clear ESR due to Pentium errata 3AP and 11AP */
  771. apic_write(APIC_ESR, 0);
  772. apic_read(APIC_ESR);
  773. }
  774. }
  775. /**
  776. * disable_local_APIC - clear and disable the local APIC
  777. */
  778. void disable_local_APIC(void)
  779. {
  780. unsigned int value;
  781. /* APIC hasn't been mapped yet */
  782. if (!apic_phys)
  783. return;
  784. clear_local_APIC();
  785. /*
  786. * Disable APIC (implies clearing of registers
  787. * for 82489DX!).
  788. */
  789. value = apic_read(APIC_SPIV);
  790. value &= ~APIC_SPIV_APIC_ENABLED;
  791. apic_write(APIC_SPIV, value);
  792. #ifdef CONFIG_X86_32
  793. /*
  794. * When LAPIC was disabled by the BIOS and enabled by the kernel,
  795. * restore the disabled state.
  796. */
  797. if (enabled_via_apicbase) {
  798. unsigned int l, h;
  799. rdmsr(MSR_IA32_APICBASE, l, h);
  800. l &= ~MSR_IA32_APICBASE_ENABLE;
  801. wrmsr(MSR_IA32_APICBASE, l, h);
  802. }
  803. #endif
  804. }
  805. /*
  806. * If Linux enabled the LAPIC against the BIOS default disable it down before
  807. * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
  808. * not power-off. Additionally clear all LVT entries before disable_local_APIC
  809. * for the case where Linux didn't enable the LAPIC.
  810. */
  811. void lapic_shutdown(void)
  812. {
  813. unsigned long flags;
  814. if (!cpu_has_apic)
  815. return;
  816. local_irq_save(flags);
  817. #ifdef CONFIG_X86_32
  818. if (!enabled_via_apicbase)
  819. clear_local_APIC();
  820. else
  821. #endif
  822. disable_local_APIC();
  823. local_irq_restore(flags);
  824. }
  825. /*
  826. * This is to verify that we're looking at a real local APIC.
  827. * Check these against your board if the CPUs aren't getting
  828. * started for no apparent reason.
  829. */
  830. int __init verify_local_APIC(void)
  831. {
  832. unsigned int reg0, reg1;
  833. /*
  834. * The version register is read-only in a real APIC.
  835. */
  836. reg0 = apic_read(APIC_LVR);
  837. apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
  838. apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
  839. reg1 = apic_read(APIC_LVR);
  840. apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
  841. /*
  842. * The two version reads above should print the same
  843. * numbers. If the second one is different, then we
  844. * poke at a non-APIC.
  845. */
  846. if (reg1 != reg0)
  847. return 0;
  848. /*
  849. * Check if the version looks reasonably.
  850. */
  851. reg1 = GET_APIC_VERSION(reg0);
  852. if (reg1 == 0x00 || reg1 == 0xff)
  853. return 0;
  854. reg1 = lapic_get_maxlvt();
  855. if (reg1 < 0x02 || reg1 == 0xff)
  856. return 0;
  857. /*
  858. * The ID register is read/write in a real APIC.
  859. */
  860. reg0 = apic_read(APIC_ID);
  861. apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
  862. apic_write(APIC_ID, reg0 ^ apic->apic_id_mask);
  863. reg1 = apic_read(APIC_ID);
  864. apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
  865. apic_write(APIC_ID, reg0);
  866. if (reg1 != (reg0 ^ apic->apic_id_mask))
  867. return 0;
  868. /*
  869. * The next two are just to see if we have sane values.
  870. * They're only really relevant if we're in Virtual Wire
  871. * compatibility mode, but most boxes are anymore.
  872. */
  873. reg0 = apic_read(APIC_LVT0);
  874. apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
  875. reg1 = apic_read(APIC_LVT1);
  876. apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
  877. return 1;
  878. }
  879. /**
  880. * sync_Arb_IDs - synchronize APIC bus arbitration IDs
  881. */
  882. void __init sync_Arb_IDs(void)
  883. {
  884. /*
  885. * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
  886. * needed on AMD.
  887. */
  888. if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
  889. return;
  890. /*
  891. * Wait for idle.
  892. */
  893. apic_wait_icr_idle();
  894. apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
  895. apic_write(APIC_ICR, APIC_DEST_ALLINC |
  896. APIC_INT_LEVELTRIG | APIC_DM_INIT);
  897. }
  898. /*
  899. * An initial setup of the virtual wire mode.
  900. */
  901. void __init init_bsp_APIC(void)
  902. {
  903. unsigned int value;
  904. /*
  905. * Don't do the setup now if we have a SMP BIOS as the
  906. * through-I/O-APIC virtual wire mode might be active.
  907. */
  908. if (smp_found_config || !cpu_has_apic)
  909. return;
  910. /*
  911. * Do not trust the local APIC being empty at bootup.
  912. */
  913. clear_local_APIC();
  914. /*
  915. * Enable APIC.
  916. */
  917. value = apic_read(APIC_SPIV);
  918. value &= ~APIC_VECTOR_MASK;
  919. value |= APIC_SPIV_APIC_ENABLED;
  920. #ifdef CONFIG_X86_32
  921. /* This bit is reserved on P4/Xeon and should be cleared */
  922. if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
  923. (boot_cpu_data.x86 == 15))
  924. value &= ~APIC_SPIV_FOCUS_DISABLED;
  925. else
  926. #endif
  927. value |= APIC_SPIV_FOCUS_DISABLED;
  928. value |= SPURIOUS_APIC_VECTOR;
  929. apic_write(APIC_SPIV, value);
  930. /*
  931. * Set up the virtual wire mode.
  932. */
  933. apic_write(APIC_LVT0, APIC_DM_EXTINT);
  934. value = APIC_DM_NMI;
  935. if (!lapic_is_integrated()) /* 82489DX */
  936. value |= APIC_LVT_LEVEL_TRIGGER;
  937. apic_write(APIC_LVT1, value);
  938. }
  939. static void __cpuinit lapic_setup_esr(void)
  940. {
  941. unsigned int oldvalue, value, maxlvt;
  942. if (!lapic_is_integrated()) {
  943. pr_info("No ESR for 82489DX.\n");
  944. return;
  945. }
  946. if (apic->disable_esr) {
  947. /*
  948. * Something untraceable is creating bad interrupts on
  949. * secondary quads ... for the moment, just leave the
  950. * ESR disabled - we can't do anything useful with the
  951. * errors anyway - mbligh
  952. */
  953. pr_info("Leaving ESR disabled.\n");
  954. return;
  955. }
  956. maxlvt = lapic_get_maxlvt();
  957. if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
  958. apic_write(APIC_ESR, 0);
  959. oldvalue = apic_read(APIC_ESR);
  960. /* enables sending errors */
  961. value = ERROR_APIC_VECTOR;
  962. apic_write(APIC_LVTERR, value);
  963. /*
  964. * spec says clear errors after enabling vector.
  965. */
  966. if (maxlvt > 3)
  967. apic_write(APIC_ESR, 0);
  968. value = apic_read(APIC_ESR);
  969. if (value != oldvalue)
  970. apic_printk(APIC_VERBOSE, "ESR value before enabling "
  971. "vector: 0x%08x after: 0x%08x\n",
  972. oldvalue, value);
  973. }
  974. /**
  975. * setup_local_APIC - setup the local APIC
  976. */
  977. void __cpuinit setup_local_APIC(void)
  978. {
  979. unsigned int value;
  980. int i, j;
  981. if (disable_apic) {
  982. #ifdef CONFIG_X86_IO_APIC
  983. disable_ioapic_setup();
  984. #endif
  985. return;
  986. }
  987. #ifdef CONFIG_X86_32
  988. /* Pound the ESR really hard over the head with a big hammer - mbligh */
  989. if (lapic_is_integrated() && apic->disable_esr) {
  990. apic_write(APIC_ESR, 0);
  991. apic_write(APIC_ESR, 0);
  992. apic_write(APIC_ESR, 0);
  993. apic_write(APIC_ESR, 0);
  994. }
  995. #endif
  996. preempt_disable();
  997. /*
  998. * Double-check whether this APIC is really registered.
  999. * This is meaningless in clustered apic mode, so we skip it.
  1000. */
  1001. if (!apic->apic_id_registered())
  1002. BUG();
  1003. /*
  1004. * Intel recommends to set DFR, LDR and TPR before enabling
  1005. * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
  1006. * document number 292116). So here it goes...
  1007. */
  1008. apic->init_apic_ldr();
  1009. /*
  1010. * Set Task Priority to 'accept all'. We never change this
  1011. * later on.
  1012. */
  1013. value = apic_read(APIC_TASKPRI);
  1014. value &= ~APIC_TPRI_MASK;
  1015. apic_write(APIC_TASKPRI, value);
  1016. /*
  1017. * After a crash, we no longer service the interrupts and a pending
  1018. * interrupt from previous kernel might still have ISR bit set.
  1019. *
  1020. * Most probably by now CPU has serviced that pending interrupt and
  1021. * it might not have done the ack_APIC_irq() because it thought,
  1022. * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
  1023. * does not clear the ISR bit and cpu thinks it has already serivced
  1024. * the interrupt. Hence a vector might get locked. It was noticed
  1025. * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
  1026. */
  1027. for (i = APIC_ISR_NR - 1; i >= 0; i--) {
  1028. value = apic_read(APIC_ISR + i*0x10);
  1029. for (j = 31; j >= 0; j--) {
  1030. if (value & (1<<j))
  1031. ack_APIC_irq();
  1032. }
  1033. }
  1034. /*
  1035. * Now that we are all set up, enable the APIC
  1036. */
  1037. value = apic_read(APIC_SPIV);
  1038. value &= ~APIC_VECTOR_MASK;
  1039. /*
  1040. * Enable APIC
  1041. */
  1042. value |= APIC_SPIV_APIC_ENABLED;
  1043. #ifdef CONFIG_X86_32
  1044. /*
  1045. * Some unknown Intel IO/APIC (or APIC) errata is biting us with
  1046. * certain networking cards. If high frequency interrupts are
  1047. * happening on a particular IOAPIC pin, plus the IOAPIC routing
  1048. * entry is masked/unmasked at a high rate as well then sooner or
  1049. * later IOAPIC line gets 'stuck', no more interrupts are received
  1050. * from the device. If focus CPU is disabled then the hang goes
  1051. * away, oh well :-(
  1052. *
  1053. * [ This bug can be reproduced easily with a level-triggered
  1054. * PCI Ne2000 networking cards and PII/PIII processors, dual
  1055. * BX chipset. ]
  1056. */
  1057. /*
  1058. * Actually disabling the focus CPU check just makes the hang less
  1059. * frequent as it makes the interrupt distributon model be more
  1060. * like LRU than MRU (the short-term load is more even across CPUs).
  1061. * See also the comment in end_level_ioapic_irq(). --macro
  1062. */
  1063. /*
  1064. * - enable focus processor (bit==0)
  1065. * - 64bit mode always use processor focus
  1066. * so no need to set it
  1067. */
  1068. value &= ~APIC_SPIV_FOCUS_DISABLED;
  1069. #endif
  1070. /*
  1071. * Set spurious IRQ vector
  1072. */
  1073. value |= SPURIOUS_APIC_VECTOR;
  1074. apic_write(APIC_SPIV, value);
  1075. /*
  1076. * Set up LVT0, LVT1:
  1077. *
  1078. * set up through-local-APIC on the BP's LINT0. This is not
  1079. * strictly necessary in pure symmetric-IO mode, but sometimes
  1080. * we delegate interrupts to the 8259A.
  1081. */
  1082. /*
  1083. * TODO: set up through-local-APIC from through-I/O-APIC? --macro
  1084. */
  1085. value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
  1086. if (!smp_processor_id() && (pic_mode || !value)) {
  1087. value = APIC_DM_EXTINT;
  1088. apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
  1089. smp_processor_id());
  1090. } else {
  1091. value = APIC_DM_EXTINT | APIC_LVT_MASKED;
  1092. apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
  1093. smp_processor_id());
  1094. }
  1095. apic_write(APIC_LVT0, value);
  1096. /*
  1097. * only the BP should see the LINT1 NMI signal, obviously.
  1098. */
  1099. if (!smp_processor_id())
  1100. value = APIC_DM_NMI;
  1101. else
  1102. value = APIC_DM_NMI | APIC_LVT_MASKED;
  1103. if (!lapic_is_integrated()) /* 82489DX */
  1104. value |= APIC_LVT_LEVEL_TRIGGER;
  1105. apic_write(APIC_LVT1, value);
  1106. preempt_enable();
  1107. }
  1108. void __cpuinit end_local_APIC_setup(void)
  1109. {
  1110. lapic_setup_esr();
  1111. #ifdef CONFIG_X86_32
  1112. {
  1113. unsigned int value;
  1114. /* Disable the local apic timer */
  1115. value = apic_read(APIC_LVTT);
  1116. value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
  1117. apic_write(APIC_LVTT, value);
  1118. }
  1119. #endif
  1120. setup_apic_nmi_watchdog(NULL);
  1121. apic_pm_activate();
  1122. }
  1123. #ifdef HAVE_X2APIC
  1124. void check_x2apic(void)
  1125. {
  1126. int msr, msr2;
  1127. rdmsr(MSR_IA32_APICBASE, msr, msr2);
  1128. if (msr & X2APIC_ENABLE) {
  1129. pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
  1130. x2apic_preenabled = x2apic = 1;
  1131. apic_ops = &x2apic_ops;
  1132. }
  1133. }
  1134. void enable_x2apic(void)
  1135. {
  1136. int msr, msr2;
  1137. rdmsr(MSR_IA32_APICBASE, msr, msr2);
  1138. if (!(msr & X2APIC_ENABLE)) {
  1139. pr_info("Enabling x2apic\n");
  1140. wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
  1141. }
  1142. }
  1143. void __init enable_IR_x2apic(void)
  1144. {
  1145. #ifdef CONFIG_INTR_REMAP
  1146. int ret;
  1147. unsigned long flags;
  1148. if (!cpu_has_x2apic)
  1149. return;
  1150. if (!x2apic_preenabled && disable_x2apic) {
  1151. pr_info("Skipped enabling x2apic and Interrupt-remapping "
  1152. "because of nox2apic\n");
  1153. return;
  1154. }
  1155. if (x2apic_preenabled && disable_x2apic)
  1156. panic("Bios already enabled x2apic, can't enforce nox2apic");
  1157. if (!x2apic_preenabled && skip_ioapic_setup) {
  1158. pr_info("Skipped enabling x2apic and Interrupt-remapping "
  1159. "because of skipping io-apic setup\n");
  1160. return;
  1161. }
  1162. ret = dmar_table_init();
  1163. if (ret) {
  1164. pr_info("dmar_table_init() failed with %d:\n", ret);
  1165. if (x2apic_preenabled)
  1166. panic("x2apic enabled by bios. But IR enabling failed");
  1167. else
  1168. pr_info("Not enabling x2apic,Intr-remapping\n");
  1169. return;
  1170. }
  1171. local_irq_save(flags);
  1172. mask_8259A();
  1173. ret = save_mask_IO_APIC_setup();
  1174. if (ret) {
  1175. pr_info("Saving IO-APIC state failed: %d\n", ret);
  1176. goto end;
  1177. }
  1178. ret = enable_intr_remapping(1);
  1179. if (ret && x2apic_preenabled) {
  1180. local_irq_restore(flags);
  1181. panic("x2apic enabled by bios. But IR enabling failed");
  1182. }
  1183. if (ret)
  1184. goto end_restore;
  1185. if (!x2apic) {
  1186. x2apic = 1;
  1187. apic_ops = &x2apic_ops;
  1188. enable_x2apic();
  1189. }
  1190. end_restore:
  1191. if (ret)
  1192. /*
  1193. * IR enabling failed
  1194. */
  1195. restore_IO_APIC_setup();
  1196. else
  1197. reinit_intr_remapped_IO_APIC(x2apic_preenabled);
  1198. end:
  1199. unmask_8259A();
  1200. local_irq_restore(flags);
  1201. if (!ret) {
  1202. if (!x2apic_preenabled)
  1203. pr_info("Enabled x2apic and interrupt-remapping\n");
  1204. else
  1205. pr_info("Enabled Interrupt-remapping\n");
  1206. } else
  1207. pr_err("Failed to enable Interrupt-remapping and x2apic\n");
  1208. #else
  1209. if (!cpu_has_x2apic)
  1210. return;
  1211. if (x2apic_preenabled)
  1212. panic("x2apic enabled prior OS handover,"
  1213. " enable CONFIG_INTR_REMAP");
  1214. pr_info("Enable CONFIG_INTR_REMAP for enabling intr-remapping "
  1215. " and x2apic\n");
  1216. #endif
  1217. return;
  1218. }
  1219. #endif /* HAVE_X2APIC */
  1220. #ifdef CONFIG_X86_64
  1221. /*
  1222. * Detect and enable local APICs on non-SMP boards.
  1223. * Original code written by Keir Fraser.
  1224. * On AMD64 we trust the BIOS - if it says no APIC it is likely
  1225. * not correctly set up (usually the APIC timer won't work etc.)
  1226. */
  1227. static int __init detect_init_APIC(void)
  1228. {
  1229. if (!cpu_has_apic) {
  1230. pr_info("No local APIC present\n");
  1231. return -1;
  1232. }
  1233. mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
  1234. boot_cpu_physical_apicid = 0;
  1235. return 0;
  1236. }
  1237. #else
  1238. /*
  1239. * Detect and initialize APIC
  1240. */
  1241. static int __init detect_init_APIC(void)
  1242. {
  1243. u32 h, l, features;
  1244. /* Disabled by kernel option? */
  1245. if (disable_apic)
  1246. return -1;
  1247. switch (boot_cpu_data.x86_vendor) {
  1248. case X86_VENDOR_AMD:
  1249. if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
  1250. (boot_cpu_data.x86 == 15))
  1251. break;
  1252. goto no_apic;
  1253. case X86_VENDOR_INTEL:
  1254. if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
  1255. (boot_cpu_data.x86 == 5 && cpu_has_apic))
  1256. break;
  1257. goto no_apic;
  1258. default:
  1259. goto no_apic;
  1260. }
  1261. if (!cpu_has_apic) {
  1262. /*
  1263. * Over-ride BIOS and try to enable the local APIC only if
  1264. * "lapic" specified.
  1265. */
  1266. if (!force_enable_local_apic) {
  1267. pr_info("Local APIC disabled by BIOS -- "
  1268. "you can enable it with \"lapic\"\n");
  1269. return -1;
  1270. }
  1271. /*
  1272. * Some BIOSes disable the local APIC in the APIC_BASE
  1273. * MSR. This can only be done in software for Intel P6 or later
  1274. * and AMD K7 (Model > 1) or later.
  1275. */
  1276. rdmsr(MSR_IA32_APICBASE, l, h);
  1277. if (!(l & MSR_IA32_APICBASE_ENABLE)) {
  1278. pr_info("Local APIC disabled by BIOS -- reenabling.\n");
  1279. l &= ~MSR_IA32_APICBASE_BASE;
  1280. l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
  1281. wrmsr(MSR_IA32_APICBASE, l, h);
  1282. enabled_via_apicbase = 1;
  1283. }
  1284. }
  1285. /*
  1286. * The APIC feature bit should now be enabled
  1287. * in `cpuid'
  1288. */
  1289. features = cpuid_edx(1);
  1290. if (!(features & (1 << X86_FEATURE_APIC))) {
  1291. pr_warning("Could not enable APIC!\n");
  1292. return -1;
  1293. }
  1294. set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
  1295. mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
  1296. /* The BIOS may have set up the APIC at some other address */
  1297. rdmsr(MSR_IA32_APICBASE, l, h);
  1298. if (l & MSR_IA32_APICBASE_ENABLE)
  1299. mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
  1300. pr_info("Found and enabled local APIC!\n");
  1301. apic_pm_activate();
  1302. return 0;
  1303. no_apic:
  1304. pr_info("No local APIC present or hardware disabled\n");
  1305. return -1;
  1306. }
  1307. #endif
  1308. #ifdef CONFIG_X86_64
  1309. void __init early_init_lapic_mapping(void)
  1310. {
  1311. unsigned long phys_addr;
  1312. /*
  1313. * If no local APIC can be found then go out
  1314. * : it means there is no mpatable and MADT
  1315. */
  1316. if (!smp_found_config)
  1317. return;
  1318. phys_addr = mp_lapic_addr;
  1319. set_fixmap_nocache(FIX_APIC_BASE, phys_addr);
  1320. apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
  1321. APIC_BASE, phys_addr);
  1322. /*
  1323. * Fetch the APIC ID of the BSP in case we have a
  1324. * default configuration (or the MP table is broken).
  1325. */
  1326. boot_cpu_physical_apicid = read_apic_id();
  1327. }
  1328. #endif
  1329. /**
  1330. * init_apic_mappings - initialize APIC mappings
  1331. */
  1332. void __init init_apic_mappings(void)
  1333. {
  1334. #ifdef HAVE_X2APIC
  1335. if (x2apic) {
  1336. boot_cpu_physical_apicid = read_apic_id();
  1337. return;
  1338. }
  1339. #endif
  1340. /*
  1341. * If no local APIC can be found then set up a fake all
  1342. * zeroes page to simulate the local APIC and another
  1343. * one for the IO-APIC.
  1344. */
  1345. if (!smp_found_config && detect_init_APIC()) {
  1346. apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
  1347. apic_phys = __pa(apic_phys);
  1348. } else
  1349. apic_phys = mp_lapic_addr;
  1350. set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
  1351. apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n",
  1352. APIC_BASE, apic_phys);
  1353. /*
  1354. * Fetch the APIC ID of the BSP in case we have a
  1355. * default configuration (or the MP table is broken).
  1356. */
  1357. if (boot_cpu_physical_apicid == -1U)
  1358. boot_cpu_physical_apicid = read_apic_id();
  1359. }
  1360. /*
  1361. * This initializes the IO-APIC and APIC hardware if this is
  1362. * a UP kernel.
  1363. */
  1364. int apic_version[MAX_APICS];
  1365. int __init APIC_init_uniprocessor(void)
  1366. {
  1367. if (disable_apic) {
  1368. pr_info("Apic disabled\n");
  1369. return -1;
  1370. }
  1371. #ifdef CONFIG_X86_64
  1372. if (!cpu_has_apic) {
  1373. disable_apic = 1;
  1374. pr_info("Apic disabled by BIOS\n");
  1375. return -1;
  1376. }
  1377. #else
  1378. if (!smp_found_config && !cpu_has_apic)
  1379. return -1;
  1380. /*
  1381. * Complain if the BIOS pretends there is one.
  1382. */
  1383. if (!cpu_has_apic &&
  1384. APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
  1385. pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
  1386. boot_cpu_physical_apicid);
  1387. clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
  1388. return -1;
  1389. }
  1390. #endif
  1391. #ifdef HAVE_X2APIC
  1392. enable_IR_x2apic();
  1393. #endif
  1394. #ifdef CONFIG_X86_64
  1395. default_setup_apic_routing();
  1396. #endif
  1397. verify_local_APIC();
  1398. connect_bsp_APIC();
  1399. #ifdef CONFIG_X86_64
  1400. apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
  1401. #else
  1402. /*
  1403. * Hack: In case of kdump, after a crash, kernel might be booting
  1404. * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
  1405. * might be zero if read from MP tables. Get it from LAPIC.
  1406. */
  1407. # ifdef CONFIG_CRASH_DUMP
  1408. boot_cpu_physical_apicid = read_apic_id();
  1409. # endif
  1410. #endif
  1411. physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
  1412. setup_local_APIC();
  1413. #ifdef CONFIG_X86_64
  1414. /*
  1415. * Now enable IO-APICs, actually call clear_IO_APIC
  1416. * We need clear_IO_APIC before enabling vector on BP
  1417. */
  1418. if (!skip_ioapic_setup && nr_ioapics)
  1419. enable_IO_APIC();
  1420. #endif
  1421. #ifdef CONFIG_X86_IO_APIC
  1422. if (!smp_found_config || skip_ioapic_setup || !nr_ioapics)
  1423. #endif
  1424. localise_nmi_watchdog();
  1425. end_local_APIC_setup();
  1426. #ifdef CONFIG_X86_IO_APIC
  1427. if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
  1428. setup_IO_APIC();
  1429. # ifdef CONFIG_X86_64
  1430. else
  1431. nr_ioapics = 0;
  1432. # endif
  1433. #endif
  1434. #ifdef CONFIG_X86_64
  1435. setup_boot_APIC_clock();
  1436. check_nmi_watchdog();
  1437. #else
  1438. setup_boot_clock();
  1439. #endif
  1440. return 0;
  1441. }
  1442. /*
  1443. * Local APIC interrupts
  1444. */
  1445. /*
  1446. * This interrupt should _never_ happen with our APIC/SMP architecture
  1447. */
  1448. void smp_spurious_interrupt(struct pt_regs *regs)
  1449. {
  1450. u32 v;
  1451. exit_idle();
  1452. irq_enter();
  1453. /*
  1454. * Check if this really is a spurious interrupt and ACK it
  1455. * if it is a vectored one. Just in case...
  1456. * Spurious interrupts should not be ACKed.
  1457. */
  1458. v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
  1459. if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
  1460. ack_APIC_irq();
  1461. inc_irq_stat(irq_spurious_count);
  1462. /* see sw-dev-man vol 3, chapter 7.4.13.5 */
  1463. pr_info("spurious APIC interrupt on CPU#%d, "
  1464. "should never happen.\n", smp_processor_id());
  1465. irq_exit();
  1466. }
  1467. /*
  1468. * This interrupt should never happen with our APIC/SMP architecture
  1469. */
  1470. void smp_error_interrupt(struct pt_regs *regs)
  1471. {
  1472. u32 v, v1;
  1473. exit_idle();
  1474. irq_enter();
  1475. /* First tickle the hardware, only then report what went on. -- REW */
  1476. v = apic_read(APIC_ESR);
  1477. apic_write(APIC_ESR, 0);
  1478. v1 = apic_read(APIC_ESR);
  1479. ack_APIC_irq();
  1480. atomic_inc(&irq_err_count);
  1481. /*
  1482. * Here is what the APIC error bits mean:
  1483. * 0: Send CS error
  1484. * 1: Receive CS error
  1485. * 2: Send accept error
  1486. * 3: Receive accept error
  1487. * 4: Reserved
  1488. * 5: Send illegal vector
  1489. * 6: Received illegal vector
  1490. * 7: Illegal register address
  1491. */
  1492. pr_debug("APIC error on CPU%d: %02x(%02x)\n",
  1493. smp_processor_id(), v , v1);
  1494. irq_exit();
  1495. }
  1496. /**
  1497. * connect_bsp_APIC - attach the APIC to the interrupt system
  1498. */
  1499. void __init connect_bsp_APIC(void)
  1500. {
  1501. #ifdef CONFIG_X86_32
  1502. if (pic_mode) {
  1503. /*
  1504. * Do not trust the local APIC being empty at bootup.
  1505. */
  1506. clear_local_APIC();
  1507. /*
  1508. * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
  1509. * local APIC to INT and NMI lines.
  1510. */
  1511. apic_printk(APIC_VERBOSE, "leaving PIC mode, "
  1512. "enabling APIC mode.\n");
  1513. outb(0x70, 0x22);
  1514. outb(0x01, 0x23);
  1515. }
  1516. #endif
  1517. if (apic->enable_apic_mode)
  1518. apic->enable_apic_mode();
  1519. }
  1520. /**
  1521. * disconnect_bsp_APIC - detach the APIC from the interrupt system
  1522. * @virt_wire_setup: indicates, whether virtual wire mode is selected
  1523. *
  1524. * Virtual wire mode is necessary to deliver legacy interrupts even when the
  1525. * APIC is disabled.
  1526. */
  1527. void disconnect_bsp_APIC(int virt_wire_setup)
  1528. {
  1529. unsigned int value;
  1530. #ifdef CONFIG_X86_32
  1531. if (pic_mode) {
  1532. /*
  1533. * Put the board back into PIC mode (has an effect only on
  1534. * certain older boards). Note that APIC interrupts, including
  1535. * IPIs, won't work beyond this point! The only exception are
  1536. * INIT IPIs.
  1537. */
  1538. apic_printk(APIC_VERBOSE, "disabling APIC mode, "
  1539. "entering PIC mode.\n");
  1540. outb(0x70, 0x22);
  1541. outb(0x00, 0x23);
  1542. return;
  1543. }
  1544. #endif
  1545. /* Go back to Virtual Wire compatibility mode */
  1546. /* For the spurious interrupt use vector F, and enable it */
  1547. value = apic_read(APIC_SPIV);
  1548. value &= ~APIC_VECTOR_MASK;
  1549. value |= APIC_SPIV_APIC_ENABLED;
  1550. value |= 0xf;
  1551. apic_write(APIC_SPIV, value);
  1552. if (!virt_wire_setup) {
  1553. /*
  1554. * For LVT0 make it edge triggered, active high,
  1555. * external and enabled
  1556. */
  1557. value = apic_read(APIC_LVT0);
  1558. value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
  1559. APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
  1560. APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
  1561. value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
  1562. value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
  1563. apic_write(APIC_LVT0, value);
  1564. } else {
  1565. /* Disable LVT0 */
  1566. apic_write(APIC_LVT0, APIC_LVT_MASKED);
  1567. }
  1568. /*
  1569. * For LVT1 make it edge triggered, active high,
  1570. * nmi and enabled
  1571. */
  1572. value = apic_read(APIC_LVT1);
  1573. value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
  1574. APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
  1575. APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
  1576. value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
  1577. value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
  1578. apic_write(APIC_LVT1, value);
  1579. }
  1580. void __cpuinit generic_processor_info(int apicid, int version)
  1581. {
  1582. int cpu;
  1583. /*
  1584. * Validate version
  1585. */
  1586. if (version == 0x0) {
  1587. pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
  1588. "fixing up to 0x10. (tell your hw vendor)\n",
  1589. version);
  1590. version = 0x10;
  1591. }
  1592. apic_version[apicid] = version;
  1593. if (num_processors >= nr_cpu_ids) {
  1594. int max = nr_cpu_ids;
  1595. int thiscpu = max + disabled_cpus;
  1596. pr_warning(
  1597. "ACPI: NR_CPUS/possible_cpus limit of %i reached."
  1598. " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
  1599. disabled_cpus++;
  1600. return;
  1601. }
  1602. num_processors++;
  1603. cpu = cpumask_next_zero(-1, cpu_present_mask);
  1604. if (version != apic_version[boot_cpu_physical_apicid])
  1605. WARN_ONCE(1,
  1606. "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n",
  1607. apic_version[boot_cpu_physical_apicid], cpu, version);
  1608. physid_set(apicid, phys_cpu_present_map);
  1609. if (apicid == boot_cpu_physical_apicid) {
  1610. /*
  1611. * x86_bios_cpu_apicid is required to have processors listed
  1612. * in same order as logical cpu numbers. Hence the first
  1613. * entry is BSP, and so on.
  1614. */
  1615. cpu = 0;
  1616. }
  1617. if (apicid > max_physical_apicid)
  1618. max_physical_apicid = apicid;
  1619. #ifdef CONFIG_X86_32
  1620. /*
  1621. * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
  1622. * but we need to work other dependencies like SMP_SUSPEND etc
  1623. * before this can be done without some confusion.
  1624. * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
  1625. * - Ashok Raj <ashok.raj@intel.com>
  1626. */
  1627. if (max_physical_apicid >= 8) {
  1628. switch (boot_cpu_data.x86_vendor) {
  1629. case X86_VENDOR_INTEL:
  1630. if (!APIC_XAPIC(version)) {
  1631. def_to_bigsmp = 0;
  1632. break;
  1633. }
  1634. /* If P4 and above fall through */
  1635. case X86_VENDOR_AMD:
  1636. def_to_bigsmp = 1;
  1637. }
  1638. }
  1639. #endif
  1640. #if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64)
  1641. early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
  1642. early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
  1643. #endif
  1644. set_cpu_possible(cpu, true);
  1645. set_cpu_present(cpu, true);
  1646. }
  1647. #ifdef CONFIG_X86_64
  1648. int hard_smp_processor_id(void)
  1649. {
  1650. return read_apic_id();
  1651. }
  1652. #endif
  1653. /*
  1654. * Power management
  1655. */
  1656. #ifdef CONFIG_PM
  1657. static struct {
  1658. /*
  1659. * 'active' is true if the local APIC was enabled by us and
  1660. * not the BIOS; this signifies that we are also responsible
  1661. * for disabling it before entering apm/acpi suspend
  1662. */
  1663. int active;
  1664. /* r/w apic fields */
  1665. unsigned int apic_id;
  1666. unsigned int apic_taskpri;
  1667. unsigned int apic_ldr;
  1668. unsigned int apic_dfr;
  1669. unsigned int apic_spiv;
  1670. unsigned int apic_lvtt;
  1671. unsigned int apic_lvtpc;
  1672. unsigned int apic_lvt0;
  1673. unsigned int apic_lvt1;
  1674. unsigned int apic_lvterr;
  1675. unsigned int apic_tmict;
  1676. unsigned int apic_tdcr;
  1677. unsigned int apic_thmr;
  1678. } apic_pm_state;
  1679. static int lapic_suspend(struct sys_device *dev, pm_message_t state)
  1680. {
  1681. unsigned long flags;
  1682. int maxlvt;
  1683. if (!apic_pm_state.active)
  1684. return 0;
  1685. maxlvt = lapic_get_maxlvt();
  1686. apic_pm_state.apic_id = apic_read(APIC_ID);
  1687. apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
  1688. apic_pm_state.apic_ldr = apic_read(APIC_LDR);
  1689. apic_pm_state.apic_dfr = apic_read(APIC_DFR);
  1690. apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
  1691. apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
  1692. if (maxlvt >= 4)
  1693. apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
  1694. apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
  1695. apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
  1696. apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
  1697. apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
  1698. apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
  1699. #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
  1700. if (maxlvt >= 5)
  1701. apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
  1702. #endif
  1703. local_irq_save(flags);
  1704. disable_local_APIC();
  1705. local_irq_restore(flags);
  1706. return 0;
  1707. }
  1708. static int lapic_resume(struct sys_device *dev)
  1709. {
  1710. unsigned int l, h;
  1711. unsigned long flags;
  1712. int maxlvt;
  1713. if (!apic_pm_state.active)
  1714. return 0;
  1715. maxlvt = lapic_get_maxlvt();
  1716. local_irq_save(flags);
  1717. #ifdef HAVE_X2APIC
  1718. if (x2apic)
  1719. enable_x2apic();
  1720. else
  1721. #endif
  1722. {
  1723. /*
  1724. * Make sure the APICBASE points to the right address
  1725. *
  1726. * FIXME! This will be wrong if we ever support suspend on
  1727. * SMP! We'll need to do this as part of the CPU restore!
  1728. */
  1729. rdmsr(MSR_IA32_APICBASE, l, h);
  1730. l &= ~MSR_IA32_APICBASE_BASE;
  1731. l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
  1732. wrmsr(MSR_IA32_APICBASE, l, h);
  1733. }
  1734. apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
  1735. apic_write(APIC_ID, apic_pm_state.apic_id);
  1736. apic_write(APIC_DFR, apic_pm_state.apic_dfr);
  1737. apic_write(APIC_LDR, apic_pm_state.apic_ldr);
  1738. apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
  1739. apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
  1740. apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
  1741. apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
  1742. #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
  1743. if (maxlvt >= 5)
  1744. apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
  1745. #endif
  1746. if (maxlvt >= 4)
  1747. apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
  1748. apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
  1749. apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
  1750. apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
  1751. apic_write(APIC_ESR, 0);
  1752. apic_read(APIC_ESR);
  1753. apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
  1754. apic_write(APIC_ESR, 0);
  1755. apic_read(APIC_ESR);
  1756. local_irq_restore(flags);
  1757. return 0;
  1758. }
  1759. /*
  1760. * This device has no shutdown method - fully functioning local APICs
  1761. * are needed on every CPU up until machine_halt/restart/poweroff.
  1762. */
  1763. static struct sysdev_class lapic_sysclass = {
  1764. .name = "lapic",
  1765. .resume = lapic_resume,
  1766. .suspend = lapic_suspend,
  1767. };
  1768. static struct sys_device device_lapic = {
  1769. .id = 0,
  1770. .cls = &lapic_sysclass,
  1771. };
  1772. static void __cpuinit apic_pm_activate(void)
  1773. {
  1774. apic_pm_state.active = 1;
  1775. }
  1776. static int __init init_lapic_sysfs(void)
  1777. {
  1778. int error;
  1779. if (!cpu_has_apic)
  1780. return 0;
  1781. /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
  1782. error = sysdev_class_register(&lapic_sysclass);
  1783. if (!error)
  1784. error = sysdev_register(&device_lapic);
  1785. return error;
  1786. }
  1787. device_initcall(init_lapic_sysfs);
  1788. #else /* CONFIG_PM */
  1789. static void apic_pm_activate(void) { }
  1790. #endif /* CONFIG_PM */
  1791. #ifdef CONFIG_X86_64
  1792. /*
  1793. * apic_is_clustered_box() -- Check if we can expect good TSC
  1794. *
  1795. * Thus far, the major user of this is IBM's Summit2 series:
  1796. *
  1797. * Clustered boxes may have unsynced TSC problems if they are
  1798. * multi-chassis. Use available data to take a good guess.
  1799. * If in doubt, go HPET.
  1800. */
  1801. __cpuinit int apic_is_clustered_box(void)
  1802. {
  1803. int i, clusters, zeros;
  1804. unsigned id;
  1805. u16 *bios_cpu_apicid;
  1806. DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
  1807. /*
  1808. * there is not this kind of box with AMD CPU yet.
  1809. * Some AMD box with quadcore cpu and 8 sockets apicid
  1810. * will be [4, 0x23] or [8, 0x27] could be thought to
  1811. * vsmp box still need checking...
  1812. */
  1813. if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box())
  1814. return 0;
  1815. bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
  1816. bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
  1817. for (i = 0; i < nr_cpu_ids; i++) {
  1818. /* are we being called early in kernel startup? */
  1819. if (bios_cpu_apicid) {
  1820. id = bios_cpu_apicid[i];
  1821. } else if (i < nr_cpu_ids) {
  1822. if (cpu_present(i))
  1823. id = per_cpu(x86_bios_cpu_apicid, i);
  1824. else
  1825. continue;
  1826. } else
  1827. break;
  1828. if (id != BAD_APICID)
  1829. __set_bit(APIC_CLUSTERID(id), clustermap);
  1830. }
  1831. /* Problem: Partially populated chassis may not have CPUs in some of
  1832. * the APIC clusters they have been allocated. Only present CPUs have
  1833. * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
  1834. * Since clusters are allocated sequentially, count zeros only if
  1835. * they are bounded by ones.
  1836. */
  1837. clusters = 0;
  1838. zeros = 0;
  1839. for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
  1840. if (test_bit(i, clustermap)) {
  1841. clusters += 1 + zeros;
  1842. zeros = 0;
  1843. } else
  1844. ++zeros;
  1845. }
  1846. /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
  1847. * not guaranteed to be synced between boards
  1848. */
  1849. if (is_vsmp_box() && clusters > 1)
  1850. return 1;
  1851. /*
  1852. * If clusters > 2, then should be multi-chassis.
  1853. * May have to revisit this when multi-core + hyperthreaded CPUs come
  1854. * out, but AFAIK this will work even for them.
  1855. */
  1856. return (clusters > 2);
  1857. }
  1858. #endif
  1859. /*
  1860. * APIC command line parameters
  1861. */
  1862. static int __init setup_disableapic(char *arg)
  1863. {
  1864. disable_apic = 1;
  1865. setup_clear_cpu_cap(X86_FEATURE_APIC);
  1866. return 0;
  1867. }
  1868. early_param("disableapic", setup_disableapic);
  1869. /* same as disableapic, for compatibility */
  1870. static int __init setup_nolapic(char *arg)
  1871. {
  1872. return setup_disableapic(arg);
  1873. }
  1874. early_param("nolapic", setup_nolapic);
  1875. static int __init parse_lapic_timer_c2_ok(char *arg)
  1876. {
  1877. local_apic_timer_c2_ok = 1;
  1878. return 0;
  1879. }
  1880. early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
  1881. static int __init parse_disable_apic_timer(char *arg)
  1882. {
  1883. disable_apic_timer = 1;
  1884. return 0;
  1885. }
  1886. early_param("noapictimer", parse_disable_apic_timer);
  1887. static int __init parse_nolapic_timer(char *arg)
  1888. {
  1889. disable_apic_timer = 1;
  1890. return 0;
  1891. }
  1892. early_param("nolapic_timer", parse_nolapic_timer);
  1893. static int __init apic_set_verbosity(char *arg)
  1894. {
  1895. if (!arg) {
  1896. #ifdef CONFIG_X86_64
  1897. skip_ioapic_setup = 0;
  1898. return 0;
  1899. #endif
  1900. return -EINVAL;
  1901. }
  1902. if (strcmp("debug", arg) == 0)
  1903. apic_verbosity = APIC_DEBUG;
  1904. else if (strcmp("verbose", arg) == 0)
  1905. apic_verbosity = APIC_VERBOSE;
  1906. else {
  1907. pr_warning("APIC Verbosity level %s not recognised"
  1908. " use apic=verbose or apic=debug\n", arg);
  1909. return -EINVAL;
  1910. }
  1911. return 0;
  1912. }
  1913. early_param("apic", apic_set_verbosity);
  1914. static int __init lapic_insert_resource(void)
  1915. {
  1916. if (!apic_phys)
  1917. return -1;
  1918. /* Put local APIC into the resource map. */
  1919. lapic_resource.start = apic_phys;
  1920. lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
  1921. insert_resource(&iomem_resource, &lapic_resource);
  1922. return 0;
  1923. }
  1924. /*
  1925. * need call insert after e820_reserve_resources()
  1926. * that is using request_resource
  1927. */
  1928. late_initcall(lapic_insert_resource);