imx.c 23 KB

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  1. /*
  2. * linux/drivers/serial/imx.c
  3. *
  4. * Driver for Motorola IMX serial ports
  5. *
  6. * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
  7. *
  8. * Author: Sascha Hauer <sascha@saschahauer.de>
  9. * Copyright (C) 2004 Pengutronix
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  24. *
  25. * [29-Mar-2005] Mike Lee
  26. * Added hardware handshake
  27. */
  28. #include <linux/config.h>
  29. #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  30. #define SUPPORT_SYSRQ
  31. #endif
  32. #include <linux/module.h>
  33. #include <linux/ioport.h>
  34. #include <linux/init.h>
  35. #include <linux/console.h>
  36. #include <linux/sysrq.h>
  37. #include <linux/platform_device.h>
  38. #include <linux/tty.h>
  39. #include <linux/tty_flip.h>
  40. #include <linux/serial_core.h>
  41. #include <linux/serial.h>
  42. #include <asm/io.h>
  43. #include <asm/irq.h>
  44. #include <asm/hardware.h>
  45. #include <asm/arch/imx-uart.h>
  46. /* We've been assigned a range on the "Low-density serial ports" major */
  47. #define SERIAL_IMX_MAJOR 204
  48. #define MINOR_START 41
  49. #define NR_PORTS 2
  50. #define IMX_ISR_PASS_LIMIT 256
  51. /*
  52. * This is the size of our serial port register set.
  53. */
  54. #define UART_PORT_SIZE 0x100
  55. /*
  56. * This determines how often we check the modem status signals
  57. * for any change. They generally aren't connected to an IRQ
  58. * so we have to poll them. We also check immediately before
  59. * filling the TX fifo incase CTS has been dropped.
  60. */
  61. #define MCTRL_TIMEOUT (250*HZ/1000)
  62. #define DRIVER_NAME "IMX-uart"
  63. struct imx_port {
  64. struct uart_port port;
  65. struct timer_list timer;
  66. unsigned int old_status;
  67. int txirq,rxirq,rtsirq;
  68. int have_rtscts:1;
  69. };
  70. /*
  71. * Handle any change of modem status signal since we were last called.
  72. */
  73. static void imx_mctrl_check(struct imx_port *sport)
  74. {
  75. unsigned int status, changed;
  76. status = sport->port.ops->get_mctrl(&sport->port);
  77. changed = status ^ sport->old_status;
  78. if (changed == 0)
  79. return;
  80. sport->old_status = status;
  81. if (changed & TIOCM_RI)
  82. sport->port.icount.rng++;
  83. if (changed & TIOCM_DSR)
  84. sport->port.icount.dsr++;
  85. if (changed & TIOCM_CAR)
  86. uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
  87. if (changed & TIOCM_CTS)
  88. uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
  89. wake_up_interruptible(&sport->port.info->delta_msr_wait);
  90. }
  91. /*
  92. * This is our per-port timeout handler, for checking the
  93. * modem status signals.
  94. */
  95. static void imx_timeout(unsigned long data)
  96. {
  97. struct imx_port *sport = (struct imx_port *)data;
  98. unsigned long flags;
  99. if (sport->port.info) {
  100. spin_lock_irqsave(&sport->port.lock, flags);
  101. imx_mctrl_check(sport);
  102. spin_unlock_irqrestore(&sport->port.lock, flags);
  103. mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
  104. }
  105. }
  106. /*
  107. * interrupts disabled on entry
  108. */
  109. static void imx_stop_tx(struct uart_port *port)
  110. {
  111. struct imx_port *sport = (struct imx_port *)port;
  112. UCR1((u32)sport->port.membase) &= ~UCR1_TXMPTYEN;
  113. }
  114. /*
  115. * interrupts disabled on entry
  116. */
  117. static void imx_stop_rx(struct uart_port *port)
  118. {
  119. struct imx_port *sport = (struct imx_port *)port;
  120. UCR2((u32)sport->port.membase) &= ~UCR2_RXEN;
  121. }
  122. /*
  123. * Set the modem control timer to fire immediately.
  124. */
  125. static void imx_enable_ms(struct uart_port *port)
  126. {
  127. struct imx_port *sport = (struct imx_port *)port;
  128. mod_timer(&sport->timer, jiffies);
  129. }
  130. static inline void imx_transmit_buffer(struct imx_port *sport)
  131. {
  132. struct circ_buf *xmit = &sport->port.info->xmit;
  133. do {
  134. /* send xmit->buf[xmit->tail]
  135. * out the port here */
  136. URTX0((u32)sport->port.membase) = xmit->buf[xmit->tail];
  137. xmit->tail = (xmit->tail + 1) &
  138. (UART_XMIT_SIZE - 1);
  139. sport->port.icount.tx++;
  140. if (uart_circ_empty(xmit))
  141. break;
  142. } while (!(UTS((u32)sport->port.membase) & UTS_TXFULL));
  143. if (uart_circ_empty(xmit))
  144. imx_stop_tx(&sport->port);
  145. }
  146. /*
  147. * interrupts disabled on entry
  148. */
  149. static void imx_start_tx(struct uart_port *port)
  150. {
  151. struct imx_port *sport = (struct imx_port *)port;
  152. UCR1((u32)sport->port.membase) |= UCR1_TXMPTYEN;
  153. if(UTS((u32)sport->port.membase) & UTS_TXEMPTY)
  154. imx_transmit_buffer(sport);
  155. }
  156. static irqreturn_t imx_rtsint(int irq, void *dev_id, struct pt_regs *regs)
  157. {
  158. struct imx_port *sport = (struct imx_port *)dev_id;
  159. unsigned int val = USR1((u32)sport->port.membase)&USR1_RTSS;
  160. unsigned long flags;
  161. spin_lock_irqsave(&sport->port.lock, flags);
  162. USR1((u32)sport->port.membase) = USR1_RTSD;
  163. uart_handle_cts_change(&sport->port, !!val);
  164. wake_up_interruptible(&sport->port.info->delta_msr_wait);
  165. spin_unlock_irqrestore(&sport->port.lock, flags);
  166. return IRQ_HANDLED;
  167. }
  168. static irqreturn_t imx_txint(int irq, void *dev_id, struct pt_regs *regs)
  169. {
  170. struct imx_port *sport = (struct imx_port *)dev_id;
  171. struct circ_buf *xmit = &sport->port.info->xmit;
  172. unsigned long flags;
  173. spin_lock_irqsave(&sport->port.lock,flags);
  174. if (sport->port.x_char)
  175. {
  176. /* Send next char */
  177. URTX0((u32)sport->port.membase) = sport->port.x_char;
  178. goto out;
  179. }
  180. if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
  181. imx_stop_tx(&sport->port);
  182. goto out;
  183. }
  184. imx_transmit_buffer(sport);
  185. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  186. uart_write_wakeup(&sport->port);
  187. out:
  188. spin_unlock_irqrestore(&sport->port.lock,flags);
  189. return IRQ_HANDLED;
  190. }
  191. static irqreturn_t imx_rxint(int irq, void *dev_id, struct pt_regs *regs)
  192. {
  193. struct imx_port *sport = dev_id;
  194. unsigned int rx,flg,ignored = 0;
  195. struct tty_struct *tty = sport->port.info->tty;
  196. unsigned long flags;
  197. rx = URXD0((u32)sport->port.membase);
  198. spin_lock_irqsave(&sport->port.lock,flags);
  199. do {
  200. flg = TTY_NORMAL;
  201. sport->port.icount.rx++;
  202. if( USR2((u32)sport->port.membase) & USR2_BRCD ) {
  203. USR2((u32)sport->port.membase) |= USR2_BRCD;
  204. if(uart_handle_break(&sport->port))
  205. goto ignore_char;
  206. }
  207. if (uart_handle_sysrq_char
  208. (&sport->port, (unsigned char)rx, regs))
  209. goto ignore_char;
  210. if( rx & (URXD_PRERR | URXD_OVRRUN | URXD_FRMERR) )
  211. goto handle_error;
  212. error_return:
  213. tty_insert_flip_char(tty, rx, flg);
  214. ignore_char:
  215. rx = URXD0((u32)sport->port.membase);
  216. } while(rx & URXD_CHARRDY);
  217. out:
  218. spin_unlock_irqrestore(&sport->port.lock,flags);
  219. tty_flip_buffer_push(tty);
  220. return IRQ_HANDLED;
  221. handle_error:
  222. if (rx & URXD_PRERR)
  223. sport->port.icount.parity++;
  224. else if (rx & URXD_FRMERR)
  225. sport->port.icount.frame++;
  226. if (rx & URXD_OVRRUN)
  227. sport->port.icount.overrun++;
  228. if (rx & sport->port.ignore_status_mask) {
  229. if (++ignored > 100)
  230. goto out;
  231. goto ignore_char;
  232. }
  233. rx &= sport->port.read_status_mask;
  234. if (rx & URXD_PRERR)
  235. flg = TTY_PARITY;
  236. else if (rx & URXD_FRMERR)
  237. flg = TTY_FRAME;
  238. if (rx & URXD_OVRRUN)
  239. flg = TTY_OVERRUN;
  240. #ifdef SUPPORT_SYSRQ
  241. sport->port.sysrq = 0;
  242. #endif
  243. goto error_return;
  244. }
  245. /*
  246. * Return TIOCSER_TEMT when transmitter is not busy.
  247. */
  248. static unsigned int imx_tx_empty(struct uart_port *port)
  249. {
  250. struct imx_port *sport = (struct imx_port *)port;
  251. return USR2((u32)sport->port.membase) & USR2_TXDC ? TIOCSER_TEMT : 0;
  252. }
  253. /*
  254. * We have a modem side uart, so the meanings of RTS and CTS are inverted.
  255. */
  256. static unsigned int imx_get_mctrl(struct uart_port *port)
  257. {
  258. struct imx_port *sport = (struct imx_port *)port;
  259. unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
  260. if (USR1((u32)sport->port.membase) & USR1_RTSS)
  261. tmp |= TIOCM_CTS;
  262. if (UCR2((u32)sport->port.membase) & UCR2_CTS)
  263. tmp |= TIOCM_RTS;
  264. return tmp;
  265. }
  266. static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
  267. {
  268. struct imx_port *sport = (struct imx_port *)port;
  269. if (mctrl & TIOCM_RTS)
  270. UCR2((u32)sport->port.membase) |= UCR2_CTS;
  271. else
  272. UCR2((u32)sport->port.membase) &= ~UCR2_CTS;
  273. }
  274. /*
  275. * Interrupts always disabled.
  276. */
  277. static void imx_break_ctl(struct uart_port *port, int break_state)
  278. {
  279. struct imx_port *sport = (struct imx_port *)port;
  280. unsigned long flags;
  281. spin_lock_irqsave(&sport->port.lock, flags);
  282. if ( break_state != 0 )
  283. UCR1((u32)sport->port.membase) |= UCR1_SNDBRK;
  284. else
  285. UCR1((u32)sport->port.membase) &= ~UCR1_SNDBRK;
  286. spin_unlock_irqrestore(&sport->port.lock, flags);
  287. }
  288. #define TXTL 2 /* reset default */
  289. #define RXTL 1 /* reset default */
  290. static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
  291. {
  292. unsigned int val;
  293. unsigned int ufcr_rfdiv;
  294. /* set receiver / transmitter trigger level.
  295. * RFDIV is set such way to satisfy requested uartclk value
  296. */
  297. val = TXTL<<10 | RXTL;
  298. ufcr_rfdiv = (imx_get_perclk1() + sport->port.uartclk / 2) / sport->port.uartclk;
  299. if(!ufcr_rfdiv)
  300. ufcr_rfdiv = 1;
  301. if(ufcr_rfdiv >= 7)
  302. ufcr_rfdiv = 6;
  303. else
  304. ufcr_rfdiv = 6 - ufcr_rfdiv;
  305. val |= UFCR_RFDIV & (ufcr_rfdiv << 7);
  306. UFCR((u32)sport->port.membase) = val;
  307. return 0;
  308. }
  309. static int imx_startup(struct uart_port *port)
  310. {
  311. struct imx_port *sport = (struct imx_port *)port;
  312. int retval;
  313. unsigned long flags;
  314. imx_setup_ufcr(sport, 0);
  315. /* disable the DREN bit (Data Ready interrupt enable) before
  316. * requesting IRQs
  317. */
  318. UCR4((u32)sport->port.membase) &= ~UCR4_DREN;
  319. /*
  320. * Allocate the IRQ
  321. */
  322. retval = request_irq(sport->rxirq, imx_rxint, 0,
  323. DRIVER_NAME, sport);
  324. if (retval) goto error_out1;
  325. retval = request_irq(sport->txirq, imx_txint, 0,
  326. DRIVER_NAME, sport);
  327. if (retval) goto error_out2;
  328. retval = request_irq(sport->rtsirq, imx_rtsint,
  329. SA_TRIGGER_FALLING | SA_TRIGGER_RISING,
  330. DRIVER_NAME, sport);
  331. if (retval) goto error_out3;
  332. /*
  333. * Finally, clear and enable interrupts
  334. */
  335. USR1((u32)sport->port.membase) = USR1_RTSD;
  336. UCR1((u32)sport->port.membase) |=
  337. (UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
  338. UCR2((u32)sport->port.membase) |= (UCR2_RXEN | UCR2_TXEN);
  339. /*
  340. * Enable modem status interrupts
  341. */
  342. spin_lock_irqsave(&sport->port.lock,flags);
  343. imx_enable_ms(&sport->port);
  344. spin_unlock_irqrestore(&sport->port.lock,flags);
  345. return 0;
  346. error_out3:
  347. free_irq(sport->txirq, sport);
  348. error_out2:
  349. free_irq(sport->rxirq, sport);
  350. error_out1:
  351. return retval;
  352. }
  353. static void imx_shutdown(struct uart_port *port)
  354. {
  355. struct imx_port *sport = (struct imx_port *)port;
  356. /*
  357. * Stop our timer.
  358. */
  359. del_timer_sync(&sport->timer);
  360. /*
  361. * Free the interrupts
  362. */
  363. free_irq(sport->rtsirq, sport);
  364. free_irq(sport->txirq, sport);
  365. free_irq(sport->rxirq, sport);
  366. /*
  367. * Disable all interrupts, port and break condition.
  368. */
  369. UCR1((u32)sport->port.membase) &=
  370. ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
  371. }
  372. static void
  373. imx_set_termios(struct uart_port *port, struct termios *termios,
  374. struct termios *old)
  375. {
  376. struct imx_port *sport = (struct imx_port *)port;
  377. unsigned long flags;
  378. unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
  379. unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
  380. /*
  381. * If we don't support modem control lines, don't allow
  382. * these to be set.
  383. */
  384. if (0) {
  385. termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
  386. termios->c_cflag |= CLOCAL;
  387. }
  388. /*
  389. * We only support CS7 and CS8.
  390. */
  391. while ((termios->c_cflag & CSIZE) != CS7 &&
  392. (termios->c_cflag & CSIZE) != CS8) {
  393. termios->c_cflag &= ~CSIZE;
  394. termios->c_cflag |= old_csize;
  395. old_csize = CS8;
  396. }
  397. if ((termios->c_cflag & CSIZE) == CS8)
  398. ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
  399. else
  400. ucr2 = UCR2_SRST | UCR2_IRTS;
  401. if (termios->c_cflag & CRTSCTS) {
  402. if( sport->have_rtscts ) {
  403. ucr2 &= ~UCR2_IRTS;
  404. ucr2 |= UCR2_CTSC;
  405. } else {
  406. termios->c_cflag &= ~CRTSCTS;
  407. }
  408. }
  409. if (termios->c_cflag & CSTOPB)
  410. ucr2 |= UCR2_STPB;
  411. if (termios->c_cflag & PARENB) {
  412. ucr2 |= UCR2_PREN;
  413. if (termios->c_cflag & PARODD)
  414. ucr2 |= UCR2_PROE;
  415. }
  416. /*
  417. * Ask the core to calculate the divisor for us.
  418. */
  419. baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
  420. quot = uart_get_divisor(port, baud);
  421. spin_lock_irqsave(&sport->port.lock, flags);
  422. sport->port.read_status_mask = 0;
  423. if (termios->c_iflag & INPCK)
  424. sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
  425. if (termios->c_iflag & (BRKINT | PARMRK))
  426. sport->port.read_status_mask |= URXD_BRK;
  427. /*
  428. * Characters to ignore
  429. */
  430. sport->port.ignore_status_mask = 0;
  431. if (termios->c_iflag & IGNPAR)
  432. sport->port.ignore_status_mask |= URXD_PRERR;
  433. if (termios->c_iflag & IGNBRK) {
  434. sport->port.ignore_status_mask |= URXD_BRK;
  435. /*
  436. * If we're ignoring parity and break indicators,
  437. * ignore overruns too (for real raw support).
  438. */
  439. if (termios->c_iflag & IGNPAR)
  440. sport->port.ignore_status_mask |= URXD_OVRRUN;
  441. }
  442. del_timer_sync(&sport->timer);
  443. /*
  444. * Update the per-port timeout.
  445. */
  446. uart_update_timeout(port, termios->c_cflag, baud);
  447. /*
  448. * disable interrupts and drain transmitter
  449. */
  450. old_ucr1 = UCR1((u32)sport->port.membase);
  451. UCR1((u32)sport->port.membase) &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
  452. while ( !(USR2((u32)sport->port.membase) & USR2_TXDC))
  453. barrier();
  454. /* then, disable everything */
  455. old_txrxen = UCR2((u32)sport->port.membase) & ( UCR2_TXEN | UCR2_RXEN );
  456. UCR2((u32)sport->port.membase) &= ~( UCR2_TXEN | UCR2_RXEN);
  457. /* set the parity, stop bits and data size */
  458. UCR2((u32)sport->port.membase) = ucr2;
  459. /* set the baud rate. We assume uartclk = 16 MHz
  460. *
  461. * baud * 16 UBIR - 1
  462. * --------- = --------
  463. * uartclk UBMR - 1
  464. */
  465. UBIR((u32)sport->port.membase) = (baud / 100) - 1;
  466. UBMR((u32)sport->port.membase) = 10000 - 1;
  467. UCR1((u32)sport->port.membase) = old_ucr1;
  468. UCR2((u32)sport->port.membase) |= old_txrxen;
  469. if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
  470. imx_enable_ms(&sport->port);
  471. spin_unlock_irqrestore(&sport->port.lock, flags);
  472. }
  473. static const char *imx_type(struct uart_port *port)
  474. {
  475. struct imx_port *sport = (struct imx_port *)port;
  476. return sport->port.type == PORT_IMX ? "IMX" : NULL;
  477. }
  478. /*
  479. * Release the memory region(s) being used by 'port'.
  480. */
  481. static void imx_release_port(struct uart_port *port)
  482. {
  483. struct imx_port *sport = (struct imx_port *)port;
  484. release_mem_region(sport->port.mapbase, UART_PORT_SIZE);
  485. }
  486. /*
  487. * Request the memory region(s) being used by 'port'.
  488. */
  489. static int imx_request_port(struct uart_port *port)
  490. {
  491. struct imx_port *sport = (struct imx_port *)port;
  492. return request_mem_region(sport->port.mapbase, UART_PORT_SIZE,
  493. "imx-uart") != NULL ? 0 : -EBUSY;
  494. }
  495. /*
  496. * Configure/autoconfigure the port.
  497. */
  498. static void imx_config_port(struct uart_port *port, int flags)
  499. {
  500. struct imx_port *sport = (struct imx_port *)port;
  501. if (flags & UART_CONFIG_TYPE &&
  502. imx_request_port(&sport->port) == 0)
  503. sport->port.type = PORT_IMX;
  504. }
  505. /*
  506. * Verify the new serial_struct (for TIOCSSERIAL).
  507. * The only change we allow are to the flags and type, and
  508. * even then only between PORT_IMX and PORT_UNKNOWN
  509. */
  510. static int
  511. imx_verify_port(struct uart_port *port, struct serial_struct *ser)
  512. {
  513. struct imx_port *sport = (struct imx_port *)port;
  514. int ret = 0;
  515. if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
  516. ret = -EINVAL;
  517. if (sport->port.irq != ser->irq)
  518. ret = -EINVAL;
  519. if (ser->io_type != UPIO_MEM)
  520. ret = -EINVAL;
  521. if (sport->port.uartclk / 16 != ser->baud_base)
  522. ret = -EINVAL;
  523. if ((void *)sport->port.mapbase != ser->iomem_base)
  524. ret = -EINVAL;
  525. if (sport->port.iobase != ser->port)
  526. ret = -EINVAL;
  527. if (ser->hub6 != 0)
  528. ret = -EINVAL;
  529. return ret;
  530. }
  531. static struct uart_ops imx_pops = {
  532. .tx_empty = imx_tx_empty,
  533. .set_mctrl = imx_set_mctrl,
  534. .get_mctrl = imx_get_mctrl,
  535. .stop_tx = imx_stop_tx,
  536. .start_tx = imx_start_tx,
  537. .stop_rx = imx_stop_rx,
  538. .enable_ms = imx_enable_ms,
  539. .break_ctl = imx_break_ctl,
  540. .startup = imx_startup,
  541. .shutdown = imx_shutdown,
  542. .set_termios = imx_set_termios,
  543. .type = imx_type,
  544. .release_port = imx_release_port,
  545. .request_port = imx_request_port,
  546. .config_port = imx_config_port,
  547. .verify_port = imx_verify_port,
  548. };
  549. static struct imx_port imx_ports[] = {
  550. {
  551. .txirq = UART1_MINT_TX,
  552. .rxirq = UART1_MINT_RX,
  553. .rtsirq = UART1_MINT_RTS,
  554. .port = {
  555. .type = PORT_IMX,
  556. .iotype = UPIO_MEM,
  557. .membase = (void *)IMX_UART1_BASE,
  558. .mapbase = IMX_UART1_BASE, /* FIXME */
  559. .irq = UART1_MINT_RX,
  560. .uartclk = 16000000,
  561. .fifosize = 8,
  562. .flags = UPF_BOOT_AUTOCONF,
  563. .ops = &imx_pops,
  564. .line = 0,
  565. },
  566. }, {
  567. .txirq = UART2_MINT_TX,
  568. .rxirq = UART2_MINT_RX,
  569. .rtsirq = UART2_MINT_RTS,
  570. .port = {
  571. .type = PORT_IMX,
  572. .iotype = UPIO_MEM,
  573. .membase = (void *)IMX_UART2_BASE,
  574. .mapbase = IMX_UART2_BASE, /* FIXME */
  575. .irq = UART2_MINT_RX,
  576. .uartclk = 16000000,
  577. .fifosize = 8,
  578. .flags = UPF_BOOT_AUTOCONF,
  579. .ops = &imx_pops,
  580. .line = 1,
  581. },
  582. }
  583. };
  584. /*
  585. * Setup the IMX serial ports.
  586. * Note also that we support "console=ttySMXx" where "x" is either 0 or 1.
  587. * Which serial port this ends up being depends on the machine you're
  588. * running this kernel on. I'm not convinced that this is a good idea,
  589. * but that's the way it traditionally works.
  590. *
  591. */
  592. static void __init imx_init_ports(void)
  593. {
  594. static int first = 1;
  595. int i;
  596. if (!first)
  597. return;
  598. first = 0;
  599. for (i = 0; i < ARRAY_SIZE(imx_ports); i++) {
  600. init_timer(&imx_ports[i].timer);
  601. imx_ports[i].timer.function = imx_timeout;
  602. imx_ports[i].timer.data = (unsigned long)&imx_ports[i];
  603. }
  604. }
  605. #ifdef CONFIG_SERIAL_IMX_CONSOLE
  606. static void imx_console_putchar(struct uart_port *port, int ch)
  607. {
  608. struct imx_port *sport = (struct imx_port *)port;
  609. while ((UTS((u32)sport->port.membase) & UTS_TXFULL))
  610. barrier();
  611. URTX0((u32)sport->port.membase) = ch;
  612. }
  613. /*
  614. * Interrupts are disabled on entering
  615. */
  616. static void
  617. imx_console_write(struct console *co, const char *s, unsigned int count)
  618. {
  619. struct imx_port *sport = &imx_ports[co->index];
  620. unsigned int old_ucr1, old_ucr2;
  621. /*
  622. * First, save UCR1/2 and then disable interrupts
  623. */
  624. old_ucr1 = UCR1((u32)sport->port.membase);
  625. old_ucr2 = UCR2((u32)sport->port.membase);
  626. UCR1((u32)sport->port.membase) =
  627. (old_ucr1 | UCR1_UARTCLKEN | UCR1_UARTEN)
  628. & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
  629. UCR2((u32)sport->port.membase) = old_ucr2 | UCR2_TXEN;
  630. uart_console_write(&sport->port, s, count, imx_console_putchar);
  631. /*
  632. * Finally, wait for transmitter to become empty
  633. * and restore UCR1/2
  634. */
  635. while (!(USR2((u32)sport->port.membase) & USR2_TXDC));
  636. UCR1((u32)sport->port.membase) = old_ucr1;
  637. UCR2((u32)sport->port.membase) = old_ucr2;
  638. }
  639. /*
  640. * If the port was already initialised (eg, by a boot loader),
  641. * try to determine the current setup.
  642. */
  643. static void __init
  644. imx_console_get_options(struct imx_port *sport, int *baud,
  645. int *parity, int *bits)
  646. {
  647. if ( UCR1((u32)sport->port.membase) | UCR1_UARTEN ) {
  648. /* ok, the port was enabled */
  649. unsigned int ucr2, ubir,ubmr, uartclk;
  650. unsigned int baud_raw;
  651. unsigned int ucfr_rfdiv;
  652. ucr2 = UCR2((u32)sport->port.membase);
  653. *parity = 'n';
  654. if (ucr2 & UCR2_PREN) {
  655. if (ucr2 & UCR2_PROE)
  656. *parity = 'o';
  657. else
  658. *parity = 'e';
  659. }
  660. if (ucr2 & UCR2_WS)
  661. *bits = 8;
  662. else
  663. *bits = 7;
  664. ubir = UBIR((u32)sport->port.membase) & 0xffff;
  665. ubmr = UBMR((u32)sport->port.membase) & 0xffff;
  666. ucfr_rfdiv = (UFCR((u32)sport->port.membase) & UFCR_RFDIV) >> 7;
  667. if (ucfr_rfdiv == 6)
  668. ucfr_rfdiv = 7;
  669. else
  670. ucfr_rfdiv = 6 - ucfr_rfdiv;
  671. uartclk = imx_get_perclk1();
  672. uartclk /= ucfr_rfdiv;
  673. { /*
  674. * The next code provides exact computation of
  675. * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
  676. * without need of float support or long long division,
  677. * which would be required to prevent 32bit arithmetic overflow
  678. */
  679. unsigned int mul = ubir + 1;
  680. unsigned int div = 16 * (ubmr + 1);
  681. unsigned int rem = uartclk % div;
  682. baud_raw = (uartclk / div) * mul;
  683. baud_raw += (rem * mul + div / 2) / div;
  684. *baud = (baud_raw + 50) / 100 * 100;
  685. }
  686. if(*baud != baud_raw)
  687. printk(KERN_INFO "Serial: Console IMX rounded baud rate from %d to %d\n",
  688. baud_raw, *baud);
  689. }
  690. }
  691. static int __init
  692. imx_console_setup(struct console *co, char *options)
  693. {
  694. struct imx_port *sport;
  695. int baud = 9600;
  696. int bits = 8;
  697. int parity = 'n';
  698. int flow = 'n';
  699. /*
  700. * Check whether an invalid uart number has been specified, and
  701. * if so, search for the first available port that does have
  702. * console support.
  703. */
  704. if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
  705. co->index = 0;
  706. sport = &imx_ports[co->index];
  707. if (options)
  708. uart_parse_options(options, &baud, &parity, &bits, &flow);
  709. else
  710. imx_console_get_options(sport, &baud, &parity, &bits);
  711. imx_setup_ufcr(sport, 0);
  712. return uart_set_options(&sport->port, co, baud, parity, bits, flow);
  713. }
  714. static struct uart_driver imx_reg;
  715. static struct console imx_console = {
  716. .name = "ttySMX",
  717. .write = imx_console_write,
  718. .device = uart_console_device,
  719. .setup = imx_console_setup,
  720. .flags = CON_PRINTBUFFER,
  721. .index = -1,
  722. .data = &imx_reg,
  723. };
  724. static int __init imx_rs_console_init(void)
  725. {
  726. imx_init_ports();
  727. register_console(&imx_console);
  728. return 0;
  729. }
  730. console_initcall(imx_rs_console_init);
  731. #define IMX_CONSOLE &imx_console
  732. #else
  733. #define IMX_CONSOLE NULL
  734. #endif
  735. static struct uart_driver imx_reg = {
  736. .owner = THIS_MODULE,
  737. .driver_name = DRIVER_NAME,
  738. .dev_name = "ttySMX",
  739. .devfs_name = "ttsmx/",
  740. .major = SERIAL_IMX_MAJOR,
  741. .minor = MINOR_START,
  742. .nr = ARRAY_SIZE(imx_ports),
  743. .cons = IMX_CONSOLE,
  744. };
  745. static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
  746. {
  747. struct imx_port *sport = platform_get_drvdata(dev);
  748. if (sport)
  749. uart_suspend_port(&imx_reg, &sport->port);
  750. return 0;
  751. }
  752. static int serial_imx_resume(struct platform_device *dev)
  753. {
  754. struct imx_port *sport = platform_get_drvdata(dev);
  755. if (sport)
  756. uart_resume_port(&imx_reg, &sport->port);
  757. return 0;
  758. }
  759. static int serial_imx_probe(struct platform_device *dev)
  760. {
  761. struct imxuart_platform_data *pdata;
  762. imx_ports[dev->id].port.dev = &dev->dev;
  763. pdata = (struct imxuart_platform_data *)dev->dev.platform_data;
  764. if(pdata && (pdata->flags & IMXUART_HAVE_RTSCTS))
  765. imx_ports[dev->id].have_rtscts = 1;
  766. uart_add_one_port(&imx_reg, &imx_ports[dev->id].port);
  767. platform_set_drvdata(dev, &imx_ports[dev->id]);
  768. return 0;
  769. }
  770. static int serial_imx_remove(struct platform_device *dev)
  771. {
  772. struct imx_port *sport = platform_get_drvdata(dev);
  773. platform_set_drvdata(dev, NULL);
  774. if (sport)
  775. uart_remove_one_port(&imx_reg, &sport->port);
  776. return 0;
  777. }
  778. static struct platform_driver serial_imx_driver = {
  779. .probe = serial_imx_probe,
  780. .remove = serial_imx_remove,
  781. .suspend = serial_imx_suspend,
  782. .resume = serial_imx_resume,
  783. .driver = {
  784. .name = "imx-uart",
  785. },
  786. };
  787. static int __init imx_serial_init(void)
  788. {
  789. int ret;
  790. printk(KERN_INFO "Serial: IMX driver\n");
  791. imx_init_ports();
  792. ret = uart_register_driver(&imx_reg);
  793. if (ret)
  794. return ret;
  795. ret = platform_driver_register(&serial_imx_driver);
  796. if (ret != 0)
  797. uart_unregister_driver(&imx_reg);
  798. return 0;
  799. }
  800. static void __exit imx_serial_exit(void)
  801. {
  802. uart_unregister_driver(&imx_reg);
  803. platform_driver_unregister(&serial_imx_driver);
  804. }
  805. module_init(imx_serial_init);
  806. module_exit(imx_serial_exit);
  807. MODULE_AUTHOR("Sascha Hauer");
  808. MODULE_DESCRIPTION("IMX generic serial port driver");
  809. MODULE_LICENSE("GPL");