hardware.h 5.1 KB

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  1. /*
  2. * arch/arm/mach-pxa/include/mach/hardware.h
  3. *
  4. * Author: Nicolas Pitre
  5. * Created: Jun 15, 2001
  6. * Copyright: MontaVista Software Inc.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #ifndef __ASM_ARCH_HARDWARE_H
  13. #define __ASM_ARCH_HARDWARE_H
  14. /*
  15. * We requires absolute addresses.
  16. */
  17. #define PCIO_BASE 0
  18. /*
  19. * Workarounds for at least 2 errata so far require this.
  20. * The mapping is set in mach-pxa/generic.c.
  21. */
  22. #define UNCACHED_PHYS_0 0xff000000
  23. #define UNCACHED_ADDR UNCACHED_PHYS_0
  24. /*
  25. * Intel PXA2xx internal register mapping:
  26. *
  27. * 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff
  28. * 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff
  29. * 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff
  30. * 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff
  31. * 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff
  32. * 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff
  33. * 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff
  34. *
  35. * Note that not all PXA2xx chips implement all those addresses, and the
  36. * kernel only maps the minimum needed range of this mapping.
  37. */
  38. #define io_p2v(x) (0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1))
  39. #define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1))
  40. #ifndef __ASSEMBLY__
  41. # define __REG(x) (*((volatile u32 *)io_p2v(x)))
  42. /* With indexed regs we don't want to feed the index through io_p2v()
  43. especially if it is a variable, otherwise horrible code will result. */
  44. # define __REG2(x,y) \
  45. (*(volatile u32 *)((u32)&__REG(x) + (y)))
  46. # define __PREG(x) (io_v2p((u32)&(x)))
  47. #else
  48. # define __REG(x) io_p2v(x)
  49. # define __PREG(x) io_v2p(x)
  50. #endif
  51. #ifndef __ASSEMBLY__
  52. #ifdef CONFIG_PXA25x
  53. #define __cpu_is_pxa21x(id) \
  54. ({ \
  55. unsigned int _id = (id) >> 4 & 0xf3f; \
  56. _id == 0x212; \
  57. })
  58. #define __cpu_is_pxa255(id) \
  59. ({ \
  60. unsigned int _id = (id) >> 4 & 0xfff; \
  61. _id == 0x2d0; \
  62. })
  63. #define __cpu_is_pxa25x(id) \
  64. ({ \
  65. unsigned int _id = (id) >> 4 & 0xfff; \
  66. _id == 0x2d0 || _id == 0x290; \
  67. })
  68. #else
  69. #define __cpu_is_pxa21x(id) (0)
  70. #define __cpu_is_pxa255(id) (0)
  71. #define __cpu_is_pxa25x(id) (0)
  72. #endif
  73. #ifdef CONFIG_PXA27x
  74. #define __cpu_is_pxa27x(id) \
  75. ({ \
  76. unsigned int _id = (id) >> 4 & 0xfff; \
  77. _id == 0x411; \
  78. })
  79. #else
  80. #define __cpu_is_pxa27x(id) (0)
  81. #endif
  82. #ifdef CONFIG_CPU_PXA300
  83. #define __cpu_is_pxa300(id) \
  84. ({ \
  85. unsigned int _id = (id) >> 4 & 0xfff; \
  86. _id == 0x688; \
  87. })
  88. #else
  89. #define __cpu_is_pxa300(id) (0)
  90. #endif
  91. #ifdef CONFIG_CPU_PXA310
  92. #define __cpu_is_pxa310(id) \
  93. ({ \
  94. unsigned int _id = (id) >> 4 & 0xfff; \
  95. _id == 0x689; \
  96. })
  97. #else
  98. #define __cpu_is_pxa310(id) (0)
  99. #endif
  100. #ifdef CONFIG_CPU_PXA320
  101. #define __cpu_is_pxa320(id) \
  102. ({ \
  103. unsigned int _id = (id) >> 4 & 0xfff; \
  104. _id == 0x603 || _id == 0x682; \
  105. })
  106. #else
  107. #define __cpu_is_pxa320(id) (0)
  108. #endif
  109. #ifdef CONFIG_CPU_PXA930
  110. #define __cpu_is_pxa930(id) \
  111. ({ \
  112. unsigned int _id = (id) >> 4 & 0xfff; \
  113. _id == 0x683; \
  114. })
  115. #else
  116. #define __cpu_is_pxa930(id) (0)
  117. #endif
  118. #define cpu_is_pxa21x() \
  119. ({ \
  120. __cpu_is_pxa21x(read_cpuid_id()); \
  121. })
  122. #define cpu_is_pxa255() \
  123. ({ \
  124. __cpu_is_pxa255(read_cpuid_id()); \
  125. })
  126. #define cpu_is_pxa25x() \
  127. ({ \
  128. __cpu_is_pxa25x(read_cpuid_id()); \
  129. })
  130. #define cpu_is_pxa27x() \
  131. ({ \
  132. __cpu_is_pxa27x(read_cpuid_id()); \
  133. })
  134. #define cpu_is_pxa300() \
  135. ({ \
  136. __cpu_is_pxa300(read_cpuid_id()); \
  137. })
  138. #define cpu_is_pxa310() \
  139. ({ \
  140. __cpu_is_pxa310(read_cpuid_id()); \
  141. })
  142. #define cpu_is_pxa320() \
  143. ({ \
  144. __cpu_is_pxa320(read_cpuid_id()); \
  145. })
  146. #define cpu_is_pxa930() \
  147. ({ \
  148. unsigned int id = read_cpuid(CPUID_ID); \
  149. __cpu_is_pxa930(id); \
  150. })
  151. /*
  152. * CPUID Core Generation Bit
  153. * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x
  154. * == 0x3 for pxa300/pxa310/pxa320
  155. */
  156. #define __cpu_is_pxa2xx(id) \
  157. ({ \
  158. unsigned int _id = (id) >> 13 & 0x7; \
  159. _id <= 0x2; \
  160. })
  161. #define __cpu_is_pxa3xx(id) \
  162. ({ \
  163. unsigned int _id = (id) >> 13 & 0x7; \
  164. _id == 0x3; \
  165. })
  166. #define cpu_is_pxa2xx() \
  167. ({ \
  168. __cpu_is_pxa2xx(read_cpuid_id()); \
  169. })
  170. #define cpu_is_pxa3xx() \
  171. ({ \
  172. __cpu_is_pxa3xx(read_cpuid_id()); \
  173. })
  174. /*
  175. * Handy routine to set GPIO alternate functions
  176. */
  177. extern int pxa_gpio_mode( int gpio_mode );
  178. /*
  179. * Return GPIO level, nonzero means high, zero is low
  180. */
  181. extern int pxa_gpio_get_value(unsigned gpio);
  182. /*
  183. * Set output GPIO level
  184. */
  185. extern void pxa_gpio_set_value(unsigned gpio, int value);
  186. /*
  187. * return current memory and LCD clock frequency in units of 10kHz
  188. */
  189. extern unsigned int get_memclk_frequency_10khz(void);
  190. #endif
  191. #if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
  192. #define PCIBIOS_MIN_IO 0
  193. #define PCIBIOS_MIN_MEM 0
  194. #define pcibios_assign_all_busses() 1
  195. #endif
  196. #endif /* _ASM_ARCH_HARDWARE_H */