dm.c 21 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2009-2010 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * wlanfae <wlanfae@realtek.com>
  23. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24. * Hsinchu 300, Taiwan.
  25. *
  26. * Larry Finger <Larry.Finger@lwfinger.net>
  27. *
  28. *****************************************************************************/
  29. #include "../wifi.h"
  30. #include "../base.h"
  31. #include "reg.h"
  32. #include "def.h"
  33. #include "phy.h"
  34. #include "dm.h"
  35. #include "fw.h"
  36. struct dig_t digtable;
  37. static const u32 edca_setting_dl[PEER_MAX] = {
  38. 0xa44f, /* 0 UNKNOWN */
  39. 0x5ea44f, /* 1 REALTEK_90 */
  40. 0x5ea44f, /* 2 REALTEK_92SE */
  41. 0xa630, /* 3 BROAD */
  42. 0xa44f, /* 4 RAL */
  43. 0xa630, /* 5 ATH */
  44. 0xa630, /* 6 CISCO */
  45. 0xa42b, /* 7 MARV */
  46. };
  47. static const u32 edca_setting_dl_gmode[PEER_MAX] = {
  48. 0x4322, /* 0 UNKNOWN */
  49. 0xa44f, /* 1 REALTEK_90 */
  50. 0x5ea44f, /* 2 REALTEK_92SE */
  51. 0xa42b, /* 3 BROAD */
  52. 0x5e4322, /* 4 RAL */
  53. 0x4322, /* 5 ATH */
  54. 0xa430, /* 6 CISCO */
  55. 0x5ea44f, /* 7 MARV */
  56. };
  57. static const u32 edca_setting_ul[PEER_MAX] = {
  58. 0x5e4322, /* 0 UNKNOWN */
  59. 0xa44f, /* 1 REALTEK_90 */
  60. 0x5ea44f, /* 2 REALTEK_92SE */
  61. 0x5ea322, /* 3 BROAD */
  62. 0x5ea422, /* 4 RAL */
  63. 0x5ea322, /* 5 ATH */
  64. 0x3ea44f, /* 6 CISCO */
  65. 0x5ea44f, /* 7 MARV */
  66. };
  67. static void _rtl92s_dm_check_edca_turbo(struct ieee80211_hw *hw)
  68. {
  69. struct rtl_priv *rtlpriv = rtl_priv(hw);
  70. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  71. static u64 last_txok_cnt;
  72. static u64 last_rxok_cnt;
  73. u64 cur_txok_cnt = 0;
  74. u64 cur_rxok_cnt = 0;
  75. u32 edca_be_ul = edca_setting_ul[mac->vendor];
  76. u32 edca_be_dl = edca_setting_dl[mac->vendor];
  77. u32 edca_gmode = edca_setting_dl_gmode[mac->vendor];
  78. if (mac->link_state != MAC80211_LINKED) {
  79. rtlpriv->dm.current_turbo_edca = false;
  80. goto dm_checkedcaturbo_exit;
  81. }
  82. if ((!rtlpriv->dm.is_any_nonbepkts) &&
  83. (!rtlpriv->dm.disable_framebursting)) {
  84. cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
  85. cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
  86. if (rtlpriv->phy.rf_type == RF_1T2R) {
  87. if (cur_txok_cnt > 4 * cur_rxok_cnt) {
  88. /* Uplink TP is present. */
  89. if (rtlpriv->dm.is_cur_rdlstate ||
  90. !rtlpriv->dm.current_turbo_edca) {
  91. rtl_write_dword(rtlpriv, EDCAPARA_BE,
  92. edca_be_ul);
  93. rtlpriv->dm.is_cur_rdlstate = false;
  94. }
  95. } else {/* Balance TP is present. */
  96. if (!rtlpriv->dm.is_cur_rdlstate ||
  97. !rtlpriv->dm.current_turbo_edca) {
  98. if (mac->mode == WIRELESS_MODE_G ||
  99. mac->mode == WIRELESS_MODE_B)
  100. rtl_write_dword(rtlpriv,
  101. EDCAPARA_BE,
  102. edca_gmode);
  103. else
  104. rtl_write_dword(rtlpriv,
  105. EDCAPARA_BE,
  106. edca_be_dl);
  107. rtlpriv->dm.is_cur_rdlstate = true;
  108. }
  109. }
  110. rtlpriv->dm.current_turbo_edca = true;
  111. } else {
  112. if (cur_rxok_cnt > 4 * cur_txok_cnt) {
  113. if (!rtlpriv->dm.is_cur_rdlstate ||
  114. !rtlpriv->dm.current_turbo_edca) {
  115. if (mac->mode == WIRELESS_MODE_G ||
  116. mac->mode == WIRELESS_MODE_B)
  117. rtl_write_dword(rtlpriv,
  118. EDCAPARA_BE,
  119. edca_gmode);
  120. else
  121. rtl_write_dword(rtlpriv,
  122. EDCAPARA_BE,
  123. edca_be_dl);
  124. rtlpriv->dm.is_cur_rdlstate = true;
  125. }
  126. } else {
  127. if (rtlpriv->dm.is_cur_rdlstate ||
  128. !rtlpriv->dm.current_turbo_edca) {
  129. rtl_write_dword(rtlpriv, EDCAPARA_BE,
  130. edca_be_ul);
  131. rtlpriv->dm.is_cur_rdlstate = false;
  132. }
  133. }
  134. rtlpriv->dm.current_turbo_edca = true;
  135. }
  136. } else {
  137. if (rtlpriv->dm.current_turbo_edca) {
  138. u8 tmp = AC0_BE;
  139. rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
  140. (u8 *)(&tmp));
  141. rtlpriv->dm.current_turbo_edca = false;
  142. }
  143. }
  144. dm_checkedcaturbo_exit:
  145. rtlpriv->dm.is_any_nonbepkts = false;
  146. last_txok_cnt = rtlpriv->stats.txbytesunicast;
  147. last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
  148. }
  149. static void _rtl92s_dm_txpowertracking_callback_thermalmeter(
  150. struct ieee80211_hw *hw)
  151. {
  152. struct rtl_priv *rtlpriv = rtl_priv(hw);
  153. struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  154. u8 thermalvalue = 0;
  155. rtlpriv->dm.txpower_trackinginit = true;
  156. thermalvalue = (u8)rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 0x1f);
  157. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  158. ("Readback Thermal Meter = 0x%x pre thermal meter 0x%x "
  159. "eeprom_thermalmeter 0x%x\n", thermalvalue,
  160. rtlpriv->dm.thermalvalue, rtlefuse->eeprom_thermalmeter));
  161. if (thermalvalue) {
  162. rtlpriv->dm.thermalvalue = thermalvalue;
  163. rtl92s_phy_set_fw_cmd(hw, FW_CMD_TXPWR_TRACK_THERMAL);
  164. }
  165. rtlpriv->dm.txpowercount = 0;
  166. }
  167. static void _rtl92s_dm_check_txpowertracking_thermalmeter(
  168. struct ieee80211_hw *hw)
  169. {
  170. struct rtl_priv *rtlpriv = rtl_priv(hw);
  171. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  172. static u8 tm_trigger;
  173. u8 tx_power_checkcnt = 5;
  174. /* 2T2R TP issue */
  175. if (rtlphy->rf_type == RF_2T2R)
  176. return;
  177. if (!rtlpriv->dm.txpower_tracking)
  178. return;
  179. if (rtlpriv->dm.txpowercount <= tx_power_checkcnt) {
  180. rtlpriv->dm.txpowercount++;
  181. return;
  182. }
  183. if (!tm_trigger) {
  184. rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER,
  185. RFREG_OFFSET_MASK, 0x60);
  186. tm_trigger = 1;
  187. } else {
  188. _rtl92s_dm_txpowertracking_callback_thermalmeter(hw);
  189. tm_trigger = 0;
  190. }
  191. }
  192. static void _rtl92s_dm_refresh_rateadaptive_mask(struct ieee80211_hw *hw)
  193. {
  194. struct rtl_priv *rtlpriv = rtl_priv(hw);
  195. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  196. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  197. struct rate_adaptive *ra = &(rtlpriv->ra);
  198. u32 low_rssi_thresh = 0;
  199. u32 middle_rssi_thresh = 0;
  200. u32 high_rssi_thresh = 0;
  201. u8 rssi_level;
  202. struct ieee80211_sta *sta = NULL;
  203. if (is_hal_stop(rtlhal))
  204. return;
  205. if (!rtlpriv->dm.useramask)
  206. return;
  207. if (!rtlpriv->dm.inform_fw_driverctrldm) {
  208. rtl92s_phy_set_fw_cmd(hw, FW_CMD_CTRL_DM_BY_DRIVER);
  209. rtlpriv->dm.inform_fw_driverctrldm = true;
  210. }
  211. rcu_read_lock();
  212. if (mac->opmode == NL80211_IFTYPE_STATION)
  213. sta = get_sta(hw, mac->vif, mac->bssid);
  214. if ((mac->link_state == MAC80211_LINKED) &&
  215. (mac->opmode == NL80211_IFTYPE_STATION)) {
  216. switch (ra->pre_ratr_state) {
  217. case DM_RATR_STA_HIGH:
  218. high_rssi_thresh = 40;
  219. middle_rssi_thresh = 30;
  220. low_rssi_thresh = 20;
  221. break;
  222. case DM_RATR_STA_MIDDLE:
  223. high_rssi_thresh = 44;
  224. middle_rssi_thresh = 30;
  225. low_rssi_thresh = 20;
  226. break;
  227. case DM_RATR_STA_LOW:
  228. high_rssi_thresh = 44;
  229. middle_rssi_thresh = 34;
  230. low_rssi_thresh = 20;
  231. break;
  232. case DM_RATR_STA_ULTRALOW:
  233. high_rssi_thresh = 44;
  234. middle_rssi_thresh = 34;
  235. low_rssi_thresh = 24;
  236. break;
  237. default:
  238. high_rssi_thresh = 44;
  239. middle_rssi_thresh = 34;
  240. low_rssi_thresh = 24;
  241. break;
  242. }
  243. if (rtlpriv->dm.undecorated_smoothed_pwdb >
  244. (long)high_rssi_thresh) {
  245. ra->ratr_state = DM_RATR_STA_HIGH;
  246. rssi_level = 1;
  247. } else if (rtlpriv->dm.undecorated_smoothed_pwdb >
  248. (long)middle_rssi_thresh) {
  249. ra->ratr_state = DM_RATR_STA_LOW;
  250. rssi_level = 3;
  251. } else if (rtlpriv->dm.undecorated_smoothed_pwdb >
  252. (long)low_rssi_thresh) {
  253. ra->ratr_state = DM_RATR_STA_LOW;
  254. rssi_level = 5;
  255. } else {
  256. ra->ratr_state = DM_RATR_STA_ULTRALOW;
  257. rssi_level = 6;
  258. }
  259. if (ra->pre_ratr_state != ra->ratr_state) {
  260. RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD, ("RSSI = %ld "
  261. "RSSI_LEVEL = %d PreState = %d, CurState = %d\n",
  262. rtlpriv->dm.undecorated_smoothed_pwdb,
  263. ra->ratr_state,
  264. ra->pre_ratr_state, ra->ratr_state));
  265. rtlpriv->cfg->ops->update_rate_tbl(hw, sta,
  266. ra->ratr_state);
  267. ra->pre_ratr_state = ra->ratr_state;
  268. }
  269. }
  270. rcu_read_unlock();
  271. }
  272. static void _rtl92s_dm_switch_baseband_mrc(struct ieee80211_hw *hw)
  273. {
  274. struct rtl_priv *rtlpriv = rtl_priv(hw);
  275. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  276. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  277. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  278. bool current_mrc;
  279. bool enable_mrc = true;
  280. long tmpentry_maxpwdb = 0;
  281. u8 rssi_a = 0;
  282. u8 rssi_b = 0;
  283. if (is_hal_stop(rtlhal))
  284. return;
  285. if ((rtlphy->rf_type == RF_1T1R) || (rtlphy->rf_type == RF_2T2R))
  286. return;
  287. rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_MRC, (u8 *)(&current_mrc));
  288. if (mac->link_state >= MAC80211_LINKED) {
  289. if (rtlpriv->dm.undecorated_smoothed_pwdb > tmpentry_maxpwdb) {
  290. rssi_a = rtlpriv->stats.rx_rssi_percentage[RF90_PATH_A];
  291. rssi_b = rtlpriv->stats.rx_rssi_percentage[RF90_PATH_B];
  292. }
  293. }
  294. /* MRC settings would NOT affect TP on Wireless B mode. */
  295. if (mac->mode != WIRELESS_MODE_B) {
  296. if ((rssi_a == 0) && (rssi_b == 0)) {
  297. enable_mrc = true;
  298. } else if (rssi_b > 30) {
  299. /* Turn on B-Path */
  300. enable_mrc = true;
  301. } else if (rssi_b < 5) {
  302. /* Turn off B-path */
  303. enable_mrc = false;
  304. /* Take care of RSSI differentiation. */
  305. } else if (rssi_a > 15 && (rssi_a >= rssi_b)) {
  306. if ((rssi_a - rssi_b) > 15)
  307. /* Turn off B-path */
  308. enable_mrc = false;
  309. else if ((rssi_a - rssi_b) < 10)
  310. /* Turn on B-Path */
  311. enable_mrc = true;
  312. else
  313. enable_mrc = current_mrc;
  314. } else {
  315. /* Turn on B-Path */
  316. enable_mrc = true;
  317. }
  318. }
  319. /* Update MRC settings if needed. */
  320. if (enable_mrc != current_mrc)
  321. rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MRC,
  322. (u8 *)&enable_mrc);
  323. }
  324. void rtl92s_dm_init_edca_turbo(struct ieee80211_hw *hw)
  325. {
  326. struct rtl_priv *rtlpriv = rtl_priv(hw);
  327. rtlpriv->dm.current_turbo_edca = false;
  328. rtlpriv->dm.is_any_nonbepkts = false;
  329. rtlpriv->dm.is_cur_rdlstate = false;
  330. }
  331. static void _rtl92s_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
  332. {
  333. struct rtl_priv *rtlpriv = rtl_priv(hw);
  334. struct rate_adaptive *ra = &(rtlpriv->ra);
  335. ra->ratr_state = DM_RATR_STA_MAX;
  336. ra->pre_ratr_state = DM_RATR_STA_MAX;
  337. if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
  338. rtlpriv->dm.useramask = true;
  339. else
  340. rtlpriv->dm.useramask = false;
  341. rtlpriv->dm.useramask = false;
  342. rtlpriv->dm.inform_fw_driverctrldm = false;
  343. }
  344. static void _rtl92s_dm_init_txpowertracking_thermalmeter(
  345. struct ieee80211_hw *hw)
  346. {
  347. struct rtl_priv *rtlpriv = rtl_priv(hw);
  348. rtlpriv->dm.txpower_tracking = true;
  349. rtlpriv->dm.txpowercount = 0;
  350. rtlpriv->dm.txpower_trackinginit = false;
  351. }
  352. static void _rtl92s_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
  353. {
  354. struct rtl_priv *rtlpriv = rtl_priv(hw);
  355. struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
  356. u32 ret_value;
  357. ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD);
  358. falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
  359. ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD);
  360. falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
  361. falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
  362. ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD);
  363. falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
  364. falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
  365. falsealm_cnt->cnt_rate_illegal + falsealm_cnt->cnt_crc8_fail +
  366. falsealm_cnt->cnt_mcs_fail;
  367. /* read CCK false alarm */
  368. ret_value = rtl_get_bbreg(hw, 0xc64, MASKDWORD);
  369. falsealm_cnt->cnt_cck_fail = (ret_value & 0xffff);
  370. falsealm_cnt->cnt_all = falsealm_cnt->cnt_ofdm_fail +
  371. falsealm_cnt->cnt_cck_fail;
  372. }
  373. static void rtl92s_backoff_enable_flag(struct ieee80211_hw *hw)
  374. {
  375. struct rtl_priv *rtlpriv = rtl_priv(hw);
  376. struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
  377. if (falsealm_cnt->cnt_all > digtable.fa_highthresh) {
  378. if ((digtable.backoff_val - 6) <
  379. digtable.backoffval_range_min)
  380. digtable.backoff_val = digtable.backoffval_range_min;
  381. else
  382. digtable.backoff_val -= 6;
  383. } else if (falsealm_cnt->cnt_all < digtable.fa_lowthresh) {
  384. if ((digtable.backoff_val + 6) >
  385. digtable.backoffval_range_max)
  386. digtable.backoff_val =
  387. digtable.backoffval_range_max;
  388. else
  389. digtable.backoff_val += 6;
  390. }
  391. }
  392. static void _rtl92s_dm_initial_gain_sta_beforeconnect(struct ieee80211_hw *hw)
  393. {
  394. struct rtl_priv *rtlpriv = rtl_priv(hw);
  395. struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
  396. static u8 initialized, force_write;
  397. u8 initial_gain = 0;
  398. if ((digtable.pre_sta_connectstate == digtable.cur_sta_connectstate) ||
  399. (digtable.cur_sta_connectstate == DIG_STA_BEFORE_CONNECT)) {
  400. if (digtable.cur_sta_connectstate == DIG_STA_BEFORE_CONNECT) {
  401. if (rtlpriv->psc.rfpwr_state != ERFON)
  402. return;
  403. if (digtable.backoff_enable_flag == true)
  404. rtl92s_backoff_enable_flag(hw);
  405. else
  406. digtable.backoff_val = DM_DIG_BACKOFF;
  407. if ((digtable.rssi_val + 10 - digtable.backoff_val) >
  408. digtable.rx_gain_range_max)
  409. digtable.cur_igvalue =
  410. digtable.rx_gain_range_max;
  411. else if ((digtable.rssi_val + 10 - digtable.backoff_val)
  412. < digtable.rx_gain_range_min)
  413. digtable.cur_igvalue =
  414. digtable.rx_gain_range_min;
  415. else
  416. digtable.cur_igvalue = digtable.rssi_val + 10 -
  417. digtable.backoff_val;
  418. if (falsealm_cnt->cnt_all > 10000)
  419. digtable.cur_igvalue =
  420. (digtable.cur_igvalue > 0x33) ?
  421. digtable.cur_igvalue : 0x33;
  422. if (falsealm_cnt->cnt_all > 16000)
  423. digtable.cur_igvalue =
  424. digtable.rx_gain_range_max;
  425. /* connected -> connected or disconnected -> disconnected */
  426. } else {
  427. /* Firmware control DIG, do nothing in driver dm */
  428. return;
  429. }
  430. /* disconnected -> connected or connected ->
  431. * disconnected or beforeconnect->(dis)connected */
  432. } else {
  433. /* Enable FW DIG */
  434. digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
  435. rtl92s_phy_set_fw_cmd(hw, FW_CMD_DIG_ENABLE);
  436. digtable.backoff_val = DM_DIG_BACKOFF;
  437. digtable.cur_igvalue = rtlpriv->phy.default_initialgain[0];
  438. digtable.pre_igvalue = 0;
  439. return;
  440. }
  441. /* Forced writing to prevent from fw-dig overwriting. */
  442. if (digtable.pre_igvalue != rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1,
  443. MASKBYTE0))
  444. force_write = 1;
  445. if ((digtable.pre_igvalue != digtable.cur_igvalue) ||
  446. !initialized || force_write) {
  447. /* Disable FW DIG */
  448. rtl92s_phy_set_fw_cmd(hw, FW_CMD_DIG_DISABLE);
  449. initial_gain = (u8)digtable.cur_igvalue;
  450. /* Set initial gain. */
  451. rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, initial_gain);
  452. rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, initial_gain);
  453. digtable.pre_igvalue = digtable.cur_igvalue;
  454. initialized = 1;
  455. force_write = 0;
  456. }
  457. }
  458. static void _rtl92s_dm_ctrl_initgain_bytwoport(struct ieee80211_hw *hw)
  459. {
  460. struct rtl_priv *rtlpriv = rtl_priv(hw);
  461. if (rtlpriv->mac80211.act_scanning)
  462. return;
  463. /* Decide the current status and if modify initial gain or not */
  464. if (rtlpriv->mac80211.link_state >= MAC80211_LINKED ||
  465. rtlpriv->mac80211.opmode == NL80211_IFTYPE_ADHOC)
  466. digtable.cur_sta_connectstate = DIG_STA_CONNECT;
  467. else
  468. digtable.cur_sta_connectstate = DIG_STA_DISCONNECT;
  469. digtable.rssi_val = rtlpriv->dm.undecorated_smoothed_pwdb;
  470. /* Change dig mode to rssi */
  471. if (digtable.cur_sta_connectstate != DIG_STA_DISCONNECT) {
  472. if (digtable.dig_twoport_algorithm ==
  473. DIG_TWO_PORT_ALGO_FALSE_ALARM) {
  474. digtable.dig_twoport_algorithm = DIG_TWO_PORT_ALGO_RSSI;
  475. rtl92s_phy_set_fw_cmd(hw, FW_CMD_DIG_MODE_SS);
  476. }
  477. }
  478. _rtl92s_dm_false_alarm_counter_statistics(hw);
  479. _rtl92s_dm_initial_gain_sta_beforeconnect(hw);
  480. digtable.pre_sta_connectstate = digtable.cur_sta_connectstate;
  481. }
  482. static void _rtl92s_dm_ctrl_initgain_byrssi(struct ieee80211_hw *hw)
  483. {
  484. struct rtl_priv *rtlpriv = rtl_priv(hw);
  485. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  486. /* 2T2R TP issue */
  487. if (rtlphy->rf_type == RF_2T2R)
  488. return;
  489. if (!rtlpriv->dm.dm_initialgain_enable)
  490. return;
  491. if (digtable.dig_enable_flag == false)
  492. return;
  493. _rtl92s_dm_ctrl_initgain_bytwoport(hw);
  494. }
  495. static void _rtl92s_dm_dynamic_txpower(struct ieee80211_hw *hw)
  496. {
  497. struct rtl_priv *rtlpriv = rtl_priv(hw);
  498. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  499. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  500. long undecorated_smoothed_pwdb;
  501. long txpwr_threshold_lv1, txpwr_threshold_lv2;
  502. /* 2T2R TP issue */
  503. if (rtlphy->rf_type == RF_2T2R)
  504. return;
  505. if (!rtlpriv->dm.dynamic_txpower_enable ||
  506. rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) {
  507. rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL;
  508. return;
  509. }
  510. if ((mac->link_state < MAC80211_LINKED) &&
  511. (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb == 0)) {
  512. RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
  513. ("Not connected to any\n"));
  514. rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL;
  515. rtlpriv->dm.last_dtp_lvl = TX_HIGHPWR_LEVEL_NORMAL;
  516. return;
  517. }
  518. if (mac->link_state >= MAC80211_LINKED) {
  519. if (mac->opmode == NL80211_IFTYPE_ADHOC) {
  520. undecorated_smoothed_pwdb =
  521. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  522. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  523. ("AP Client PWDB = 0x%lx\n",
  524. undecorated_smoothed_pwdb));
  525. } else {
  526. undecorated_smoothed_pwdb =
  527. rtlpriv->dm.undecorated_smoothed_pwdb;
  528. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  529. ("STA Default Port PWDB = 0x%lx\n",
  530. undecorated_smoothed_pwdb));
  531. }
  532. } else {
  533. undecorated_smoothed_pwdb =
  534. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  535. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  536. ("AP Ext Port PWDB = 0x%lx\n",
  537. undecorated_smoothed_pwdb));
  538. }
  539. txpwr_threshold_lv2 = TX_POWER_NEAR_FIELD_THRESH_LVL2;
  540. txpwr_threshold_lv1 = TX_POWER_NEAR_FIELD_THRESH_LVL1;
  541. if (rtl_get_bbreg(hw, 0xc90, MASKBYTE0) == 1)
  542. rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL;
  543. else if (undecorated_smoothed_pwdb >= txpwr_threshold_lv2)
  544. rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL2;
  545. else if ((undecorated_smoothed_pwdb < (txpwr_threshold_lv2 - 3)) &&
  546. (undecorated_smoothed_pwdb >= txpwr_threshold_lv1))
  547. rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL1;
  548. else if (undecorated_smoothed_pwdb < (txpwr_threshold_lv1 - 3))
  549. rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL;
  550. if ((rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl))
  551. rtl92s_phy_set_txpower(hw, rtlphy->current_channel);
  552. rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl;
  553. }
  554. static void _rtl92s_dm_init_dig(struct ieee80211_hw *hw)
  555. {
  556. struct rtl_priv *rtlpriv = rtl_priv(hw);
  557. /* Disable DIG scheme now.*/
  558. digtable.dig_enable_flag = true;
  559. digtable.backoff_enable_flag = true;
  560. if ((rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER) &&
  561. (hal_get_firmwareversion(rtlpriv) >= 0x3c))
  562. digtable.dig_algorithm = DIG_ALGO_BY_TOW_PORT;
  563. else
  564. digtable.dig_algorithm =
  565. DIG_ALGO_BEFORE_CONNECT_BY_RSSI_AND_ALARM;
  566. digtable.dig_twoport_algorithm = DIG_TWO_PORT_ALGO_RSSI;
  567. digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
  568. /* off=by real rssi value, on=by digtable.rssi_val for new dig */
  569. digtable.dig_dbgmode = DM_DBG_OFF;
  570. digtable.dig_slgorithm_switch = 0;
  571. /* 2007/10/04 MH Define init gain threshol. */
  572. digtable.dig_state = DM_STA_DIG_MAX;
  573. digtable.dig_highpwrstate = DM_STA_DIG_MAX;
  574. digtable.cur_sta_connectstate = DIG_STA_DISCONNECT;
  575. digtable.pre_sta_connectstate = DIG_STA_DISCONNECT;
  576. digtable.cur_ap_connectstate = DIG_AP_DISCONNECT;
  577. digtable.pre_ap_connectstate = DIG_AP_DISCONNECT;
  578. digtable.rssi_lowthresh = DM_DIG_THRESH_LOW;
  579. digtable.rssi_highthresh = DM_DIG_THRESH_HIGH;
  580. digtable.fa_lowthresh = DM_FALSEALARM_THRESH_LOW;
  581. digtable.fa_highthresh = DM_FALSEALARM_THRESH_HIGH;
  582. digtable.rssi_highpower_lowthresh = DM_DIG_HIGH_PWR_THRESH_LOW;
  583. digtable.rssi_highpower_highthresh = DM_DIG_HIGH_PWR_THRESH_HIGH;
  584. /* for dig debug rssi value */
  585. digtable.rssi_val = 50;
  586. digtable.backoff_val = DM_DIG_BACKOFF;
  587. digtable.rx_gain_range_max = DM_DIG_MAX;
  588. digtable.rx_gain_range_min = DM_DIG_MIN;
  589. digtable.backoffval_range_max = DM_DIG_BACKOFF_MAX;
  590. digtable.backoffval_range_min = DM_DIG_BACKOFF_MIN;
  591. }
  592. static void _rtl92s_dm_init_dynamic_txpower(struct ieee80211_hw *hw)
  593. {
  594. struct rtl_priv *rtlpriv = rtl_priv(hw);
  595. if ((hal_get_firmwareversion(rtlpriv) >= 60) &&
  596. (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER))
  597. rtlpriv->dm.dynamic_txpower_enable = true;
  598. else
  599. rtlpriv->dm.dynamic_txpower_enable = false;
  600. rtlpriv->dm.last_dtp_lvl = TX_HIGHPWR_LEVEL_NORMAL;
  601. rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL;
  602. }
  603. void rtl92s_dm_init(struct ieee80211_hw *hw)
  604. {
  605. struct rtl_priv *rtlpriv = rtl_priv(hw);
  606. rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
  607. rtlpriv->dm.undecorated_smoothed_pwdb = -1;
  608. _rtl92s_dm_init_dynamic_txpower(hw);
  609. rtl92s_dm_init_edca_turbo(hw);
  610. _rtl92s_dm_init_rate_adaptive_mask(hw);
  611. _rtl92s_dm_init_txpowertracking_thermalmeter(hw);
  612. _rtl92s_dm_init_dig(hw);
  613. rtl_write_dword(rtlpriv, WFM5, FW_CCA_CHK_ENABLE);
  614. }
  615. void rtl92s_dm_watchdog(struct ieee80211_hw *hw)
  616. {
  617. _rtl92s_dm_check_edca_turbo(hw);
  618. _rtl92s_dm_check_txpowertracking_thermalmeter(hw);
  619. _rtl92s_dm_ctrl_initgain_byrssi(hw);
  620. _rtl92s_dm_dynamic_txpower(hw);
  621. _rtl92s_dm_refresh_rateadaptive_mask(hw);
  622. _rtl92s_dm_switch_baseband_mrc(hw);
  623. }