iwl-core.c 55 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033
  1. /******************************************************************************
  2. *
  3. * GPL LICENSE SUMMARY
  4. *
  5. * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of version 2 of the GNU General Public License as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14. * General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  19. * USA
  20. *
  21. * The full GNU General Public License is included in this distribution
  22. * in the file called LICENSE.GPL.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *****************************************************************************/
  28. #include <linux/kernel.h>
  29. #include <linux/module.h>
  30. #include <linux/etherdevice.h>
  31. #include <linux/sched.h>
  32. #include <linux/slab.h>
  33. #include <net/mac80211.h>
  34. #include "iwl-eeprom.h"
  35. #include "iwl-dev.h" /* FIXME: remove */
  36. #include "iwl-debug.h"
  37. #include "iwl-core.h"
  38. #include "iwl-io.h"
  39. #include "iwl-power.h"
  40. #include "iwl-sta.h"
  41. #include "iwl-helpers.h"
  42. #include "iwl-agn.h"
  43. /*
  44. * set bt_coex_active to true, uCode will do kill/defer
  45. * every time the priority line is asserted (BT is sending signals on the
  46. * priority line in the PCIx).
  47. * set bt_coex_active to false, uCode will ignore the BT activity and
  48. * perform the normal operation
  49. *
  50. * User might experience transmit issue on some platform due to WiFi/BT
  51. * co-exist problem. The possible behaviors are:
  52. * Able to scan and finding all the available AP
  53. * Not able to associate with any AP
  54. * On those platforms, WiFi communication can be restored by set
  55. * "bt_coex_active" module parameter to "false"
  56. *
  57. * default: bt_coex_active = true (BT_COEX_ENABLE)
  58. */
  59. bool bt_coex_active = true;
  60. module_param(bt_coex_active, bool, S_IRUGO);
  61. MODULE_PARM_DESC(bt_coex_active, "enable wifi/bluetooth co-exist");
  62. u32 iwl_debug_level;
  63. const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
  64. #define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
  65. #define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
  66. static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
  67. struct ieee80211_sta_ht_cap *ht_info,
  68. enum ieee80211_band band)
  69. {
  70. u16 max_bit_rate = 0;
  71. u8 rx_chains_num = priv->hw_params.rx_chains_num;
  72. u8 tx_chains_num = priv->hw_params.tx_chains_num;
  73. ht_info->cap = 0;
  74. memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
  75. ht_info->ht_supported = true;
  76. if (priv->cfg->ht_params &&
  77. priv->cfg->ht_params->ht_greenfield_support)
  78. ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD;
  79. ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
  80. max_bit_rate = MAX_BIT_RATE_20_MHZ;
  81. if (priv->hw_params.ht40_channel & BIT(band)) {
  82. ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
  83. ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
  84. ht_info->mcs.rx_mask[4] = 0x01;
  85. max_bit_rate = MAX_BIT_RATE_40_MHZ;
  86. }
  87. if (iwlagn_mod_params.amsdu_size_8K)
  88. ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
  89. ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
  90. if (priv->cfg->bt_params && priv->cfg->bt_params->ampdu_factor)
  91. ht_info->ampdu_factor = priv->cfg->bt_params->ampdu_factor;
  92. ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
  93. if (priv->cfg->bt_params && priv->cfg->bt_params->ampdu_density)
  94. ht_info->ampdu_density = priv->cfg->bt_params->ampdu_density;
  95. ht_info->mcs.rx_mask[0] = 0xFF;
  96. if (rx_chains_num >= 2)
  97. ht_info->mcs.rx_mask[1] = 0xFF;
  98. if (rx_chains_num >= 3)
  99. ht_info->mcs.rx_mask[2] = 0xFF;
  100. /* Highest supported Rx data rate */
  101. max_bit_rate *= rx_chains_num;
  102. WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
  103. ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
  104. /* Tx MCS capabilities */
  105. ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
  106. if (tx_chains_num != rx_chains_num) {
  107. ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
  108. ht_info->mcs.tx_params |= ((tx_chains_num - 1) <<
  109. IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
  110. }
  111. }
  112. /**
  113. * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
  114. */
  115. int iwlcore_init_geos(struct iwl_priv *priv)
  116. {
  117. struct iwl_channel_info *ch;
  118. struct ieee80211_supported_band *sband;
  119. struct ieee80211_channel *channels;
  120. struct ieee80211_channel *geo_ch;
  121. struct ieee80211_rate *rates;
  122. int i = 0;
  123. s8 max_tx_power = IWLAGN_TX_POWER_TARGET_POWER_MIN;
  124. if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
  125. priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
  126. IWL_DEBUG_INFO(priv, "Geography modes already initialized.\n");
  127. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  128. return 0;
  129. }
  130. channels = kzalloc(sizeof(struct ieee80211_channel) *
  131. priv->channel_count, GFP_KERNEL);
  132. if (!channels)
  133. return -ENOMEM;
  134. rates = kzalloc((sizeof(struct ieee80211_rate) * IWL_RATE_COUNT_LEGACY),
  135. GFP_KERNEL);
  136. if (!rates) {
  137. kfree(channels);
  138. return -ENOMEM;
  139. }
  140. /* 5.2GHz channels start after the 2.4GHz channels */
  141. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  142. sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
  143. /* just OFDM */
  144. sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
  145. sband->n_bitrates = IWL_RATE_COUNT_LEGACY - IWL_FIRST_OFDM_RATE;
  146. if (priv->cfg->sku & IWL_SKU_N)
  147. iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
  148. IEEE80211_BAND_5GHZ);
  149. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  150. sband->channels = channels;
  151. /* OFDM & CCK */
  152. sband->bitrates = rates;
  153. sband->n_bitrates = IWL_RATE_COUNT_LEGACY;
  154. if (priv->cfg->sku & IWL_SKU_N)
  155. iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
  156. IEEE80211_BAND_2GHZ);
  157. priv->ieee_channels = channels;
  158. priv->ieee_rates = rates;
  159. for (i = 0; i < priv->channel_count; i++) {
  160. ch = &priv->channel_info[i];
  161. /* FIXME: might be removed if scan is OK */
  162. if (!is_channel_valid(ch))
  163. continue;
  164. sband = &priv->bands[ch->band];
  165. geo_ch = &sband->channels[sband->n_channels++];
  166. geo_ch->center_freq =
  167. ieee80211_channel_to_frequency(ch->channel, ch->band);
  168. geo_ch->max_power = ch->max_power_avg;
  169. geo_ch->max_antenna_gain = 0xff;
  170. geo_ch->hw_value = ch->channel;
  171. if (is_channel_valid(ch)) {
  172. if (!(ch->flags & EEPROM_CHANNEL_IBSS))
  173. geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
  174. if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
  175. geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
  176. if (ch->flags & EEPROM_CHANNEL_RADAR)
  177. geo_ch->flags |= IEEE80211_CHAN_RADAR;
  178. geo_ch->flags |= ch->ht40_extension_channel;
  179. if (ch->max_power_avg > max_tx_power)
  180. max_tx_power = ch->max_power_avg;
  181. } else {
  182. geo_ch->flags |= IEEE80211_CHAN_DISABLED;
  183. }
  184. IWL_DEBUG_INFO(priv, "Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
  185. ch->channel, geo_ch->center_freq,
  186. is_channel_a_band(ch) ? "5.2" : "2.4",
  187. geo_ch->flags & IEEE80211_CHAN_DISABLED ?
  188. "restricted" : "valid",
  189. geo_ch->flags);
  190. }
  191. priv->tx_power_device_lmt = max_tx_power;
  192. priv->tx_power_user_lmt = max_tx_power;
  193. priv->tx_power_next = max_tx_power;
  194. if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
  195. priv->cfg->sku & IWL_SKU_A) {
  196. IWL_INFO(priv, "Incorrectly detected BG card as ABG. "
  197. "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
  198. priv->pci_dev->device,
  199. priv->pci_dev->subsystem_device);
  200. priv->cfg->sku &= ~IWL_SKU_A;
  201. }
  202. IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n",
  203. priv->bands[IEEE80211_BAND_2GHZ].n_channels,
  204. priv->bands[IEEE80211_BAND_5GHZ].n_channels);
  205. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  206. return 0;
  207. }
  208. /*
  209. * iwlcore_free_geos - undo allocations in iwlcore_init_geos
  210. */
  211. void iwlcore_free_geos(struct iwl_priv *priv)
  212. {
  213. kfree(priv->ieee_channels);
  214. kfree(priv->ieee_rates);
  215. clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
  216. }
  217. static bool iwl_is_channel_extension(struct iwl_priv *priv,
  218. enum ieee80211_band band,
  219. u16 channel, u8 extension_chan_offset)
  220. {
  221. const struct iwl_channel_info *ch_info;
  222. ch_info = iwl_get_channel_info(priv, band, channel);
  223. if (!is_channel_valid(ch_info))
  224. return false;
  225. if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
  226. return !(ch_info->ht40_extension_channel &
  227. IEEE80211_CHAN_NO_HT40PLUS);
  228. else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
  229. return !(ch_info->ht40_extension_channel &
  230. IEEE80211_CHAN_NO_HT40MINUS);
  231. return false;
  232. }
  233. bool iwl_is_ht40_tx_allowed(struct iwl_priv *priv,
  234. struct iwl_rxon_context *ctx,
  235. struct ieee80211_sta_ht_cap *ht_cap)
  236. {
  237. if (!ctx->ht.enabled || !ctx->ht.is_40mhz)
  238. return false;
  239. /*
  240. * We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40
  241. * the bit will not set if it is pure 40MHz case
  242. */
  243. if (ht_cap && !ht_cap->ht_supported)
  244. return false;
  245. #ifdef CONFIG_IWLWIFI_DEBUGFS
  246. if (priv->disable_ht40)
  247. return false;
  248. #endif
  249. return iwl_is_channel_extension(priv, priv->band,
  250. le16_to_cpu(ctx->staging.channel),
  251. ctx->ht.extension_chan_offset);
  252. }
  253. static u16 iwl_adjust_beacon_interval(u16 beacon_val, u16 max_beacon_val)
  254. {
  255. u16 new_val;
  256. u16 beacon_factor;
  257. /*
  258. * If mac80211 hasn't given us a beacon interval, program
  259. * the default into the device (not checking this here
  260. * would cause the adjustment below to return the maximum
  261. * value, which may break PAN.)
  262. */
  263. if (!beacon_val)
  264. return DEFAULT_BEACON_INTERVAL;
  265. /*
  266. * If the beacon interval we obtained from the peer
  267. * is too large, we'll have to wake up more often
  268. * (and in IBSS case, we'll beacon too much)
  269. *
  270. * For example, if max_beacon_val is 4096, and the
  271. * requested beacon interval is 7000, we'll have to
  272. * use 3500 to be able to wake up on the beacons.
  273. *
  274. * This could badly influence beacon detection stats.
  275. */
  276. beacon_factor = (beacon_val + max_beacon_val) / max_beacon_val;
  277. new_val = beacon_val / beacon_factor;
  278. if (!new_val)
  279. new_val = max_beacon_val;
  280. return new_val;
  281. }
  282. int iwl_send_rxon_timing(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
  283. {
  284. u64 tsf;
  285. s32 interval_tm, rem;
  286. struct ieee80211_conf *conf = NULL;
  287. u16 beacon_int;
  288. struct ieee80211_vif *vif = ctx->vif;
  289. conf = ieee80211_get_hw_conf(priv->hw);
  290. lockdep_assert_held(&priv->mutex);
  291. memset(&ctx->timing, 0, sizeof(struct iwl_rxon_time_cmd));
  292. ctx->timing.timestamp = cpu_to_le64(priv->timestamp);
  293. ctx->timing.listen_interval = cpu_to_le16(conf->listen_interval);
  294. beacon_int = vif ? vif->bss_conf.beacon_int : 0;
  295. /*
  296. * TODO: For IBSS we need to get atim_window from mac80211,
  297. * for now just always use 0
  298. */
  299. ctx->timing.atim_window = 0;
  300. if (ctx->ctxid == IWL_RXON_CTX_PAN &&
  301. (!ctx->vif || ctx->vif->type != NL80211_IFTYPE_STATION) &&
  302. iwl_is_associated(priv, IWL_RXON_CTX_BSS) &&
  303. priv->contexts[IWL_RXON_CTX_BSS].vif &&
  304. priv->contexts[IWL_RXON_CTX_BSS].vif->bss_conf.beacon_int) {
  305. ctx->timing.beacon_interval =
  306. priv->contexts[IWL_RXON_CTX_BSS].timing.beacon_interval;
  307. beacon_int = le16_to_cpu(ctx->timing.beacon_interval);
  308. } else if (ctx->ctxid == IWL_RXON_CTX_BSS &&
  309. iwl_is_associated(priv, IWL_RXON_CTX_PAN) &&
  310. priv->contexts[IWL_RXON_CTX_PAN].vif &&
  311. priv->contexts[IWL_RXON_CTX_PAN].vif->bss_conf.beacon_int &&
  312. (!iwl_is_associated_ctx(ctx) || !ctx->vif ||
  313. !ctx->vif->bss_conf.beacon_int)) {
  314. ctx->timing.beacon_interval =
  315. priv->contexts[IWL_RXON_CTX_PAN].timing.beacon_interval;
  316. beacon_int = le16_to_cpu(ctx->timing.beacon_interval);
  317. } else {
  318. beacon_int = iwl_adjust_beacon_interval(beacon_int,
  319. priv->hw_params.max_beacon_itrvl * TIME_UNIT);
  320. ctx->timing.beacon_interval = cpu_to_le16(beacon_int);
  321. }
  322. tsf = priv->timestamp; /* tsf is modifed by do_div: copy it */
  323. interval_tm = beacon_int * TIME_UNIT;
  324. rem = do_div(tsf, interval_tm);
  325. ctx->timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
  326. ctx->timing.dtim_period = vif ? (vif->bss_conf.dtim_period ?: 1) : 1;
  327. IWL_DEBUG_ASSOC(priv,
  328. "beacon interval %d beacon timer %d beacon tim %d\n",
  329. le16_to_cpu(ctx->timing.beacon_interval),
  330. le32_to_cpu(ctx->timing.beacon_init_val),
  331. le16_to_cpu(ctx->timing.atim_window));
  332. return iwl_send_cmd_pdu(priv, ctx->rxon_timing_cmd,
  333. sizeof(ctx->timing), &ctx->timing);
  334. }
  335. void iwl_set_rxon_hwcrypto(struct iwl_priv *priv, struct iwl_rxon_context *ctx,
  336. int hw_decrypt)
  337. {
  338. struct iwl_rxon_cmd *rxon = &ctx->staging;
  339. if (hw_decrypt)
  340. rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
  341. else
  342. rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
  343. }
  344. /* validate RXON structure is valid */
  345. int iwl_check_rxon_cmd(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
  346. {
  347. struct iwl_rxon_cmd *rxon = &ctx->staging;
  348. u32 errors = 0;
  349. if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
  350. if (rxon->flags & RXON_FLG_TGJ_NARROW_BAND_MSK) {
  351. IWL_WARN(priv, "check 2.4G: wrong narrow\n");
  352. errors |= BIT(0);
  353. }
  354. if (rxon->flags & RXON_FLG_RADAR_DETECT_MSK) {
  355. IWL_WARN(priv, "check 2.4G: wrong radar\n");
  356. errors |= BIT(1);
  357. }
  358. } else {
  359. if (!(rxon->flags & RXON_FLG_SHORT_SLOT_MSK)) {
  360. IWL_WARN(priv, "check 5.2G: not short slot!\n");
  361. errors |= BIT(2);
  362. }
  363. if (rxon->flags & RXON_FLG_CCK_MSK) {
  364. IWL_WARN(priv, "check 5.2G: CCK!\n");
  365. errors |= BIT(3);
  366. }
  367. }
  368. if ((rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1) {
  369. IWL_WARN(priv, "mac/bssid mcast!\n");
  370. errors |= BIT(4);
  371. }
  372. /* make sure basic rates 6Mbps and 1Mbps are supported */
  373. if ((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0 &&
  374. (rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0) {
  375. IWL_WARN(priv, "neither 1 nor 6 are basic\n");
  376. errors |= BIT(5);
  377. }
  378. if (le16_to_cpu(rxon->assoc_id) > 2007) {
  379. IWL_WARN(priv, "aid > 2007\n");
  380. errors |= BIT(6);
  381. }
  382. if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
  383. == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) {
  384. IWL_WARN(priv, "CCK and short slot\n");
  385. errors |= BIT(7);
  386. }
  387. if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
  388. == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) {
  389. IWL_WARN(priv, "CCK and auto detect");
  390. errors |= BIT(8);
  391. }
  392. if ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
  393. RXON_FLG_TGG_PROTECT_MSK)) ==
  394. RXON_FLG_TGG_PROTECT_MSK) {
  395. IWL_WARN(priv, "TGg but no auto-detect\n");
  396. errors |= BIT(9);
  397. }
  398. if (rxon->channel == 0) {
  399. IWL_WARN(priv, "zero channel is invalid\n");
  400. errors |= BIT(10);
  401. }
  402. WARN(errors, "Invalid RXON (%#x), channel %d",
  403. errors, le16_to_cpu(rxon->channel));
  404. return errors ? -EINVAL : 0;
  405. }
  406. /**
  407. * iwl_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
  408. * @priv: staging_rxon is compared to active_rxon
  409. *
  410. * If the RXON structure is changing enough to require a new tune,
  411. * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
  412. * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
  413. */
  414. int iwl_full_rxon_required(struct iwl_priv *priv,
  415. struct iwl_rxon_context *ctx)
  416. {
  417. const struct iwl_rxon_cmd *staging = &ctx->staging;
  418. const struct iwl_rxon_cmd *active = &ctx->active;
  419. #define CHK(cond) \
  420. if ((cond)) { \
  421. IWL_DEBUG_INFO(priv, "need full RXON - " #cond "\n"); \
  422. return 1; \
  423. }
  424. #define CHK_NEQ(c1, c2) \
  425. if ((c1) != (c2)) { \
  426. IWL_DEBUG_INFO(priv, "need full RXON - " \
  427. #c1 " != " #c2 " - %d != %d\n", \
  428. (c1), (c2)); \
  429. return 1; \
  430. }
  431. /* These items are only settable from the full RXON command */
  432. CHK(!iwl_is_associated_ctx(ctx));
  433. CHK(compare_ether_addr(staging->bssid_addr, active->bssid_addr));
  434. CHK(compare_ether_addr(staging->node_addr, active->node_addr));
  435. CHK(compare_ether_addr(staging->wlap_bssid_addr,
  436. active->wlap_bssid_addr));
  437. CHK_NEQ(staging->dev_type, active->dev_type);
  438. CHK_NEQ(staging->channel, active->channel);
  439. CHK_NEQ(staging->air_propagation, active->air_propagation);
  440. CHK_NEQ(staging->ofdm_ht_single_stream_basic_rates,
  441. active->ofdm_ht_single_stream_basic_rates);
  442. CHK_NEQ(staging->ofdm_ht_dual_stream_basic_rates,
  443. active->ofdm_ht_dual_stream_basic_rates);
  444. CHK_NEQ(staging->ofdm_ht_triple_stream_basic_rates,
  445. active->ofdm_ht_triple_stream_basic_rates);
  446. CHK_NEQ(staging->assoc_id, active->assoc_id);
  447. /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
  448. * be updated with the RXON_ASSOC command -- however only some
  449. * flag transitions are allowed using RXON_ASSOC */
  450. /* Check if we are not switching bands */
  451. CHK_NEQ(staging->flags & RXON_FLG_BAND_24G_MSK,
  452. active->flags & RXON_FLG_BAND_24G_MSK);
  453. /* Check if we are switching association toggle */
  454. CHK_NEQ(staging->filter_flags & RXON_FILTER_ASSOC_MSK,
  455. active->filter_flags & RXON_FILTER_ASSOC_MSK);
  456. #undef CHK
  457. #undef CHK_NEQ
  458. return 0;
  459. }
  460. u8 iwl_rate_get_lowest_plcp(struct iwl_priv *priv,
  461. struct iwl_rxon_context *ctx)
  462. {
  463. /*
  464. * Assign the lowest rate -- should really get this from
  465. * the beacon skb from mac80211.
  466. */
  467. if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK)
  468. return IWL_RATE_1M_PLCP;
  469. else
  470. return IWL_RATE_6M_PLCP;
  471. }
  472. static void _iwl_set_rxon_ht(struct iwl_priv *priv,
  473. struct iwl_ht_config *ht_conf,
  474. struct iwl_rxon_context *ctx)
  475. {
  476. struct iwl_rxon_cmd *rxon = &ctx->staging;
  477. if (!ctx->ht.enabled) {
  478. rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
  479. RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK |
  480. RXON_FLG_HT40_PROT_MSK |
  481. RXON_FLG_HT_PROT_MSK);
  482. return;
  483. }
  484. /* FIXME: if the definition of ht.protection changed, the "translation"
  485. * will be needed for rxon->flags
  486. */
  487. rxon->flags |= cpu_to_le32(ctx->ht.protection << RXON_FLG_HT_OPERATING_MODE_POS);
  488. /* Set up channel bandwidth:
  489. * 20 MHz only, 20/40 mixed or pure 40 if ht40 ok */
  490. /* clear the HT channel mode before set the mode */
  491. rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
  492. RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
  493. if (iwl_is_ht40_tx_allowed(priv, ctx, NULL)) {
  494. /* pure ht40 */
  495. if (ctx->ht.protection == IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) {
  496. rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40;
  497. /* Note: control channel is opposite of extension channel */
  498. switch (ctx->ht.extension_chan_offset) {
  499. case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
  500. rxon->flags &= ~RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  501. break;
  502. case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
  503. rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  504. break;
  505. }
  506. } else {
  507. /* Note: control channel is opposite of extension channel */
  508. switch (ctx->ht.extension_chan_offset) {
  509. case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
  510. rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
  511. rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
  512. break;
  513. case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
  514. rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  515. rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
  516. break;
  517. case IEEE80211_HT_PARAM_CHA_SEC_NONE:
  518. default:
  519. /* channel location only valid if in Mixed mode */
  520. IWL_ERR(priv, "invalid extension channel offset\n");
  521. break;
  522. }
  523. }
  524. } else {
  525. rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY;
  526. }
  527. if (priv->cfg->ops->hcmd->set_rxon_chain)
  528. priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
  529. IWL_DEBUG_ASSOC(priv, "rxon flags 0x%X operation mode :0x%X "
  530. "extension channel offset 0x%x\n",
  531. le32_to_cpu(rxon->flags), ctx->ht.protection,
  532. ctx->ht.extension_chan_offset);
  533. }
  534. void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_config *ht_conf)
  535. {
  536. struct iwl_rxon_context *ctx;
  537. for_each_context(priv, ctx)
  538. _iwl_set_rxon_ht(priv, ht_conf, ctx);
  539. }
  540. /* Return valid, unused, channel for a passive scan to reset the RF */
  541. u8 iwl_get_single_channel_number(struct iwl_priv *priv,
  542. enum ieee80211_band band)
  543. {
  544. const struct iwl_channel_info *ch_info;
  545. int i;
  546. u8 channel = 0;
  547. u8 min, max;
  548. struct iwl_rxon_context *ctx;
  549. if (band == IEEE80211_BAND_5GHZ) {
  550. min = 14;
  551. max = priv->channel_count;
  552. } else {
  553. min = 0;
  554. max = 14;
  555. }
  556. for (i = min; i < max; i++) {
  557. bool busy = false;
  558. for_each_context(priv, ctx) {
  559. busy = priv->channel_info[i].channel ==
  560. le16_to_cpu(ctx->staging.channel);
  561. if (busy)
  562. break;
  563. }
  564. if (busy)
  565. continue;
  566. channel = priv->channel_info[i].channel;
  567. ch_info = iwl_get_channel_info(priv, band, channel);
  568. if (is_channel_valid(ch_info))
  569. break;
  570. }
  571. return channel;
  572. }
  573. /**
  574. * iwl_set_rxon_channel - Set the band and channel values in staging RXON
  575. * @ch: requested channel as a pointer to struct ieee80211_channel
  576. * NOTE: Does not commit to the hardware; it sets appropriate bit fields
  577. * in the staging RXON flag structure based on the ch->band
  578. */
  579. int iwl_set_rxon_channel(struct iwl_priv *priv, struct ieee80211_channel *ch,
  580. struct iwl_rxon_context *ctx)
  581. {
  582. enum ieee80211_band band = ch->band;
  583. u16 channel = ch->hw_value;
  584. if ((le16_to_cpu(ctx->staging.channel) == channel) &&
  585. (priv->band == band))
  586. return 0;
  587. ctx->staging.channel = cpu_to_le16(channel);
  588. if (band == IEEE80211_BAND_5GHZ)
  589. ctx->staging.flags &= ~RXON_FLG_BAND_24G_MSK;
  590. else
  591. ctx->staging.flags |= RXON_FLG_BAND_24G_MSK;
  592. priv->band = band;
  593. IWL_DEBUG_INFO(priv, "Staging channel set to %d [%d]\n", channel, band);
  594. return 0;
  595. }
  596. void iwl_set_flags_for_band(struct iwl_priv *priv,
  597. struct iwl_rxon_context *ctx,
  598. enum ieee80211_band band,
  599. struct ieee80211_vif *vif)
  600. {
  601. if (band == IEEE80211_BAND_5GHZ) {
  602. ctx->staging.flags &=
  603. ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
  604. | RXON_FLG_CCK_MSK);
  605. ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
  606. } else {
  607. /* Copied from iwl_post_associate() */
  608. if (vif && vif->bss_conf.use_short_slot)
  609. ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
  610. else
  611. ctx->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  612. ctx->staging.flags |= RXON_FLG_BAND_24G_MSK;
  613. ctx->staging.flags |= RXON_FLG_AUTO_DETECT_MSK;
  614. ctx->staging.flags &= ~RXON_FLG_CCK_MSK;
  615. }
  616. }
  617. /*
  618. * initialize rxon structure with default values from eeprom
  619. */
  620. void iwl_connection_init_rx_config(struct iwl_priv *priv,
  621. struct iwl_rxon_context *ctx)
  622. {
  623. const struct iwl_channel_info *ch_info;
  624. memset(&ctx->staging, 0, sizeof(ctx->staging));
  625. if (!ctx->vif) {
  626. ctx->staging.dev_type = ctx->unused_devtype;
  627. } else switch (ctx->vif->type) {
  628. case NL80211_IFTYPE_AP:
  629. ctx->staging.dev_type = ctx->ap_devtype;
  630. break;
  631. case NL80211_IFTYPE_STATION:
  632. ctx->staging.dev_type = ctx->station_devtype;
  633. ctx->staging.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
  634. break;
  635. case NL80211_IFTYPE_ADHOC:
  636. ctx->staging.dev_type = ctx->ibss_devtype;
  637. ctx->staging.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
  638. ctx->staging.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
  639. RXON_FILTER_ACCEPT_GRP_MSK;
  640. break;
  641. default:
  642. IWL_ERR(priv, "Unsupported interface type %d\n",
  643. ctx->vif->type);
  644. break;
  645. }
  646. #if 0
  647. /* TODO: Figure out when short_preamble would be set and cache from
  648. * that */
  649. if (!hw_to_local(priv->hw)->short_preamble)
  650. ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  651. else
  652. ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  653. #endif
  654. ch_info = iwl_get_channel_info(priv, priv->band,
  655. le16_to_cpu(ctx->active.channel));
  656. if (!ch_info)
  657. ch_info = &priv->channel_info[0];
  658. ctx->staging.channel = cpu_to_le16(ch_info->channel);
  659. priv->band = ch_info->band;
  660. iwl_set_flags_for_band(priv, ctx, priv->band, ctx->vif);
  661. ctx->staging.ofdm_basic_rates =
  662. (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  663. ctx->staging.cck_basic_rates =
  664. (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  665. /* clear both MIX and PURE40 mode flag */
  666. ctx->staging.flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED |
  667. RXON_FLG_CHANNEL_MODE_PURE_40);
  668. if (ctx->vif)
  669. memcpy(ctx->staging.node_addr, ctx->vif->addr, ETH_ALEN);
  670. ctx->staging.ofdm_ht_single_stream_basic_rates = 0xff;
  671. ctx->staging.ofdm_ht_dual_stream_basic_rates = 0xff;
  672. ctx->staging.ofdm_ht_triple_stream_basic_rates = 0xff;
  673. }
  674. void iwl_set_rate(struct iwl_priv *priv)
  675. {
  676. const struct ieee80211_supported_band *hw = NULL;
  677. struct ieee80211_rate *rate;
  678. struct iwl_rxon_context *ctx;
  679. int i;
  680. hw = iwl_get_hw_mode(priv, priv->band);
  681. if (!hw) {
  682. IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n");
  683. return;
  684. }
  685. priv->active_rate = 0;
  686. for (i = 0; i < hw->n_bitrates; i++) {
  687. rate = &(hw->bitrates[i]);
  688. if (rate->hw_value < IWL_RATE_COUNT_LEGACY)
  689. priv->active_rate |= (1 << rate->hw_value);
  690. }
  691. IWL_DEBUG_RATE(priv, "Set active_rate = %0x\n", priv->active_rate);
  692. for_each_context(priv, ctx) {
  693. ctx->staging.cck_basic_rates =
  694. (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  695. ctx->staging.ofdm_basic_rates =
  696. (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  697. }
  698. }
  699. void iwl_chswitch_done(struct iwl_priv *priv, bool is_success)
  700. {
  701. /*
  702. * MULTI-FIXME
  703. * See iwl_mac_channel_switch.
  704. */
  705. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  706. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  707. return;
  708. if (priv->switch_rxon.switch_in_progress) {
  709. ieee80211_chswitch_done(ctx->vif, is_success);
  710. mutex_lock(&priv->mutex);
  711. priv->switch_rxon.switch_in_progress = false;
  712. mutex_unlock(&priv->mutex);
  713. }
  714. }
  715. #ifdef CONFIG_IWLWIFI_DEBUG
  716. void iwl_print_rx_config_cmd(struct iwl_priv *priv,
  717. struct iwl_rxon_context *ctx)
  718. {
  719. struct iwl_rxon_cmd *rxon = &ctx->staging;
  720. IWL_DEBUG_RADIO(priv, "RX CONFIG:\n");
  721. iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
  722. IWL_DEBUG_RADIO(priv, "u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
  723. IWL_DEBUG_RADIO(priv, "u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
  724. IWL_DEBUG_RADIO(priv, "u32 filter_flags: 0x%08x\n",
  725. le32_to_cpu(rxon->filter_flags));
  726. IWL_DEBUG_RADIO(priv, "u8 dev_type: 0x%x\n", rxon->dev_type);
  727. IWL_DEBUG_RADIO(priv, "u8 ofdm_basic_rates: 0x%02x\n",
  728. rxon->ofdm_basic_rates);
  729. IWL_DEBUG_RADIO(priv, "u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
  730. IWL_DEBUG_RADIO(priv, "u8[6] node_addr: %pM\n", rxon->node_addr);
  731. IWL_DEBUG_RADIO(priv, "u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
  732. IWL_DEBUG_RADIO(priv, "u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
  733. }
  734. #endif
  735. static void iwlagn_abort_notification_waits(struct iwl_priv *priv)
  736. {
  737. unsigned long flags;
  738. struct iwl_notification_wait *wait_entry;
  739. spin_lock_irqsave(&priv->_agn.notif_wait_lock, flags);
  740. list_for_each_entry(wait_entry, &priv->_agn.notif_waits, list)
  741. wait_entry->aborted = true;
  742. spin_unlock_irqrestore(&priv->_agn.notif_wait_lock, flags);
  743. wake_up_all(&priv->_agn.notif_waitq);
  744. }
  745. void iwlagn_fw_error(struct iwl_priv *priv, bool ondemand)
  746. {
  747. unsigned int reload_msec;
  748. unsigned long reload_jiffies;
  749. /* Set the FW error flag -- cleared on iwl_down */
  750. set_bit(STATUS_FW_ERROR, &priv->status);
  751. /* Cancel currently queued command. */
  752. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  753. iwlagn_abort_notification_waits(priv);
  754. /* Keep the restart process from trying to send host
  755. * commands by clearing the ready bit */
  756. clear_bit(STATUS_READY, &priv->status);
  757. wake_up_interruptible(&priv->wait_command_queue);
  758. if (!ondemand) {
  759. /*
  760. * If firmware keep reloading, then it indicate something
  761. * serious wrong and firmware having problem to recover
  762. * from it. Instead of keep trying which will fill the syslog
  763. * and hang the system, let's just stop it
  764. */
  765. reload_jiffies = jiffies;
  766. reload_msec = jiffies_to_msecs((long) reload_jiffies -
  767. (long) priv->reload_jiffies);
  768. priv->reload_jiffies = reload_jiffies;
  769. if (reload_msec <= IWL_MIN_RELOAD_DURATION) {
  770. priv->reload_count++;
  771. if (priv->reload_count >= IWL_MAX_CONTINUE_RELOAD_CNT) {
  772. IWL_ERR(priv, "BUG_ON, Stop restarting\n");
  773. return;
  774. }
  775. } else
  776. priv->reload_count = 0;
  777. }
  778. if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  779. if (iwlagn_mod_params.restart_fw) {
  780. IWL_DEBUG(priv, IWL_DL_FW_ERRORS,
  781. "Restarting adapter due to uCode error.\n");
  782. queue_work(priv->workqueue, &priv->restart);
  783. } else
  784. IWL_DEBUG(priv, IWL_DL_FW_ERRORS,
  785. "Detected FW error, but not restarting\n");
  786. }
  787. }
  788. /**
  789. * iwl_irq_handle_error - called for HW or SW error interrupt from card
  790. */
  791. void iwl_irq_handle_error(struct iwl_priv *priv)
  792. {
  793. /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
  794. if (priv->cfg->internal_wimax_coex &&
  795. (!(iwl_read_prph(priv, APMG_CLK_CTRL_REG) &
  796. APMS_CLK_VAL_MRB_FUNC_MODE) ||
  797. (iwl_read_prph(priv, APMG_PS_CTRL_REG) &
  798. APMG_PS_CTRL_VAL_RESET_REQ))) {
  799. /*
  800. * Keep the restart process from trying to send host
  801. * commands by clearing the ready bit.
  802. */
  803. clear_bit(STATUS_READY, &priv->status);
  804. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  805. wake_up_interruptible(&priv->wait_command_queue);
  806. IWL_ERR(priv, "RF is used by WiMAX\n");
  807. return;
  808. }
  809. IWL_ERR(priv, "Loaded firmware version: %s\n",
  810. priv->hw->wiphy->fw_version);
  811. iwl_dump_nic_error_log(priv);
  812. iwl_dump_csr(priv);
  813. iwl_dump_fh(priv, NULL, false);
  814. iwl_dump_nic_event_log(priv, false, NULL, false);
  815. #ifdef CONFIG_IWLWIFI_DEBUG
  816. if (iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS)
  817. iwl_print_rx_config_cmd(priv,
  818. &priv->contexts[IWL_RXON_CTX_BSS]);
  819. #endif
  820. iwlagn_fw_error(priv, false);
  821. }
  822. static int iwl_apm_stop_master(struct iwl_priv *priv)
  823. {
  824. int ret = 0;
  825. /* stop device's busmaster DMA activity */
  826. iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
  827. ret = iwl_poll_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_MASTER_DISABLED,
  828. CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
  829. if (ret)
  830. IWL_WARN(priv, "Master Disable Timed Out, 100 usec\n");
  831. IWL_DEBUG_INFO(priv, "stop master\n");
  832. return ret;
  833. }
  834. void iwl_apm_stop(struct iwl_priv *priv)
  835. {
  836. IWL_DEBUG_INFO(priv, "Stop card, put in low power state\n");
  837. clear_bit(STATUS_DEVICE_ENABLED, &priv->status);
  838. /* Stop device's DMA activity */
  839. iwl_apm_stop_master(priv);
  840. /* Reset the entire device */
  841. iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  842. udelay(10);
  843. /*
  844. * Clear "initialization complete" bit to move adapter from
  845. * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
  846. */
  847. iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  848. }
  849. /*
  850. * Start up NIC's basic functionality after it has been reset
  851. * (e.g. after platform boot, or shutdown via iwl_apm_stop())
  852. * NOTE: This does not load uCode nor start the embedded processor
  853. */
  854. int iwl_apm_init(struct iwl_priv *priv)
  855. {
  856. int ret = 0;
  857. u16 lctl;
  858. IWL_DEBUG_INFO(priv, "Init card's basic functions\n");
  859. /*
  860. * Use "set_bit" below rather than "write", to preserve any hardware
  861. * bits already set by default after reset.
  862. */
  863. /* Disable L0S exit timer (platform NMI Work/Around) */
  864. iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  865. CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  866. /*
  867. * Disable L0s without affecting L1;
  868. * don't wait for ICH L0s (ICH bug W/A)
  869. */
  870. iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  871. CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
  872. /* Set FH wait threshold to maximum (HW error during stress W/A) */
  873. iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
  874. /*
  875. * Enable HAP INTA (interrupt from management bus) to
  876. * wake device's PCI Express link L1a -> L0s
  877. */
  878. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  879. CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
  880. /*
  881. * HW bug W/A for instability in PCIe bus L0->L0S->L1 transition.
  882. * Check if BIOS (or OS) enabled L1-ASPM on this device.
  883. * If so (likely), disable L0S, so device moves directly L0->L1;
  884. * costs negligible amount of power savings.
  885. * If not (unlikely), enable L0S, so there is at least some
  886. * power savings, even without L1.
  887. */
  888. lctl = iwl_pcie_link_ctl(priv);
  889. if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
  890. PCI_CFG_LINK_CTRL_VAL_L1_EN) {
  891. /* L1-ASPM enabled; disable(!) L0S */
  892. iwl_set_bit(priv, CSR_GIO_REG,
  893. CSR_GIO_REG_VAL_L0S_ENABLED);
  894. IWL_DEBUG_POWER(priv, "L1 Enabled; Disabling L0S\n");
  895. } else {
  896. /* L1-ASPM disabled; enable(!) L0S */
  897. iwl_clear_bit(priv, CSR_GIO_REG,
  898. CSR_GIO_REG_VAL_L0S_ENABLED);
  899. IWL_DEBUG_POWER(priv, "L1 Disabled; Enabling L0S\n");
  900. }
  901. /* Configure analog phase-lock-loop before activating to D0A */
  902. if (priv->cfg->base_params->pll_cfg_val)
  903. iwl_set_bit(priv, CSR_ANA_PLL_CFG,
  904. priv->cfg->base_params->pll_cfg_val);
  905. /*
  906. * Set "initialization complete" bit to move adapter from
  907. * D0U* --> D0A* (powered-up active) state.
  908. */
  909. iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  910. /*
  911. * Wait for clock stabilization; once stabilized, access to
  912. * device-internal resources is supported, e.g. iwl_write_prph()
  913. * and accesses to uCode SRAM.
  914. */
  915. ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
  916. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  917. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  918. if (ret < 0) {
  919. IWL_DEBUG_INFO(priv, "Failed to init the card\n");
  920. goto out;
  921. }
  922. /*
  923. * Enable DMA clock and wait for it to stabilize.
  924. *
  925. * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
  926. * do not disable clocks. This preserves any hardware bits already
  927. * set by default in "CLK_CTRL_REG" after reset.
  928. */
  929. iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
  930. udelay(20);
  931. /* Disable L1-Active */
  932. iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
  933. APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
  934. set_bit(STATUS_DEVICE_ENABLED, &priv->status);
  935. out:
  936. return ret;
  937. }
  938. int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
  939. {
  940. int ret;
  941. s8 prev_tx_power;
  942. bool defer;
  943. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  944. lockdep_assert_held(&priv->mutex);
  945. if (priv->tx_power_user_lmt == tx_power && !force)
  946. return 0;
  947. if (!priv->cfg->ops->lib->send_tx_power)
  948. return -EOPNOTSUPP;
  949. if (tx_power < IWLAGN_TX_POWER_TARGET_POWER_MIN) {
  950. IWL_WARN(priv,
  951. "Requested user TXPOWER %d below lower limit %d.\n",
  952. tx_power,
  953. IWLAGN_TX_POWER_TARGET_POWER_MIN);
  954. return -EINVAL;
  955. }
  956. if (tx_power > priv->tx_power_device_lmt) {
  957. IWL_WARN(priv,
  958. "Requested user TXPOWER %d above upper limit %d.\n",
  959. tx_power, priv->tx_power_device_lmt);
  960. return -EINVAL;
  961. }
  962. if (!iwl_is_ready_rf(priv))
  963. return -EIO;
  964. /* scan complete and commit_rxon use tx_power_next value,
  965. * it always need to be updated for newest request */
  966. priv->tx_power_next = tx_power;
  967. /* do not set tx power when scanning or channel changing */
  968. defer = test_bit(STATUS_SCANNING, &priv->status) ||
  969. memcmp(&ctx->active, &ctx->staging, sizeof(ctx->staging));
  970. if (defer && !force) {
  971. IWL_DEBUG_INFO(priv, "Deferring tx power set\n");
  972. return 0;
  973. }
  974. prev_tx_power = priv->tx_power_user_lmt;
  975. priv->tx_power_user_lmt = tx_power;
  976. ret = priv->cfg->ops->lib->send_tx_power(priv);
  977. /* if fail to set tx_power, restore the orig. tx power */
  978. if (ret) {
  979. priv->tx_power_user_lmt = prev_tx_power;
  980. priv->tx_power_next = prev_tx_power;
  981. }
  982. return ret;
  983. }
  984. void iwl_send_bt_config(struct iwl_priv *priv)
  985. {
  986. struct iwl_bt_cmd bt_cmd = {
  987. .lead_time = BT_LEAD_TIME_DEF,
  988. .max_kill = BT_MAX_KILL_DEF,
  989. .kill_ack_mask = 0,
  990. .kill_cts_mask = 0,
  991. };
  992. if (!bt_coex_active)
  993. bt_cmd.flags = BT_COEX_DISABLE;
  994. else
  995. bt_cmd.flags = BT_COEX_ENABLE;
  996. priv->bt_enable_flag = bt_cmd.flags;
  997. IWL_DEBUG_INFO(priv, "BT coex %s\n",
  998. (bt_cmd.flags == BT_COEX_DISABLE) ? "disable" : "active");
  999. if (iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG,
  1000. sizeof(struct iwl_bt_cmd), &bt_cmd))
  1001. IWL_ERR(priv, "failed to send BT Coex Config\n");
  1002. }
  1003. int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags, bool clear)
  1004. {
  1005. struct iwl_statistics_cmd statistics_cmd = {
  1006. .configuration_flags =
  1007. clear ? IWL_STATS_CONF_CLEAR_STATS : 0,
  1008. };
  1009. if (flags & CMD_ASYNC)
  1010. return iwl_send_cmd_pdu_async(priv, REPLY_STATISTICS_CMD,
  1011. sizeof(struct iwl_statistics_cmd),
  1012. &statistics_cmd, NULL);
  1013. else
  1014. return iwl_send_cmd_pdu(priv, REPLY_STATISTICS_CMD,
  1015. sizeof(struct iwl_statistics_cmd),
  1016. &statistics_cmd);
  1017. }
  1018. void iwl_clear_isr_stats(struct iwl_priv *priv)
  1019. {
  1020. memset(&priv->isr_stats, 0, sizeof(priv->isr_stats));
  1021. }
  1022. int iwl_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
  1023. const struct ieee80211_tx_queue_params *params)
  1024. {
  1025. struct iwl_priv *priv = hw->priv;
  1026. struct iwl_rxon_context *ctx;
  1027. unsigned long flags;
  1028. int q;
  1029. IWL_DEBUG_MAC80211(priv, "enter\n");
  1030. if (!iwl_is_ready_rf(priv)) {
  1031. IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
  1032. return -EIO;
  1033. }
  1034. if (queue >= AC_NUM) {
  1035. IWL_DEBUG_MAC80211(priv, "leave - queue >= AC_NUM %d\n", queue);
  1036. return 0;
  1037. }
  1038. q = AC_NUM - 1 - queue;
  1039. spin_lock_irqsave(&priv->lock, flags);
  1040. /*
  1041. * MULTI-FIXME
  1042. * This may need to be done per interface in nl80211/cfg80211/mac80211.
  1043. */
  1044. for_each_context(priv, ctx) {
  1045. ctx->qos_data.def_qos_parm.ac[q].cw_min =
  1046. cpu_to_le16(params->cw_min);
  1047. ctx->qos_data.def_qos_parm.ac[q].cw_max =
  1048. cpu_to_le16(params->cw_max);
  1049. ctx->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
  1050. ctx->qos_data.def_qos_parm.ac[q].edca_txop =
  1051. cpu_to_le16((params->txop * 32));
  1052. ctx->qos_data.def_qos_parm.ac[q].reserved1 = 0;
  1053. }
  1054. spin_unlock_irqrestore(&priv->lock, flags);
  1055. IWL_DEBUG_MAC80211(priv, "leave\n");
  1056. return 0;
  1057. }
  1058. int iwl_mac_tx_last_beacon(struct ieee80211_hw *hw)
  1059. {
  1060. struct iwl_priv *priv = hw->priv;
  1061. return priv->ibss_manager == IWL_IBSS_MANAGER;
  1062. }
  1063. static int iwl_set_mode(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
  1064. {
  1065. iwl_connection_init_rx_config(priv, ctx);
  1066. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1067. priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
  1068. return iwlcore_commit_rxon(priv, ctx);
  1069. }
  1070. static int iwl_setup_interface(struct iwl_priv *priv,
  1071. struct iwl_rxon_context *ctx)
  1072. {
  1073. struct ieee80211_vif *vif = ctx->vif;
  1074. int err;
  1075. lockdep_assert_held(&priv->mutex);
  1076. /*
  1077. * This variable will be correct only when there's just
  1078. * a single context, but all code using it is for hardware
  1079. * that supports only one context.
  1080. */
  1081. priv->iw_mode = vif->type;
  1082. ctx->is_active = true;
  1083. err = iwl_set_mode(priv, ctx);
  1084. if (err) {
  1085. if (!ctx->always_active)
  1086. ctx->is_active = false;
  1087. return err;
  1088. }
  1089. if (priv->cfg->bt_params && priv->cfg->bt_params->advanced_bt_coexist &&
  1090. vif->type == NL80211_IFTYPE_ADHOC) {
  1091. /*
  1092. * pretend to have high BT traffic as long as we
  1093. * are operating in IBSS mode, as this will cause
  1094. * the rate scaling etc. to behave as intended.
  1095. */
  1096. priv->bt_traffic_load = IWL_BT_COEX_TRAFFIC_LOAD_HIGH;
  1097. }
  1098. return 0;
  1099. }
  1100. int iwl_mac_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1101. {
  1102. struct iwl_priv *priv = hw->priv;
  1103. struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
  1104. struct iwl_rxon_context *tmp, *ctx = NULL;
  1105. int err;
  1106. enum nl80211_iftype viftype = ieee80211_vif_type_p2p(vif);
  1107. IWL_DEBUG_MAC80211(priv, "enter: type %d, addr %pM\n",
  1108. viftype, vif->addr);
  1109. mutex_lock(&priv->mutex);
  1110. if (!iwl_is_ready_rf(priv)) {
  1111. IWL_WARN(priv, "Try to add interface when device not ready\n");
  1112. err = -EINVAL;
  1113. goto out;
  1114. }
  1115. for_each_context(priv, tmp) {
  1116. u32 possible_modes =
  1117. tmp->interface_modes | tmp->exclusive_interface_modes;
  1118. if (tmp->vif) {
  1119. /* check if this busy context is exclusive */
  1120. if (tmp->exclusive_interface_modes &
  1121. BIT(tmp->vif->type)) {
  1122. err = -EINVAL;
  1123. goto out;
  1124. }
  1125. continue;
  1126. }
  1127. if (!(possible_modes & BIT(viftype)))
  1128. continue;
  1129. /* have maybe usable context w/o interface */
  1130. ctx = tmp;
  1131. break;
  1132. }
  1133. if (!ctx) {
  1134. err = -EOPNOTSUPP;
  1135. goto out;
  1136. }
  1137. vif_priv->ctx = ctx;
  1138. ctx->vif = vif;
  1139. err = iwl_setup_interface(priv, ctx);
  1140. if (!err)
  1141. goto out;
  1142. ctx->vif = NULL;
  1143. priv->iw_mode = NL80211_IFTYPE_STATION;
  1144. out:
  1145. mutex_unlock(&priv->mutex);
  1146. IWL_DEBUG_MAC80211(priv, "leave\n");
  1147. return err;
  1148. }
  1149. static void iwl_teardown_interface(struct iwl_priv *priv,
  1150. struct ieee80211_vif *vif,
  1151. bool mode_change)
  1152. {
  1153. struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif);
  1154. lockdep_assert_held(&priv->mutex);
  1155. if (priv->scan_vif == vif) {
  1156. iwl_scan_cancel_timeout(priv, 200);
  1157. iwl_force_scan_end(priv);
  1158. }
  1159. if (!mode_change) {
  1160. iwl_set_mode(priv, ctx);
  1161. if (!ctx->always_active)
  1162. ctx->is_active = false;
  1163. }
  1164. /*
  1165. * When removing the IBSS interface, overwrite the
  1166. * BT traffic load with the stored one from the last
  1167. * notification, if any. If this is a device that
  1168. * doesn't implement this, this has no effect since
  1169. * both values are the same and zero.
  1170. */
  1171. if (vif->type == NL80211_IFTYPE_ADHOC)
  1172. priv->bt_traffic_load = priv->last_bt_traffic_load;
  1173. }
  1174. void iwl_mac_remove_interface(struct ieee80211_hw *hw,
  1175. struct ieee80211_vif *vif)
  1176. {
  1177. struct iwl_priv *priv = hw->priv;
  1178. struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif);
  1179. IWL_DEBUG_MAC80211(priv, "enter\n");
  1180. mutex_lock(&priv->mutex);
  1181. WARN_ON(ctx->vif != vif);
  1182. ctx->vif = NULL;
  1183. iwl_teardown_interface(priv, vif, false);
  1184. mutex_unlock(&priv->mutex);
  1185. IWL_DEBUG_MAC80211(priv, "leave\n");
  1186. }
  1187. int iwl_alloc_txq_mem(struct iwl_priv *priv)
  1188. {
  1189. if (!priv->txq)
  1190. priv->txq = kzalloc(
  1191. sizeof(struct iwl_tx_queue) *
  1192. priv->cfg->base_params->num_of_queues,
  1193. GFP_KERNEL);
  1194. if (!priv->txq) {
  1195. IWL_ERR(priv, "Not enough memory for txq\n");
  1196. return -ENOMEM;
  1197. }
  1198. return 0;
  1199. }
  1200. void iwl_free_txq_mem(struct iwl_priv *priv)
  1201. {
  1202. kfree(priv->txq);
  1203. priv->txq = NULL;
  1204. }
  1205. #ifdef CONFIG_IWLWIFI_DEBUGFS
  1206. #define IWL_TRAFFIC_DUMP_SIZE (IWL_TRAFFIC_ENTRY_SIZE * IWL_TRAFFIC_ENTRIES)
  1207. void iwl_reset_traffic_log(struct iwl_priv *priv)
  1208. {
  1209. priv->tx_traffic_idx = 0;
  1210. priv->rx_traffic_idx = 0;
  1211. if (priv->tx_traffic)
  1212. memset(priv->tx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE);
  1213. if (priv->rx_traffic)
  1214. memset(priv->rx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE);
  1215. }
  1216. int iwl_alloc_traffic_mem(struct iwl_priv *priv)
  1217. {
  1218. u32 traffic_size = IWL_TRAFFIC_DUMP_SIZE;
  1219. if (iwl_debug_level & IWL_DL_TX) {
  1220. if (!priv->tx_traffic) {
  1221. priv->tx_traffic =
  1222. kzalloc(traffic_size, GFP_KERNEL);
  1223. if (!priv->tx_traffic)
  1224. return -ENOMEM;
  1225. }
  1226. }
  1227. if (iwl_debug_level & IWL_DL_RX) {
  1228. if (!priv->rx_traffic) {
  1229. priv->rx_traffic =
  1230. kzalloc(traffic_size, GFP_KERNEL);
  1231. if (!priv->rx_traffic)
  1232. return -ENOMEM;
  1233. }
  1234. }
  1235. iwl_reset_traffic_log(priv);
  1236. return 0;
  1237. }
  1238. void iwl_free_traffic_mem(struct iwl_priv *priv)
  1239. {
  1240. kfree(priv->tx_traffic);
  1241. priv->tx_traffic = NULL;
  1242. kfree(priv->rx_traffic);
  1243. priv->rx_traffic = NULL;
  1244. }
  1245. void iwl_dbg_log_tx_data_frame(struct iwl_priv *priv,
  1246. u16 length, struct ieee80211_hdr *header)
  1247. {
  1248. __le16 fc;
  1249. u16 len;
  1250. if (likely(!(iwl_debug_level & IWL_DL_TX)))
  1251. return;
  1252. if (!priv->tx_traffic)
  1253. return;
  1254. fc = header->frame_control;
  1255. if (ieee80211_is_data(fc)) {
  1256. len = (length > IWL_TRAFFIC_ENTRY_SIZE)
  1257. ? IWL_TRAFFIC_ENTRY_SIZE : length;
  1258. memcpy((priv->tx_traffic +
  1259. (priv->tx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)),
  1260. header, len);
  1261. priv->tx_traffic_idx =
  1262. (priv->tx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES;
  1263. }
  1264. }
  1265. void iwl_dbg_log_rx_data_frame(struct iwl_priv *priv,
  1266. u16 length, struct ieee80211_hdr *header)
  1267. {
  1268. __le16 fc;
  1269. u16 len;
  1270. if (likely(!(iwl_debug_level & IWL_DL_RX)))
  1271. return;
  1272. if (!priv->rx_traffic)
  1273. return;
  1274. fc = header->frame_control;
  1275. if (ieee80211_is_data(fc)) {
  1276. len = (length > IWL_TRAFFIC_ENTRY_SIZE)
  1277. ? IWL_TRAFFIC_ENTRY_SIZE : length;
  1278. memcpy((priv->rx_traffic +
  1279. (priv->rx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)),
  1280. header, len);
  1281. priv->rx_traffic_idx =
  1282. (priv->rx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES;
  1283. }
  1284. }
  1285. const char *get_mgmt_string(int cmd)
  1286. {
  1287. switch (cmd) {
  1288. IWL_CMD(MANAGEMENT_ASSOC_REQ);
  1289. IWL_CMD(MANAGEMENT_ASSOC_RESP);
  1290. IWL_CMD(MANAGEMENT_REASSOC_REQ);
  1291. IWL_CMD(MANAGEMENT_REASSOC_RESP);
  1292. IWL_CMD(MANAGEMENT_PROBE_REQ);
  1293. IWL_CMD(MANAGEMENT_PROBE_RESP);
  1294. IWL_CMD(MANAGEMENT_BEACON);
  1295. IWL_CMD(MANAGEMENT_ATIM);
  1296. IWL_CMD(MANAGEMENT_DISASSOC);
  1297. IWL_CMD(MANAGEMENT_AUTH);
  1298. IWL_CMD(MANAGEMENT_DEAUTH);
  1299. IWL_CMD(MANAGEMENT_ACTION);
  1300. default:
  1301. return "UNKNOWN";
  1302. }
  1303. }
  1304. const char *get_ctrl_string(int cmd)
  1305. {
  1306. switch (cmd) {
  1307. IWL_CMD(CONTROL_BACK_REQ);
  1308. IWL_CMD(CONTROL_BACK);
  1309. IWL_CMD(CONTROL_PSPOLL);
  1310. IWL_CMD(CONTROL_RTS);
  1311. IWL_CMD(CONTROL_CTS);
  1312. IWL_CMD(CONTROL_ACK);
  1313. IWL_CMD(CONTROL_CFEND);
  1314. IWL_CMD(CONTROL_CFENDACK);
  1315. default:
  1316. return "UNKNOWN";
  1317. }
  1318. }
  1319. void iwl_clear_traffic_stats(struct iwl_priv *priv)
  1320. {
  1321. memset(&priv->tx_stats, 0, sizeof(struct traffic_stats));
  1322. memset(&priv->rx_stats, 0, sizeof(struct traffic_stats));
  1323. }
  1324. /*
  1325. * if CONFIG_IWLWIFI_DEBUGFS defined, iwl_update_stats function will
  1326. * record all the MGMT, CTRL and DATA pkt for both TX and Rx pass.
  1327. * Use debugFs to display the rx/rx_statistics
  1328. * if CONFIG_IWLWIFI_DEBUGFS not being defined, then no MGMT and CTRL
  1329. * information will be recorded, but DATA pkt still will be recorded
  1330. * for the reason of iwl_led.c need to control the led blinking based on
  1331. * number of tx and rx data.
  1332. *
  1333. */
  1334. void iwl_update_stats(struct iwl_priv *priv, bool is_tx, __le16 fc, u16 len)
  1335. {
  1336. struct traffic_stats *stats;
  1337. if (is_tx)
  1338. stats = &priv->tx_stats;
  1339. else
  1340. stats = &priv->rx_stats;
  1341. if (ieee80211_is_mgmt(fc)) {
  1342. switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
  1343. case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
  1344. stats->mgmt[MANAGEMENT_ASSOC_REQ]++;
  1345. break;
  1346. case cpu_to_le16(IEEE80211_STYPE_ASSOC_RESP):
  1347. stats->mgmt[MANAGEMENT_ASSOC_RESP]++;
  1348. break;
  1349. case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
  1350. stats->mgmt[MANAGEMENT_REASSOC_REQ]++;
  1351. break;
  1352. case cpu_to_le16(IEEE80211_STYPE_REASSOC_RESP):
  1353. stats->mgmt[MANAGEMENT_REASSOC_RESP]++;
  1354. break;
  1355. case cpu_to_le16(IEEE80211_STYPE_PROBE_REQ):
  1356. stats->mgmt[MANAGEMENT_PROBE_REQ]++;
  1357. break;
  1358. case cpu_to_le16(IEEE80211_STYPE_PROBE_RESP):
  1359. stats->mgmt[MANAGEMENT_PROBE_RESP]++;
  1360. break;
  1361. case cpu_to_le16(IEEE80211_STYPE_BEACON):
  1362. stats->mgmt[MANAGEMENT_BEACON]++;
  1363. break;
  1364. case cpu_to_le16(IEEE80211_STYPE_ATIM):
  1365. stats->mgmt[MANAGEMENT_ATIM]++;
  1366. break;
  1367. case cpu_to_le16(IEEE80211_STYPE_DISASSOC):
  1368. stats->mgmt[MANAGEMENT_DISASSOC]++;
  1369. break;
  1370. case cpu_to_le16(IEEE80211_STYPE_AUTH):
  1371. stats->mgmt[MANAGEMENT_AUTH]++;
  1372. break;
  1373. case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
  1374. stats->mgmt[MANAGEMENT_DEAUTH]++;
  1375. break;
  1376. case cpu_to_le16(IEEE80211_STYPE_ACTION):
  1377. stats->mgmt[MANAGEMENT_ACTION]++;
  1378. break;
  1379. }
  1380. } else if (ieee80211_is_ctl(fc)) {
  1381. switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
  1382. case cpu_to_le16(IEEE80211_STYPE_BACK_REQ):
  1383. stats->ctrl[CONTROL_BACK_REQ]++;
  1384. break;
  1385. case cpu_to_le16(IEEE80211_STYPE_BACK):
  1386. stats->ctrl[CONTROL_BACK]++;
  1387. break;
  1388. case cpu_to_le16(IEEE80211_STYPE_PSPOLL):
  1389. stats->ctrl[CONTROL_PSPOLL]++;
  1390. break;
  1391. case cpu_to_le16(IEEE80211_STYPE_RTS):
  1392. stats->ctrl[CONTROL_RTS]++;
  1393. break;
  1394. case cpu_to_le16(IEEE80211_STYPE_CTS):
  1395. stats->ctrl[CONTROL_CTS]++;
  1396. break;
  1397. case cpu_to_le16(IEEE80211_STYPE_ACK):
  1398. stats->ctrl[CONTROL_ACK]++;
  1399. break;
  1400. case cpu_to_le16(IEEE80211_STYPE_CFEND):
  1401. stats->ctrl[CONTROL_CFEND]++;
  1402. break;
  1403. case cpu_to_le16(IEEE80211_STYPE_CFENDACK):
  1404. stats->ctrl[CONTROL_CFENDACK]++;
  1405. break;
  1406. }
  1407. } else {
  1408. /* data */
  1409. stats->data_cnt++;
  1410. stats->data_bytes += len;
  1411. }
  1412. }
  1413. #endif
  1414. static void iwl_force_rf_reset(struct iwl_priv *priv)
  1415. {
  1416. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1417. return;
  1418. if (!iwl_is_any_associated(priv)) {
  1419. IWL_DEBUG_SCAN(priv, "force reset rejected: not associated\n");
  1420. return;
  1421. }
  1422. /*
  1423. * There is no easy and better way to force reset the radio,
  1424. * the only known method is switching channel which will force to
  1425. * reset and tune the radio.
  1426. * Use internal short scan (single channel) operation to should
  1427. * achieve this objective.
  1428. * Driver should reset the radio when number of consecutive missed
  1429. * beacon, or any other uCode error condition detected.
  1430. */
  1431. IWL_DEBUG_INFO(priv, "perform radio reset.\n");
  1432. iwl_internal_short_hw_scan(priv);
  1433. }
  1434. int iwl_force_reset(struct iwl_priv *priv, int mode, bool external)
  1435. {
  1436. struct iwl_force_reset *force_reset;
  1437. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1438. return -EINVAL;
  1439. if (mode >= IWL_MAX_FORCE_RESET) {
  1440. IWL_DEBUG_INFO(priv, "invalid reset request.\n");
  1441. return -EINVAL;
  1442. }
  1443. force_reset = &priv->force_reset[mode];
  1444. force_reset->reset_request_count++;
  1445. if (!external) {
  1446. if (force_reset->last_force_reset_jiffies &&
  1447. time_after(force_reset->last_force_reset_jiffies +
  1448. force_reset->reset_duration, jiffies)) {
  1449. IWL_DEBUG_INFO(priv, "force reset rejected\n");
  1450. force_reset->reset_reject_count++;
  1451. return -EAGAIN;
  1452. }
  1453. }
  1454. force_reset->reset_success_count++;
  1455. force_reset->last_force_reset_jiffies = jiffies;
  1456. IWL_DEBUG_INFO(priv, "perform force reset (%d)\n", mode);
  1457. switch (mode) {
  1458. case IWL_RF_RESET:
  1459. iwl_force_rf_reset(priv);
  1460. break;
  1461. case IWL_FW_RESET:
  1462. /*
  1463. * if the request is from external(ex: debugfs),
  1464. * then always perform the request in regardless the module
  1465. * parameter setting
  1466. * if the request is from internal (uCode error or driver
  1467. * detect failure), then fw_restart module parameter
  1468. * need to be check before performing firmware reload
  1469. */
  1470. if (!external && !iwlagn_mod_params.restart_fw) {
  1471. IWL_DEBUG_INFO(priv, "Cancel firmware reload based on "
  1472. "module parameter setting\n");
  1473. break;
  1474. }
  1475. IWL_ERR(priv, "On demand firmware reload\n");
  1476. iwlagn_fw_error(priv, true);
  1477. break;
  1478. }
  1479. return 0;
  1480. }
  1481. int iwl_mac_change_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  1482. enum nl80211_iftype newtype, bool newp2p)
  1483. {
  1484. struct iwl_priv *priv = hw->priv;
  1485. struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif);
  1486. struct iwl_rxon_context *bss_ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  1487. struct iwl_rxon_context *tmp;
  1488. u32 interface_modes;
  1489. int err;
  1490. newtype = ieee80211_iftype_p2p(newtype, newp2p);
  1491. mutex_lock(&priv->mutex);
  1492. if (!ctx->vif || !iwl_is_ready_rf(priv)) {
  1493. /*
  1494. * Huh? But wait ... this can maybe happen when
  1495. * we're in the middle of a firmware restart!
  1496. */
  1497. err = -EBUSY;
  1498. goto out;
  1499. }
  1500. interface_modes = ctx->interface_modes | ctx->exclusive_interface_modes;
  1501. if (!(interface_modes & BIT(newtype))) {
  1502. err = -EBUSY;
  1503. goto out;
  1504. }
  1505. /*
  1506. * Refuse a change that should be done by moving from the PAN
  1507. * context to the BSS context instead, if the BSS context is
  1508. * available and can support the new interface type.
  1509. */
  1510. if (ctx->ctxid == IWL_RXON_CTX_PAN && !bss_ctx->vif &&
  1511. (bss_ctx->interface_modes & BIT(newtype) ||
  1512. bss_ctx->exclusive_interface_modes & BIT(newtype))) {
  1513. BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
  1514. err = -EBUSY;
  1515. goto out;
  1516. }
  1517. if (ctx->exclusive_interface_modes & BIT(newtype)) {
  1518. for_each_context(priv, tmp) {
  1519. if (ctx == tmp)
  1520. continue;
  1521. if (!tmp->vif)
  1522. continue;
  1523. /*
  1524. * The current mode switch would be exclusive, but
  1525. * another context is active ... refuse the switch.
  1526. */
  1527. err = -EBUSY;
  1528. goto out;
  1529. }
  1530. }
  1531. /* success */
  1532. iwl_teardown_interface(priv, vif, true);
  1533. vif->type = newtype;
  1534. vif->p2p = newp2p;
  1535. err = iwl_setup_interface(priv, ctx);
  1536. WARN_ON(err);
  1537. /*
  1538. * We've switched internally, but submitting to the
  1539. * device may have failed for some reason. Mask this
  1540. * error, because otherwise mac80211 will not switch
  1541. * (and set the interface type back) and we'll be
  1542. * out of sync with it.
  1543. */
  1544. err = 0;
  1545. out:
  1546. mutex_unlock(&priv->mutex);
  1547. return err;
  1548. }
  1549. /*
  1550. * On every watchdog tick we check (latest) time stamp. If it does not
  1551. * change during timeout period and queue is not empty we reset firmware.
  1552. */
  1553. static int iwl_check_stuck_queue(struct iwl_priv *priv, int cnt)
  1554. {
  1555. struct iwl_tx_queue *txq = &priv->txq[cnt];
  1556. struct iwl_queue *q = &txq->q;
  1557. unsigned long timeout;
  1558. int ret;
  1559. if (q->read_ptr == q->write_ptr) {
  1560. txq->time_stamp = jiffies;
  1561. return 0;
  1562. }
  1563. timeout = txq->time_stamp +
  1564. msecs_to_jiffies(priv->cfg->base_params->wd_timeout);
  1565. if (time_after(jiffies, timeout)) {
  1566. IWL_ERR(priv, "Queue %d stuck for %u ms.\n",
  1567. q->id, priv->cfg->base_params->wd_timeout);
  1568. ret = iwl_force_reset(priv, IWL_FW_RESET, false);
  1569. return (ret == -EAGAIN) ? 0 : 1;
  1570. }
  1571. return 0;
  1572. }
  1573. /*
  1574. * Making watchdog tick be a quarter of timeout assure we will
  1575. * discover the queue hung between timeout and 1.25*timeout
  1576. */
  1577. #define IWL_WD_TICK(timeout) ((timeout) / 4)
  1578. /*
  1579. * Watchdog timer callback, we check each tx queue for stuck, if if hung
  1580. * we reset the firmware. If everything is fine just rearm the timer.
  1581. */
  1582. void iwl_bg_watchdog(unsigned long data)
  1583. {
  1584. struct iwl_priv *priv = (struct iwl_priv *)data;
  1585. int cnt;
  1586. unsigned long timeout;
  1587. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1588. return;
  1589. timeout = priv->cfg->base_params->wd_timeout;
  1590. if (timeout == 0)
  1591. return;
  1592. /* monitor and check for stuck cmd queue */
  1593. if (iwl_check_stuck_queue(priv, priv->cmd_queue))
  1594. return;
  1595. /* monitor and check for other stuck queues */
  1596. if (iwl_is_any_associated(priv)) {
  1597. for (cnt = 0; cnt < priv->hw_params.max_txq_num; cnt++) {
  1598. /* skip as we already checked the command queue */
  1599. if (cnt == priv->cmd_queue)
  1600. continue;
  1601. if (iwl_check_stuck_queue(priv, cnt))
  1602. return;
  1603. }
  1604. }
  1605. mod_timer(&priv->watchdog, jiffies +
  1606. msecs_to_jiffies(IWL_WD_TICK(timeout)));
  1607. }
  1608. void iwl_setup_watchdog(struct iwl_priv *priv)
  1609. {
  1610. unsigned int timeout = priv->cfg->base_params->wd_timeout;
  1611. if (timeout)
  1612. mod_timer(&priv->watchdog,
  1613. jiffies + msecs_to_jiffies(IWL_WD_TICK(timeout)));
  1614. else
  1615. del_timer(&priv->watchdog);
  1616. }
  1617. /*
  1618. * extended beacon time format
  1619. * time in usec will be changed into a 32-bit value in extended:internal format
  1620. * the extended part is the beacon counts
  1621. * the internal part is the time in usec within one beacon interval
  1622. */
  1623. u32 iwl_usecs_to_beacons(struct iwl_priv *priv, u32 usec, u32 beacon_interval)
  1624. {
  1625. u32 quot;
  1626. u32 rem;
  1627. u32 interval = beacon_interval * TIME_UNIT;
  1628. if (!interval || !usec)
  1629. return 0;
  1630. quot = (usec / interval) &
  1631. (iwl_beacon_time_mask_high(priv,
  1632. priv->hw_params.beacon_time_tsf_bits) >>
  1633. priv->hw_params.beacon_time_tsf_bits);
  1634. rem = (usec % interval) & iwl_beacon_time_mask_low(priv,
  1635. priv->hw_params.beacon_time_tsf_bits);
  1636. return (quot << priv->hw_params.beacon_time_tsf_bits) + rem;
  1637. }
  1638. /* base is usually what we get from ucode with each received frame,
  1639. * the same as HW timer counter counting down
  1640. */
  1641. __le32 iwl_add_beacon_time(struct iwl_priv *priv, u32 base,
  1642. u32 addon, u32 beacon_interval)
  1643. {
  1644. u32 base_low = base & iwl_beacon_time_mask_low(priv,
  1645. priv->hw_params.beacon_time_tsf_bits);
  1646. u32 addon_low = addon & iwl_beacon_time_mask_low(priv,
  1647. priv->hw_params.beacon_time_tsf_bits);
  1648. u32 interval = beacon_interval * TIME_UNIT;
  1649. u32 res = (base & iwl_beacon_time_mask_high(priv,
  1650. priv->hw_params.beacon_time_tsf_bits)) +
  1651. (addon & iwl_beacon_time_mask_high(priv,
  1652. priv->hw_params.beacon_time_tsf_bits));
  1653. if (base_low > addon_low)
  1654. res += base_low - addon_low;
  1655. else if (base_low < addon_low) {
  1656. res += interval + base_low - addon_low;
  1657. res += (1 << priv->hw_params.beacon_time_tsf_bits);
  1658. } else
  1659. res += (1 << priv->hw_params.beacon_time_tsf_bits);
  1660. return cpu_to_le32(res);
  1661. }
  1662. #ifdef CONFIG_PM
  1663. int iwl_pci_suspend(struct device *device)
  1664. {
  1665. struct pci_dev *pdev = to_pci_dev(device);
  1666. struct iwl_priv *priv = pci_get_drvdata(pdev);
  1667. /*
  1668. * This function is called when system goes into suspend state
  1669. * mac80211 will call iwl_mac_stop() from the mac80211 suspend function
  1670. * first but since iwl_mac_stop() has no knowledge of who the caller is,
  1671. * it will not call apm_ops.stop() to stop the DMA operation.
  1672. * Calling apm_ops.stop here to make sure we stop the DMA.
  1673. */
  1674. iwl_apm_stop(priv);
  1675. return 0;
  1676. }
  1677. int iwl_pci_resume(struct device *device)
  1678. {
  1679. struct pci_dev *pdev = to_pci_dev(device);
  1680. struct iwl_priv *priv = pci_get_drvdata(pdev);
  1681. bool hw_rfkill = false;
  1682. /*
  1683. * We disable the RETRY_TIMEOUT register (0x41) to keep
  1684. * PCI Tx retries from interfering with C3 CPU state.
  1685. */
  1686. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  1687. iwl_enable_interrupts(priv);
  1688. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  1689. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  1690. hw_rfkill = true;
  1691. if (hw_rfkill)
  1692. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1693. else
  1694. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1695. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rfkill);
  1696. return 0;
  1697. }
  1698. const struct dev_pm_ops iwl_pm_ops = {
  1699. .suspend = iwl_pci_suspend,
  1700. .resume = iwl_pci_resume,
  1701. .freeze = iwl_pci_suspend,
  1702. .thaw = iwl_pci_resume,
  1703. .poweroff = iwl_pci_suspend,
  1704. .restore = iwl_pci_resume,
  1705. };
  1706. #endif /* CONFIG_PM */