cnic.c 139 KB

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  1. /* cnic.c: Broadcom CNIC core network driver.
  2. *
  3. * Copyright (c) 2006-2010 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
  10. * Modified and maintained by: Michael Chan <mchan@broadcom.com>
  11. */
  12. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/errno.h>
  16. #include <linux/list.h>
  17. #include <linux/slab.h>
  18. #include <linux/pci.h>
  19. #include <linux/init.h>
  20. #include <linux/netdevice.h>
  21. #include <linux/uio_driver.h>
  22. #include <linux/in.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/delay.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/if_vlan.h>
  27. #include <linux/prefetch.h>
  28. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  29. #define BCM_VLAN 1
  30. #endif
  31. #include <net/ip.h>
  32. #include <net/tcp.h>
  33. #include <net/route.h>
  34. #include <net/ipv6.h>
  35. #include <net/ip6_route.h>
  36. #include <net/ip6_checksum.h>
  37. #include <scsi/iscsi_if.h>
  38. #include "cnic_if.h"
  39. #include "bnx2.h"
  40. #include "bnx2x/bnx2x_reg.h"
  41. #include "bnx2x/bnx2x_fw_defs.h"
  42. #include "bnx2x/bnx2x_hsi.h"
  43. #include "../scsi/bnx2i/57xx_iscsi_constants.h"
  44. #include "../scsi/bnx2i/57xx_iscsi_hsi.h"
  45. #include "cnic.h"
  46. #include "cnic_defs.h"
  47. #define DRV_MODULE_NAME "cnic"
  48. static char version[] __devinitdata =
  49. "Broadcom NetXtreme II CNIC Driver " DRV_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
  50. MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
  51. "Chen (zongxi@broadcom.com");
  52. MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver");
  53. MODULE_LICENSE("GPL");
  54. MODULE_VERSION(CNIC_MODULE_VERSION);
  55. /* cnic_dev_list modifications are protected by both rtnl and cnic_dev_lock */
  56. static LIST_HEAD(cnic_dev_list);
  57. static LIST_HEAD(cnic_udev_list);
  58. static DEFINE_RWLOCK(cnic_dev_lock);
  59. static DEFINE_MUTEX(cnic_lock);
  60. static struct cnic_ulp_ops __rcu *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
  61. /* helper function, assuming cnic_lock is held */
  62. static inline struct cnic_ulp_ops *cnic_ulp_tbl_prot(int type)
  63. {
  64. return rcu_dereference_protected(cnic_ulp_tbl[type],
  65. lockdep_is_held(&cnic_lock));
  66. }
  67. static int cnic_service_bnx2(void *, void *);
  68. static int cnic_service_bnx2x(void *, void *);
  69. static int cnic_ctl(void *, struct cnic_ctl_info *);
  70. static struct cnic_ops cnic_bnx2_ops = {
  71. .cnic_owner = THIS_MODULE,
  72. .cnic_handler = cnic_service_bnx2,
  73. .cnic_ctl = cnic_ctl,
  74. };
  75. static struct cnic_ops cnic_bnx2x_ops = {
  76. .cnic_owner = THIS_MODULE,
  77. .cnic_handler = cnic_service_bnx2x,
  78. .cnic_ctl = cnic_ctl,
  79. };
  80. static struct workqueue_struct *cnic_wq;
  81. static void cnic_shutdown_rings(struct cnic_dev *);
  82. static void cnic_init_rings(struct cnic_dev *);
  83. static int cnic_cm_set_pg(struct cnic_sock *);
  84. static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
  85. {
  86. struct cnic_uio_dev *udev = uinfo->priv;
  87. struct cnic_dev *dev;
  88. if (!capable(CAP_NET_ADMIN))
  89. return -EPERM;
  90. if (udev->uio_dev != -1)
  91. return -EBUSY;
  92. rtnl_lock();
  93. dev = udev->dev;
  94. if (!dev || !test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  95. rtnl_unlock();
  96. return -ENODEV;
  97. }
  98. udev->uio_dev = iminor(inode);
  99. cnic_shutdown_rings(dev);
  100. cnic_init_rings(dev);
  101. rtnl_unlock();
  102. return 0;
  103. }
  104. static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
  105. {
  106. struct cnic_uio_dev *udev = uinfo->priv;
  107. udev->uio_dev = -1;
  108. return 0;
  109. }
  110. static inline void cnic_hold(struct cnic_dev *dev)
  111. {
  112. atomic_inc(&dev->ref_count);
  113. }
  114. static inline void cnic_put(struct cnic_dev *dev)
  115. {
  116. atomic_dec(&dev->ref_count);
  117. }
  118. static inline void csk_hold(struct cnic_sock *csk)
  119. {
  120. atomic_inc(&csk->ref_count);
  121. }
  122. static inline void csk_put(struct cnic_sock *csk)
  123. {
  124. atomic_dec(&csk->ref_count);
  125. }
  126. static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
  127. {
  128. struct cnic_dev *cdev;
  129. read_lock(&cnic_dev_lock);
  130. list_for_each_entry(cdev, &cnic_dev_list, list) {
  131. if (netdev == cdev->netdev) {
  132. cnic_hold(cdev);
  133. read_unlock(&cnic_dev_lock);
  134. return cdev;
  135. }
  136. }
  137. read_unlock(&cnic_dev_lock);
  138. return NULL;
  139. }
  140. static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
  141. {
  142. atomic_inc(&ulp_ops->ref_count);
  143. }
  144. static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
  145. {
  146. atomic_dec(&ulp_ops->ref_count);
  147. }
  148. static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
  149. {
  150. struct cnic_local *cp = dev->cnic_priv;
  151. struct cnic_eth_dev *ethdev = cp->ethdev;
  152. struct drv_ctl_info info;
  153. struct drv_ctl_io *io = &info.data.io;
  154. info.cmd = DRV_CTL_CTX_WR_CMD;
  155. io->cid_addr = cid_addr;
  156. io->offset = off;
  157. io->data = val;
  158. ethdev->drv_ctl(dev->netdev, &info);
  159. }
  160. static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
  161. {
  162. struct cnic_local *cp = dev->cnic_priv;
  163. struct cnic_eth_dev *ethdev = cp->ethdev;
  164. struct drv_ctl_info info;
  165. struct drv_ctl_io *io = &info.data.io;
  166. info.cmd = DRV_CTL_CTXTBL_WR_CMD;
  167. io->offset = off;
  168. io->dma_addr = addr;
  169. ethdev->drv_ctl(dev->netdev, &info);
  170. }
  171. static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
  172. {
  173. struct cnic_local *cp = dev->cnic_priv;
  174. struct cnic_eth_dev *ethdev = cp->ethdev;
  175. struct drv_ctl_info info;
  176. struct drv_ctl_l2_ring *ring = &info.data.ring;
  177. if (start)
  178. info.cmd = DRV_CTL_START_L2_CMD;
  179. else
  180. info.cmd = DRV_CTL_STOP_L2_CMD;
  181. ring->cid = cid;
  182. ring->client_id = cl_id;
  183. ethdev->drv_ctl(dev->netdev, &info);
  184. }
  185. static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
  186. {
  187. struct cnic_local *cp = dev->cnic_priv;
  188. struct cnic_eth_dev *ethdev = cp->ethdev;
  189. struct drv_ctl_info info;
  190. struct drv_ctl_io *io = &info.data.io;
  191. info.cmd = DRV_CTL_IO_WR_CMD;
  192. io->offset = off;
  193. io->data = val;
  194. ethdev->drv_ctl(dev->netdev, &info);
  195. }
  196. static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
  197. {
  198. struct cnic_local *cp = dev->cnic_priv;
  199. struct cnic_eth_dev *ethdev = cp->ethdev;
  200. struct drv_ctl_info info;
  201. struct drv_ctl_io *io = &info.data.io;
  202. info.cmd = DRV_CTL_IO_RD_CMD;
  203. io->offset = off;
  204. ethdev->drv_ctl(dev->netdev, &info);
  205. return io->data;
  206. }
  207. static int cnic_in_use(struct cnic_sock *csk)
  208. {
  209. return test_bit(SK_F_INUSE, &csk->flags);
  210. }
  211. static void cnic_spq_completion(struct cnic_dev *dev, int cmd, u32 count)
  212. {
  213. struct cnic_local *cp = dev->cnic_priv;
  214. struct cnic_eth_dev *ethdev = cp->ethdev;
  215. struct drv_ctl_info info;
  216. info.cmd = cmd;
  217. info.data.credit.credit_count = count;
  218. ethdev->drv_ctl(dev->netdev, &info);
  219. }
  220. static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
  221. {
  222. u32 i;
  223. for (i = 0; i < cp->max_cid_space; i++) {
  224. if (cp->ctx_tbl[i].cid == cid) {
  225. *l5_cid = i;
  226. return 0;
  227. }
  228. }
  229. return -EINVAL;
  230. }
  231. static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
  232. struct cnic_sock *csk)
  233. {
  234. struct iscsi_path path_req;
  235. char *buf = NULL;
  236. u16 len = 0;
  237. u32 msg_type = ISCSI_KEVENT_IF_DOWN;
  238. struct cnic_ulp_ops *ulp_ops;
  239. struct cnic_uio_dev *udev = cp->udev;
  240. int rc = 0, retry = 0;
  241. if (!udev || udev->uio_dev == -1)
  242. return -ENODEV;
  243. if (csk) {
  244. len = sizeof(path_req);
  245. buf = (char *) &path_req;
  246. memset(&path_req, 0, len);
  247. msg_type = ISCSI_KEVENT_PATH_REQ;
  248. path_req.handle = (u64) csk->l5_cid;
  249. if (test_bit(SK_F_IPV6, &csk->flags)) {
  250. memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
  251. sizeof(struct in6_addr));
  252. path_req.ip_addr_len = 16;
  253. } else {
  254. memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
  255. sizeof(struct in_addr));
  256. path_req.ip_addr_len = 4;
  257. }
  258. path_req.vlan_id = csk->vlan_id;
  259. path_req.pmtu = csk->mtu;
  260. }
  261. while (retry < 3) {
  262. rc = 0;
  263. rcu_read_lock();
  264. ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
  265. if (ulp_ops)
  266. rc = ulp_ops->iscsi_nl_send_msg(
  267. cp->ulp_handle[CNIC_ULP_ISCSI],
  268. msg_type, buf, len);
  269. rcu_read_unlock();
  270. if (rc == 0 || msg_type != ISCSI_KEVENT_PATH_REQ)
  271. break;
  272. msleep(100);
  273. retry++;
  274. }
  275. return 0;
  276. }
  277. static void cnic_cm_upcall(struct cnic_local *, struct cnic_sock *, u8);
  278. static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
  279. char *buf, u16 len)
  280. {
  281. int rc = -EINVAL;
  282. switch (msg_type) {
  283. case ISCSI_UEVENT_PATH_UPDATE: {
  284. struct cnic_local *cp;
  285. u32 l5_cid;
  286. struct cnic_sock *csk;
  287. struct iscsi_path *path_resp;
  288. if (len < sizeof(*path_resp))
  289. break;
  290. path_resp = (struct iscsi_path *) buf;
  291. cp = dev->cnic_priv;
  292. l5_cid = (u32) path_resp->handle;
  293. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  294. break;
  295. rcu_read_lock();
  296. if (!rcu_dereference(cp->ulp_ops[CNIC_ULP_L4])) {
  297. rc = -ENODEV;
  298. rcu_read_unlock();
  299. break;
  300. }
  301. csk = &cp->csk_tbl[l5_cid];
  302. csk_hold(csk);
  303. if (cnic_in_use(csk) &&
  304. test_bit(SK_F_CONNECT_START, &csk->flags)) {
  305. memcpy(csk->ha, path_resp->mac_addr, 6);
  306. if (test_bit(SK_F_IPV6, &csk->flags))
  307. memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
  308. sizeof(struct in6_addr));
  309. else
  310. memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
  311. sizeof(struct in_addr));
  312. if (is_valid_ether_addr(csk->ha)) {
  313. cnic_cm_set_pg(csk);
  314. } else if (!test_bit(SK_F_OFFLD_SCHED, &csk->flags) &&
  315. !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  316. cnic_cm_upcall(cp, csk,
  317. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  318. clear_bit(SK_F_CONNECT_START, &csk->flags);
  319. }
  320. }
  321. csk_put(csk);
  322. rcu_read_unlock();
  323. rc = 0;
  324. }
  325. }
  326. return rc;
  327. }
  328. static int cnic_offld_prep(struct cnic_sock *csk)
  329. {
  330. if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  331. return 0;
  332. if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
  333. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  334. return 0;
  335. }
  336. return 1;
  337. }
  338. static int cnic_close_prep(struct cnic_sock *csk)
  339. {
  340. clear_bit(SK_F_CONNECT_START, &csk->flags);
  341. smp_mb__after_clear_bit();
  342. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  343. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  344. msleep(1);
  345. return 1;
  346. }
  347. return 0;
  348. }
  349. static int cnic_abort_prep(struct cnic_sock *csk)
  350. {
  351. clear_bit(SK_F_CONNECT_START, &csk->flags);
  352. smp_mb__after_clear_bit();
  353. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  354. msleep(1);
  355. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  356. csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  357. return 1;
  358. }
  359. return 0;
  360. }
  361. int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
  362. {
  363. struct cnic_dev *dev;
  364. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  365. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  366. return -EINVAL;
  367. }
  368. mutex_lock(&cnic_lock);
  369. if (cnic_ulp_tbl_prot(ulp_type)) {
  370. pr_err("%s: Type %d has already been registered\n",
  371. __func__, ulp_type);
  372. mutex_unlock(&cnic_lock);
  373. return -EBUSY;
  374. }
  375. read_lock(&cnic_dev_lock);
  376. list_for_each_entry(dev, &cnic_dev_list, list) {
  377. struct cnic_local *cp = dev->cnic_priv;
  378. clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
  379. }
  380. read_unlock(&cnic_dev_lock);
  381. atomic_set(&ulp_ops->ref_count, 0);
  382. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
  383. mutex_unlock(&cnic_lock);
  384. /* Prevent race conditions with netdev_event */
  385. rtnl_lock();
  386. list_for_each_entry(dev, &cnic_dev_list, list) {
  387. struct cnic_local *cp = dev->cnic_priv;
  388. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
  389. ulp_ops->cnic_init(dev);
  390. }
  391. rtnl_unlock();
  392. return 0;
  393. }
  394. int cnic_unregister_driver(int ulp_type)
  395. {
  396. struct cnic_dev *dev;
  397. struct cnic_ulp_ops *ulp_ops;
  398. int i = 0;
  399. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  400. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  401. return -EINVAL;
  402. }
  403. mutex_lock(&cnic_lock);
  404. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  405. if (!ulp_ops) {
  406. pr_err("%s: Type %d has not been registered\n",
  407. __func__, ulp_type);
  408. goto out_unlock;
  409. }
  410. read_lock(&cnic_dev_lock);
  411. list_for_each_entry(dev, &cnic_dev_list, list) {
  412. struct cnic_local *cp = dev->cnic_priv;
  413. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  414. pr_err("%s: Type %d still has devices registered\n",
  415. __func__, ulp_type);
  416. read_unlock(&cnic_dev_lock);
  417. goto out_unlock;
  418. }
  419. }
  420. read_unlock(&cnic_dev_lock);
  421. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], NULL);
  422. mutex_unlock(&cnic_lock);
  423. synchronize_rcu();
  424. while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
  425. msleep(100);
  426. i++;
  427. }
  428. if (atomic_read(&ulp_ops->ref_count) != 0)
  429. netdev_warn(dev->netdev, "Failed waiting for ref count to go to zero\n");
  430. return 0;
  431. out_unlock:
  432. mutex_unlock(&cnic_lock);
  433. return -EINVAL;
  434. }
  435. static int cnic_start_hw(struct cnic_dev *);
  436. static void cnic_stop_hw(struct cnic_dev *);
  437. static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
  438. void *ulp_ctx)
  439. {
  440. struct cnic_local *cp = dev->cnic_priv;
  441. struct cnic_ulp_ops *ulp_ops;
  442. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  443. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  444. return -EINVAL;
  445. }
  446. mutex_lock(&cnic_lock);
  447. if (cnic_ulp_tbl_prot(ulp_type) == NULL) {
  448. pr_err("%s: Driver with type %d has not been registered\n",
  449. __func__, ulp_type);
  450. mutex_unlock(&cnic_lock);
  451. return -EAGAIN;
  452. }
  453. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  454. pr_err("%s: Type %d has already been registered to this device\n",
  455. __func__, ulp_type);
  456. mutex_unlock(&cnic_lock);
  457. return -EBUSY;
  458. }
  459. clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
  460. cp->ulp_handle[ulp_type] = ulp_ctx;
  461. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  462. rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
  463. cnic_hold(dev);
  464. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  465. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
  466. ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
  467. mutex_unlock(&cnic_lock);
  468. return 0;
  469. }
  470. EXPORT_SYMBOL(cnic_register_driver);
  471. static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
  472. {
  473. struct cnic_local *cp = dev->cnic_priv;
  474. int i = 0;
  475. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  476. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  477. return -EINVAL;
  478. }
  479. mutex_lock(&cnic_lock);
  480. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  481. rcu_assign_pointer(cp->ulp_ops[ulp_type], NULL);
  482. cnic_put(dev);
  483. } else {
  484. pr_err("%s: device not registered to this ulp type %d\n",
  485. __func__, ulp_type);
  486. mutex_unlock(&cnic_lock);
  487. return -EINVAL;
  488. }
  489. mutex_unlock(&cnic_lock);
  490. if (ulp_type == CNIC_ULP_ISCSI)
  491. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  492. synchronize_rcu();
  493. while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
  494. i < 20) {
  495. msleep(100);
  496. i++;
  497. }
  498. if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
  499. netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
  500. return 0;
  501. }
  502. EXPORT_SYMBOL(cnic_unregister_driver);
  503. static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id)
  504. {
  505. id_tbl->start = start_id;
  506. id_tbl->max = size;
  507. id_tbl->next = 0;
  508. spin_lock_init(&id_tbl->lock);
  509. id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
  510. if (!id_tbl->table)
  511. return -ENOMEM;
  512. return 0;
  513. }
  514. static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
  515. {
  516. kfree(id_tbl->table);
  517. id_tbl->table = NULL;
  518. }
  519. static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
  520. {
  521. int ret = -1;
  522. id -= id_tbl->start;
  523. if (id >= id_tbl->max)
  524. return ret;
  525. spin_lock(&id_tbl->lock);
  526. if (!test_bit(id, id_tbl->table)) {
  527. set_bit(id, id_tbl->table);
  528. ret = 0;
  529. }
  530. spin_unlock(&id_tbl->lock);
  531. return ret;
  532. }
  533. /* Returns -1 if not successful */
  534. static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
  535. {
  536. u32 id;
  537. spin_lock(&id_tbl->lock);
  538. id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
  539. if (id >= id_tbl->max) {
  540. id = -1;
  541. if (id_tbl->next != 0) {
  542. id = find_first_zero_bit(id_tbl->table, id_tbl->next);
  543. if (id >= id_tbl->next)
  544. id = -1;
  545. }
  546. }
  547. if (id < id_tbl->max) {
  548. set_bit(id, id_tbl->table);
  549. id_tbl->next = (id + 1) & (id_tbl->max - 1);
  550. id += id_tbl->start;
  551. }
  552. spin_unlock(&id_tbl->lock);
  553. return id;
  554. }
  555. static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
  556. {
  557. if (id == -1)
  558. return;
  559. id -= id_tbl->start;
  560. if (id >= id_tbl->max)
  561. return;
  562. clear_bit(id, id_tbl->table);
  563. }
  564. static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
  565. {
  566. int i;
  567. if (!dma->pg_arr)
  568. return;
  569. for (i = 0; i < dma->num_pages; i++) {
  570. if (dma->pg_arr[i]) {
  571. dma_free_coherent(&dev->pcidev->dev, BCM_PAGE_SIZE,
  572. dma->pg_arr[i], dma->pg_map_arr[i]);
  573. dma->pg_arr[i] = NULL;
  574. }
  575. }
  576. if (dma->pgtbl) {
  577. dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  578. dma->pgtbl, dma->pgtbl_map);
  579. dma->pgtbl = NULL;
  580. }
  581. kfree(dma->pg_arr);
  582. dma->pg_arr = NULL;
  583. dma->num_pages = 0;
  584. }
  585. static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
  586. {
  587. int i;
  588. __le32 *page_table = (__le32 *) dma->pgtbl;
  589. for (i = 0; i < dma->num_pages; i++) {
  590. /* Each entry needs to be in big endian format. */
  591. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  592. page_table++;
  593. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  594. page_table++;
  595. }
  596. }
  597. static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
  598. {
  599. int i;
  600. __le32 *page_table = (__le32 *) dma->pgtbl;
  601. for (i = 0; i < dma->num_pages; i++) {
  602. /* Each entry needs to be in little endian format. */
  603. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  604. page_table++;
  605. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  606. page_table++;
  607. }
  608. }
  609. static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
  610. int pages, int use_pg_tbl)
  611. {
  612. int i, size;
  613. struct cnic_local *cp = dev->cnic_priv;
  614. size = pages * (sizeof(void *) + sizeof(dma_addr_t));
  615. dma->pg_arr = kzalloc(size, GFP_ATOMIC);
  616. if (dma->pg_arr == NULL)
  617. return -ENOMEM;
  618. dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
  619. dma->num_pages = pages;
  620. for (i = 0; i < pages; i++) {
  621. dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
  622. BCM_PAGE_SIZE,
  623. &dma->pg_map_arr[i],
  624. GFP_ATOMIC);
  625. if (dma->pg_arr[i] == NULL)
  626. goto error;
  627. }
  628. if (!use_pg_tbl)
  629. return 0;
  630. dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) &
  631. ~(BCM_PAGE_SIZE - 1);
  632. dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  633. &dma->pgtbl_map, GFP_ATOMIC);
  634. if (dma->pgtbl == NULL)
  635. goto error;
  636. cp->setup_pgtbl(dev, dma);
  637. return 0;
  638. error:
  639. cnic_free_dma(dev, dma);
  640. return -ENOMEM;
  641. }
  642. static void cnic_free_context(struct cnic_dev *dev)
  643. {
  644. struct cnic_local *cp = dev->cnic_priv;
  645. int i;
  646. for (i = 0; i < cp->ctx_blks; i++) {
  647. if (cp->ctx_arr[i].ctx) {
  648. dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  649. cp->ctx_arr[i].ctx,
  650. cp->ctx_arr[i].mapping);
  651. cp->ctx_arr[i].ctx = NULL;
  652. }
  653. }
  654. }
  655. static void __cnic_free_uio(struct cnic_uio_dev *udev)
  656. {
  657. uio_unregister_device(&udev->cnic_uinfo);
  658. if (udev->l2_buf) {
  659. dma_free_coherent(&udev->pdev->dev, udev->l2_buf_size,
  660. udev->l2_buf, udev->l2_buf_map);
  661. udev->l2_buf = NULL;
  662. }
  663. if (udev->l2_ring) {
  664. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  665. udev->l2_ring, udev->l2_ring_map);
  666. udev->l2_ring = NULL;
  667. }
  668. pci_dev_put(udev->pdev);
  669. kfree(udev);
  670. }
  671. static void cnic_free_uio(struct cnic_uio_dev *udev)
  672. {
  673. if (!udev)
  674. return;
  675. write_lock(&cnic_dev_lock);
  676. list_del_init(&udev->list);
  677. write_unlock(&cnic_dev_lock);
  678. __cnic_free_uio(udev);
  679. }
  680. static void cnic_free_resc(struct cnic_dev *dev)
  681. {
  682. struct cnic_local *cp = dev->cnic_priv;
  683. struct cnic_uio_dev *udev = cp->udev;
  684. if (udev) {
  685. udev->dev = NULL;
  686. cp->udev = NULL;
  687. }
  688. cnic_free_context(dev);
  689. kfree(cp->ctx_arr);
  690. cp->ctx_arr = NULL;
  691. cp->ctx_blks = 0;
  692. cnic_free_dma(dev, &cp->gbl_buf_info);
  693. cnic_free_dma(dev, &cp->conn_buf_info);
  694. cnic_free_dma(dev, &cp->kwq_info);
  695. cnic_free_dma(dev, &cp->kwq_16_data_info);
  696. cnic_free_dma(dev, &cp->kcq2.dma);
  697. cnic_free_dma(dev, &cp->kcq1.dma);
  698. kfree(cp->iscsi_tbl);
  699. cp->iscsi_tbl = NULL;
  700. kfree(cp->ctx_tbl);
  701. cp->ctx_tbl = NULL;
  702. cnic_free_id_tbl(&cp->fcoe_cid_tbl);
  703. cnic_free_id_tbl(&cp->cid_tbl);
  704. }
  705. static int cnic_alloc_context(struct cnic_dev *dev)
  706. {
  707. struct cnic_local *cp = dev->cnic_priv;
  708. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  709. int i, k, arr_size;
  710. cp->ctx_blk_size = BCM_PAGE_SIZE;
  711. cp->cids_per_blk = BCM_PAGE_SIZE / 128;
  712. arr_size = BNX2_MAX_CID / cp->cids_per_blk *
  713. sizeof(struct cnic_ctx);
  714. cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
  715. if (cp->ctx_arr == NULL)
  716. return -ENOMEM;
  717. k = 0;
  718. for (i = 0; i < 2; i++) {
  719. u32 j, reg, off, lo, hi;
  720. if (i == 0)
  721. off = BNX2_PG_CTX_MAP;
  722. else
  723. off = BNX2_ISCSI_CTX_MAP;
  724. reg = cnic_reg_rd_ind(dev, off);
  725. lo = reg >> 16;
  726. hi = reg & 0xffff;
  727. for (j = lo; j < hi; j += cp->cids_per_blk, k++)
  728. cp->ctx_arr[k].cid = j;
  729. }
  730. cp->ctx_blks = k;
  731. if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
  732. cp->ctx_blks = 0;
  733. return -ENOMEM;
  734. }
  735. for (i = 0; i < cp->ctx_blks; i++) {
  736. cp->ctx_arr[i].ctx =
  737. dma_alloc_coherent(&dev->pcidev->dev,
  738. BCM_PAGE_SIZE,
  739. &cp->ctx_arr[i].mapping,
  740. GFP_KERNEL);
  741. if (cp->ctx_arr[i].ctx == NULL)
  742. return -ENOMEM;
  743. }
  744. }
  745. return 0;
  746. }
  747. static int cnic_alloc_kcq(struct cnic_dev *dev, struct kcq_info *info)
  748. {
  749. int err, i, is_bnx2 = 0;
  750. struct kcqe **kcq;
  751. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags))
  752. is_bnx2 = 1;
  753. err = cnic_alloc_dma(dev, &info->dma, KCQ_PAGE_CNT, is_bnx2);
  754. if (err)
  755. return err;
  756. kcq = (struct kcqe **) info->dma.pg_arr;
  757. info->kcq = kcq;
  758. if (is_bnx2)
  759. return 0;
  760. for (i = 0; i < KCQ_PAGE_CNT; i++) {
  761. struct bnx2x_bd_chain_next *next =
  762. (struct bnx2x_bd_chain_next *) &kcq[i][MAX_KCQE_CNT];
  763. int j = i + 1;
  764. if (j >= KCQ_PAGE_CNT)
  765. j = 0;
  766. next->addr_hi = (u64) info->dma.pg_map_arr[j] >> 32;
  767. next->addr_lo = info->dma.pg_map_arr[j] & 0xffffffff;
  768. }
  769. return 0;
  770. }
  771. static int cnic_alloc_uio_rings(struct cnic_dev *dev, int pages)
  772. {
  773. struct cnic_local *cp = dev->cnic_priv;
  774. struct cnic_uio_dev *udev;
  775. read_lock(&cnic_dev_lock);
  776. list_for_each_entry(udev, &cnic_udev_list, list) {
  777. if (udev->pdev == dev->pcidev) {
  778. udev->dev = dev;
  779. cp->udev = udev;
  780. read_unlock(&cnic_dev_lock);
  781. return 0;
  782. }
  783. }
  784. read_unlock(&cnic_dev_lock);
  785. udev = kzalloc(sizeof(struct cnic_uio_dev), GFP_ATOMIC);
  786. if (!udev)
  787. return -ENOMEM;
  788. udev->uio_dev = -1;
  789. udev->dev = dev;
  790. udev->pdev = dev->pcidev;
  791. udev->l2_ring_size = pages * BCM_PAGE_SIZE;
  792. udev->l2_ring = dma_alloc_coherent(&udev->pdev->dev, udev->l2_ring_size,
  793. &udev->l2_ring_map,
  794. GFP_KERNEL | __GFP_COMP);
  795. if (!udev->l2_ring)
  796. goto err_udev;
  797. udev->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
  798. udev->l2_buf_size = PAGE_ALIGN(udev->l2_buf_size);
  799. udev->l2_buf = dma_alloc_coherent(&udev->pdev->dev, udev->l2_buf_size,
  800. &udev->l2_buf_map,
  801. GFP_KERNEL | __GFP_COMP);
  802. if (!udev->l2_buf)
  803. goto err_dma;
  804. write_lock(&cnic_dev_lock);
  805. list_add(&udev->list, &cnic_udev_list);
  806. write_unlock(&cnic_dev_lock);
  807. pci_dev_get(udev->pdev);
  808. cp->udev = udev;
  809. return 0;
  810. err_dma:
  811. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  812. udev->l2_ring, udev->l2_ring_map);
  813. err_udev:
  814. kfree(udev);
  815. return -ENOMEM;
  816. }
  817. static int cnic_init_uio(struct cnic_dev *dev)
  818. {
  819. struct cnic_local *cp = dev->cnic_priv;
  820. struct cnic_uio_dev *udev = cp->udev;
  821. struct uio_info *uinfo;
  822. int ret = 0;
  823. if (!udev)
  824. return -ENOMEM;
  825. uinfo = &udev->cnic_uinfo;
  826. uinfo->mem[0].addr = dev->netdev->base_addr;
  827. uinfo->mem[0].internal_addr = dev->regview;
  828. uinfo->mem[0].size = dev->netdev->mem_end - dev->netdev->mem_start;
  829. uinfo->mem[0].memtype = UIO_MEM_PHYS;
  830. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  831. uinfo->mem[1].addr = (unsigned long) cp->status_blk.gen &
  832. PAGE_MASK;
  833. if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  834. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
  835. else
  836. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
  837. uinfo->name = "bnx2_cnic";
  838. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  839. uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
  840. PAGE_MASK;
  841. uinfo->mem[1].size = sizeof(*cp->bnx2x_def_status_blk);
  842. uinfo->name = "bnx2x_cnic";
  843. }
  844. uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
  845. uinfo->mem[2].addr = (unsigned long) udev->l2_ring;
  846. uinfo->mem[2].size = udev->l2_ring_size;
  847. uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
  848. uinfo->mem[3].addr = (unsigned long) udev->l2_buf;
  849. uinfo->mem[3].size = udev->l2_buf_size;
  850. uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
  851. uinfo->version = CNIC_MODULE_VERSION;
  852. uinfo->irq = UIO_IRQ_CUSTOM;
  853. uinfo->open = cnic_uio_open;
  854. uinfo->release = cnic_uio_close;
  855. if (udev->uio_dev == -1) {
  856. if (!uinfo->priv) {
  857. uinfo->priv = udev;
  858. ret = uio_register_device(&udev->pdev->dev, uinfo);
  859. }
  860. } else {
  861. cnic_init_rings(dev);
  862. }
  863. return ret;
  864. }
  865. static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
  866. {
  867. struct cnic_local *cp = dev->cnic_priv;
  868. int ret;
  869. ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
  870. if (ret)
  871. goto error;
  872. cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
  873. ret = cnic_alloc_kcq(dev, &cp->kcq1);
  874. if (ret)
  875. goto error;
  876. ret = cnic_alloc_context(dev);
  877. if (ret)
  878. goto error;
  879. ret = cnic_alloc_uio_rings(dev, 2);
  880. if (ret)
  881. goto error;
  882. ret = cnic_init_uio(dev);
  883. if (ret)
  884. goto error;
  885. return 0;
  886. error:
  887. cnic_free_resc(dev);
  888. return ret;
  889. }
  890. static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
  891. {
  892. struct cnic_local *cp = dev->cnic_priv;
  893. int ctx_blk_size = cp->ethdev->ctx_blk_size;
  894. int total_mem, blks, i;
  895. total_mem = BNX2X_CONTEXT_MEM_SIZE * cp->max_cid_space;
  896. blks = total_mem / ctx_blk_size;
  897. if (total_mem % ctx_blk_size)
  898. blks++;
  899. if (blks > cp->ethdev->ctx_tbl_len)
  900. return -ENOMEM;
  901. cp->ctx_arr = kcalloc(blks, sizeof(struct cnic_ctx), GFP_KERNEL);
  902. if (cp->ctx_arr == NULL)
  903. return -ENOMEM;
  904. cp->ctx_blks = blks;
  905. cp->ctx_blk_size = ctx_blk_size;
  906. if (!BNX2X_CHIP_IS_57710(cp->chip_id))
  907. cp->ctx_align = 0;
  908. else
  909. cp->ctx_align = ctx_blk_size;
  910. cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
  911. for (i = 0; i < blks; i++) {
  912. cp->ctx_arr[i].ctx =
  913. dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  914. &cp->ctx_arr[i].mapping,
  915. GFP_KERNEL);
  916. if (cp->ctx_arr[i].ctx == NULL)
  917. return -ENOMEM;
  918. if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
  919. if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
  920. cnic_free_context(dev);
  921. cp->ctx_blk_size += cp->ctx_align;
  922. i = -1;
  923. continue;
  924. }
  925. }
  926. }
  927. return 0;
  928. }
  929. static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
  930. {
  931. struct cnic_local *cp = dev->cnic_priv;
  932. struct cnic_eth_dev *ethdev = cp->ethdev;
  933. u32 start_cid = ethdev->starting_cid;
  934. int i, j, n, ret, pages;
  935. struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
  936. cp->iro_arr = ethdev->iro_arr;
  937. cp->max_cid_space = MAX_ISCSI_TBL_SZ + BNX2X_FCOE_NUM_CONNECTIONS;
  938. cp->iscsi_start_cid = start_cid;
  939. cp->fcoe_start_cid = start_cid + MAX_ISCSI_TBL_SZ;
  940. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  941. cp->max_cid_space += BNX2X_FCOE_NUM_CONNECTIONS;
  942. cp->fcoe_init_cid = ethdev->fcoe_init_cid;
  943. if (!cp->fcoe_init_cid)
  944. cp->fcoe_init_cid = 0x10;
  945. }
  946. if (start_cid < BNX2X_ISCSI_START_CID) {
  947. u32 delta = BNX2X_ISCSI_START_CID - start_cid;
  948. cp->iscsi_start_cid = BNX2X_ISCSI_START_CID;
  949. cp->fcoe_start_cid += delta;
  950. cp->max_cid_space += delta;
  951. }
  952. cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ,
  953. GFP_KERNEL);
  954. if (!cp->iscsi_tbl)
  955. goto error;
  956. cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) *
  957. cp->max_cid_space, GFP_KERNEL);
  958. if (!cp->ctx_tbl)
  959. goto error;
  960. for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
  961. cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
  962. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
  963. }
  964. for (i = MAX_ISCSI_TBL_SZ; i < cp->max_cid_space; i++)
  965. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_FCOE;
  966. pages = PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /
  967. PAGE_SIZE;
  968. ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
  969. if (ret)
  970. return -ENOMEM;
  971. n = PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
  972. for (i = 0, j = 0; i < cp->max_cid_space; i++) {
  973. long off = CNIC_KWQ16_DATA_SIZE * (i % n);
  974. cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
  975. cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
  976. off;
  977. if ((i % n) == (n - 1))
  978. j++;
  979. }
  980. ret = cnic_alloc_kcq(dev, &cp->kcq1);
  981. if (ret)
  982. goto error;
  983. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  984. ret = cnic_alloc_kcq(dev, &cp->kcq2);
  985. if (ret)
  986. goto error;
  987. }
  988. pages = PAGE_ALIGN(BNX2X_ISCSI_NUM_CONNECTIONS *
  989. BNX2X_ISCSI_CONN_BUF_SIZE) / PAGE_SIZE;
  990. ret = cnic_alloc_dma(dev, &cp->conn_buf_info, pages, 1);
  991. if (ret)
  992. goto error;
  993. pages = PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / PAGE_SIZE;
  994. ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
  995. if (ret)
  996. goto error;
  997. ret = cnic_alloc_bnx2x_context(dev);
  998. if (ret)
  999. goto error;
  1000. cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
  1001. cp->l2_rx_ring_size = 15;
  1002. ret = cnic_alloc_uio_rings(dev, 4);
  1003. if (ret)
  1004. goto error;
  1005. ret = cnic_init_uio(dev);
  1006. if (ret)
  1007. goto error;
  1008. return 0;
  1009. error:
  1010. cnic_free_resc(dev);
  1011. return -ENOMEM;
  1012. }
  1013. static inline u32 cnic_kwq_avail(struct cnic_local *cp)
  1014. {
  1015. return cp->max_kwq_idx -
  1016. ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
  1017. }
  1018. static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  1019. u32 num_wqes)
  1020. {
  1021. struct cnic_local *cp = dev->cnic_priv;
  1022. struct kwqe *prod_qe;
  1023. u16 prod, sw_prod, i;
  1024. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  1025. return -EAGAIN; /* bnx2 is down */
  1026. spin_lock_bh(&cp->cnic_ulp_lock);
  1027. if (num_wqes > cnic_kwq_avail(cp) &&
  1028. !test_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags)) {
  1029. spin_unlock_bh(&cp->cnic_ulp_lock);
  1030. return -EAGAIN;
  1031. }
  1032. clear_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  1033. prod = cp->kwq_prod_idx;
  1034. sw_prod = prod & MAX_KWQ_IDX;
  1035. for (i = 0; i < num_wqes; i++) {
  1036. prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
  1037. memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
  1038. prod++;
  1039. sw_prod = prod & MAX_KWQ_IDX;
  1040. }
  1041. cp->kwq_prod_idx = prod;
  1042. CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
  1043. spin_unlock_bh(&cp->cnic_ulp_lock);
  1044. return 0;
  1045. }
  1046. static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
  1047. union l5cm_specific_data *l5_data)
  1048. {
  1049. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1050. dma_addr_t map;
  1051. map = ctx->kwqe_data_mapping;
  1052. l5_data->phy_address.lo = (u64) map & 0xffffffff;
  1053. l5_data->phy_address.hi = (u64) map >> 32;
  1054. return ctx->kwqe_data;
  1055. }
  1056. static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
  1057. u32 type, union l5cm_specific_data *l5_data)
  1058. {
  1059. struct cnic_local *cp = dev->cnic_priv;
  1060. struct l5cm_spe kwqe;
  1061. struct kwqe_16 *kwq[1];
  1062. u16 type_16;
  1063. int ret;
  1064. kwqe.hdr.conn_and_cmd_data =
  1065. cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
  1066. BNX2X_HW_CID(cp, cid)));
  1067. type_16 = (type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
  1068. type_16 |= (cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  1069. SPE_HDR_FUNCTION_ID;
  1070. kwqe.hdr.type = cpu_to_le16(type_16);
  1071. kwqe.hdr.reserved1 = 0;
  1072. kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
  1073. kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
  1074. kwq[0] = (struct kwqe_16 *) &kwqe;
  1075. spin_lock_bh(&cp->cnic_ulp_lock);
  1076. ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
  1077. spin_unlock_bh(&cp->cnic_ulp_lock);
  1078. if (ret == 1)
  1079. return 0;
  1080. return -EBUSY;
  1081. }
  1082. static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
  1083. struct kcqe *cqes[], u32 num_cqes)
  1084. {
  1085. struct cnic_local *cp = dev->cnic_priv;
  1086. struct cnic_ulp_ops *ulp_ops;
  1087. rcu_read_lock();
  1088. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  1089. if (likely(ulp_ops)) {
  1090. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  1091. cqes, num_cqes);
  1092. }
  1093. rcu_read_unlock();
  1094. }
  1095. static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
  1096. {
  1097. struct cnic_local *cp = dev->cnic_priv;
  1098. struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
  1099. int hq_bds, pages;
  1100. u32 pfid = cp->pfid;
  1101. cp->num_iscsi_tasks = req1->num_tasks_per_conn;
  1102. cp->num_ccells = req1->num_ccells_per_conn;
  1103. cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
  1104. cp->num_iscsi_tasks;
  1105. cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
  1106. BNX2X_ISCSI_R2TQE_SIZE;
  1107. cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
  1108. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1109. hq_bds = pages * (PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
  1110. cp->num_cqs = req1->num_cqs;
  1111. if (!dev->max_iscsi_conn)
  1112. return 0;
  1113. /* init Tstorm RAM */
  1114. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1115. req1->rq_num_wqes);
  1116. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1117. PAGE_SIZE);
  1118. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1119. TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1120. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1121. TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1122. req1->num_tasks_per_conn);
  1123. /* init Ustorm RAM */
  1124. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1125. USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfid),
  1126. req1->rq_buffer_size);
  1127. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1128. PAGE_SIZE);
  1129. CNIC_WR8(dev, BAR_USTRORM_INTMEM +
  1130. USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1131. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1132. USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1133. req1->num_tasks_per_conn);
  1134. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1135. req1->rq_num_wqes);
  1136. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1137. req1->cq_num_wqes);
  1138. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1139. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1140. /* init Xstorm RAM */
  1141. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1142. PAGE_SIZE);
  1143. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1144. XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1145. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1146. XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1147. req1->num_tasks_per_conn);
  1148. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1149. hq_bds);
  1150. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(pfid),
  1151. req1->num_tasks_per_conn);
  1152. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1153. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1154. /* init Cstorm RAM */
  1155. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1156. PAGE_SIZE);
  1157. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  1158. CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1159. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1160. CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1161. req1->num_tasks_per_conn);
  1162. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1163. req1->cq_num_wqes);
  1164. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1165. hq_bds);
  1166. return 0;
  1167. }
  1168. static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
  1169. {
  1170. struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
  1171. struct cnic_local *cp = dev->cnic_priv;
  1172. u32 pfid = cp->pfid;
  1173. struct iscsi_kcqe kcqe;
  1174. struct kcqe *cqes[1];
  1175. memset(&kcqe, 0, sizeof(kcqe));
  1176. if (!dev->max_iscsi_conn) {
  1177. kcqe.completion_status =
  1178. ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
  1179. goto done;
  1180. }
  1181. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1182. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1183. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1184. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1185. req2->error_bit_map[1]);
  1186. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1187. USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1188. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1189. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1190. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1191. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1192. req2->error_bit_map[1]);
  1193. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1194. CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1195. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1196. done:
  1197. kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
  1198. cqes[0] = (struct kcqe *) &kcqe;
  1199. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1200. return 0;
  1201. }
  1202. static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1203. {
  1204. struct cnic_local *cp = dev->cnic_priv;
  1205. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1206. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
  1207. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1208. cnic_free_dma(dev, &iscsi->hq_info);
  1209. cnic_free_dma(dev, &iscsi->r2tq_info);
  1210. cnic_free_dma(dev, &iscsi->task_array_info);
  1211. cnic_free_id(&cp->cid_tbl, ctx->cid);
  1212. } else {
  1213. cnic_free_id(&cp->fcoe_cid_tbl, ctx->cid);
  1214. }
  1215. ctx->cid = 0;
  1216. }
  1217. static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1218. {
  1219. u32 cid;
  1220. int ret, pages;
  1221. struct cnic_local *cp = dev->cnic_priv;
  1222. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1223. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1224. if (ctx->ulp_proto_id == CNIC_ULP_FCOE) {
  1225. cid = cnic_alloc_new_id(&cp->fcoe_cid_tbl);
  1226. if (cid == -1) {
  1227. ret = -ENOMEM;
  1228. goto error;
  1229. }
  1230. ctx->cid = cid;
  1231. return 0;
  1232. }
  1233. cid = cnic_alloc_new_id(&cp->cid_tbl);
  1234. if (cid == -1) {
  1235. ret = -ENOMEM;
  1236. goto error;
  1237. }
  1238. ctx->cid = cid;
  1239. pages = PAGE_ALIGN(cp->task_array_size) / PAGE_SIZE;
  1240. ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
  1241. if (ret)
  1242. goto error;
  1243. pages = PAGE_ALIGN(cp->r2tq_size) / PAGE_SIZE;
  1244. ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
  1245. if (ret)
  1246. goto error;
  1247. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1248. ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
  1249. if (ret)
  1250. goto error;
  1251. return 0;
  1252. error:
  1253. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1254. return ret;
  1255. }
  1256. static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
  1257. struct regpair *ctx_addr)
  1258. {
  1259. struct cnic_local *cp = dev->cnic_priv;
  1260. struct cnic_eth_dev *ethdev = cp->ethdev;
  1261. int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
  1262. int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
  1263. unsigned long align_off = 0;
  1264. dma_addr_t ctx_map;
  1265. void *ctx;
  1266. if (cp->ctx_align) {
  1267. unsigned long mask = cp->ctx_align - 1;
  1268. if (cp->ctx_arr[blk].mapping & mask)
  1269. align_off = cp->ctx_align -
  1270. (cp->ctx_arr[blk].mapping & mask);
  1271. }
  1272. ctx_map = cp->ctx_arr[blk].mapping + align_off +
  1273. (off * BNX2X_CONTEXT_MEM_SIZE);
  1274. ctx = cp->ctx_arr[blk].ctx + align_off +
  1275. (off * BNX2X_CONTEXT_MEM_SIZE);
  1276. if (init)
  1277. memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
  1278. ctx_addr->lo = ctx_map & 0xffffffff;
  1279. ctx_addr->hi = (u64) ctx_map >> 32;
  1280. return ctx;
  1281. }
  1282. static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
  1283. u32 num)
  1284. {
  1285. struct cnic_local *cp = dev->cnic_priv;
  1286. struct iscsi_kwqe_conn_offload1 *req1 =
  1287. (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1288. struct iscsi_kwqe_conn_offload2 *req2 =
  1289. (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1290. struct iscsi_kwqe_conn_offload3 *req3;
  1291. struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
  1292. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1293. u32 cid = ctx->cid;
  1294. u32 hw_cid = BNX2X_HW_CID(cp, cid);
  1295. struct iscsi_context *ictx;
  1296. struct regpair context_addr;
  1297. int i, j, n = 2, n_max;
  1298. ctx->ctx_flags = 0;
  1299. if (!req2->num_additional_wqes)
  1300. return -EINVAL;
  1301. n_max = req2->num_additional_wqes + 2;
  1302. ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
  1303. if (ictx == NULL)
  1304. return -ENOMEM;
  1305. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1306. ictx->xstorm_ag_context.hq_prod = 1;
  1307. ictx->xstorm_st_context.iscsi.first_burst_length =
  1308. ISCSI_DEF_FIRST_BURST_LEN;
  1309. ictx->xstorm_st_context.iscsi.max_send_pdu_length =
  1310. ISCSI_DEF_MAX_RECV_SEG_LEN;
  1311. ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
  1312. req1->sq_page_table_addr_lo;
  1313. ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
  1314. req1->sq_page_table_addr_hi;
  1315. ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
  1316. ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
  1317. ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
  1318. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1319. ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
  1320. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1321. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
  1322. iscsi->hq_info.pgtbl[0];
  1323. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
  1324. iscsi->hq_info.pgtbl[1];
  1325. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
  1326. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1327. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
  1328. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1329. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
  1330. iscsi->r2tq_info.pgtbl[0];
  1331. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
  1332. iscsi->r2tq_info.pgtbl[1];
  1333. ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
  1334. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1335. ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
  1336. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1337. ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
  1338. BNX2X_ISCSI_PBL_NOT_CACHED;
  1339. ictx->xstorm_st_context.iscsi.flags.flags |=
  1340. XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
  1341. ictx->xstorm_st_context.iscsi.flags.flags |=
  1342. XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
  1343. ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
  1344. /* TSTORM requires the base address of RQ DB & not PTE */
  1345. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
  1346. req2->rq_page_table_addr_lo & PAGE_MASK;
  1347. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
  1348. req2->rq_page_table_addr_hi;
  1349. ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
  1350. ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
  1351. ictx->tstorm_st_context.tcp.flags2 |=
  1352. TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
  1353. ictx->tstorm_st_context.tcp.ooo_support_mode =
  1354. TCP_TSTORM_OOO_DROP_AND_PROC_ACK;
  1355. ictx->timers_context.flags |= TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
  1356. ictx->ustorm_st_context.ring.rq.pbl_base.lo =
  1357. req2->rq_page_table_addr_lo;
  1358. ictx->ustorm_st_context.ring.rq.pbl_base.hi =
  1359. req2->rq_page_table_addr_hi;
  1360. ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
  1361. ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
  1362. ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
  1363. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1364. ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
  1365. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1366. ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
  1367. iscsi->r2tq_info.pgtbl[0];
  1368. ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
  1369. iscsi->r2tq_info.pgtbl[1];
  1370. ictx->ustorm_st_context.ring.cq_pbl_base.lo =
  1371. req1->cq_page_table_addr_lo;
  1372. ictx->ustorm_st_context.ring.cq_pbl_base.hi =
  1373. req1->cq_page_table_addr_hi;
  1374. ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
  1375. ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
  1376. ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
  1377. ictx->ustorm_st_context.task_pbe_cache_index =
  1378. BNX2X_ISCSI_PBL_NOT_CACHED;
  1379. ictx->ustorm_st_context.task_pdu_cache_index =
  1380. BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
  1381. for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
  1382. if (j == 3) {
  1383. if (n >= n_max)
  1384. break;
  1385. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1386. j = 0;
  1387. }
  1388. ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
  1389. ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
  1390. req3->qp_first_pte[j].hi;
  1391. ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
  1392. req3->qp_first_pte[j].lo;
  1393. }
  1394. ictx->ustorm_st_context.task_pbl_base.lo =
  1395. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1396. ictx->ustorm_st_context.task_pbl_base.hi =
  1397. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1398. ictx->ustorm_st_context.tce_phy_addr.lo =
  1399. iscsi->task_array_info.pgtbl[0];
  1400. ictx->ustorm_st_context.tce_phy_addr.hi =
  1401. iscsi->task_array_info.pgtbl[1];
  1402. ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1403. ictx->ustorm_st_context.num_cqs = cp->num_cqs;
  1404. ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
  1405. ictx->ustorm_st_context.negotiated_rx_and_flags |=
  1406. ISCSI_DEF_MAX_BURST_LEN;
  1407. ictx->ustorm_st_context.negotiated_rx |=
  1408. ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
  1409. USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
  1410. ictx->cstorm_st_context.hq_pbl_base.lo =
  1411. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1412. ictx->cstorm_st_context.hq_pbl_base.hi =
  1413. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1414. ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
  1415. ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
  1416. ictx->cstorm_st_context.task_pbl_base.lo =
  1417. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1418. ictx->cstorm_st_context.task_pbl_base.hi =
  1419. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1420. /* CSTORM and USTORM initialization is different, CSTORM requires
  1421. * CQ DB base & not PTE addr */
  1422. ictx->cstorm_st_context.cq_db_base.lo =
  1423. req1->cq_page_table_addr_lo & PAGE_MASK;
  1424. ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
  1425. ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1426. ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
  1427. for (i = 0; i < cp->num_cqs; i++) {
  1428. ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
  1429. ISCSI_INITIAL_SN;
  1430. ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
  1431. ISCSI_INITIAL_SN;
  1432. }
  1433. ictx->xstorm_ag_context.cdu_reserved =
  1434. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1435. ISCSI_CONNECTION_TYPE);
  1436. ictx->ustorm_ag_context.cdu_usage =
  1437. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1438. ISCSI_CONNECTION_TYPE);
  1439. return 0;
  1440. }
  1441. static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1442. u32 num, int *work)
  1443. {
  1444. struct iscsi_kwqe_conn_offload1 *req1;
  1445. struct iscsi_kwqe_conn_offload2 *req2;
  1446. struct cnic_local *cp = dev->cnic_priv;
  1447. struct cnic_context *ctx;
  1448. struct iscsi_kcqe kcqe;
  1449. struct kcqe *cqes[1];
  1450. u32 l5_cid;
  1451. int ret = 0;
  1452. if (num < 2) {
  1453. *work = num;
  1454. return -EINVAL;
  1455. }
  1456. req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1457. req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1458. if ((num - 2) < req2->num_additional_wqes) {
  1459. *work = num;
  1460. return -EINVAL;
  1461. }
  1462. *work = 2 + req2->num_additional_wqes;
  1463. l5_cid = req1->iscsi_conn_id;
  1464. if (l5_cid >= MAX_ISCSI_TBL_SZ)
  1465. return -EINVAL;
  1466. memset(&kcqe, 0, sizeof(kcqe));
  1467. kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
  1468. kcqe.iscsi_conn_id = l5_cid;
  1469. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1470. ctx = &cp->ctx_tbl[l5_cid];
  1471. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags)) {
  1472. kcqe.completion_status =
  1473. ISCSI_KCQE_COMPLETION_STATUS_CID_BUSY;
  1474. goto done;
  1475. }
  1476. if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
  1477. atomic_dec(&cp->iscsi_conn);
  1478. goto done;
  1479. }
  1480. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1481. if (ret) {
  1482. atomic_dec(&cp->iscsi_conn);
  1483. ret = 0;
  1484. goto done;
  1485. }
  1486. ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
  1487. if (ret < 0) {
  1488. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1489. atomic_dec(&cp->iscsi_conn);
  1490. goto done;
  1491. }
  1492. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1493. kcqe.iscsi_conn_context_id = BNX2X_HW_CID(cp, cp->ctx_tbl[l5_cid].cid);
  1494. done:
  1495. cqes[0] = (struct kcqe *) &kcqe;
  1496. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1497. return ret;
  1498. }
  1499. static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
  1500. {
  1501. struct cnic_local *cp = dev->cnic_priv;
  1502. struct iscsi_kwqe_conn_update *req =
  1503. (struct iscsi_kwqe_conn_update *) kwqe;
  1504. void *data;
  1505. union l5cm_specific_data l5_data;
  1506. u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
  1507. int ret;
  1508. if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
  1509. return -EINVAL;
  1510. data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1511. if (!data)
  1512. return -ENOMEM;
  1513. memcpy(data, kwqe, sizeof(struct kwqe));
  1514. ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
  1515. req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
  1516. return ret;
  1517. }
  1518. static int cnic_bnx2x_destroy_ramrod(struct cnic_dev *dev, u32 l5_cid)
  1519. {
  1520. struct cnic_local *cp = dev->cnic_priv;
  1521. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1522. union l5cm_specific_data l5_data;
  1523. int ret;
  1524. u32 hw_cid;
  1525. init_waitqueue_head(&ctx->waitq);
  1526. ctx->wait_cond = 0;
  1527. memset(&l5_data, 0, sizeof(l5_data));
  1528. hw_cid = BNX2X_HW_CID(cp, ctx->cid);
  1529. ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  1530. hw_cid, NONE_CONNECTION_TYPE, &l5_data);
  1531. if (ret == 0)
  1532. wait_event(ctx->waitq, ctx->wait_cond);
  1533. return ret;
  1534. }
  1535. static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  1536. {
  1537. struct cnic_local *cp = dev->cnic_priv;
  1538. struct iscsi_kwqe_conn_destroy *req =
  1539. (struct iscsi_kwqe_conn_destroy *) kwqe;
  1540. u32 l5_cid = req->reserved0;
  1541. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1542. int ret = 0;
  1543. struct iscsi_kcqe kcqe;
  1544. struct kcqe *cqes[1];
  1545. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1546. goto skip_cfc_delete;
  1547. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  1548. unsigned long delta = ctx->timestamp + (2 * HZ) - jiffies;
  1549. if (delta > (2 * HZ))
  1550. delta = 0;
  1551. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  1552. queue_delayed_work(cnic_wq, &cp->delete_task, delta);
  1553. goto destroy_reply;
  1554. }
  1555. ret = cnic_bnx2x_destroy_ramrod(dev, l5_cid);
  1556. skip_cfc_delete:
  1557. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1558. atomic_dec(&cp->iscsi_conn);
  1559. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1560. destroy_reply:
  1561. memset(&kcqe, 0, sizeof(kcqe));
  1562. kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
  1563. kcqe.iscsi_conn_id = l5_cid;
  1564. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1565. kcqe.iscsi_conn_context_id = req->context_id;
  1566. cqes[0] = (struct kcqe *) &kcqe;
  1567. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1568. return ret;
  1569. }
  1570. static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
  1571. struct l4_kwq_connect_req1 *kwqe1,
  1572. struct l4_kwq_connect_req3 *kwqe3,
  1573. struct l5cm_active_conn_buffer *conn_buf)
  1574. {
  1575. struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
  1576. struct l5cm_xstorm_conn_buffer *xstorm_buf =
  1577. &conn_buf->xstorm_conn_buffer;
  1578. struct l5cm_tstorm_conn_buffer *tstorm_buf =
  1579. &conn_buf->tstorm_conn_buffer;
  1580. struct regpair context_addr;
  1581. u32 cid = BNX2X_SW_CID(kwqe1->cid);
  1582. struct in6_addr src_ip, dst_ip;
  1583. int i;
  1584. u32 *addrp;
  1585. addrp = (u32 *) &conn_addr->local_ip_addr;
  1586. for (i = 0; i < 4; i++, addrp++)
  1587. src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1588. addrp = (u32 *) &conn_addr->remote_ip_addr;
  1589. for (i = 0; i < 4; i++, addrp++)
  1590. dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1591. cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
  1592. xstorm_buf->context_addr.hi = context_addr.hi;
  1593. xstorm_buf->context_addr.lo = context_addr.lo;
  1594. xstorm_buf->mss = 0xffff;
  1595. xstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1596. if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
  1597. xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
  1598. xstorm_buf->pseudo_header_checksum =
  1599. swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
  1600. if (!(kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK))
  1601. tstorm_buf->params |=
  1602. L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE;
  1603. if (kwqe3->ka_timeout) {
  1604. tstorm_buf->ka_enable = 1;
  1605. tstorm_buf->ka_timeout = kwqe3->ka_timeout;
  1606. tstorm_buf->ka_interval = kwqe3->ka_interval;
  1607. tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
  1608. }
  1609. tstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1610. tstorm_buf->snd_buf = kwqe3->snd_buf;
  1611. tstorm_buf->max_rt_time = 0xffffffff;
  1612. }
  1613. static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
  1614. {
  1615. struct cnic_local *cp = dev->cnic_priv;
  1616. u32 pfid = cp->pfid;
  1617. u8 *mac = dev->mac_addr;
  1618. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1619. XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfid), mac[0]);
  1620. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1621. XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfid), mac[1]);
  1622. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1623. XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfid), mac[2]);
  1624. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1625. XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfid), mac[3]);
  1626. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1627. XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfid), mac[4]);
  1628. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1629. XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfid), mac[5]);
  1630. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1631. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[5]);
  1632. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1633. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1634. mac[4]);
  1635. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1636. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[3]);
  1637. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1638. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1639. mac[2]);
  1640. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1641. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 2,
  1642. mac[1]);
  1643. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1644. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 3,
  1645. mac[0]);
  1646. }
  1647. static void cnic_bnx2x_set_tcp_timestamp(struct cnic_dev *dev, int tcp_ts)
  1648. {
  1649. struct cnic_local *cp = dev->cnic_priv;
  1650. u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
  1651. u16 tstorm_flags = 0;
  1652. if (tcp_ts) {
  1653. xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1654. tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1655. }
  1656. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1657. XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), xstorm_flags);
  1658. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1659. TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), tstorm_flags);
  1660. }
  1661. static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
  1662. u32 num, int *work)
  1663. {
  1664. struct cnic_local *cp = dev->cnic_priv;
  1665. struct l4_kwq_connect_req1 *kwqe1 =
  1666. (struct l4_kwq_connect_req1 *) wqes[0];
  1667. struct l4_kwq_connect_req3 *kwqe3;
  1668. struct l5cm_active_conn_buffer *conn_buf;
  1669. struct l5cm_conn_addr_params *conn_addr;
  1670. union l5cm_specific_data l5_data;
  1671. u32 l5_cid = kwqe1->pg_cid;
  1672. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  1673. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1674. int ret;
  1675. if (num < 2) {
  1676. *work = num;
  1677. return -EINVAL;
  1678. }
  1679. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
  1680. *work = 3;
  1681. else
  1682. *work = 2;
  1683. if (num < *work) {
  1684. *work = num;
  1685. return -EINVAL;
  1686. }
  1687. if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
  1688. netdev_err(dev->netdev, "conn_buf size too big\n");
  1689. return -ENOMEM;
  1690. }
  1691. conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1692. if (!conn_buf)
  1693. return -ENOMEM;
  1694. memset(conn_buf, 0, sizeof(*conn_buf));
  1695. conn_addr = &conn_buf->conn_addr_buf;
  1696. conn_addr->remote_addr_0 = csk->ha[0];
  1697. conn_addr->remote_addr_1 = csk->ha[1];
  1698. conn_addr->remote_addr_2 = csk->ha[2];
  1699. conn_addr->remote_addr_3 = csk->ha[3];
  1700. conn_addr->remote_addr_4 = csk->ha[4];
  1701. conn_addr->remote_addr_5 = csk->ha[5];
  1702. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
  1703. struct l4_kwq_connect_req2 *kwqe2 =
  1704. (struct l4_kwq_connect_req2 *) wqes[1];
  1705. conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
  1706. conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
  1707. conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
  1708. conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
  1709. conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
  1710. conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
  1711. conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
  1712. }
  1713. kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
  1714. conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
  1715. conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
  1716. conn_addr->local_tcp_port = kwqe1->src_port;
  1717. conn_addr->remote_tcp_port = kwqe1->dst_port;
  1718. conn_addr->pmtu = kwqe3->pmtu;
  1719. cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
  1720. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1721. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(cp->pfid), csk->vlan_id);
  1722. cnic_bnx2x_set_tcp_timestamp(dev,
  1723. kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_TIME_STAMP);
  1724. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
  1725. kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1726. if (!ret)
  1727. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1728. return ret;
  1729. }
  1730. static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
  1731. {
  1732. struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
  1733. union l5cm_specific_data l5_data;
  1734. int ret;
  1735. memset(&l5_data, 0, sizeof(l5_data));
  1736. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
  1737. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1738. return ret;
  1739. }
  1740. static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
  1741. {
  1742. struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
  1743. union l5cm_specific_data l5_data;
  1744. int ret;
  1745. memset(&l5_data, 0, sizeof(l5_data));
  1746. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
  1747. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1748. return ret;
  1749. }
  1750. static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1751. {
  1752. struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
  1753. struct l4_kcq kcqe;
  1754. struct kcqe *cqes[1];
  1755. memset(&kcqe, 0, sizeof(kcqe));
  1756. kcqe.pg_host_opaque = req->host_opaque;
  1757. kcqe.pg_cid = req->host_opaque;
  1758. kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
  1759. cqes[0] = (struct kcqe *) &kcqe;
  1760. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1761. return 0;
  1762. }
  1763. static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1764. {
  1765. struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
  1766. struct l4_kcq kcqe;
  1767. struct kcqe *cqes[1];
  1768. memset(&kcqe, 0, sizeof(kcqe));
  1769. kcqe.pg_host_opaque = req->pg_host_opaque;
  1770. kcqe.pg_cid = req->pg_cid;
  1771. kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
  1772. cqes[0] = (struct kcqe *) &kcqe;
  1773. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1774. return 0;
  1775. }
  1776. static int cnic_bnx2x_fcoe_stat(struct cnic_dev *dev, struct kwqe *kwqe)
  1777. {
  1778. struct fcoe_kwqe_stat *req;
  1779. struct fcoe_stat_ramrod_params *fcoe_stat;
  1780. union l5cm_specific_data l5_data;
  1781. struct cnic_local *cp = dev->cnic_priv;
  1782. int ret;
  1783. u32 cid;
  1784. req = (struct fcoe_kwqe_stat *) kwqe;
  1785. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  1786. fcoe_stat = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1787. if (!fcoe_stat)
  1788. return -ENOMEM;
  1789. memset(fcoe_stat, 0, sizeof(*fcoe_stat));
  1790. memcpy(&fcoe_stat->stat_kwqe, req, sizeof(*req));
  1791. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_STAT, cid,
  1792. FCOE_CONNECTION_TYPE, &l5_data);
  1793. return ret;
  1794. }
  1795. static int cnic_bnx2x_fcoe_init1(struct cnic_dev *dev, struct kwqe *wqes[],
  1796. u32 num, int *work)
  1797. {
  1798. int ret;
  1799. struct cnic_local *cp = dev->cnic_priv;
  1800. u32 cid;
  1801. struct fcoe_init_ramrod_params *fcoe_init;
  1802. struct fcoe_kwqe_init1 *req1;
  1803. struct fcoe_kwqe_init2 *req2;
  1804. struct fcoe_kwqe_init3 *req3;
  1805. union l5cm_specific_data l5_data;
  1806. if (num < 3) {
  1807. *work = num;
  1808. return -EINVAL;
  1809. }
  1810. req1 = (struct fcoe_kwqe_init1 *) wqes[0];
  1811. req2 = (struct fcoe_kwqe_init2 *) wqes[1];
  1812. req3 = (struct fcoe_kwqe_init3 *) wqes[2];
  1813. if (req2->hdr.op_code != FCOE_KWQE_OPCODE_INIT2) {
  1814. *work = 1;
  1815. return -EINVAL;
  1816. }
  1817. if (req3->hdr.op_code != FCOE_KWQE_OPCODE_INIT3) {
  1818. *work = 2;
  1819. return -EINVAL;
  1820. }
  1821. if (sizeof(*fcoe_init) > CNIC_KWQ16_DATA_SIZE) {
  1822. netdev_err(dev->netdev, "fcoe_init size too big\n");
  1823. return -ENOMEM;
  1824. }
  1825. fcoe_init = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1826. if (!fcoe_init)
  1827. return -ENOMEM;
  1828. memset(fcoe_init, 0, sizeof(*fcoe_init));
  1829. memcpy(&fcoe_init->init_kwqe1, req1, sizeof(*req1));
  1830. memcpy(&fcoe_init->init_kwqe2, req2, sizeof(*req2));
  1831. memcpy(&fcoe_init->init_kwqe3, req3, sizeof(*req3));
  1832. fcoe_init->eq_addr.lo = cp->kcq2.dma.pg_map_arr[0] & 0xffffffff;
  1833. fcoe_init->eq_addr.hi = (u64) cp->kcq2.dma.pg_map_arr[0] >> 32;
  1834. fcoe_init->eq_next_page_addr.lo =
  1835. cp->kcq2.dma.pg_map_arr[1] & 0xffffffff;
  1836. fcoe_init->eq_next_page_addr.hi =
  1837. (u64) cp->kcq2.dma.pg_map_arr[1] >> 32;
  1838. fcoe_init->sb_num = cp->status_blk_num;
  1839. fcoe_init->eq_prod = MAX_KCQ_IDX;
  1840. fcoe_init->sb_id = HC_INDEX_FCOE_EQ_CONS;
  1841. cp->kcq2.sw_prod_idx = 0;
  1842. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  1843. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_INIT, cid,
  1844. FCOE_CONNECTION_TYPE, &l5_data);
  1845. *work = 3;
  1846. return ret;
  1847. }
  1848. static int cnic_bnx2x_fcoe_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1849. u32 num, int *work)
  1850. {
  1851. int ret = 0;
  1852. u32 cid = -1, l5_cid;
  1853. struct cnic_local *cp = dev->cnic_priv;
  1854. struct fcoe_kwqe_conn_offload1 *req1;
  1855. struct fcoe_kwqe_conn_offload2 *req2;
  1856. struct fcoe_kwqe_conn_offload3 *req3;
  1857. struct fcoe_kwqe_conn_offload4 *req4;
  1858. struct fcoe_conn_offload_ramrod_params *fcoe_offload;
  1859. struct cnic_context *ctx;
  1860. struct fcoe_context *fctx;
  1861. struct regpair ctx_addr;
  1862. union l5cm_specific_data l5_data;
  1863. struct fcoe_kcqe kcqe;
  1864. struct kcqe *cqes[1];
  1865. if (num < 4) {
  1866. *work = num;
  1867. return -EINVAL;
  1868. }
  1869. req1 = (struct fcoe_kwqe_conn_offload1 *) wqes[0];
  1870. req2 = (struct fcoe_kwqe_conn_offload2 *) wqes[1];
  1871. req3 = (struct fcoe_kwqe_conn_offload3 *) wqes[2];
  1872. req4 = (struct fcoe_kwqe_conn_offload4 *) wqes[3];
  1873. *work = 4;
  1874. l5_cid = req1->fcoe_conn_id;
  1875. if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
  1876. goto err_reply;
  1877. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  1878. ctx = &cp->ctx_tbl[l5_cid];
  1879. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1880. goto err_reply;
  1881. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1882. if (ret) {
  1883. ret = 0;
  1884. goto err_reply;
  1885. }
  1886. cid = ctx->cid;
  1887. fctx = cnic_get_bnx2x_ctx(dev, cid, 1, &ctx_addr);
  1888. if (fctx) {
  1889. u32 hw_cid = BNX2X_HW_CID(cp, cid);
  1890. u32 val;
  1891. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1892. FCOE_CONNECTION_TYPE);
  1893. fctx->xstorm_ag_context.cdu_reserved = val;
  1894. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1895. FCOE_CONNECTION_TYPE);
  1896. fctx->ustorm_ag_context.cdu_usage = val;
  1897. }
  1898. if (sizeof(*fcoe_offload) > CNIC_KWQ16_DATA_SIZE) {
  1899. netdev_err(dev->netdev, "fcoe_offload size too big\n");
  1900. goto err_reply;
  1901. }
  1902. fcoe_offload = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1903. if (!fcoe_offload)
  1904. goto err_reply;
  1905. memset(fcoe_offload, 0, sizeof(*fcoe_offload));
  1906. memcpy(&fcoe_offload->offload_kwqe1, req1, sizeof(*req1));
  1907. memcpy(&fcoe_offload->offload_kwqe2, req2, sizeof(*req2));
  1908. memcpy(&fcoe_offload->offload_kwqe3, req3, sizeof(*req3));
  1909. memcpy(&fcoe_offload->offload_kwqe4, req4, sizeof(*req4));
  1910. cid = BNX2X_HW_CID(cp, cid);
  1911. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_OFFLOAD_CONN, cid,
  1912. FCOE_CONNECTION_TYPE, &l5_data);
  1913. if (!ret)
  1914. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1915. return ret;
  1916. err_reply:
  1917. if (cid != -1)
  1918. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1919. memset(&kcqe, 0, sizeof(kcqe));
  1920. kcqe.op_code = FCOE_KCQE_OPCODE_OFFLOAD_CONN;
  1921. kcqe.fcoe_conn_id = req1->fcoe_conn_id;
  1922. kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1923. cqes[0] = (struct kcqe *) &kcqe;
  1924. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  1925. return ret;
  1926. }
  1927. static int cnic_bnx2x_fcoe_enable(struct cnic_dev *dev, struct kwqe *kwqe)
  1928. {
  1929. struct fcoe_kwqe_conn_enable_disable *req;
  1930. struct fcoe_conn_enable_disable_ramrod_params *fcoe_enable;
  1931. union l5cm_specific_data l5_data;
  1932. int ret;
  1933. u32 cid, l5_cid;
  1934. struct cnic_local *cp = dev->cnic_priv;
  1935. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  1936. cid = req->context_id;
  1937. l5_cid = req->conn_id + BNX2X_FCOE_L5_CID_BASE;
  1938. if (sizeof(*fcoe_enable) > CNIC_KWQ16_DATA_SIZE) {
  1939. netdev_err(dev->netdev, "fcoe_enable size too big\n");
  1940. return -ENOMEM;
  1941. }
  1942. fcoe_enable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1943. if (!fcoe_enable)
  1944. return -ENOMEM;
  1945. memset(fcoe_enable, 0, sizeof(*fcoe_enable));
  1946. memcpy(&fcoe_enable->enable_disable_kwqe, req, sizeof(*req));
  1947. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_ENABLE_CONN, cid,
  1948. FCOE_CONNECTION_TYPE, &l5_data);
  1949. return ret;
  1950. }
  1951. static int cnic_bnx2x_fcoe_disable(struct cnic_dev *dev, struct kwqe *kwqe)
  1952. {
  1953. struct fcoe_kwqe_conn_enable_disable *req;
  1954. struct fcoe_conn_enable_disable_ramrod_params *fcoe_disable;
  1955. union l5cm_specific_data l5_data;
  1956. int ret;
  1957. u32 cid, l5_cid;
  1958. struct cnic_local *cp = dev->cnic_priv;
  1959. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  1960. cid = req->context_id;
  1961. l5_cid = req->conn_id;
  1962. if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
  1963. return -EINVAL;
  1964. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  1965. if (sizeof(*fcoe_disable) > CNIC_KWQ16_DATA_SIZE) {
  1966. netdev_err(dev->netdev, "fcoe_disable size too big\n");
  1967. return -ENOMEM;
  1968. }
  1969. fcoe_disable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1970. if (!fcoe_disable)
  1971. return -ENOMEM;
  1972. memset(fcoe_disable, 0, sizeof(*fcoe_disable));
  1973. memcpy(&fcoe_disable->enable_disable_kwqe, req, sizeof(*req));
  1974. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DISABLE_CONN, cid,
  1975. FCOE_CONNECTION_TYPE, &l5_data);
  1976. return ret;
  1977. }
  1978. static int cnic_bnx2x_fcoe_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  1979. {
  1980. struct fcoe_kwqe_conn_destroy *req;
  1981. union l5cm_specific_data l5_data;
  1982. int ret;
  1983. u32 cid, l5_cid;
  1984. struct cnic_local *cp = dev->cnic_priv;
  1985. struct cnic_context *ctx;
  1986. struct fcoe_kcqe kcqe;
  1987. struct kcqe *cqes[1];
  1988. req = (struct fcoe_kwqe_conn_destroy *) kwqe;
  1989. cid = req->context_id;
  1990. l5_cid = req->conn_id;
  1991. if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
  1992. return -EINVAL;
  1993. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  1994. ctx = &cp->ctx_tbl[l5_cid];
  1995. init_waitqueue_head(&ctx->waitq);
  1996. ctx->wait_cond = 0;
  1997. memset(&l5_data, 0, sizeof(l5_data));
  1998. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_TERMINATE_CONN, cid,
  1999. FCOE_CONNECTION_TYPE, &l5_data);
  2000. if (ret == 0) {
  2001. wait_event(ctx->waitq, ctx->wait_cond);
  2002. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  2003. queue_delayed_work(cnic_wq, &cp->delete_task,
  2004. msecs_to_jiffies(2000));
  2005. }
  2006. memset(&kcqe, 0, sizeof(kcqe));
  2007. kcqe.op_code = FCOE_KCQE_OPCODE_DESTROY_CONN;
  2008. kcqe.fcoe_conn_id = req->conn_id;
  2009. kcqe.fcoe_conn_context_id = cid;
  2010. cqes[0] = (struct kcqe *) &kcqe;
  2011. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  2012. return ret;
  2013. }
  2014. static int cnic_bnx2x_fcoe_fw_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  2015. {
  2016. struct fcoe_kwqe_destroy *req;
  2017. union l5cm_specific_data l5_data;
  2018. struct cnic_local *cp = dev->cnic_priv;
  2019. int ret;
  2020. u32 cid;
  2021. req = (struct fcoe_kwqe_destroy *) kwqe;
  2022. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  2023. memset(&l5_data, 0, sizeof(l5_data));
  2024. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DESTROY, cid,
  2025. FCOE_CONNECTION_TYPE, &l5_data);
  2026. return ret;
  2027. }
  2028. static int cnic_submit_bnx2x_iscsi_kwqes(struct cnic_dev *dev,
  2029. struct kwqe *wqes[], u32 num_wqes)
  2030. {
  2031. int i, work, ret;
  2032. u32 opcode;
  2033. struct kwqe *kwqe;
  2034. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2035. return -EAGAIN; /* bnx2 is down */
  2036. for (i = 0; i < num_wqes; ) {
  2037. kwqe = wqes[i];
  2038. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2039. work = 1;
  2040. switch (opcode) {
  2041. case ISCSI_KWQE_OPCODE_INIT1:
  2042. ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
  2043. break;
  2044. case ISCSI_KWQE_OPCODE_INIT2:
  2045. ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
  2046. break;
  2047. case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
  2048. ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
  2049. num_wqes - i, &work);
  2050. break;
  2051. case ISCSI_KWQE_OPCODE_UPDATE_CONN:
  2052. ret = cnic_bnx2x_iscsi_update(dev, kwqe);
  2053. break;
  2054. case ISCSI_KWQE_OPCODE_DESTROY_CONN:
  2055. ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
  2056. break;
  2057. case L4_KWQE_OPCODE_VALUE_CONNECT1:
  2058. ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
  2059. &work);
  2060. break;
  2061. case L4_KWQE_OPCODE_VALUE_CLOSE:
  2062. ret = cnic_bnx2x_close(dev, kwqe);
  2063. break;
  2064. case L4_KWQE_OPCODE_VALUE_RESET:
  2065. ret = cnic_bnx2x_reset(dev, kwqe);
  2066. break;
  2067. case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
  2068. ret = cnic_bnx2x_offload_pg(dev, kwqe);
  2069. break;
  2070. case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
  2071. ret = cnic_bnx2x_update_pg(dev, kwqe);
  2072. break;
  2073. case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
  2074. ret = 0;
  2075. break;
  2076. default:
  2077. ret = 0;
  2078. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2079. opcode);
  2080. break;
  2081. }
  2082. if (ret < 0)
  2083. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2084. opcode);
  2085. i += work;
  2086. }
  2087. return 0;
  2088. }
  2089. static int cnic_submit_bnx2x_fcoe_kwqes(struct cnic_dev *dev,
  2090. struct kwqe *wqes[], u32 num_wqes)
  2091. {
  2092. struct cnic_local *cp = dev->cnic_priv;
  2093. int i, work, ret;
  2094. u32 opcode;
  2095. struct kwqe *kwqe;
  2096. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2097. return -EAGAIN; /* bnx2 is down */
  2098. if (BNX2X_CHIP_NUM(cp->chip_id) == BNX2X_CHIP_NUM_57710)
  2099. return -EINVAL;
  2100. for (i = 0; i < num_wqes; ) {
  2101. kwqe = wqes[i];
  2102. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2103. work = 1;
  2104. switch (opcode) {
  2105. case FCOE_KWQE_OPCODE_INIT1:
  2106. ret = cnic_bnx2x_fcoe_init1(dev, &wqes[i],
  2107. num_wqes - i, &work);
  2108. break;
  2109. case FCOE_KWQE_OPCODE_OFFLOAD_CONN1:
  2110. ret = cnic_bnx2x_fcoe_ofld1(dev, &wqes[i],
  2111. num_wqes - i, &work);
  2112. break;
  2113. case FCOE_KWQE_OPCODE_ENABLE_CONN:
  2114. ret = cnic_bnx2x_fcoe_enable(dev, kwqe);
  2115. break;
  2116. case FCOE_KWQE_OPCODE_DISABLE_CONN:
  2117. ret = cnic_bnx2x_fcoe_disable(dev, kwqe);
  2118. break;
  2119. case FCOE_KWQE_OPCODE_DESTROY_CONN:
  2120. ret = cnic_bnx2x_fcoe_destroy(dev, kwqe);
  2121. break;
  2122. case FCOE_KWQE_OPCODE_DESTROY:
  2123. ret = cnic_bnx2x_fcoe_fw_destroy(dev, kwqe);
  2124. break;
  2125. case FCOE_KWQE_OPCODE_STAT:
  2126. ret = cnic_bnx2x_fcoe_stat(dev, kwqe);
  2127. break;
  2128. default:
  2129. ret = 0;
  2130. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2131. opcode);
  2132. break;
  2133. }
  2134. if (ret < 0)
  2135. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2136. opcode);
  2137. i += work;
  2138. }
  2139. return 0;
  2140. }
  2141. static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  2142. u32 num_wqes)
  2143. {
  2144. int ret = -EINVAL;
  2145. u32 layer_code;
  2146. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2147. return -EAGAIN; /* bnx2x is down */
  2148. if (!num_wqes)
  2149. return 0;
  2150. layer_code = wqes[0]->kwqe_op_flag & KWQE_LAYER_MASK;
  2151. switch (layer_code) {
  2152. case KWQE_FLAGS_LAYER_MASK_L5_ISCSI:
  2153. case KWQE_FLAGS_LAYER_MASK_L4:
  2154. case KWQE_FLAGS_LAYER_MASK_L2:
  2155. ret = cnic_submit_bnx2x_iscsi_kwqes(dev, wqes, num_wqes);
  2156. break;
  2157. case KWQE_FLAGS_LAYER_MASK_L5_FCOE:
  2158. ret = cnic_submit_bnx2x_fcoe_kwqes(dev, wqes, num_wqes);
  2159. break;
  2160. }
  2161. return ret;
  2162. }
  2163. static inline u32 cnic_get_kcqe_layer_mask(u32 opflag)
  2164. {
  2165. if (unlikely(KCQE_OPCODE(opflag) == FCOE_RAMROD_CMD_ID_TERMINATE_CONN))
  2166. return KCQE_FLAGS_LAYER_MASK_L4;
  2167. return opflag & KCQE_FLAGS_LAYER_MASK;
  2168. }
  2169. static void service_kcqes(struct cnic_dev *dev, int num_cqes)
  2170. {
  2171. struct cnic_local *cp = dev->cnic_priv;
  2172. int i, j, comp = 0;
  2173. i = 0;
  2174. j = 1;
  2175. while (num_cqes) {
  2176. struct cnic_ulp_ops *ulp_ops;
  2177. int ulp_type;
  2178. u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
  2179. u32 kcqe_layer = cnic_get_kcqe_layer_mask(kcqe_op_flag);
  2180. if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
  2181. comp++;
  2182. while (j < num_cqes) {
  2183. u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
  2184. if (cnic_get_kcqe_layer_mask(next_op) != kcqe_layer)
  2185. break;
  2186. if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
  2187. comp++;
  2188. j++;
  2189. }
  2190. if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
  2191. ulp_type = CNIC_ULP_RDMA;
  2192. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
  2193. ulp_type = CNIC_ULP_ISCSI;
  2194. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_FCOE)
  2195. ulp_type = CNIC_ULP_FCOE;
  2196. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
  2197. ulp_type = CNIC_ULP_L4;
  2198. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
  2199. goto end;
  2200. else {
  2201. netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n",
  2202. kcqe_op_flag);
  2203. goto end;
  2204. }
  2205. rcu_read_lock();
  2206. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  2207. if (likely(ulp_ops)) {
  2208. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  2209. cp->completed_kcq + i, j);
  2210. }
  2211. rcu_read_unlock();
  2212. end:
  2213. num_cqes -= j;
  2214. i += j;
  2215. j = 1;
  2216. }
  2217. if (unlikely(comp))
  2218. cnic_spq_completion(dev, DRV_CTL_RET_L5_SPQ_CREDIT_CMD, comp);
  2219. }
  2220. static u16 cnic_bnx2_next_idx(u16 idx)
  2221. {
  2222. return idx + 1;
  2223. }
  2224. static u16 cnic_bnx2_hw_idx(u16 idx)
  2225. {
  2226. return idx;
  2227. }
  2228. static u16 cnic_bnx2x_next_idx(u16 idx)
  2229. {
  2230. idx++;
  2231. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  2232. idx++;
  2233. return idx;
  2234. }
  2235. static u16 cnic_bnx2x_hw_idx(u16 idx)
  2236. {
  2237. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  2238. idx++;
  2239. return idx;
  2240. }
  2241. static int cnic_get_kcqes(struct cnic_dev *dev, struct kcq_info *info)
  2242. {
  2243. struct cnic_local *cp = dev->cnic_priv;
  2244. u16 i, ri, hw_prod, last;
  2245. struct kcqe *kcqe;
  2246. int kcqe_cnt = 0, last_cnt = 0;
  2247. i = ri = last = info->sw_prod_idx;
  2248. ri &= MAX_KCQ_IDX;
  2249. hw_prod = *info->hw_prod_idx_ptr;
  2250. hw_prod = cp->hw_idx(hw_prod);
  2251. while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
  2252. kcqe = &info->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
  2253. cp->completed_kcq[kcqe_cnt++] = kcqe;
  2254. i = cp->next_idx(i);
  2255. ri = i & MAX_KCQ_IDX;
  2256. if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
  2257. last_cnt = kcqe_cnt;
  2258. last = i;
  2259. }
  2260. }
  2261. info->sw_prod_idx = last;
  2262. return last_cnt;
  2263. }
  2264. static int cnic_l2_completion(struct cnic_local *cp)
  2265. {
  2266. u16 hw_cons, sw_cons;
  2267. struct cnic_uio_dev *udev = cp->udev;
  2268. union eth_rx_cqe *cqe, *cqe_ring = (union eth_rx_cqe *)
  2269. (udev->l2_ring + (2 * BCM_PAGE_SIZE));
  2270. u32 cmd;
  2271. int comp = 0;
  2272. if (!test_bit(CNIC_F_BNX2X_CLASS, &cp->dev->flags))
  2273. return 0;
  2274. hw_cons = *cp->rx_cons_ptr;
  2275. if ((hw_cons & BNX2X_MAX_RCQ_DESC_CNT) == BNX2X_MAX_RCQ_DESC_CNT)
  2276. hw_cons++;
  2277. sw_cons = cp->rx_cons;
  2278. while (sw_cons != hw_cons) {
  2279. u8 cqe_fp_flags;
  2280. cqe = &cqe_ring[sw_cons & BNX2X_MAX_RCQ_DESC_CNT];
  2281. cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
  2282. if (cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE) {
  2283. cmd = le32_to_cpu(cqe->ramrod_cqe.conn_and_cmd_data);
  2284. cmd >>= COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT;
  2285. if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP ||
  2286. cmd == RAMROD_CMD_ID_ETH_HALT)
  2287. comp++;
  2288. }
  2289. sw_cons = BNX2X_NEXT_RCQE(sw_cons);
  2290. }
  2291. return comp;
  2292. }
  2293. static void cnic_chk_pkt_rings(struct cnic_local *cp)
  2294. {
  2295. u16 rx_cons, tx_cons;
  2296. int comp = 0;
  2297. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  2298. return;
  2299. rx_cons = *cp->rx_cons_ptr;
  2300. tx_cons = *cp->tx_cons_ptr;
  2301. if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
  2302. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  2303. comp = cnic_l2_completion(cp);
  2304. cp->tx_cons = tx_cons;
  2305. cp->rx_cons = rx_cons;
  2306. if (cp->udev)
  2307. uio_event_notify(&cp->udev->cnic_uinfo);
  2308. }
  2309. if (comp)
  2310. clear_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  2311. }
  2312. static u32 cnic_service_bnx2_queues(struct cnic_dev *dev)
  2313. {
  2314. struct cnic_local *cp = dev->cnic_priv;
  2315. u32 status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2316. int kcqe_cnt;
  2317. /* status block index must be read before reading other fields */
  2318. rmb();
  2319. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2320. while ((kcqe_cnt = cnic_get_kcqes(dev, &cp->kcq1))) {
  2321. service_kcqes(dev, kcqe_cnt);
  2322. /* Tell compiler that status_blk fields can change. */
  2323. barrier();
  2324. if (status_idx != *cp->kcq1.status_idx_ptr) {
  2325. status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2326. /* status block index must be read first */
  2327. rmb();
  2328. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2329. } else
  2330. break;
  2331. }
  2332. CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx);
  2333. cnic_chk_pkt_rings(cp);
  2334. return status_idx;
  2335. }
  2336. static int cnic_service_bnx2(void *data, void *status_blk)
  2337. {
  2338. struct cnic_dev *dev = data;
  2339. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2340. struct status_block *sblk = status_blk;
  2341. return sblk->status_idx;
  2342. }
  2343. return cnic_service_bnx2_queues(dev);
  2344. }
  2345. static void cnic_service_bnx2_msix(unsigned long data)
  2346. {
  2347. struct cnic_dev *dev = (struct cnic_dev *) data;
  2348. struct cnic_local *cp = dev->cnic_priv;
  2349. cp->last_status_idx = cnic_service_bnx2_queues(dev);
  2350. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  2351. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  2352. }
  2353. static void cnic_doirq(struct cnic_dev *dev)
  2354. {
  2355. struct cnic_local *cp = dev->cnic_priv;
  2356. if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2357. u16 prod = cp->kcq1.sw_prod_idx & MAX_KCQ_IDX;
  2358. prefetch(cp->status_blk.gen);
  2359. prefetch(&cp->kcq1.kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
  2360. tasklet_schedule(&cp->cnic_irq_task);
  2361. }
  2362. }
  2363. static irqreturn_t cnic_irq(int irq, void *dev_instance)
  2364. {
  2365. struct cnic_dev *dev = dev_instance;
  2366. struct cnic_local *cp = dev->cnic_priv;
  2367. if (cp->ack_int)
  2368. cp->ack_int(dev);
  2369. cnic_doirq(dev);
  2370. return IRQ_HANDLED;
  2371. }
  2372. static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
  2373. u16 index, u8 op, u8 update)
  2374. {
  2375. struct cnic_local *cp = dev->cnic_priv;
  2376. u32 hc_addr = (HC_REG_COMMAND_REG + CNIC_PORT(cp) * 32 +
  2377. COMMAND_REG_INT_ACK);
  2378. struct igu_ack_register igu_ack;
  2379. igu_ack.status_block_index = index;
  2380. igu_ack.sb_id_and_flags =
  2381. ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
  2382. (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
  2383. (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
  2384. (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
  2385. CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
  2386. }
  2387. static void cnic_ack_igu_sb(struct cnic_dev *dev, u8 igu_sb_id, u8 segment,
  2388. u16 index, u8 op, u8 update)
  2389. {
  2390. struct igu_regular cmd_data;
  2391. u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
  2392. cmd_data.sb_id_and_flags =
  2393. (index << IGU_REGULAR_SB_INDEX_SHIFT) |
  2394. (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
  2395. (update << IGU_REGULAR_BUPDATE_SHIFT) |
  2396. (op << IGU_REGULAR_ENABLE_INT_SHIFT);
  2397. CNIC_WR(dev, igu_addr, cmd_data.sb_id_and_flags);
  2398. }
  2399. static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
  2400. {
  2401. struct cnic_local *cp = dev->cnic_priv;
  2402. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, 0,
  2403. IGU_INT_DISABLE, 0);
  2404. }
  2405. static void cnic_ack_bnx2x_e2_msix(struct cnic_dev *dev)
  2406. {
  2407. struct cnic_local *cp = dev->cnic_priv;
  2408. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, 0,
  2409. IGU_INT_DISABLE, 0);
  2410. }
  2411. static u32 cnic_service_bnx2x_kcq(struct cnic_dev *dev, struct kcq_info *info)
  2412. {
  2413. u32 last_status = *info->status_idx_ptr;
  2414. int kcqe_cnt;
  2415. /* status block index must be read before reading the KCQ */
  2416. rmb();
  2417. while ((kcqe_cnt = cnic_get_kcqes(dev, info))) {
  2418. service_kcqes(dev, kcqe_cnt);
  2419. /* Tell compiler that sblk fields can change. */
  2420. barrier();
  2421. if (last_status == *info->status_idx_ptr)
  2422. break;
  2423. last_status = *info->status_idx_ptr;
  2424. /* status block index must be read before reading the KCQ */
  2425. rmb();
  2426. }
  2427. return last_status;
  2428. }
  2429. static void cnic_service_bnx2x_bh(unsigned long data)
  2430. {
  2431. struct cnic_dev *dev = (struct cnic_dev *) data;
  2432. struct cnic_local *cp = dev->cnic_priv;
  2433. u32 status_idx, new_status_idx;
  2434. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  2435. return;
  2436. while (1) {
  2437. status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
  2438. CNIC_WR16(dev, cp->kcq1.io_addr,
  2439. cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
  2440. if (!BNX2X_CHIP_IS_E2(cp->chip_id)) {
  2441. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, USTORM_ID,
  2442. status_idx, IGU_INT_ENABLE, 1);
  2443. break;
  2444. }
  2445. new_status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq2);
  2446. if (new_status_idx != status_idx)
  2447. continue;
  2448. CNIC_WR16(dev, cp->kcq2.io_addr, cp->kcq2.sw_prod_idx +
  2449. MAX_KCQ_IDX);
  2450. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF,
  2451. status_idx, IGU_INT_ENABLE, 1);
  2452. break;
  2453. }
  2454. }
  2455. static int cnic_service_bnx2x(void *data, void *status_blk)
  2456. {
  2457. struct cnic_dev *dev = data;
  2458. struct cnic_local *cp = dev->cnic_priv;
  2459. if (!(cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  2460. cnic_doirq(dev);
  2461. cnic_chk_pkt_rings(cp);
  2462. return 0;
  2463. }
  2464. static void cnic_ulp_stop_one(struct cnic_local *cp, int if_type)
  2465. {
  2466. struct cnic_ulp_ops *ulp_ops;
  2467. if (if_type == CNIC_ULP_ISCSI)
  2468. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  2469. mutex_lock(&cnic_lock);
  2470. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  2471. lockdep_is_held(&cnic_lock));
  2472. if (!ulp_ops) {
  2473. mutex_unlock(&cnic_lock);
  2474. return;
  2475. }
  2476. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2477. mutex_unlock(&cnic_lock);
  2478. if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2479. ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
  2480. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2481. }
  2482. static void cnic_ulp_stop(struct cnic_dev *dev)
  2483. {
  2484. struct cnic_local *cp = dev->cnic_priv;
  2485. int if_type;
  2486. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++)
  2487. cnic_ulp_stop_one(cp, if_type);
  2488. }
  2489. static void cnic_ulp_start(struct cnic_dev *dev)
  2490. {
  2491. struct cnic_local *cp = dev->cnic_priv;
  2492. int if_type;
  2493. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  2494. struct cnic_ulp_ops *ulp_ops;
  2495. mutex_lock(&cnic_lock);
  2496. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  2497. lockdep_is_held(&cnic_lock));
  2498. if (!ulp_ops || !ulp_ops->cnic_start) {
  2499. mutex_unlock(&cnic_lock);
  2500. continue;
  2501. }
  2502. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2503. mutex_unlock(&cnic_lock);
  2504. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2505. ulp_ops->cnic_start(cp->ulp_handle[if_type]);
  2506. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2507. }
  2508. }
  2509. static int cnic_ctl(void *data, struct cnic_ctl_info *info)
  2510. {
  2511. struct cnic_dev *dev = data;
  2512. switch (info->cmd) {
  2513. case CNIC_CTL_STOP_CMD:
  2514. cnic_hold(dev);
  2515. cnic_ulp_stop(dev);
  2516. cnic_stop_hw(dev);
  2517. cnic_put(dev);
  2518. break;
  2519. case CNIC_CTL_START_CMD:
  2520. cnic_hold(dev);
  2521. if (!cnic_start_hw(dev))
  2522. cnic_ulp_start(dev);
  2523. cnic_put(dev);
  2524. break;
  2525. case CNIC_CTL_STOP_ISCSI_CMD: {
  2526. struct cnic_local *cp = dev->cnic_priv;
  2527. set_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags);
  2528. queue_delayed_work(cnic_wq, &cp->delete_task, 0);
  2529. break;
  2530. }
  2531. case CNIC_CTL_COMPLETION_CMD: {
  2532. u32 cid = BNX2X_SW_CID(info->data.comp.cid);
  2533. u32 l5_cid;
  2534. struct cnic_local *cp = dev->cnic_priv;
  2535. if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
  2536. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2537. ctx->wait_cond = 1;
  2538. wake_up(&ctx->waitq);
  2539. }
  2540. break;
  2541. }
  2542. default:
  2543. return -EINVAL;
  2544. }
  2545. return 0;
  2546. }
  2547. static void cnic_ulp_init(struct cnic_dev *dev)
  2548. {
  2549. int i;
  2550. struct cnic_local *cp = dev->cnic_priv;
  2551. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2552. struct cnic_ulp_ops *ulp_ops;
  2553. mutex_lock(&cnic_lock);
  2554. ulp_ops = cnic_ulp_tbl_prot(i);
  2555. if (!ulp_ops || !ulp_ops->cnic_init) {
  2556. mutex_unlock(&cnic_lock);
  2557. continue;
  2558. }
  2559. ulp_get(ulp_ops);
  2560. mutex_unlock(&cnic_lock);
  2561. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2562. ulp_ops->cnic_init(dev);
  2563. ulp_put(ulp_ops);
  2564. }
  2565. }
  2566. static void cnic_ulp_exit(struct cnic_dev *dev)
  2567. {
  2568. int i;
  2569. struct cnic_local *cp = dev->cnic_priv;
  2570. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2571. struct cnic_ulp_ops *ulp_ops;
  2572. mutex_lock(&cnic_lock);
  2573. ulp_ops = cnic_ulp_tbl_prot(i);
  2574. if (!ulp_ops || !ulp_ops->cnic_exit) {
  2575. mutex_unlock(&cnic_lock);
  2576. continue;
  2577. }
  2578. ulp_get(ulp_ops);
  2579. mutex_unlock(&cnic_lock);
  2580. if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2581. ulp_ops->cnic_exit(dev);
  2582. ulp_put(ulp_ops);
  2583. }
  2584. }
  2585. static int cnic_cm_offload_pg(struct cnic_sock *csk)
  2586. {
  2587. struct cnic_dev *dev = csk->dev;
  2588. struct l4_kwq_offload_pg *l4kwqe;
  2589. struct kwqe *wqes[1];
  2590. l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
  2591. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2592. wqes[0] = (struct kwqe *) l4kwqe;
  2593. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
  2594. l4kwqe->flags =
  2595. L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
  2596. l4kwqe->l2hdr_nbytes = ETH_HLEN;
  2597. l4kwqe->da0 = csk->ha[0];
  2598. l4kwqe->da1 = csk->ha[1];
  2599. l4kwqe->da2 = csk->ha[2];
  2600. l4kwqe->da3 = csk->ha[3];
  2601. l4kwqe->da4 = csk->ha[4];
  2602. l4kwqe->da5 = csk->ha[5];
  2603. l4kwqe->sa0 = dev->mac_addr[0];
  2604. l4kwqe->sa1 = dev->mac_addr[1];
  2605. l4kwqe->sa2 = dev->mac_addr[2];
  2606. l4kwqe->sa3 = dev->mac_addr[3];
  2607. l4kwqe->sa4 = dev->mac_addr[4];
  2608. l4kwqe->sa5 = dev->mac_addr[5];
  2609. l4kwqe->etype = ETH_P_IP;
  2610. l4kwqe->ipid_start = DEF_IPID_START;
  2611. l4kwqe->host_opaque = csk->l5_cid;
  2612. if (csk->vlan_id) {
  2613. l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
  2614. l4kwqe->vlan_tag = csk->vlan_id;
  2615. l4kwqe->l2hdr_nbytes += 4;
  2616. }
  2617. return dev->submit_kwqes(dev, wqes, 1);
  2618. }
  2619. static int cnic_cm_update_pg(struct cnic_sock *csk)
  2620. {
  2621. struct cnic_dev *dev = csk->dev;
  2622. struct l4_kwq_update_pg *l4kwqe;
  2623. struct kwqe *wqes[1];
  2624. l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
  2625. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2626. wqes[0] = (struct kwqe *) l4kwqe;
  2627. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
  2628. l4kwqe->flags =
  2629. L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
  2630. l4kwqe->pg_cid = csk->pg_cid;
  2631. l4kwqe->da0 = csk->ha[0];
  2632. l4kwqe->da1 = csk->ha[1];
  2633. l4kwqe->da2 = csk->ha[2];
  2634. l4kwqe->da3 = csk->ha[3];
  2635. l4kwqe->da4 = csk->ha[4];
  2636. l4kwqe->da5 = csk->ha[5];
  2637. l4kwqe->pg_host_opaque = csk->l5_cid;
  2638. l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
  2639. return dev->submit_kwqes(dev, wqes, 1);
  2640. }
  2641. static int cnic_cm_upload_pg(struct cnic_sock *csk)
  2642. {
  2643. struct cnic_dev *dev = csk->dev;
  2644. struct l4_kwq_upload *l4kwqe;
  2645. struct kwqe *wqes[1];
  2646. l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
  2647. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2648. wqes[0] = (struct kwqe *) l4kwqe;
  2649. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
  2650. l4kwqe->flags =
  2651. L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
  2652. l4kwqe->cid = csk->pg_cid;
  2653. return dev->submit_kwqes(dev, wqes, 1);
  2654. }
  2655. static int cnic_cm_conn_req(struct cnic_sock *csk)
  2656. {
  2657. struct cnic_dev *dev = csk->dev;
  2658. struct l4_kwq_connect_req1 *l4kwqe1;
  2659. struct l4_kwq_connect_req2 *l4kwqe2;
  2660. struct l4_kwq_connect_req3 *l4kwqe3;
  2661. struct kwqe *wqes[3];
  2662. u8 tcp_flags = 0;
  2663. int num_wqes = 2;
  2664. l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
  2665. l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
  2666. l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
  2667. memset(l4kwqe1, 0, sizeof(*l4kwqe1));
  2668. memset(l4kwqe2, 0, sizeof(*l4kwqe2));
  2669. memset(l4kwqe3, 0, sizeof(*l4kwqe3));
  2670. l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
  2671. l4kwqe3->flags =
  2672. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
  2673. l4kwqe3->ka_timeout = csk->ka_timeout;
  2674. l4kwqe3->ka_interval = csk->ka_interval;
  2675. l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
  2676. l4kwqe3->tos = csk->tos;
  2677. l4kwqe3->ttl = csk->ttl;
  2678. l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
  2679. l4kwqe3->pmtu = csk->mtu;
  2680. l4kwqe3->rcv_buf = csk->rcv_buf;
  2681. l4kwqe3->snd_buf = csk->snd_buf;
  2682. l4kwqe3->seed = csk->seed;
  2683. wqes[0] = (struct kwqe *) l4kwqe1;
  2684. if (test_bit(SK_F_IPV6, &csk->flags)) {
  2685. wqes[1] = (struct kwqe *) l4kwqe2;
  2686. wqes[2] = (struct kwqe *) l4kwqe3;
  2687. num_wqes = 3;
  2688. l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
  2689. l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
  2690. l4kwqe2->flags =
  2691. L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
  2692. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
  2693. l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
  2694. l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
  2695. l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
  2696. l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
  2697. l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
  2698. l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
  2699. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
  2700. sizeof(struct tcphdr);
  2701. } else {
  2702. wqes[1] = (struct kwqe *) l4kwqe3;
  2703. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
  2704. sizeof(struct tcphdr);
  2705. }
  2706. l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
  2707. l4kwqe1->flags =
  2708. (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
  2709. L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
  2710. l4kwqe1->cid = csk->cid;
  2711. l4kwqe1->pg_cid = csk->pg_cid;
  2712. l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
  2713. l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
  2714. l4kwqe1->src_port = be16_to_cpu(csk->src_port);
  2715. l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
  2716. if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
  2717. tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
  2718. if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
  2719. tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
  2720. if (csk->tcp_flags & SK_TCP_NAGLE)
  2721. tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
  2722. if (csk->tcp_flags & SK_TCP_TIMESTAMP)
  2723. tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
  2724. if (csk->tcp_flags & SK_TCP_SACK)
  2725. tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
  2726. if (csk->tcp_flags & SK_TCP_SEG_SCALING)
  2727. tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
  2728. l4kwqe1->tcp_flags = tcp_flags;
  2729. return dev->submit_kwqes(dev, wqes, num_wqes);
  2730. }
  2731. static int cnic_cm_close_req(struct cnic_sock *csk)
  2732. {
  2733. struct cnic_dev *dev = csk->dev;
  2734. struct l4_kwq_close_req *l4kwqe;
  2735. struct kwqe *wqes[1];
  2736. l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
  2737. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2738. wqes[0] = (struct kwqe *) l4kwqe;
  2739. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
  2740. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
  2741. l4kwqe->cid = csk->cid;
  2742. return dev->submit_kwqes(dev, wqes, 1);
  2743. }
  2744. static int cnic_cm_abort_req(struct cnic_sock *csk)
  2745. {
  2746. struct cnic_dev *dev = csk->dev;
  2747. struct l4_kwq_reset_req *l4kwqe;
  2748. struct kwqe *wqes[1];
  2749. l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
  2750. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2751. wqes[0] = (struct kwqe *) l4kwqe;
  2752. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
  2753. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
  2754. l4kwqe->cid = csk->cid;
  2755. return dev->submit_kwqes(dev, wqes, 1);
  2756. }
  2757. static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
  2758. u32 l5_cid, struct cnic_sock **csk, void *context)
  2759. {
  2760. struct cnic_local *cp = dev->cnic_priv;
  2761. struct cnic_sock *csk1;
  2762. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2763. return -EINVAL;
  2764. if (cp->ctx_tbl) {
  2765. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2766. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2767. return -EAGAIN;
  2768. }
  2769. csk1 = &cp->csk_tbl[l5_cid];
  2770. if (atomic_read(&csk1->ref_count))
  2771. return -EAGAIN;
  2772. if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
  2773. return -EBUSY;
  2774. csk1->dev = dev;
  2775. csk1->cid = cid;
  2776. csk1->l5_cid = l5_cid;
  2777. csk1->ulp_type = ulp_type;
  2778. csk1->context = context;
  2779. csk1->ka_timeout = DEF_KA_TIMEOUT;
  2780. csk1->ka_interval = DEF_KA_INTERVAL;
  2781. csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
  2782. csk1->tos = DEF_TOS;
  2783. csk1->ttl = DEF_TTL;
  2784. csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
  2785. csk1->rcv_buf = DEF_RCV_BUF;
  2786. csk1->snd_buf = DEF_SND_BUF;
  2787. csk1->seed = DEF_SEED;
  2788. *csk = csk1;
  2789. return 0;
  2790. }
  2791. static void cnic_cm_cleanup(struct cnic_sock *csk)
  2792. {
  2793. if (csk->src_port) {
  2794. struct cnic_dev *dev = csk->dev;
  2795. struct cnic_local *cp = dev->cnic_priv;
  2796. cnic_free_id(&cp->csk_port_tbl, be16_to_cpu(csk->src_port));
  2797. csk->src_port = 0;
  2798. }
  2799. }
  2800. static void cnic_close_conn(struct cnic_sock *csk)
  2801. {
  2802. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
  2803. cnic_cm_upload_pg(csk);
  2804. clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  2805. }
  2806. cnic_cm_cleanup(csk);
  2807. }
  2808. static int cnic_cm_destroy(struct cnic_sock *csk)
  2809. {
  2810. if (!cnic_in_use(csk))
  2811. return -EINVAL;
  2812. csk_hold(csk);
  2813. clear_bit(SK_F_INUSE, &csk->flags);
  2814. smp_mb__after_clear_bit();
  2815. while (atomic_read(&csk->ref_count) != 1)
  2816. msleep(1);
  2817. cnic_cm_cleanup(csk);
  2818. csk->flags = 0;
  2819. csk_put(csk);
  2820. return 0;
  2821. }
  2822. static inline u16 cnic_get_vlan(struct net_device *dev,
  2823. struct net_device **vlan_dev)
  2824. {
  2825. if (dev->priv_flags & IFF_802_1Q_VLAN) {
  2826. *vlan_dev = vlan_dev_real_dev(dev);
  2827. return vlan_dev_vlan_id(dev);
  2828. }
  2829. *vlan_dev = dev;
  2830. return 0;
  2831. }
  2832. static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
  2833. struct dst_entry **dst)
  2834. {
  2835. #if defined(CONFIG_INET)
  2836. struct rtable *rt;
  2837. rt = ip_route_output(&init_net, dst_addr->sin_addr.s_addr, 0, 0, 0);
  2838. if (!IS_ERR(rt)) {
  2839. *dst = &rt->dst;
  2840. return 0;
  2841. }
  2842. return PTR_ERR(rt);
  2843. #else
  2844. return -ENETUNREACH;
  2845. #endif
  2846. }
  2847. static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
  2848. struct dst_entry **dst)
  2849. {
  2850. #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
  2851. struct flowi6 fl6;
  2852. memset(&fl6, 0, sizeof(fl6));
  2853. ipv6_addr_copy(&fl6.daddr, &dst_addr->sin6_addr);
  2854. if (ipv6_addr_type(&fl6.daddr) & IPV6_ADDR_LINKLOCAL)
  2855. fl6.flowi6_oif = dst_addr->sin6_scope_id;
  2856. *dst = ip6_route_output(&init_net, NULL, &fl6);
  2857. if (*dst)
  2858. return 0;
  2859. #endif
  2860. return -ENETUNREACH;
  2861. }
  2862. static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
  2863. int ulp_type)
  2864. {
  2865. struct cnic_dev *dev = NULL;
  2866. struct dst_entry *dst;
  2867. struct net_device *netdev = NULL;
  2868. int err = -ENETUNREACH;
  2869. if (dst_addr->sin_family == AF_INET)
  2870. err = cnic_get_v4_route(dst_addr, &dst);
  2871. else if (dst_addr->sin_family == AF_INET6) {
  2872. struct sockaddr_in6 *dst_addr6 =
  2873. (struct sockaddr_in6 *) dst_addr;
  2874. err = cnic_get_v6_route(dst_addr6, &dst);
  2875. } else
  2876. return NULL;
  2877. if (err)
  2878. return NULL;
  2879. if (!dst->dev)
  2880. goto done;
  2881. cnic_get_vlan(dst->dev, &netdev);
  2882. dev = cnic_from_netdev(netdev);
  2883. done:
  2884. dst_release(dst);
  2885. if (dev)
  2886. cnic_put(dev);
  2887. return dev;
  2888. }
  2889. static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2890. {
  2891. struct cnic_dev *dev = csk->dev;
  2892. struct cnic_local *cp = dev->cnic_priv;
  2893. return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
  2894. }
  2895. static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2896. {
  2897. struct cnic_dev *dev = csk->dev;
  2898. struct cnic_local *cp = dev->cnic_priv;
  2899. int is_v6, rc = 0;
  2900. struct dst_entry *dst = NULL;
  2901. struct net_device *realdev;
  2902. __be16 local_port;
  2903. u32 port_id;
  2904. if (saddr->local.v6.sin6_family == AF_INET6 &&
  2905. saddr->remote.v6.sin6_family == AF_INET6)
  2906. is_v6 = 1;
  2907. else if (saddr->local.v4.sin_family == AF_INET &&
  2908. saddr->remote.v4.sin_family == AF_INET)
  2909. is_v6 = 0;
  2910. else
  2911. return -EINVAL;
  2912. clear_bit(SK_F_IPV6, &csk->flags);
  2913. if (is_v6) {
  2914. set_bit(SK_F_IPV6, &csk->flags);
  2915. cnic_get_v6_route(&saddr->remote.v6, &dst);
  2916. memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
  2917. sizeof(struct in6_addr));
  2918. csk->dst_port = saddr->remote.v6.sin6_port;
  2919. local_port = saddr->local.v6.sin6_port;
  2920. } else {
  2921. cnic_get_v4_route(&saddr->remote.v4, &dst);
  2922. csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
  2923. csk->dst_port = saddr->remote.v4.sin_port;
  2924. local_port = saddr->local.v4.sin_port;
  2925. }
  2926. csk->vlan_id = 0;
  2927. csk->mtu = dev->netdev->mtu;
  2928. if (dst && dst->dev) {
  2929. u16 vlan = cnic_get_vlan(dst->dev, &realdev);
  2930. if (realdev == dev->netdev) {
  2931. csk->vlan_id = vlan;
  2932. csk->mtu = dst_mtu(dst);
  2933. }
  2934. }
  2935. port_id = be16_to_cpu(local_port);
  2936. if (port_id >= CNIC_LOCAL_PORT_MIN &&
  2937. port_id < CNIC_LOCAL_PORT_MAX) {
  2938. if (cnic_alloc_id(&cp->csk_port_tbl, port_id))
  2939. port_id = 0;
  2940. } else
  2941. port_id = 0;
  2942. if (!port_id) {
  2943. port_id = cnic_alloc_new_id(&cp->csk_port_tbl);
  2944. if (port_id == -1) {
  2945. rc = -ENOMEM;
  2946. goto err_out;
  2947. }
  2948. local_port = cpu_to_be16(port_id);
  2949. }
  2950. csk->src_port = local_port;
  2951. err_out:
  2952. dst_release(dst);
  2953. return rc;
  2954. }
  2955. static void cnic_init_csk_state(struct cnic_sock *csk)
  2956. {
  2957. csk->state = 0;
  2958. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2959. clear_bit(SK_F_CLOSING, &csk->flags);
  2960. }
  2961. static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2962. {
  2963. struct cnic_local *cp = csk->dev->cnic_priv;
  2964. int err = 0;
  2965. if (cp->ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI)
  2966. return -EOPNOTSUPP;
  2967. if (!cnic_in_use(csk))
  2968. return -EINVAL;
  2969. if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
  2970. return -EINVAL;
  2971. cnic_init_csk_state(csk);
  2972. err = cnic_get_route(csk, saddr);
  2973. if (err)
  2974. goto err_out;
  2975. err = cnic_resolve_addr(csk, saddr);
  2976. if (!err)
  2977. return 0;
  2978. err_out:
  2979. clear_bit(SK_F_CONNECT_START, &csk->flags);
  2980. return err;
  2981. }
  2982. static int cnic_cm_abort(struct cnic_sock *csk)
  2983. {
  2984. struct cnic_local *cp = csk->dev->cnic_priv;
  2985. u32 opcode = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  2986. if (!cnic_in_use(csk))
  2987. return -EINVAL;
  2988. if (cnic_abort_prep(csk))
  2989. return cnic_cm_abort_req(csk);
  2990. /* Getting here means that we haven't started connect, or
  2991. * connect was not successful.
  2992. */
  2993. cp->close_conn(csk, opcode);
  2994. if (csk->state != opcode)
  2995. return -EALREADY;
  2996. return 0;
  2997. }
  2998. static int cnic_cm_close(struct cnic_sock *csk)
  2999. {
  3000. if (!cnic_in_use(csk))
  3001. return -EINVAL;
  3002. if (cnic_close_prep(csk)) {
  3003. csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  3004. return cnic_cm_close_req(csk);
  3005. } else {
  3006. return -EALREADY;
  3007. }
  3008. return 0;
  3009. }
  3010. static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
  3011. u8 opcode)
  3012. {
  3013. struct cnic_ulp_ops *ulp_ops;
  3014. int ulp_type = csk->ulp_type;
  3015. rcu_read_lock();
  3016. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  3017. if (ulp_ops) {
  3018. if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
  3019. ulp_ops->cm_connect_complete(csk);
  3020. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  3021. ulp_ops->cm_close_complete(csk);
  3022. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
  3023. ulp_ops->cm_remote_abort(csk);
  3024. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
  3025. ulp_ops->cm_abort_complete(csk);
  3026. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
  3027. ulp_ops->cm_remote_close(csk);
  3028. }
  3029. rcu_read_unlock();
  3030. }
  3031. static int cnic_cm_set_pg(struct cnic_sock *csk)
  3032. {
  3033. if (cnic_offld_prep(csk)) {
  3034. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3035. cnic_cm_update_pg(csk);
  3036. else
  3037. cnic_cm_offload_pg(csk);
  3038. }
  3039. return 0;
  3040. }
  3041. static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
  3042. {
  3043. struct cnic_local *cp = dev->cnic_priv;
  3044. u32 l5_cid = kcqe->pg_host_opaque;
  3045. u8 opcode = kcqe->op_code;
  3046. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  3047. csk_hold(csk);
  3048. if (!cnic_in_use(csk))
  3049. goto done;
  3050. if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3051. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3052. goto done;
  3053. }
  3054. /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */
  3055. if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) {
  3056. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3057. cnic_cm_upcall(cp, csk,
  3058. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3059. goto done;
  3060. }
  3061. csk->pg_cid = kcqe->pg_cid;
  3062. set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  3063. cnic_cm_conn_req(csk);
  3064. done:
  3065. csk_put(csk);
  3066. }
  3067. static void cnic_process_fcoe_term_conn(struct cnic_dev *dev, struct kcqe *kcqe)
  3068. {
  3069. struct cnic_local *cp = dev->cnic_priv;
  3070. struct fcoe_kcqe *fc_kcqe = (struct fcoe_kcqe *) kcqe;
  3071. u32 l5_cid = fc_kcqe->fcoe_conn_id + BNX2X_FCOE_L5_CID_BASE;
  3072. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  3073. ctx->timestamp = jiffies;
  3074. ctx->wait_cond = 1;
  3075. wake_up(&ctx->waitq);
  3076. }
  3077. static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
  3078. {
  3079. struct cnic_local *cp = dev->cnic_priv;
  3080. struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
  3081. u8 opcode = l4kcqe->op_code;
  3082. u32 l5_cid;
  3083. struct cnic_sock *csk;
  3084. if (opcode == FCOE_RAMROD_CMD_ID_TERMINATE_CONN) {
  3085. cnic_process_fcoe_term_conn(dev, kcqe);
  3086. return;
  3087. }
  3088. if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
  3089. opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3090. cnic_cm_process_offld_pg(dev, l4kcqe);
  3091. return;
  3092. }
  3093. l5_cid = l4kcqe->conn_id;
  3094. if (opcode & 0x80)
  3095. l5_cid = l4kcqe->cid;
  3096. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  3097. return;
  3098. csk = &cp->csk_tbl[l5_cid];
  3099. csk_hold(csk);
  3100. if (!cnic_in_use(csk)) {
  3101. csk_put(csk);
  3102. return;
  3103. }
  3104. switch (opcode) {
  3105. case L5CM_RAMROD_CMD_ID_TCP_CONNECT:
  3106. if (l4kcqe->status != 0) {
  3107. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3108. cnic_cm_upcall(cp, csk,
  3109. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3110. }
  3111. break;
  3112. case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
  3113. if (l4kcqe->status == 0)
  3114. set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
  3115. smp_mb__before_clear_bit();
  3116. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3117. cnic_cm_upcall(cp, csk, opcode);
  3118. break;
  3119. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3120. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3121. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3122. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3123. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3124. cp->close_conn(csk, opcode);
  3125. break;
  3126. case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
  3127. cnic_cm_upcall(cp, csk, opcode);
  3128. break;
  3129. }
  3130. csk_put(csk);
  3131. }
  3132. static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
  3133. {
  3134. struct cnic_dev *dev = data;
  3135. int i;
  3136. for (i = 0; i < num; i++)
  3137. cnic_cm_process_kcqe(dev, kcqe[i]);
  3138. }
  3139. static struct cnic_ulp_ops cm_ulp_ops = {
  3140. .indicate_kcqes = cnic_cm_indicate_kcqe,
  3141. };
  3142. static void cnic_cm_free_mem(struct cnic_dev *dev)
  3143. {
  3144. struct cnic_local *cp = dev->cnic_priv;
  3145. kfree(cp->csk_tbl);
  3146. cp->csk_tbl = NULL;
  3147. cnic_free_id_tbl(&cp->csk_port_tbl);
  3148. }
  3149. static int cnic_cm_alloc_mem(struct cnic_dev *dev)
  3150. {
  3151. struct cnic_local *cp = dev->cnic_priv;
  3152. cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ,
  3153. GFP_KERNEL);
  3154. if (!cp->csk_tbl)
  3155. return -ENOMEM;
  3156. if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
  3157. CNIC_LOCAL_PORT_MIN)) {
  3158. cnic_cm_free_mem(dev);
  3159. return -ENOMEM;
  3160. }
  3161. return 0;
  3162. }
  3163. static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
  3164. {
  3165. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  3166. /* Unsolicited RESET_COMP or RESET_RECEIVED */
  3167. opcode = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;
  3168. csk->state = opcode;
  3169. }
  3170. /* 1. If event opcode matches the expected event in csk->state
  3171. * 2. If the expected event is CLOSE_COMP, we accept any event
  3172. * 3. If the expected event is 0, meaning the connection was never
  3173. * never established, we accept the opcode from cm_abort.
  3174. */
  3175. if (opcode == csk->state || csk->state == 0 ||
  3176. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP) {
  3177. if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) {
  3178. if (csk->state == 0)
  3179. csk->state = opcode;
  3180. return 1;
  3181. }
  3182. }
  3183. return 0;
  3184. }
  3185. static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
  3186. {
  3187. struct cnic_dev *dev = csk->dev;
  3188. struct cnic_local *cp = dev->cnic_priv;
  3189. if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED) {
  3190. cnic_cm_upcall(cp, csk, opcode);
  3191. return;
  3192. }
  3193. clear_bit(SK_F_CONNECT_START, &csk->flags);
  3194. cnic_close_conn(csk);
  3195. csk->state = opcode;
  3196. cnic_cm_upcall(cp, csk, opcode);
  3197. }
  3198. static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
  3199. {
  3200. }
  3201. static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
  3202. {
  3203. u32 seed;
  3204. get_random_bytes(&seed, 4);
  3205. cnic_ctx_wr(dev, 45, 0, seed);
  3206. return 0;
  3207. }
  3208. static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
  3209. {
  3210. struct cnic_dev *dev = csk->dev;
  3211. struct cnic_local *cp = dev->cnic_priv;
  3212. struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
  3213. union l5cm_specific_data l5_data;
  3214. u32 cmd = 0;
  3215. int close_complete = 0;
  3216. switch (opcode) {
  3217. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3218. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3219. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3220. if (cnic_ready_to_close(csk, opcode)) {
  3221. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3222. cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
  3223. else
  3224. close_complete = 1;
  3225. }
  3226. break;
  3227. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3228. cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
  3229. break;
  3230. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3231. close_complete = 1;
  3232. break;
  3233. }
  3234. if (cmd) {
  3235. memset(&l5_data, 0, sizeof(l5_data));
  3236. cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
  3237. &l5_data);
  3238. } else if (close_complete) {
  3239. ctx->timestamp = jiffies;
  3240. cnic_close_conn(csk);
  3241. cnic_cm_upcall(cp, csk, csk->state);
  3242. }
  3243. }
  3244. static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
  3245. {
  3246. struct cnic_local *cp = dev->cnic_priv;
  3247. int i;
  3248. if (!cp->ctx_tbl)
  3249. return;
  3250. if (!netif_running(dev->netdev))
  3251. return;
  3252. for (i = 0; i < cp->max_cid_space; i++) {
  3253. struct cnic_context *ctx = &cp->ctx_tbl[i];
  3254. while (test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3255. msleep(10);
  3256. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  3257. netdev_warn(dev->netdev, "CID %x not deleted\n",
  3258. ctx->cid);
  3259. }
  3260. cancel_delayed_work(&cp->delete_task);
  3261. flush_workqueue(cnic_wq);
  3262. if (atomic_read(&cp->iscsi_conn) != 0)
  3263. netdev_warn(dev->netdev, "%d iSCSI connections not destroyed\n",
  3264. atomic_read(&cp->iscsi_conn));
  3265. }
  3266. static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
  3267. {
  3268. struct cnic_local *cp = dev->cnic_priv;
  3269. u32 pfid = cp->pfid;
  3270. u32 port = CNIC_PORT(cp);
  3271. cnic_init_bnx2x_mac(dev);
  3272. cnic_bnx2x_set_tcp_timestamp(dev, 1);
  3273. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  3274. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfid), 0);
  3275. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3276. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port), 1);
  3277. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3278. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port),
  3279. DEF_MAX_DA_COUNT);
  3280. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3281. XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfid), DEF_TTL);
  3282. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3283. XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfid), DEF_TOS);
  3284. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3285. XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfid), 2);
  3286. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3287. XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfid), DEF_SWS_TIMER);
  3288. CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(pfid),
  3289. DEF_MAX_CWND);
  3290. return 0;
  3291. }
  3292. static void cnic_delete_task(struct work_struct *work)
  3293. {
  3294. struct cnic_local *cp;
  3295. struct cnic_dev *dev;
  3296. u32 i;
  3297. int need_resched = 0;
  3298. cp = container_of(work, struct cnic_local, delete_task.work);
  3299. dev = cp->dev;
  3300. if (test_and_clear_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags)) {
  3301. struct drv_ctl_info info;
  3302. cnic_ulp_stop_one(cp, CNIC_ULP_ISCSI);
  3303. info.cmd = DRV_CTL_ISCSI_STOPPED_CMD;
  3304. cp->ethdev->drv_ctl(dev->netdev, &info);
  3305. }
  3306. for (i = 0; i < cp->max_cid_space; i++) {
  3307. struct cnic_context *ctx = &cp->ctx_tbl[i];
  3308. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags) ||
  3309. !test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3310. continue;
  3311. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  3312. need_resched = 1;
  3313. continue;
  3314. }
  3315. if (!test_and_clear_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3316. continue;
  3317. cnic_bnx2x_destroy_ramrod(dev, i);
  3318. cnic_free_bnx2x_conn_resc(dev, i);
  3319. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI)
  3320. atomic_dec(&cp->iscsi_conn);
  3321. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  3322. }
  3323. if (need_resched)
  3324. queue_delayed_work(cnic_wq, &cp->delete_task,
  3325. msecs_to_jiffies(10));
  3326. }
  3327. static int cnic_cm_open(struct cnic_dev *dev)
  3328. {
  3329. struct cnic_local *cp = dev->cnic_priv;
  3330. int err;
  3331. err = cnic_cm_alloc_mem(dev);
  3332. if (err)
  3333. return err;
  3334. err = cp->start_cm(dev);
  3335. if (err)
  3336. goto err_out;
  3337. INIT_DELAYED_WORK(&cp->delete_task, cnic_delete_task);
  3338. dev->cm_create = cnic_cm_create;
  3339. dev->cm_destroy = cnic_cm_destroy;
  3340. dev->cm_connect = cnic_cm_connect;
  3341. dev->cm_abort = cnic_cm_abort;
  3342. dev->cm_close = cnic_cm_close;
  3343. dev->cm_select_dev = cnic_cm_select_dev;
  3344. cp->ulp_handle[CNIC_ULP_L4] = dev;
  3345. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
  3346. return 0;
  3347. err_out:
  3348. cnic_cm_free_mem(dev);
  3349. return err;
  3350. }
  3351. static int cnic_cm_shutdown(struct cnic_dev *dev)
  3352. {
  3353. struct cnic_local *cp = dev->cnic_priv;
  3354. int i;
  3355. cp->stop_cm(dev);
  3356. if (!cp->csk_tbl)
  3357. return 0;
  3358. for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
  3359. struct cnic_sock *csk = &cp->csk_tbl[i];
  3360. clear_bit(SK_F_INUSE, &csk->flags);
  3361. cnic_cm_cleanup(csk);
  3362. }
  3363. cnic_cm_free_mem(dev);
  3364. return 0;
  3365. }
  3366. static void cnic_init_context(struct cnic_dev *dev, u32 cid)
  3367. {
  3368. u32 cid_addr;
  3369. int i;
  3370. cid_addr = GET_CID_ADDR(cid);
  3371. for (i = 0; i < CTX_SIZE; i += 4)
  3372. cnic_ctx_wr(dev, cid_addr, i, 0);
  3373. }
  3374. static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
  3375. {
  3376. struct cnic_local *cp = dev->cnic_priv;
  3377. int ret = 0, i;
  3378. u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
  3379. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3380. return 0;
  3381. for (i = 0; i < cp->ctx_blks; i++) {
  3382. int j;
  3383. u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
  3384. u32 val;
  3385. memset(cp->ctx_arr[i].ctx, 0, BCM_PAGE_SIZE);
  3386. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
  3387. (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
  3388. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
  3389. (u64) cp->ctx_arr[i].mapping >> 32);
  3390. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
  3391. BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
  3392. for (j = 0; j < 10; j++) {
  3393. val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
  3394. if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
  3395. break;
  3396. udelay(5);
  3397. }
  3398. if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
  3399. ret = -EBUSY;
  3400. break;
  3401. }
  3402. }
  3403. return ret;
  3404. }
  3405. static void cnic_free_irq(struct cnic_dev *dev)
  3406. {
  3407. struct cnic_local *cp = dev->cnic_priv;
  3408. struct cnic_eth_dev *ethdev = cp->ethdev;
  3409. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3410. cp->disable_int_sync(dev);
  3411. tasklet_kill(&cp->cnic_irq_task);
  3412. free_irq(ethdev->irq_arr[0].vector, dev);
  3413. }
  3414. }
  3415. static int cnic_request_irq(struct cnic_dev *dev)
  3416. {
  3417. struct cnic_local *cp = dev->cnic_priv;
  3418. struct cnic_eth_dev *ethdev = cp->ethdev;
  3419. int err;
  3420. err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0, "cnic", dev);
  3421. if (err)
  3422. tasklet_disable(&cp->cnic_irq_task);
  3423. return err;
  3424. }
  3425. static int cnic_init_bnx2_irq(struct cnic_dev *dev)
  3426. {
  3427. struct cnic_local *cp = dev->cnic_priv;
  3428. struct cnic_eth_dev *ethdev = cp->ethdev;
  3429. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3430. int err, i = 0;
  3431. int sblk_num = cp->status_blk_num;
  3432. u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
  3433. BNX2_HC_SB_CONFIG_1;
  3434. CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
  3435. CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
  3436. CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
  3437. CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
  3438. cp->last_status_idx = cp->status_blk.bnx2->status_idx;
  3439. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2_msix,
  3440. (unsigned long) dev);
  3441. err = cnic_request_irq(dev);
  3442. if (err)
  3443. return err;
  3444. while (cp->status_blk.bnx2->status_completion_producer_index &&
  3445. i < 10) {
  3446. CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
  3447. 1 << (11 + sblk_num));
  3448. udelay(10);
  3449. i++;
  3450. barrier();
  3451. }
  3452. if (cp->status_blk.bnx2->status_completion_producer_index) {
  3453. cnic_free_irq(dev);
  3454. goto failed;
  3455. }
  3456. } else {
  3457. struct status_block *sblk = cp->status_blk.gen;
  3458. u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
  3459. int i = 0;
  3460. while (sblk->status_completion_producer_index && i < 10) {
  3461. CNIC_WR(dev, BNX2_HC_COMMAND,
  3462. hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  3463. udelay(10);
  3464. i++;
  3465. barrier();
  3466. }
  3467. if (sblk->status_completion_producer_index)
  3468. goto failed;
  3469. }
  3470. return 0;
  3471. failed:
  3472. netdev_err(dev->netdev, "KCQ index not resetting to 0\n");
  3473. return -EBUSY;
  3474. }
  3475. static void cnic_enable_bnx2_int(struct cnic_dev *dev)
  3476. {
  3477. struct cnic_local *cp = dev->cnic_priv;
  3478. struct cnic_eth_dev *ethdev = cp->ethdev;
  3479. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3480. return;
  3481. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3482. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  3483. }
  3484. static void cnic_get_bnx2_iscsi_info(struct cnic_dev *dev)
  3485. {
  3486. u32 max_conn;
  3487. max_conn = cnic_reg_rd_ind(dev, BNX2_FW_MAX_ISCSI_CONN);
  3488. dev->max_iscsi_conn = max_conn;
  3489. }
  3490. static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
  3491. {
  3492. struct cnic_local *cp = dev->cnic_priv;
  3493. struct cnic_eth_dev *ethdev = cp->ethdev;
  3494. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3495. return;
  3496. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3497. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  3498. CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
  3499. synchronize_irq(ethdev->irq_arr[0].vector);
  3500. }
  3501. static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
  3502. {
  3503. struct cnic_local *cp = dev->cnic_priv;
  3504. struct cnic_eth_dev *ethdev = cp->ethdev;
  3505. struct cnic_uio_dev *udev = cp->udev;
  3506. u32 cid_addr, tx_cid, sb_id;
  3507. u32 val, offset0, offset1, offset2, offset3;
  3508. int i;
  3509. struct tx_bd *txbd;
  3510. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3511. struct status_block *s_blk = cp->status_blk.gen;
  3512. sb_id = cp->status_blk_num;
  3513. tx_cid = 20;
  3514. cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
  3515. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3516. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3517. tx_cid = TX_TSS_CID + sb_id - 1;
  3518. CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
  3519. (TX_TSS_CID << 7));
  3520. cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
  3521. }
  3522. cp->tx_cons = *cp->tx_cons_ptr;
  3523. cid_addr = GET_CID_ADDR(tx_cid);
  3524. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  3525. u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
  3526. for (i = 0; i < PHY_CTX_SIZE; i += 4)
  3527. cnic_ctx_wr(dev, cid_addr2, i, 0);
  3528. offset0 = BNX2_L2CTX_TYPE_XI;
  3529. offset1 = BNX2_L2CTX_CMD_TYPE_XI;
  3530. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
  3531. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
  3532. } else {
  3533. cnic_init_context(dev, tx_cid);
  3534. cnic_init_context(dev, tx_cid + 1);
  3535. offset0 = BNX2_L2CTX_TYPE;
  3536. offset1 = BNX2_L2CTX_CMD_TYPE;
  3537. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
  3538. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
  3539. }
  3540. val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
  3541. cnic_ctx_wr(dev, cid_addr, offset0, val);
  3542. val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
  3543. cnic_ctx_wr(dev, cid_addr, offset1, val);
  3544. txbd = (struct tx_bd *) udev->l2_ring;
  3545. buf_map = udev->l2_buf_map;
  3546. for (i = 0; i < MAX_TX_DESC_CNT; i++, txbd++) {
  3547. txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
  3548. txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3549. }
  3550. val = (u64) ring_map >> 32;
  3551. cnic_ctx_wr(dev, cid_addr, offset2, val);
  3552. txbd->tx_bd_haddr_hi = val;
  3553. val = (u64) ring_map & 0xffffffff;
  3554. cnic_ctx_wr(dev, cid_addr, offset3, val);
  3555. txbd->tx_bd_haddr_lo = val;
  3556. }
  3557. static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
  3558. {
  3559. struct cnic_local *cp = dev->cnic_priv;
  3560. struct cnic_eth_dev *ethdev = cp->ethdev;
  3561. struct cnic_uio_dev *udev = cp->udev;
  3562. u32 cid_addr, sb_id, val, coal_reg, coal_val;
  3563. int i;
  3564. struct rx_bd *rxbd;
  3565. struct status_block *s_blk = cp->status_blk.gen;
  3566. dma_addr_t ring_map = udev->l2_ring_map;
  3567. sb_id = cp->status_blk_num;
  3568. cnic_init_context(dev, 2);
  3569. cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
  3570. coal_reg = BNX2_HC_COMMAND;
  3571. coal_val = CNIC_RD(dev, coal_reg);
  3572. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3573. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3574. cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
  3575. coal_reg = BNX2_HC_COALESCE_NOW;
  3576. coal_val = 1 << (11 + sb_id);
  3577. }
  3578. i = 0;
  3579. while (!(*cp->rx_cons_ptr != 0) && i < 10) {
  3580. CNIC_WR(dev, coal_reg, coal_val);
  3581. udelay(10);
  3582. i++;
  3583. barrier();
  3584. }
  3585. cp->rx_cons = *cp->rx_cons_ptr;
  3586. cid_addr = GET_CID_ADDR(2);
  3587. val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
  3588. BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
  3589. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
  3590. if (sb_id == 0)
  3591. val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
  3592. else
  3593. val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
  3594. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
  3595. rxbd = (struct rx_bd *) (udev->l2_ring + BCM_PAGE_SIZE);
  3596. for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
  3597. dma_addr_t buf_map;
  3598. int n = (i % cp->l2_rx_ring_size) + 1;
  3599. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  3600. rxbd->rx_bd_len = cp->l2_single_buf_size;
  3601. rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
  3602. rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
  3603. rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3604. }
  3605. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  3606. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
  3607. rxbd->rx_bd_haddr_hi = val;
  3608. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3609. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
  3610. rxbd->rx_bd_haddr_lo = val;
  3611. val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
  3612. cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
  3613. }
  3614. static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
  3615. {
  3616. struct kwqe *wqes[1], l2kwqe;
  3617. memset(&l2kwqe, 0, sizeof(l2kwqe));
  3618. wqes[0] = &l2kwqe;
  3619. l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_LAYER_SHIFT) |
  3620. (L2_KWQE_OPCODE_VALUE_FLUSH <<
  3621. KWQE_OPCODE_SHIFT) | 2;
  3622. dev->submit_kwqes(dev, wqes, 1);
  3623. }
  3624. static void cnic_set_bnx2_mac(struct cnic_dev *dev)
  3625. {
  3626. struct cnic_local *cp = dev->cnic_priv;
  3627. u32 val;
  3628. val = cp->func << 2;
  3629. cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
  3630. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3631. BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
  3632. dev->mac_addr[0] = (u8) (val >> 8);
  3633. dev->mac_addr[1] = (u8) val;
  3634. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
  3635. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3636. BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
  3637. dev->mac_addr[2] = (u8) (val >> 24);
  3638. dev->mac_addr[3] = (u8) (val >> 16);
  3639. dev->mac_addr[4] = (u8) (val >> 8);
  3640. dev->mac_addr[5] = (u8) val;
  3641. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
  3642. val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
  3643. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3644. val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
  3645. CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
  3646. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
  3647. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
  3648. }
  3649. static int cnic_start_bnx2_hw(struct cnic_dev *dev)
  3650. {
  3651. struct cnic_local *cp = dev->cnic_priv;
  3652. struct cnic_eth_dev *ethdev = cp->ethdev;
  3653. struct status_block *sblk = cp->status_blk.gen;
  3654. u32 val, kcq_cid_addr, kwq_cid_addr;
  3655. int err;
  3656. cnic_set_bnx2_mac(dev);
  3657. val = CNIC_RD(dev, BNX2_MQ_CONFIG);
  3658. val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
  3659. if (BCM_PAGE_BITS > 12)
  3660. val |= (12 - 8) << 4;
  3661. else
  3662. val |= (BCM_PAGE_BITS - 8) << 4;
  3663. CNIC_WR(dev, BNX2_MQ_CONFIG, val);
  3664. CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
  3665. CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
  3666. CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
  3667. err = cnic_setup_5709_context(dev, 1);
  3668. if (err)
  3669. return err;
  3670. cnic_init_context(dev, KWQ_CID);
  3671. cnic_init_context(dev, KCQ_CID);
  3672. kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
  3673. cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
  3674. cp->max_kwq_idx = MAX_KWQ_IDX;
  3675. cp->kwq_prod_idx = 0;
  3676. cp->kwq_con_idx = 0;
  3677. set_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  3678. if (CHIP_NUM(cp) == CHIP_NUM_5706 || CHIP_NUM(cp) == CHIP_NUM_5708)
  3679. cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
  3680. else
  3681. cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
  3682. /* Initialize the kernel work queue context. */
  3683. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3684. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3685. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val);
  3686. val = (BCM_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
  3687. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3688. val = ((BCM_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
  3689. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3690. val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
  3691. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3692. val = (u32) cp->kwq_info.pgtbl_map;
  3693. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3694. kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
  3695. cp->kcq1.io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
  3696. cp->kcq1.sw_prod_idx = 0;
  3697. cp->kcq1.hw_prod_idx_ptr =
  3698. (u16 *) &sblk->status_completion_producer_index;
  3699. cp->kcq1.status_idx_ptr = (u16 *) &sblk->status_idx;
  3700. /* Initialize the kernel complete queue context. */
  3701. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3702. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3703. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val);
  3704. val = (BCM_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
  3705. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3706. val = ((BCM_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
  3707. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3708. val = (u32) ((u64) cp->kcq1.dma.pgtbl_map >> 32);
  3709. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3710. val = (u32) cp->kcq1.dma.pgtbl_map;
  3711. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3712. cp->int_num = 0;
  3713. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3714. struct status_block_msix *msblk = cp->status_blk.bnx2;
  3715. u32 sb_id = cp->status_blk_num;
  3716. u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
  3717. cp->kcq1.hw_prod_idx_ptr =
  3718. (u16 *) &msblk->status_completion_producer_index;
  3719. cp->kcq1.status_idx_ptr = (u16 *) &msblk->status_idx;
  3720. cp->kwq_con_idx_ptr = (u16 *) &msblk->status_cmd_consumer_index;
  3721. cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
  3722. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3723. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3724. }
  3725. /* Enable Commnad Scheduler notification when we write to the
  3726. * host producer index of the kernel contexts. */
  3727. CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
  3728. /* Enable Command Scheduler notification when we write to either
  3729. * the Send Queue or Receive Queue producer indexes of the kernel
  3730. * bypass contexts. */
  3731. CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
  3732. CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
  3733. /* Notify COM when the driver post an application buffer. */
  3734. CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
  3735. /* Set the CP and COM doorbells. These two processors polls the
  3736. * doorbell for a non zero value before running. This must be done
  3737. * after setting up the kernel queue contexts. */
  3738. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
  3739. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
  3740. cnic_init_bnx2_tx_ring(dev);
  3741. cnic_init_bnx2_rx_ring(dev);
  3742. err = cnic_init_bnx2_irq(dev);
  3743. if (err) {
  3744. netdev_err(dev->netdev, "cnic_init_irq failed\n");
  3745. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3746. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3747. return err;
  3748. }
  3749. cnic_get_bnx2_iscsi_info(dev);
  3750. return 0;
  3751. }
  3752. static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
  3753. {
  3754. struct cnic_local *cp = dev->cnic_priv;
  3755. struct cnic_eth_dev *ethdev = cp->ethdev;
  3756. u32 start_offset = ethdev->ctx_tbl_offset;
  3757. int i;
  3758. for (i = 0; i < cp->ctx_blks; i++) {
  3759. struct cnic_ctx *ctx = &cp->ctx_arr[i];
  3760. dma_addr_t map = ctx->mapping;
  3761. if (cp->ctx_align) {
  3762. unsigned long mask = cp->ctx_align - 1;
  3763. map = (map + mask) & ~mask;
  3764. }
  3765. cnic_ctx_tbl_wr(dev, start_offset + i, map);
  3766. }
  3767. }
  3768. static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
  3769. {
  3770. struct cnic_local *cp = dev->cnic_priv;
  3771. struct cnic_eth_dev *ethdev = cp->ethdev;
  3772. int err = 0;
  3773. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2x_bh,
  3774. (unsigned long) dev);
  3775. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  3776. err = cnic_request_irq(dev);
  3777. return err;
  3778. }
  3779. static inline void cnic_storm_memset_hc_disable(struct cnic_dev *dev,
  3780. u16 sb_id, u8 sb_index,
  3781. u8 disable)
  3782. {
  3783. u32 addr = BAR_CSTRORM_INTMEM +
  3784. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3785. offsetof(struct hc_status_block_data_e1x, index_data) +
  3786. sizeof(struct hc_index_data)*sb_index +
  3787. offsetof(struct hc_index_data, flags);
  3788. u16 flags = CNIC_RD16(dev, addr);
  3789. /* clear and set */
  3790. flags &= ~HC_INDEX_DATA_HC_ENABLED;
  3791. flags |= (((~disable) << HC_INDEX_DATA_HC_ENABLED_SHIFT) &
  3792. HC_INDEX_DATA_HC_ENABLED);
  3793. CNIC_WR16(dev, addr, flags);
  3794. }
  3795. static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
  3796. {
  3797. struct cnic_local *cp = dev->cnic_priv;
  3798. u8 sb_id = cp->status_blk_num;
  3799. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3800. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3801. offsetof(struct hc_status_block_data_e1x, index_data) +
  3802. sizeof(struct hc_index_data)*HC_INDEX_ISCSI_EQ_CONS +
  3803. offsetof(struct hc_index_data, timeout), 64 / 12);
  3804. cnic_storm_memset_hc_disable(dev, sb_id, HC_INDEX_ISCSI_EQ_CONS, 0);
  3805. }
  3806. static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
  3807. {
  3808. }
  3809. static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
  3810. struct client_init_ramrod_data *data)
  3811. {
  3812. struct cnic_local *cp = dev->cnic_priv;
  3813. struct cnic_uio_dev *udev = cp->udev;
  3814. union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) udev->l2_ring;
  3815. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3816. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  3817. int port = CNIC_PORT(cp);
  3818. int i;
  3819. u32 cli = cp->ethdev->iscsi_l2_client_id;
  3820. u32 val;
  3821. memset(txbd, 0, BCM_PAGE_SIZE);
  3822. buf_map = udev->l2_buf_map;
  3823. for (i = 0; i < MAX_TX_DESC_CNT; i += 3, txbd += 3) {
  3824. struct eth_tx_start_bd *start_bd = &txbd->start_bd;
  3825. struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
  3826. start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3827. start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3828. reg_bd->addr_hi = start_bd->addr_hi;
  3829. reg_bd->addr_lo = start_bd->addr_lo + 0x10;
  3830. start_bd->nbytes = cpu_to_le16(0x10);
  3831. start_bd->nbd = cpu_to_le16(3);
  3832. start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
  3833. start_bd->general_data = (UNICAST_ADDRESS <<
  3834. ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
  3835. start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
  3836. }
  3837. val = (u64) ring_map >> 32;
  3838. txbd->next_bd.addr_hi = cpu_to_le32(val);
  3839. data->tx.tx_bd_page_base.hi = cpu_to_le32(val);
  3840. val = (u64) ring_map & 0xffffffff;
  3841. txbd->next_bd.addr_lo = cpu_to_le32(val);
  3842. data->tx.tx_bd_page_base.lo = cpu_to_le32(val);
  3843. /* Other ramrod params */
  3844. data->tx.tx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_CQ_CONS;
  3845. data->tx.tx_status_block_id = BNX2X_DEF_SB_ID;
  3846. /* reset xstorm per client statistics */
  3847. if (cli < MAX_STAT_COUNTER_ID) {
  3848. val = BAR_XSTRORM_INTMEM +
  3849. XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3850. for (i = 0; i < sizeof(struct xstorm_per_client_stats) / 4; i++)
  3851. CNIC_WR(dev, val + i * 4, 0);
  3852. }
  3853. cp->tx_cons_ptr =
  3854. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_CQ_CONS];
  3855. }
  3856. static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
  3857. struct client_init_ramrod_data *data)
  3858. {
  3859. struct cnic_local *cp = dev->cnic_priv;
  3860. struct cnic_uio_dev *udev = cp->udev;
  3861. struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (udev->l2_ring +
  3862. BCM_PAGE_SIZE);
  3863. struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
  3864. (udev->l2_ring + (2 * BCM_PAGE_SIZE));
  3865. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  3866. int i;
  3867. int port = CNIC_PORT(cp);
  3868. u32 cli = cp->ethdev->iscsi_l2_client_id;
  3869. int cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  3870. u32 val;
  3871. dma_addr_t ring_map = udev->l2_ring_map;
  3872. /* General data */
  3873. data->general.client_id = cli;
  3874. data->general.statistics_en_flg = 1;
  3875. data->general.statistics_counter_id = cli;
  3876. data->general.activate_flg = 1;
  3877. data->general.sp_client_id = cli;
  3878. for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
  3879. dma_addr_t buf_map;
  3880. int n = (i % cp->l2_rx_ring_size) + 1;
  3881. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  3882. rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3883. rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3884. }
  3885. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  3886. rxbd->addr_hi = cpu_to_le32(val);
  3887. data->rx.bd_page_base.hi = cpu_to_le32(val);
  3888. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3889. rxbd->addr_lo = cpu_to_le32(val);
  3890. data->rx.bd_page_base.lo = cpu_to_le32(val);
  3891. rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
  3892. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) >> 32;
  3893. rxcqe->addr_hi = cpu_to_le32(val);
  3894. data->rx.cqe_page_base.hi = cpu_to_le32(val);
  3895. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) & 0xffffffff;
  3896. rxcqe->addr_lo = cpu_to_le32(val);
  3897. data->rx.cqe_page_base.lo = cpu_to_le32(val);
  3898. /* Other ramrod params */
  3899. data->rx.client_qzone_id = cl_qzone_id;
  3900. data->rx.rx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS;
  3901. data->rx.status_block_id = BNX2X_DEF_SB_ID;
  3902. data->rx.cache_line_alignment_log_size = L1_CACHE_SHIFT;
  3903. data->rx.bd_buff_size = cpu_to_le16(cp->l2_single_buf_size);
  3904. data->rx.mtu = cpu_to_le16(cp->l2_single_buf_size - 14);
  3905. data->rx.outer_vlan_removal_enable_flg = 1;
  3906. /* reset tstorm and ustorm per client statistics */
  3907. if (cli < MAX_STAT_COUNTER_ID) {
  3908. val = BAR_TSTRORM_INTMEM +
  3909. TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3910. for (i = 0; i < sizeof(struct tstorm_per_client_stats) / 4; i++)
  3911. CNIC_WR(dev, val + i * 4, 0);
  3912. val = BAR_USTRORM_INTMEM +
  3913. USTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3914. for (i = 0; i < sizeof(struct ustorm_per_client_stats) / 4; i++)
  3915. CNIC_WR(dev, val + i * 4, 0);
  3916. }
  3917. cp->rx_cons_ptr =
  3918. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS];
  3919. cp->rx_cons = *cp->rx_cons_ptr;
  3920. }
  3921. static void cnic_init_bnx2x_kcq(struct cnic_dev *dev)
  3922. {
  3923. struct cnic_local *cp = dev->cnic_priv;
  3924. u32 pfid = cp->pfid;
  3925. cp->kcq1.io_addr = BAR_CSTRORM_INTMEM +
  3926. CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
  3927. cp->kcq1.sw_prod_idx = 0;
  3928. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  3929. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  3930. cp->kcq1.hw_prod_idx_ptr =
  3931. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  3932. cp->kcq1.status_idx_ptr =
  3933. &sb->sb.running_index[SM_RX_ID];
  3934. } else {
  3935. struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
  3936. cp->kcq1.hw_prod_idx_ptr =
  3937. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  3938. cp->kcq1.status_idx_ptr =
  3939. &sb->sb.running_index[SM_RX_ID];
  3940. }
  3941. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  3942. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  3943. cp->kcq2.io_addr = BAR_USTRORM_INTMEM +
  3944. USTORM_FCOE_EQ_PROD_OFFSET(pfid);
  3945. cp->kcq2.sw_prod_idx = 0;
  3946. cp->kcq2.hw_prod_idx_ptr =
  3947. &sb->sb.index_values[HC_INDEX_FCOE_EQ_CONS];
  3948. cp->kcq2.status_idx_ptr =
  3949. &sb->sb.running_index[SM_RX_ID];
  3950. }
  3951. }
  3952. static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
  3953. {
  3954. struct cnic_local *cp = dev->cnic_priv;
  3955. struct cnic_eth_dev *ethdev = cp->ethdev;
  3956. int func = CNIC_FUNC(cp), ret, i;
  3957. u32 pfid;
  3958. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  3959. u32 val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN_OVWR);
  3960. if (!(val & 1))
  3961. val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN);
  3962. else
  3963. val = (val >> 1) & 1;
  3964. if (val)
  3965. cp->pfid = func >> 1;
  3966. else
  3967. cp->pfid = func & 0x6;
  3968. } else {
  3969. cp->pfid = func;
  3970. }
  3971. pfid = cp->pfid;
  3972. ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
  3973. cp->iscsi_start_cid);
  3974. if (ret)
  3975. return -ENOMEM;
  3976. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  3977. ret = cnic_init_id_tbl(&cp->fcoe_cid_tbl,
  3978. BNX2X_FCOE_NUM_CONNECTIONS,
  3979. cp->fcoe_start_cid);
  3980. if (ret)
  3981. return -ENOMEM;
  3982. }
  3983. cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2;
  3984. cnic_init_bnx2x_kcq(dev);
  3985. /* Only 1 EQ */
  3986. CNIC_WR16(dev, cp->kcq1.io_addr, MAX_KCQ_IDX);
  3987. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3988. CSTORM_ISCSI_EQ_CONS_OFFSET(pfid, 0), 0);
  3989. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3990. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0),
  3991. cp->kcq1.dma.pg_map_arr[1] & 0xffffffff);
  3992. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3993. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0) + 4,
  3994. (u64) cp->kcq1.dma.pg_map_arr[1] >> 32);
  3995. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3996. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0),
  3997. cp->kcq1.dma.pg_map_arr[0] & 0xffffffff);
  3998. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3999. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0) + 4,
  4000. (u64) cp->kcq1.dma.pg_map_arr[0] >> 32);
  4001. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4002. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfid, 0), 1);
  4003. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  4004. CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfid, 0), cp->status_blk_num);
  4005. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4006. CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfid, 0),
  4007. HC_INDEX_ISCSI_EQ_CONS);
  4008. for (i = 0; i < cp->conn_buf_info.num_pages; i++) {
  4009. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  4010. TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(pfid, i),
  4011. cp->conn_buf_info.pgtbl[2 * i]);
  4012. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  4013. TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(pfid, i) + 4,
  4014. cp->conn_buf_info.pgtbl[(2 * i) + 1]);
  4015. }
  4016. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4017. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid),
  4018. cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
  4019. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4020. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid) + 4,
  4021. (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
  4022. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  4023. TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfid), DEF_RCV_BUF);
  4024. cnic_setup_bnx2x_context(dev);
  4025. ret = cnic_init_bnx2x_irq(dev);
  4026. if (ret)
  4027. return ret;
  4028. return 0;
  4029. }
  4030. static void cnic_init_rings(struct cnic_dev *dev)
  4031. {
  4032. struct cnic_local *cp = dev->cnic_priv;
  4033. struct cnic_uio_dev *udev = cp->udev;
  4034. if (test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4035. return;
  4036. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4037. cnic_init_bnx2_tx_ring(dev);
  4038. cnic_init_bnx2_rx_ring(dev);
  4039. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4040. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4041. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4042. u32 cid = cp->ethdev->iscsi_l2_cid;
  4043. u32 cl_qzone_id;
  4044. struct client_init_ramrod_data *data;
  4045. union l5cm_specific_data l5_data;
  4046. struct ustorm_eth_rx_producers rx_prods = {0};
  4047. u32 off, i;
  4048. rx_prods.bd_prod = 0;
  4049. rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
  4050. barrier();
  4051. cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  4052. off = BAR_USTRORM_INTMEM +
  4053. (BNX2X_CHIP_IS_E2(cp->chip_id) ?
  4054. USTORM_RX_PRODS_E2_OFFSET(cl_qzone_id) :
  4055. USTORM_RX_PRODS_E1X_OFFSET(CNIC_PORT(cp), cli));
  4056. for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
  4057. CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
  4058. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4059. data = udev->l2_buf;
  4060. memset(data, 0, sizeof(*data));
  4061. cnic_init_bnx2x_tx_ring(dev, data);
  4062. cnic_init_bnx2x_rx_ring(dev, data);
  4063. l5_data.phy_address.lo = udev->l2_buf_map & 0xffffffff;
  4064. l5_data.phy_address.hi = (u64) udev->l2_buf_map >> 32;
  4065. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4066. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
  4067. cid, ETH_CONNECTION_TYPE, &l5_data);
  4068. i = 0;
  4069. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4070. ++i < 10)
  4071. msleep(1);
  4072. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4073. netdev_err(dev->netdev,
  4074. "iSCSI CLIENT_SETUP did not complete\n");
  4075. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4076. cnic_ring_ctl(dev, cid, cli, 1);
  4077. }
  4078. }
  4079. static void cnic_shutdown_rings(struct cnic_dev *dev)
  4080. {
  4081. struct cnic_local *cp = dev->cnic_priv;
  4082. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4083. return;
  4084. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4085. cnic_shutdown_bnx2_rx_ring(dev);
  4086. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4087. struct cnic_local *cp = dev->cnic_priv;
  4088. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4089. u32 cid = cp->ethdev->iscsi_l2_cid;
  4090. union l5cm_specific_data l5_data;
  4091. int i;
  4092. cnic_ring_ctl(dev, cid, cli, 0);
  4093. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4094. l5_data.phy_address.lo = cli;
  4095. l5_data.phy_address.hi = 0;
  4096. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
  4097. cid, ETH_CONNECTION_TYPE, &l5_data);
  4098. i = 0;
  4099. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4100. ++i < 10)
  4101. msleep(1);
  4102. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4103. netdev_err(dev->netdev,
  4104. "iSCSI CLIENT_HALT did not complete\n");
  4105. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4106. memset(&l5_data, 0, sizeof(l5_data));
  4107. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  4108. cid, NONE_CONNECTION_TYPE, &l5_data);
  4109. msleep(10);
  4110. }
  4111. clear_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4112. }
  4113. static int cnic_register_netdev(struct cnic_dev *dev)
  4114. {
  4115. struct cnic_local *cp = dev->cnic_priv;
  4116. struct cnic_eth_dev *ethdev = cp->ethdev;
  4117. int err;
  4118. if (!ethdev)
  4119. return -ENODEV;
  4120. if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
  4121. return 0;
  4122. err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
  4123. if (err)
  4124. netdev_err(dev->netdev, "register_cnic failed\n");
  4125. return err;
  4126. }
  4127. static void cnic_unregister_netdev(struct cnic_dev *dev)
  4128. {
  4129. struct cnic_local *cp = dev->cnic_priv;
  4130. struct cnic_eth_dev *ethdev = cp->ethdev;
  4131. if (!ethdev)
  4132. return;
  4133. ethdev->drv_unregister_cnic(dev->netdev);
  4134. }
  4135. static int cnic_start_hw(struct cnic_dev *dev)
  4136. {
  4137. struct cnic_local *cp = dev->cnic_priv;
  4138. struct cnic_eth_dev *ethdev = cp->ethdev;
  4139. int err;
  4140. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  4141. return -EALREADY;
  4142. dev->regview = ethdev->io_base;
  4143. pci_dev_get(dev->pcidev);
  4144. cp->func = PCI_FUNC(dev->pcidev->devfn);
  4145. cp->status_blk.gen = ethdev->irq_arr[0].status_blk;
  4146. cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
  4147. err = cp->alloc_resc(dev);
  4148. if (err) {
  4149. netdev_err(dev->netdev, "allocate resource failure\n");
  4150. goto err1;
  4151. }
  4152. err = cp->start_hw(dev);
  4153. if (err)
  4154. goto err1;
  4155. err = cnic_cm_open(dev);
  4156. if (err)
  4157. goto err1;
  4158. set_bit(CNIC_F_CNIC_UP, &dev->flags);
  4159. cp->enable_int(dev);
  4160. return 0;
  4161. err1:
  4162. cp->free_resc(dev);
  4163. pci_dev_put(dev->pcidev);
  4164. return err;
  4165. }
  4166. static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
  4167. {
  4168. cnic_disable_bnx2_int_sync(dev);
  4169. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  4170. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  4171. cnic_init_context(dev, KWQ_CID);
  4172. cnic_init_context(dev, KCQ_CID);
  4173. cnic_setup_5709_context(dev, 0);
  4174. cnic_free_irq(dev);
  4175. cnic_free_resc(dev);
  4176. }
  4177. static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
  4178. {
  4179. struct cnic_local *cp = dev->cnic_priv;
  4180. cnic_free_irq(dev);
  4181. *cp->kcq1.hw_prod_idx_ptr = 0;
  4182. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4183. CSTORM_ISCSI_EQ_CONS_OFFSET(cp->pfid, 0), 0);
  4184. CNIC_WR16(dev, cp->kcq1.io_addr, 0);
  4185. cnic_free_resc(dev);
  4186. }
  4187. static void cnic_stop_hw(struct cnic_dev *dev)
  4188. {
  4189. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  4190. struct cnic_local *cp = dev->cnic_priv;
  4191. int i = 0;
  4192. /* Need to wait for the ring shutdown event to complete
  4193. * before clearing the CNIC_UP flag.
  4194. */
  4195. while (cp->udev->uio_dev != -1 && i < 15) {
  4196. msleep(100);
  4197. i++;
  4198. }
  4199. cnic_shutdown_rings(dev);
  4200. clear_bit(CNIC_F_CNIC_UP, &dev->flags);
  4201. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], NULL);
  4202. synchronize_rcu();
  4203. cnic_cm_shutdown(dev);
  4204. cp->stop_hw(dev);
  4205. pci_dev_put(dev->pcidev);
  4206. }
  4207. }
  4208. static void cnic_free_dev(struct cnic_dev *dev)
  4209. {
  4210. int i = 0;
  4211. while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
  4212. msleep(100);
  4213. i++;
  4214. }
  4215. if (atomic_read(&dev->ref_count) != 0)
  4216. netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n");
  4217. netdev_info(dev->netdev, "Removed CNIC device\n");
  4218. dev_put(dev->netdev);
  4219. kfree(dev);
  4220. }
  4221. static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
  4222. struct pci_dev *pdev)
  4223. {
  4224. struct cnic_dev *cdev;
  4225. struct cnic_local *cp;
  4226. int alloc_size;
  4227. alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
  4228. cdev = kzalloc(alloc_size , GFP_KERNEL);
  4229. if (cdev == NULL) {
  4230. netdev_err(dev, "allocate dev struct failure\n");
  4231. return NULL;
  4232. }
  4233. cdev->netdev = dev;
  4234. cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
  4235. cdev->register_device = cnic_register_device;
  4236. cdev->unregister_device = cnic_unregister_device;
  4237. cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
  4238. cp = cdev->cnic_priv;
  4239. cp->dev = cdev;
  4240. cp->l2_single_buf_size = 0x400;
  4241. cp->l2_rx_ring_size = 3;
  4242. spin_lock_init(&cp->cnic_ulp_lock);
  4243. netdev_info(dev, "Added CNIC device\n");
  4244. return cdev;
  4245. }
  4246. static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
  4247. {
  4248. struct pci_dev *pdev;
  4249. struct cnic_dev *cdev;
  4250. struct cnic_local *cp;
  4251. struct cnic_eth_dev *ethdev = NULL;
  4252. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  4253. probe = symbol_get(bnx2_cnic_probe);
  4254. if (probe) {
  4255. ethdev = (*probe)(dev);
  4256. symbol_put(bnx2_cnic_probe);
  4257. }
  4258. if (!ethdev)
  4259. return NULL;
  4260. pdev = ethdev->pdev;
  4261. if (!pdev)
  4262. return NULL;
  4263. dev_hold(dev);
  4264. pci_dev_get(pdev);
  4265. if ((pdev->device == PCI_DEVICE_ID_NX2_5709 ||
  4266. pdev->device == PCI_DEVICE_ID_NX2_5709S) &&
  4267. (pdev->revision < 0x10)) {
  4268. pci_dev_put(pdev);
  4269. goto cnic_err;
  4270. }
  4271. pci_dev_put(pdev);
  4272. cdev = cnic_alloc_dev(dev, pdev);
  4273. if (cdev == NULL)
  4274. goto cnic_err;
  4275. set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
  4276. cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
  4277. cp = cdev->cnic_priv;
  4278. cp->ethdev = ethdev;
  4279. cdev->pcidev = pdev;
  4280. cp->chip_id = ethdev->chip_id;
  4281. cp->cnic_ops = &cnic_bnx2_ops;
  4282. cp->start_hw = cnic_start_bnx2_hw;
  4283. cp->stop_hw = cnic_stop_bnx2_hw;
  4284. cp->setup_pgtbl = cnic_setup_page_tbl;
  4285. cp->alloc_resc = cnic_alloc_bnx2_resc;
  4286. cp->free_resc = cnic_free_resc;
  4287. cp->start_cm = cnic_cm_init_bnx2_hw;
  4288. cp->stop_cm = cnic_cm_stop_bnx2_hw;
  4289. cp->enable_int = cnic_enable_bnx2_int;
  4290. cp->disable_int_sync = cnic_disable_bnx2_int_sync;
  4291. cp->close_conn = cnic_close_bnx2_conn;
  4292. cp->next_idx = cnic_bnx2_next_idx;
  4293. cp->hw_idx = cnic_bnx2_hw_idx;
  4294. return cdev;
  4295. cnic_err:
  4296. dev_put(dev);
  4297. return NULL;
  4298. }
  4299. static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
  4300. {
  4301. struct pci_dev *pdev;
  4302. struct cnic_dev *cdev;
  4303. struct cnic_local *cp;
  4304. struct cnic_eth_dev *ethdev = NULL;
  4305. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  4306. probe = symbol_get(bnx2x_cnic_probe);
  4307. if (probe) {
  4308. ethdev = (*probe)(dev);
  4309. symbol_put(bnx2x_cnic_probe);
  4310. }
  4311. if (!ethdev)
  4312. return NULL;
  4313. pdev = ethdev->pdev;
  4314. if (!pdev)
  4315. return NULL;
  4316. dev_hold(dev);
  4317. cdev = cnic_alloc_dev(dev, pdev);
  4318. if (cdev == NULL) {
  4319. dev_put(dev);
  4320. return NULL;
  4321. }
  4322. set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
  4323. cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
  4324. cp = cdev->cnic_priv;
  4325. cp->ethdev = ethdev;
  4326. cdev->pcidev = pdev;
  4327. cp->chip_id = ethdev->chip_id;
  4328. if (!(ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI))
  4329. cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4330. if (BNX2X_CHIP_IS_E2(cp->chip_id) &&
  4331. !(ethdev->drv_state & CNIC_DRV_STATE_NO_FCOE))
  4332. cdev->max_fcoe_conn = ethdev->max_fcoe_conn;
  4333. memcpy(cdev->mac_addr, ethdev->iscsi_mac, 6);
  4334. cp->cnic_ops = &cnic_bnx2x_ops;
  4335. cp->start_hw = cnic_start_bnx2x_hw;
  4336. cp->stop_hw = cnic_stop_bnx2x_hw;
  4337. cp->setup_pgtbl = cnic_setup_page_tbl_le;
  4338. cp->alloc_resc = cnic_alloc_bnx2x_resc;
  4339. cp->free_resc = cnic_free_resc;
  4340. cp->start_cm = cnic_cm_init_bnx2x_hw;
  4341. cp->stop_cm = cnic_cm_stop_bnx2x_hw;
  4342. cp->enable_int = cnic_enable_bnx2x_int;
  4343. cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
  4344. if (BNX2X_CHIP_IS_E2(cp->chip_id))
  4345. cp->ack_int = cnic_ack_bnx2x_e2_msix;
  4346. else
  4347. cp->ack_int = cnic_ack_bnx2x_msix;
  4348. cp->close_conn = cnic_close_bnx2x_conn;
  4349. cp->next_idx = cnic_bnx2x_next_idx;
  4350. cp->hw_idx = cnic_bnx2x_hw_idx;
  4351. return cdev;
  4352. }
  4353. static struct cnic_dev *is_cnic_dev(struct net_device *dev)
  4354. {
  4355. struct ethtool_drvinfo drvinfo;
  4356. struct cnic_dev *cdev = NULL;
  4357. if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
  4358. memset(&drvinfo, 0, sizeof(drvinfo));
  4359. dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
  4360. if (!strcmp(drvinfo.driver, "bnx2"))
  4361. cdev = init_bnx2_cnic(dev);
  4362. if (!strcmp(drvinfo.driver, "bnx2x"))
  4363. cdev = init_bnx2x_cnic(dev);
  4364. if (cdev) {
  4365. write_lock(&cnic_dev_lock);
  4366. list_add(&cdev->list, &cnic_dev_list);
  4367. write_unlock(&cnic_dev_lock);
  4368. }
  4369. }
  4370. return cdev;
  4371. }
  4372. /**
  4373. * netdev event handler
  4374. */
  4375. static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
  4376. void *ptr)
  4377. {
  4378. struct net_device *netdev = ptr;
  4379. struct cnic_dev *dev;
  4380. int if_type;
  4381. int new_dev = 0;
  4382. dev = cnic_from_netdev(netdev);
  4383. if (!dev && (event == NETDEV_REGISTER || event == NETDEV_UP)) {
  4384. /* Check for the hot-plug device */
  4385. dev = is_cnic_dev(netdev);
  4386. if (dev) {
  4387. new_dev = 1;
  4388. cnic_hold(dev);
  4389. }
  4390. }
  4391. if (dev) {
  4392. struct cnic_local *cp = dev->cnic_priv;
  4393. if (new_dev)
  4394. cnic_ulp_init(dev);
  4395. else if (event == NETDEV_UNREGISTER)
  4396. cnic_ulp_exit(dev);
  4397. if (event == NETDEV_UP) {
  4398. if (cnic_register_netdev(dev) != 0) {
  4399. cnic_put(dev);
  4400. goto done;
  4401. }
  4402. if (!cnic_start_hw(dev))
  4403. cnic_ulp_start(dev);
  4404. }
  4405. rcu_read_lock();
  4406. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  4407. struct cnic_ulp_ops *ulp_ops;
  4408. void *ctx;
  4409. ulp_ops = rcu_dereference(cp->ulp_ops[if_type]);
  4410. if (!ulp_ops || !ulp_ops->indicate_netevent)
  4411. continue;
  4412. ctx = cp->ulp_handle[if_type];
  4413. ulp_ops->indicate_netevent(ctx, event);
  4414. }
  4415. rcu_read_unlock();
  4416. if (event == NETDEV_GOING_DOWN) {
  4417. cnic_ulp_stop(dev);
  4418. cnic_stop_hw(dev);
  4419. cnic_unregister_netdev(dev);
  4420. } else if (event == NETDEV_UNREGISTER) {
  4421. write_lock(&cnic_dev_lock);
  4422. list_del_init(&dev->list);
  4423. write_unlock(&cnic_dev_lock);
  4424. cnic_put(dev);
  4425. cnic_free_dev(dev);
  4426. goto done;
  4427. }
  4428. cnic_put(dev);
  4429. }
  4430. done:
  4431. return NOTIFY_DONE;
  4432. }
  4433. static struct notifier_block cnic_netdev_notifier = {
  4434. .notifier_call = cnic_netdev_event
  4435. };
  4436. static void cnic_release(void)
  4437. {
  4438. struct cnic_dev *dev;
  4439. struct cnic_uio_dev *udev;
  4440. while (!list_empty(&cnic_dev_list)) {
  4441. dev = list_entry(cnic_dev_list.next, struct cnic_dev, list);
  4442. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  4443. cnic_ulp_stop(dev);
  4444. cnic_stop_hw(dev);
  4445. }
  4446. cnic_ulp_exit(dev);
  4447. cnic_unregister_netdev(dev);
  4448. list_del_init(&dev->list);
  4449. cnic_free_dev(dev);
  4450. }
  4451. while (!list_empty(&cnic_udev_list)) {
  4452. udev = list_entry(cnic_udev_list.next, struct cnic_uio_dev,
  4453. list);
  4454. cnic_free_uio(udev);
  4455. }
  4456. }
  4457. static int __init cnic_init(void)
  4458. {
  4459. int rc = 0;
  4460. pr_info("%s", version);
  4461. rc = register_netdevice_notifier(&cnic_netdev_notifier);
  4462. if (rc) {
  4463. cnic_release();
  4464. return rc;
  4465. }
  4466. cnic_wq = create_singlethread_workqueue("cnic_wq");
  4467. if (!cnic_wq) {
  4468. cnic_release();
  4469. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4470. return -ENOMEM;
  4471. }
  4472. return 0;
  4473. }
  4474. static void __exit cnic_exit(void)
  4475. {
  4476. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4477. cnic_release();
  4478. destroy_workqueue(cnic_wq);
  4479. }
  4480. module_init(cnic_init);
  4481. module_exit(cnic_exit);