bnad.c 79 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241324232433244324532463247324832493250325132523253325432553256325732583259326032613262326332643265326632673268326932703271327232733274327532763277327832793280328132823283328432853286328732883289
  1. /*
  2. * Linux network driver for Brocade Converged Network Adapter.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License (GPL) Version 2 as
  6. * published by the Free Software Foundation
  7. *
  8. * This program is distributed in the hope that it will be useful, but
  9. * WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  11. * General Public License for more details.
  12. */
  13. /*
  14. * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
  15. * All rights reserved
  16. * www.brocade.com
  17. */
  18. #include <linux/netdevice.h>
  19. #include <linux/skbuff.h>
  20. #include <linux/etherdevice.h>
  21. #include <linux/in.h>
  22. #include <linux/ethtool.h>
  23. #include <linux/if_vlan.h>
  24. #include <linux/if_ether.h>
  25. #include <linux/ip.h>
  26. #include <linux/prefetch.h>
  27. #include "bnad.h"
  28. #include "bna.h"
  29. #include "cna.h"
  30. static DEFINE_MUTEX(bnad_fwimg_mutex);
  31. /*
  32. * Module params
  33. */
  34. static uint bnad_msix_disable;
  35. module_param(bnad_msix_disable, uint, 0444);
  36. MODULE_PARM_DESC(bnad_msix_disable, "Disable MSIX mode");
  37. static uint bnad_ioc_auto_recover = 1;
  38. module_param(bnad_ioc_auto_recover, uint, 0444);
  39. MODULE_PARM_DESC(bnad_ioc_auto_recover, "Enable / Disable auto recovery");
  40. /*
  41. * Global variables
  42. */
  43. u32 bnad_rxqs_per_cq = 2;
  44. static const u8 bnad_bcast_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
  45. /*
  46. * Local MACROS
  47. */
  48. #define BNAD_TX_UNMAPQ_DEPTH (bnad->txq_depth * 2)
  49. #define BNAD_RX_UNMAPQ_DEPTH (bnad->rxq_depth)
  50. #define BNAD_GET_MBOX_IRQ(_bnad) \
  51. (((_bnad)->cfg_flags & BNAD_CF_MSIX) ? \
  52. ((_bnad)->msix_table[(_bnad)->msix_num - 1].vector) : \
  53. ((_bnad)->pcidev->irq))
  54. #define BNAD_FILL_UNMAPQ_MEM_REQ(_res_info, _num, _depth) \
  55. do { \
  56. (_res_info)->res_type = BNA_RES_T_MEM; \
  57. (_res_info)->res_u.mem_info.mem_type = BNA_MEM_T_KVA; \
  58. (_res_info)->res_u.mem_info.num = (_num); \
  59. (_res_info)->res_u.mem_info.len = \
  60. sizeof(struct bnad_unmap_q) + \
  61. (sizeof(struct bnad_skb_unmap) * ((_depth) - 1)); \
  62. } while (0)
  63. #define BNAD_TXRX_SYNC_MDELAY 250 /* 250 msecs */
  64. /*
  65. * Reinitialize completions in CQ, once Rx is taken down
  66. */
  67. static void
  68. bnad_cq_cmpl_init(struct bnad *bnad, struct bna_ccb *ccb)
  69. {
  70. struct bna_cq_entry *cmpl, *next_cmpl;
  71. unsigned int wi_range, wis = 0, ccb_prod = 0;
  72. int i;
  73. BNA_CQ_QPGE_PTR_GET(ccb_prod, ccb->sw_qpt, cmpl,
  74. wi_range);
  75. for (i = 0; i < ccb->q_depth; i++) {
  76. wis++;
  77. if (likely(--wi_range))
  78. next_cmpl = cmpl + 1;
  79. else {
  80. BNA_QE_INDX_ADD(ccb_prod, wis, ccb->q_depth);
  81. wis = 0;
  82. BNA_CQ_QPGE_PTR_GET(ccb_prod, ccb->sw_qpt,
  83. next_cmpl, wi_range);
  84. }
  85. cmpl->valid = 0;
  86. cmpl = next_cmpl;
  87. }
  88. }
  89. /*
  90. * Frees all pending Tx Bufs
  91. * At this point no activity is expected on the Q,
  92. * so DMA unmap & freeing is fine.
  93. */
  94. static void
  95. bnad_free_all_txbufs(struct bnad *bnad,
  96. struct bna_tcb *tcb)
  97. {
  98. u32 unmap_cons;
  99. struct bnad_unmap_q *unmap_q = tcb->unmap_q;
  100. struct bnad_skb_unmap *unmap_array;
  101. struct sk_buff *skb = NULL;
  102. int i;
  103. unmap_array = unmap_q->unmap_array;
  104. unmap_cons = 0;
  105. while (unmap_cons < unmap_q->q_depth) {
  106. skb = unmap_array[unmap_cons].skb;
  107. if (!skb) {
  108. unmap_cons++;
  109. continue;
  110. }
  111. unmap_array[unmap_cons].skb = NULL;
  112. dma_unmap_single(&bnad->pcidev->dev,
  113. dma_unmap_addr(&unmap_array[unmap_cons],
  114. dma_addr), skb_headlen(skb),
  115. DMA_TO_DEVICE);
  116. dma_unmap_addr_set(&unmap_array[unmap_cons], dma_addr, 0);
  117. if (++unmap_cons >= unmap_q->q_depth)
  118. break;
  119. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  120. dma_unmap_page(&bnad->pcidev->dev,
  121. dma_unmap_addr(&unmap_array[unmap_cons],
  122. dma_addr),
  123. skb_shinfo(skb)->frags[i].size,
  124. DMA_TO_DEVICE);
  125. dma_unmap_addr_set(&unmap_array[unmap_cons], dma_addr,
  126. 0);
  127. if (++unmap_cons >= unmap_q->q_depth)
  128. break;
  129. }
  130. dev_kfree_skb_any(skb);
  131. }
  132. }
  133. /* Data Path Handlers */
  134. /*
  135. * bnad_free_txbufs : Frees the Tx bufs on Tx completion
  136. * Can be called in a) Interrupt context
  137. * b) Sending context
  138. * c) Tasklet context
  139. */
  140. static u32
  141. bnad_free_txbufs(struct bnad *bnad,
  142. struct bna_tcb *tcb)
  143. {
  144. u32 sent_packets = 0, sent_bytes = 0;
  145. u16 wis, unmap_cons, updated_hw_cons;
  146. struct bnad_unmap_q *unmap_q = tcb->unmap_q;
  147. struct bnad_skb_unmap *unmap_array;
  148. struct sk_buff *skb;
  149. int i;
  150. /*
  151. * Just return if TX is stopped. This check is useful
  152. * when bnad_free_txbufs() runs out of a tasklet scheduled
  153. * before bnad_cb_tx_cleanup() cleared BNAD_TXQ_TX_STARTED bit
  154. * but this routine runs actually after the cleanup has been
  155. * executed.
  156. */
  157. if (!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))
  158. return 0;
  159. updated_hw_cons = *(tcb->hw_consumer_index);
  160. wis = BNA_Q_INDEX_CHANGE(tcb->consumer_index,
  161. updated_hw_cons, tcb->q_depth);
  162. BUG_ON(!(wis <= BNA_QE_IN_USE_CNT(tcb, tcb->q_depth)));
  163. unmap_array = unmap_q->unmap_array;
  164. unmap_cons = unmap_q->consumer_index;
  165. prefetch(&unmap_array[unmap_cons + 1]);
  166. while (wis) {
  167. skb = unmap_array[unmap_cons].skb;
  168. unmap_array[unmap_cons].skb = NULL;
  169. sent_packets++;
  170. sent_bytes += skb->len;
  171. wis -= BNA_TXQ_WI_NEEDED(1 + skb_shinfo(skb)->nr_frags);
  172. dma_unmap_single(&bnad->pcidev->dev,
  173. dma_unmap_addr(&unmap_array[unmap_cons],
  174. dma_addr), skb_headlen(skb),
  175. DMA_TO_DEVICE);
  176. dma_unmap_addr_set(&unmap_array[unmap_cons], dma_addr, 0);
  177. BNA_QE_INDX_ADD(unmap_cons, 1, unmap_q->q_depth);
  178. prefetch(&unmap_array[unmap_cons + 1]);
  179. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  180. prefetch(&unmap_array[unmap_cons + 1]);
  181. dma_unmap_page(&bnad->pcidev->dev,
  182. dma_unmap_addr(&unmap_array[unmap_cons],
  183. dma_addr),
  184. skb_shinfo(skb)->frags[i].size,
  185. DMA_TO_DEVICE);
  186. dma_unmap_addr_set(&unmap_array[unmap_cons], dma_addr,
  187. 0);
  188. BNA_QE_INDX_ADD(unmap_cons, 1, unmap_q->q_depth);
  189. }
  190. dev_kfree_skb_any(skb);
  191. }
  192. /* Update consumer pointers. */
  193. tcb->consumer_index = updated_hw_cons;
  194. unmap_q->consumer_index = unmap_cons;
  195. tcb->txq->tx_packets += sent_packets;
  196. tcb->txq->tx_bytes += sent_bytes;
  197. return sent_packets;
  198. }
  199. /* Tx Free Tasklet function */
  200. /* Frees for all the tcb's in all the Tx's */
  201. /*
  202. * Scheduled from sending context, so that
  203. * the fat Tx lock is not held for too long
  204. * in the sending context.
  205. */
  206. static void
  207. bnad_tx_free_tasklet(unsigned long bnad_ptr)
  208. {
  209. struct bnad *bnad = (struct bnad *)bnad_ptr;
  210. struct bna_tcb *tcb;
  211. u32 acked = 0;
  212. int i, j;
  213. for (i = 0; i < bnad->num_tx; i++) {
  214. for (j = 0; j < bnad->num_txq_per_tx; j++) {
  215. tcb = bnad->tx_info[i].tcb[j];
  216. if (!tcb)
  217. continue;
  218. if (((u16) (*tcb->hw_consumer_index) !=
  219. tcb->consumer_index) &&
  220. (!test_and_set_bit(BNAD_TXQ_FREE_SENT,
  221. &tcb->flags))) {
  222. acked = bnad_free_txbufs(bnad, tcb);
  223. if (likely(test_bit(BNAD_TXQ_TX_STARTED,
  224. &tcb->flags)))
  225. bna_ib_ack(tcb->i_dbell, acked);
  226. smp_mb__before_clear_bit();
  227. clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
  228. }
  229. if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED,
  230. &tcb->flags)))
  231. continue;
  232. if (netif_queue_stopped(bnad->netdev)) {
  233. if (acked && netif_carrier_ok(bnad->netdev) &&
  234. BNA_QE_FREE_CNT(tcb, tcb->q_depth) >=
  235. BNAD_NETIF_WAKE_THRESHOLD) {
  236. netif_wake_queue(bnad->netdev);
  237. /* TODO */
  238. /* Counters for individual TxQs? */
  239. BNAD_UPDATE_CTR(bnad,
  240. netif_queue_wakeup);
  241. }
  242. }
  243. }
  244. }
  245. }
  246. static u32
  247. bnad_tx(struct bnad *bnad, struct bna_tcb *tcb)
  248. {
  249. struct net_device *netdev = bnad->netdev;
  250. u32 sent = 0;
  251. if (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags))
  252. return 0;
  253. sent = bnad_free_txbufs(bnad, tcb);
  254. if (sent) {
  255. if (netif_queue_stopped(netdev) &&
  256. netif_carrier_ok(netdev) &&
  257. BNA_QE_FREE_CNT(tcb, tcb->q_depth) >=
  258. BNAD_NETIF_WAKE_THRESHOLD) {
  259. if (test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)) {
  260. netif_wake_queue(netdev);
  261. BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
  262. }
  263. }
  264. }
  265. if (likely(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)))
  266. bna_ib_ack(tcb->i_dbell, sent);
  267. smp_mb__before_clear_bit();
  268. clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
  269. return sent;
  270. }
  271. /* MSIX Tx Completion Handler */
  272. static irqreturn_t
  273. bnad_msix_tx(int irq, void *data)
  274. {
  275. struct bna_tcb *tcb = (struct bna_tcb *)data;
  276. struct bnad *bnad = tcb->bnad;
  277. bnad_tx(bnad, tcb);
  278. return IRQ_HANDLED;
  279. }
  280. static void
  281. bnad_reset_rcb(struct bnad *bnad, struct bna_rcb *rcb)
  282. {
  283. struct bnad_unmap_q *unmap_q = rcb->unmap_q;
  284. rcb->producer_index = 0;
  285. rcb->consumer_index = 0;
  286. unmap_q->producer_index = 0;
  287. unmap_q->consumer_index = 0;
  288. }
  289. static void
  290. bnad_free_all_rxbufs(struct bnad *bnad, struct bna_rcb *rcb)
  291. {
  292. struct bnad_unmap_q *unmap_q;
  293. struct bnad_skb_unmap *unmap_array;
  294. struct sk_buff *skb;
  295. int unmap_cons;
  296. unmap_q = rcb->unmap_q;
  297. unmap_array = unmap_q->unmap_array;
  298. for (unmap_cons = 0; unmap_cons < unmap_q->q_depth; unmap_cons++) {
  299. skb = unmap_array[unmap_cons].skb;
  300. if (!skb)
  301. continue;
  302. unmap_array[unmap_cons].skb = NULL;
  303. dma_unmap_single(&bnad->pcidev->dev,
  304. dma_unmap_addr(&unmap_array[unmap_cons],
  305. dma_addr),
  306. rcb->rxq->buffer_size,
  307. DMA_FROM_DEVICE);
  308. dev_kfree_skb(skb);
  309. }
  310. bnad_reset_rcb(bnad, rcb);
  311. }
  312. static void
  313. bnad_alloc_n_post_rxbufs(struct bnad *bnad, struct bna_rcb *rcb)
  314. {
  315. u16 to_alloc, alloced, unmap_prod, wi_range;
  316. struct bnad_unmap_q *unmap_q = rcb->unmap_q;
  317. struct bnad_skb_unmap *unmap_array;
  318. struct bna_rxq_entry *rxent;
  319. struct sk_buff *skb;
  320. dma_addr_t dma_addr;
  321. alloced = 0;
  322. to_alloc =
  323. BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth);
  324. unmap_array = unmap_q->unmap_array;
  325. unmap_prod = unmap_q->producer_index;
  326. BNA_RXQ_QPGE_PTR_GET(unmap_prod, rcb->sw_qpt, rxent, wi_range);
  327. while (to_alloc--) {
  328. if (!wi_range) {
  329. BNA_RXQ_QPGE_PTR_GET(unmap_prod, rcb->sw_qpt, rxent,
  330. wi_range);
  331. }
  332. skb = alloc_skb(rcb->rxq->buffer_size + NET_IP_ALIGN,
  333. GFP_ATOMIC);
  334. if (unlikely(!skb)) {
  335. BNAD_UPDATE_CTR(bnad, rxbuf_alloc_failed);
  336. goto finishing;
  337. }
  338. skb->dev = bnad->netdev;
  339. skb_reserve(skb, NET_IP_ALIGN);
  340. unmap_array[unmap_prod].skb = skb;
  341. dma_addr = dma_map_single(&bnad->pcidev->dev, skb->data,
  342. rcb->rxq->buffer_size,
  343. DMA_FROM_DEVICE);
  344. dma_unmap_addr_set(&unmap_array[unmap_prod], dma_addr,
  345. dma_addr);
  346. BNA_SET_DMA_ADDR(dma_addr, &rxent->host_addr);
  347. BNA_QE_INDX_ADD(unmap_prod, 1, unmap_q->q_depth);
  348. rxent++;
  349. wi_range--;
  350. alloced++;
  351. }
  352. finishing:
  353. if (likely(alloced)) {
  354. unmap_q->producer_index = unmap_prod;
  355. rcb->producer_index = unmap_prod;
  356. smp_mb();
  357. if (likely(test_bit(BNAD_RXQ_STARTED, &rcb->flags)))
  358. bna_rxq_prod_indx_doorbell(rcb);
  359. }
  360. }
  361. static inline void
  362. bnad_refill_rxq(struct bnad *bnad, struct bna_rcb *rcb)
  363. {
  364. struct bnad_unmap_q *unmap_q = rcb->unmap_q;
  365. if (!test_and_set_bit(BNAD_RXQ_REFILL, &rcb->flags)) {
  366. if (BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth)
  367. >> BNAD_RXQ_REFILL_THRESHOLD_SHIFT)
  368. bnad_alloc_n_post_rxbufs(bnad, rcb);
  369. smp_mb__before_clear_bit();
  370. clear_bit(BNAD_RXQ_REFILL, &rcb->flags);
  371. }
  372. }
  373. static u32
  374. bnad_poll_cq(struct bnad *bnad, struct bna_ccb *ccb, int budget)
  375. {
  376. struct bna_cq_entry *cmpl, *next_cmpl;
  377. struct bna_rcb *rcb = NULL;
  378. unsigned int wi_range, packets = 0, wis = 0;
  379. struct bnad_unmap_q *unmap_q;
  380. struct bnad_skb_unmap *unmap_array;
  381. struct sk_buff *skb;
  382. u32 flags, unmap_cons;
  383. u32 qid0 = ccb->rcb[0]->rxq->rxq_id;
  384. struct bna_pkt_rate *pkt_rt = &ccb->pkt_rate;
  385. if (!test_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags))
  386. return 0;
  387. prefetch(bnad->netdev);
  388. BNA_CQ_QPGE_PTR_GET(ccb->producer_index, ccb->sw_qpt, cmpl,
  389. wi_range);
  390. BUG_ON(!(wi_range <= ccb->q_depth));
  391. while (cmpl->valid && packets < budget) {
  392. packets++;
  393. BNA_UPDATE_PKT_CNT(pkt_rt, ntohs(cmpl->length));
  394. if (qid0 == cmpl->rxq_id)
  395. rcb = ccb->rcb[0];
  396. else
  397. rcb = ccb->rcb[1];
  398. unmap_q = rcb->unmap_q;
  399. unmap_array = unmap_q->unmap_array;
  400. unmap_cons = unmap_q->consumer_index;
  401. skb = unmap_array[unmap_cons].skb;
  402. BUG_ON(!(skb));
  403. unmap_array[unmap_cons].skb = NULL;
  404. dma_unmap_single(&bnad->pcidev->dev,
  405. dma_unmap_addr(&unmap_array[unmap_cons],
  406. dma_addr),
  407. rcb->rxq->buffer_size,
  408. DMA_FROM_DEVICE);
  409. BNA_QE_INDX_ADD(unmap_q->consumer_index, 1, unmap_q->q_depth);
  410. /* Should be more efficient ? Performance ? */
  411. BNA_QE_INDX_ADD(rcb->consumer_index, 1, rcb->q_depth);
  412. wis++;
  413. if (likely(--wi_range))
  414. next_cmpl = cmpl + 1;
  415. else {
  416. BNA_QE_INDX_ADD(ccb->producer_index, wis, ccb->q_depth);
  417. wis = 0;
  418. BNA_CQ_QPGE_PTR_GET(ccb->producer_index, ccb->sw_qpt,
  419. next_cmpl, wi_range);
  420. BUG_ON(!(wi_range <= ccb->q_depth));
  421. }
  422. prefetch(next_cmpl);
  423. flags = ntohl(cmpl->flags);
  424. if (unlikely
  425. (flags &
  426. (BNA_CQ_EF_MAC_ERROR | BNA_CQ_EF_FCS_ERROR |
  427. BNA_CQ_EF_TOO_LONG))) {
  428. dev_kfree_skb_any(skb);
  429. rcb->rxq->rx_packets_with_error++;
  430. goto next;
  431. }
  432. skb_put(skb, ntohs(cmpl->length));
  433. if (likely
  434. ((bnad->netdev->features & NETIF_F_RXCSUM) &&
  435. (((flags & BNA_CQ_EF_IPV4) &&
  436. (flags & BNA_CQ_EF_L3_CKSUM_OK)) ||
  437. (flags & BNA_CQ_EF_IPV6)) &&
  438. (flags & (BNA_CQ_EF_TCP | BNA_CQ_EF_UDP)) &&
  439. (flags & BNA_CQ_EF_L4_CKSUM_OK)))
  440. skb->ip_summed = CHECKSUM_UNNECESSARY;
  441. else
  442. skb_checksum_none_assert(skb);
  443. rcb->rxq->rx_packets++;
  444. rcb->rxq->rx_bytes += skb->len;
  445. skb->protocol = eth_type_trans(skb, bnad->netdev);
  446. if (bnad->vlan_grp && (flags & BNA_CQ_EF_VLAN)) {
  447. struct bnad_rx_ctrl *rx_ctrl =
  448. (struct bnad_rx_ctrl *)ccb->ctrl;
  449. if (skb->ip_summed == CHECKSUM_UNNECESSARY)
  450. vlan_gro_receive(&rx_ctrl->napi, bnad->vlan_grp,
  451. ntohs(cmpl->vlan_tag), skb);
  452. else
  453. vlan_hwaccel_receive_skb(skb,
  454. bnad->vlan_grp,
  455. ntohs(cmpl->vlan_tag));
  456. } else { /* Not VLAN tagged/stripped */
  457. struct bnad_rx_ctrl *rx_ctrl =
  458. (struct bnad_rx_ctrl *)ccb->ctrl;
  459. if (skb->ip_summed == CHECKSUM_UNNECESSARY)
  460. napi_gro_receive(&rx_ctrl->napi, skb);
  461. else
  462. netif_receive_skb(skb);
  463. }
  464. next:
  465. cmpl->valid = 0;
  466. cmpl = next_cmpl;
  467. }
  468. BNA_QE_INDX_ADD(ccb->producer_index, wis, ccb->q_depth);
  469. if (likely(ccb)) {
  470. if (likely(test_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags)))
  471. bna_ib_ack(ccb->i_dbell, packets);
  472. bnad_refill_rxq(bnad, ccb->rcb[0]);
  473. if (ccb->rcb[1])
  474. bnad_refill_rxq(bnad, ccb->rcb[1]);
  475. } else {
  476. if (likely(test_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags)))
  477. bna_ib_ack(ccb->i_dbell, 0);
  478. }
  479. return packets;
  480. }
  481. static void
  482. bnad_disable_rx_irq(struct bnad *bnad, struct bna_ccb *ccb)
  483. {
  484. if (unlikely(!test_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags)))
  485. return;
  486. bna_ib_coalescing_timer_set(ccb->i_dbell, 0);
  487. bna_ib_ack(ccb->i_dbell, 0);
  488. }
  489. static void
  490. bnad_enable_rx_irq(struct bnad *bnad, struct bna_ccb *ccb)
  491. {
  492. unsigned long flags;
  493. /* Because of polling context */
  494. spin_lock_irqsave(&bnad->bna_lock, flags);
  495. bnad_enable_rx_irq_unsafe(ccb);
  496. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  497. }
  498. static void
  499. bnad_netif_rx_schedule_poll(struct bnad *bnad, struct bna_ccb *ccb)
  500. {
  501. struct bnad_rx_ctrl *rx_ctrl = (struct bnad_rx_ctrl *)(ccb->ctrl);
  502. struct napi_struct *napi = &rx_ctrl->napi;
  503. if (likely(napi_schedule_prep(napi))) {
  504. bnad_disable_rx_irq(bnad, ccb);
  505. __napi_schedule(napi);
  506. }
  507. BNAD_UPDATE_CTR(bnad, netif_rx_schedule);
  508. }
  509. /* MSIX Rx Path Handler */
  510. static irqreturn_t
  511. bnad_msix_rx(int irq, void *data)
  512. {
  513. struct bna_ccb *ccb = (struct bna_ccb *)data;
  514. struct bnad *bnad = ccb->bnad;
  515. bnad_netif_rx_schedule_poll(bnad, ccb);
  516. return IRQ_HANDLED;
  517. }
  518. /* Interrupt handlers */
  519. /* Mbox Interrupt Handlers */
  520. static irqreturn_t
  521. bnad_msix_mbox_handler(int irq, void *data)
  522. {
  523. u32 intr_status;
  524. unsigned long flags;
  525. struct bnad *bnad = (struct bnad *)data;
  526. if (unlikely(test_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags)))
  527. return IRQ_HANDLED;
  528. spin_lock_irqsave(&bnad->bna_lock, flags);
  529. bna_intr_status_get(&bnad->bna, intr_status);
  530. if (BNA_IS_MBOX_ERR_INTR(intr_status))
  531. bna_mbox_handler(&bnad->bna, intr_status);
  532. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  533. return IRQ_HANDLED;
  534. }
  535. static irqreturn_t
  536. bnad_isr(int irq, void *data)
  537. {
  538. int i, j;
  539. u32 intr_status;
  540. unsigned long flags;
  541. struct bnad *bnad = (struct bnad *)data;
  542. struct bnad_rx_info *rx_info;
  543. struct bnad_rx_ctrl *rx_ctrl;
  544. if (unlikely(test_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags)))
  545. return IRQ_NONE;
  546. bna_intr_status_get(&bnad->bna, intr_status);
  547. if (unlikely(!intr_status))
  548. return IRQ_NONE;
  549. spin_lock_irqsave(&bnad->bna_lock, flags);
  550. if (BNA_IS_MBOX_ERR_INTR(intr_status))
  551. bna_mbox_handler(&bnad->bna, intr_status);
  552. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  553. if (!BNA_IS_INTX_DATA_INTR(intr_status))
  554. return IRQ_HANDLED;
  555. /* Process data interrupts */
  556. /* Tx processing */
  557. for (i = 0; i < bnad->num_tx; i++) {
  558. for (j = 0; j < bnad->num_txq_per_tx; j++)
  559. bnad_tx(bnad, bnad->tx_info[i].tcb[j]);
  560. }
  561. /* Rx processing */
  562. for (i = 0; i < bnad->num_rx; i++) {
  563. rx_info = &bnad->rx_info[i];
  564. if (!rx_info->rx)
  565. continue;
  566. for (j = 0; j < bnad->num_rxp_per_rx; j++) {
  567. rx_ctrl = &rx_info->rx_ctrl[j];
  568. if (rx_ctrl->ccb)
  569. bnad_netif_rx_schedule_poll(bnad,
  570. rx_ctrl->ccb);
  571. }
  572. }
  573. return IRQ_HANDLED;
  574. }
  575. /*
  576. * Called in interrupt / callback context
  577. * with bna_lock held, so cfg_flags access is OK
  578. */
  579. static void
  580. bnad_enable_mbox_irq(struct bnad *bnad)
  581. {
  582. clear_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags);
  583. BNAD_UPDATE_CTR(bnad, mbox_intr_enabled);
  584. }
  585. /*
  586. * Called with bnad->bna_lock held b'cos of
  587. * bnad->cfg_flags access.
  588. */
  589. static void
  590. bnad_disable_mbox_irq(struct bnad *bnad)
  591. {
  592. set_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags);
  593. BNAD_UPDATE_CTR(bnad, mbox_intr_disabled);
  594. }
  595. static void
  596. bnad_set_netdev_perm_addr(struct bnad *bnad)
  597. {
  598. struct net_device *netdev = bnad->netdev;
  599. memcpy(netdev->perm_addr, &bnad->perm_addr, netdev->addr_len);
  600. if (is_zero_ether_addr(netdev->dev_addr))
  601. memcpy(netdev->dev_addr, &bnad->perm_addr, netdev->addr_len);
  602. }
  603. /* Control Path Handlers */
  604. /* Callbacks */
  605. void
  606. bnad_cb_device_enable_mbox_intr(struct bnad *bnad)
  607. {
  608. bnad_enable_mbox_irq(bnad);
  609. }
  610. void
  611. bnad_cb_device_disable_mbox_intr(struct bnad *bnad)
  612. {
  613. bnad_disable_mbox_irq(bnad);
  614. }
  615. void
  616. bnad_cb_device_enabled(struct bnad *bnad, enum bna_cb_status status)
  617. {
  618. complete(&bnad->bnad_completions.ioc_comp);
  619. bnad->bnad_completions.ioc_comp_status = status;
  620. }
  621. void
  622. bnad_cb_device_disabled(struct bnad *bnad, enum bna_cb_status status)
  623. {
  624. complete(&bnad->bnad_completions.ioc_comp);
  625. bnad->bnad_completions.ioc_comp_status = status;
  626. }
  627. static void
  628. bnad_cb_port_disabled(void *arg, enum bna_cb_status status)
  629. {
  630. struct bnad *bnad = (struct bnad *)arg;
  631. complete(&bnad->bnad_completions.port_comp);
  632. netif_carrier_off(bnad->netdev);
  633. }
  634. void
  635. bnad_cb_port_link_status(struct bnad *bnad,
  636. enum bna_link_status link_status)
  637. {
  638. bool link_up = 0;
  639. link_up = (link_status == BNA_LINK_UP) || (link_status == BNA_CEE_UP);
  640. if (link_status == BNA_CEE_UP) {
  641. set_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags);
  642. BNAD_UPDATE_CTR(bnad, cee_up);
  643. } else
  644. clear_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags);
  645. if (link_up) {
  646. if (!netif_carrier_ok(bnad->netdev)) {
  647. struct bna_tcb *tcb = bnad->tx_info[0].tcb[0];
  648. if (!tcb)
  649. return;
  650. pr_warn("bna: %s link up\n",
  651. bnad->netdev->name);
  652. netif_carrier_on(bnad->netdev);
  653. BNAD_UPDATE_CTR(bnad, link_toggle);
  654. if (test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)) {
  655. /* Force an immediate Transmit Schedule */
  656. pr_info("bna: %s TX_STARTED\n",
  657. bnad->netdev->name);
  658. netif_wake_queue(bnad->netdev);
  659. BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
  660. } else {
  661. netif_stop_queue(bnad->netdev);
  662. BNAD_UPDATE_CTR(bnad, netif_queue_stop);
  663. }
  664. }
  665. } else {
  666. if (netif_carrier_ok(bnad->netdev)) {
  667. pr_warn("bna: %s link down\n",
  668. bnad->netdev->name);
  669. netif_carrier_off(bnad->netdev);
  670. BNAD_UPDATE_CTR(bnad, link_toggle);
  671. }
  672. }
  673. }
  674. static void
  675. bnad_cb_tx_disabled(void *arg, struct bna_tx *tx,
  676. enum bna_cb_status status)
  677. {
  678. struct bnad *bnad = (struct bnad *)arg;
  679. complete(&bnad->bnad_completions.tx_comp);
  680. }
  681. static void
  682. bnad_cb_tcb_setup(struct bnad *bnad, struct bna_tcb *tcb)
  683. {
  684. struct bnad_tx_info *tx_info =
  685. (struct bnad_tx_info *)tcb->txq->tx->priv;
  686. struct bnad_unmap_q *unmap_q = tcb->unmap_q;
  687. tx_info->tcb[tcb->id] = tcb;
  688. unmap_q->producer_index = 0;
  689. unmap_q->consumer_index = 0;
  690. unmap_q->q_depth = BNAD_TX_UNMAPQ_DEPTH;
  691. }
  692. static void
  693. bnad_cb_tcb_destroy(struct bnad *bnad, struct bna_tcb *tcb)
  694. {
  695. struct bnad_tx_info *tx_info =
  696. (struct bnad_tx_info *)tcb->txq->tx->priv;
  697. struct bnad_unmap_q *unmap_q = tcb->unmap_q;
  698. while (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags))
  699. cpu_relax();
  700. bnad_free_all_txbufs(bnad, tcb);
  701. unmap_q->producer_index = 0;
  702. unmap_q->consumer_index = 0;
  703. smp_mb__before_clear_bit();
  704. clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
  705. tx_info->tcb[tcb->id] = NULL;
  706. }
  707. static void
  708. bnad_cb_rcb_setup(struct bnad *bnad, struct bna_rcb *rcb)
  709. {
  710. struct bnad_unmap_q *unmap_q = rcb->unmap_q;
  711. unmap_q->producer_index = 0;
  712. unmap_q->consumer_index = 0;
  713. unmap_q->q_depth = BNAD_RX_UNMAPQ_DEPTH;
  714. }
  715. static void
  716. bnad_cb_rcb_destroy(struct bnad *bnad, struct bna_rcb *rcb)
  717. {
  718. bnad_free_all_rxbufs(bnad, rcb);
  719. }
  720. static void
  721. bnad_cb_ccb_setup(struct bnad *bnad, struct bna_ccb *ccb)
  722. {
  723. struct bnad_rx_info *rx_info =
  724. (struct bnad_rx_info *)ccb->cq->rx->priv;
  725. rx_info->rx_ctrl[ccb->id].ccb = ccb;
  726. ccb->ctrl = &rx_info->rx_ctrl[ccb->id];
  727. }
  728. static void
  729. bnad_cb_ccb_destroy(struct bnad *bnad, struct bna_ccb *ccb)
  730. {
  731. struct bnad_rx_info *rx_info =
  732. (struct bnad_rx_info *)ccb->cq->rx->priv;
  733. rx_info->rx_ctrl[ccb->id].ccb = NULL;
  734. }
  735. static void
  736. bnad_cb_tx_stall(struct bnad *bnad, struct bna_tcb *tcb)
  737. {
  738. struct bnad_tx_info *tx_info =
  739. (struct bnad_tx_info *)tcb->txq->tx->priv;
  740. if (tx_info != &bnad->tx_info[0])
  741. return;
  742. clear_bit(BNAD_TXQ_TX_STARTED, &tcb->flags);
  743. netif_stop_queue(bnad->netdev);
  744. pr_info("bna: %s TX_STOPPED\n", bnad->netdev->name);
  745. }
  746. static void
  747. bnad_cb_tx_resume(struct bnad *bnad, struct bna_tcb *tcb)
  748. {
  749. struct bnad_unmap_q *unmap_q = tcb->unmap_q;
  750. if (test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))
  751. return;
  752. clear_bit(BNAD_RF_TX_SHUTDOWN_DELAYED, &bnad->run_flags);
  753. while (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags))
  754. cpu_relax();
  755. bnad_free_all_txbufs(bnad, tcb);
  756. unmap_q->producer_index = 0;
  757. unmap_q->consumer_index = 0;
  758. smp_mb__before_clear_bit();
  759. clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
  760. /*
  761. * Workaround for first device enable failure & we
  762. * get a 0 MAC address. We try to get the MAC address
  763. * again here.
  764. */
  765. if (is_zero_ether_addr(&bnad->perm_addr.mac[0])) {
  766. bna_port_mac_get(&bnad->bna.port, &bnad->perm_addr);
  767. bnad_set_netdev_perm_addr(bnad);
  768. }
  769. set_bit(BNAD_TXQ_TX_STARTED, &tcb->flags);
  770. if (netif_carrier_ok(bnad->netdev)) {
  771. pr_info("bna: %s TX_STARTED\n", bnad->netdev->name);
  772. netif_wake_queue(bnad->netdev);
  773. BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
  774. }
  775. }
  776. static void
  777. bnad_cb_tx_cleanup(struct bnad *bnad, struct bna_tcb *tcb)
  778. {
  779. /* Delay only once for the whole Tx Path Shutdown */
  780. if (!test_and_set_bit(BNAD_RF_TX_SHUTDOWN_DELAYED, &bnad->run_flags))
  781. mdelay(BNAD_TXRX_SYNC_MDELAY);
  782. }
  783. static void
  784. bnad_cb_rx_cleanup(struct bnad *bnad,
  785. struct bna_ccb *ccb)
  786. {
  787. clear_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags);
  788. if (ccb->rcb[1])
  789. clear_bit(BNAD_RXQ_STARTED, &ccb->rcb[1]->flags);
  790. if (!test_and_set_bit(BNAD_RF_RX_SHUTDOWN_DELAYED, &bnad->run_flags))
  791. mdelay(BNAD_TXRX_SYNC_MDELAY);
  792. }
  793. static void
  794. bnad_cb_rx_post(struct bnad *bnad, struct bna_rcb *rcb)
  795. {
  796. struct bnad_unmap_q *unmap_q = rcb->unmap_q;
  797. clear_bit(BNAD_RF_RX_SHUTDOWN_DELAYED, &bnad->run_flags);
  798. if (rcb == rcb->cq->ccb->rcb[0])
  799. bnad_cq_cmpl_init(bnad, rcb->cq->ccb);
  800. bnad_free_all_rxbufs(bnad, rcb);
  801. set_bit(BNAD_RXQ_STARTED, &rcb->flags);
  802. /* Now allocate & post buffers for this RCB */
  803. /* !!Allocation in callback context */
  804. if (!test_and_set_bit(BNAD_RXQ_REFILL, &rcb->flags)) {
  805. if (BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth)
  806. >> BNAD_RXQ_REFILL_THRESHOLD_SHIFT)
  807. bnad_alloc_n_post_rxbufs(bnad, rcb);
  808. smp_mb__before_clear_bit();
  809. clear_bit(BNAD_RXQ_REFILL, &rcb->flags);
  810. }
  811. }
  812. static void
  813. bnad_cb_rx_disabled(void *arg, struct bna_rx *rx,
  814. enum bna_cb_status status)
  815. {
  816. struct bnad *bnad = (struct bnad *)arg;
  817. complete(&bnad->bnad_completions.rx_comp);
  818. }
  819. static void
  820. bnad_cb_rx_mcast_add(struct bnad *bnad, struct bna_rx *rx,
  821. enum bna_cb_status status)
  822. {
  823. bnad->bnad_completions.mcast_comp_status = status;
  824. complete(&bnad->bnad_completions.mcast_comp);
  825. }
  826. void
  827. bnad_cb_stats_get(struct bnad *bnad, enum bna_cb_status status,
  828. struct bna_stats *stats)
  829. {
  830. if (status == BNA_CB_SUCCESS)
  831. BNAD_UPDATE_CTR(bnad, hw_stats_updates);
  832. if (!netif_running(bnad->netdev) ||
  833. !test_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
  834. return;
  835. mod_timer(&bnad->stats_timer,
  836. jiffies + msecs_to_jiffies(BNAD_STATS_TIMER_FREQ));
  837. }
  838. /* Resource allocation, free functions */
  839. static void
  840. bnad_mem_free(struct bnad *bnad,
  841. struct bna_mem_info *mem_info)
  842. {
  843. int i;
  844. dma_addr_t dma_pa;
  845. if (mem_info->mdl == NULL)
  846. return;
  847. for (i = 0; i < mem_info->num; i++) {
  848. if (mem_info->mdl[i].kva != NULL) {
  849. if (mem_info->mem_type == BNA_MEM_T_DMA) {
  850. BNA_GET_DMA_ADDR(&(mem_info->mdl[i].dma),
  851. dma_pa);
  852. dma_free_coherent(&bnad->pcidev->dev,
  853. mem_info->mdl[i].len,
  854. mem_info->mdl[i].kva, dma_pa);
  855. } else
  856. kfree(mem_info->mdl[i].kva);
  857. }
  858. }
  859. kfree(mem_info->mdl);
  860. mem_info->mdl = NULL;
  861. }
  862. static int
  863. bnad_mem_alloc(struct bnad *bnad,
  864. struct bna_mem_info *mem_info)
  865. {
  866. int i;
  867. dma_addr_t dma_pa;
  868. if ((mem_info->num == 0) || (mem_info->len == 0)) {
  869. mem_info->mdl = NULL;
  870. return 0;
  871. }
  872. mem_info->mdl = kcalloc(mem_info->num, sizeof(struct bna_mem_descr),
  873. GFP_KERNEL);
  874. if (mem_info->mdl == NULL)
  875. return -ENOMEM;
  876. if (mem_info->mem_type == BNA_MEM_T_DMA) {
  877. for (i = 0; i < mem_info->num; i++) {
  878. mem_info->mdl[i].len = mem_info->len;
  879. mem_info->mdl[i].kva =
  880. dma_alloc_coherent(&bnad->pcidev->dev,
  881. mem_info->len, &dma_pa,
  882. GFP_KERNEL);
  883. if (mem_info->mdl[i].kva == NULL)
  884. goto err_return;
  885. BNA_SET_DMA_ADDR(dma_pa,
  886. &(mem_info->mdl[i].dma));
  887. }
  888. } else {
  889. for (i = 0; i < mem_info->num; i++) {
  890. mem_info->mdl[i].len = mem_info->len;
  891. mem_info->mdl[i].kva = kzalloc(mem_info->len,
  892. GFP_KERNEL);
  893. if (mem_info->mdl[i].kva == NULL)
  894. goto err_return;
  895. }
  896. }
  897. return 0;
  898. err_return:
  899. bnad_mem_free(bnad, mem_info);
  900. return -ENOMEM;
  901. }
  902. /* Free IRQ for Mailbox */
  903. static void
  904. bnad_mbox_irq_free(struct bnad *bnad,
  905. struct bna_intr_info *intr_info)
  906. {
  907. int irq;
  908. unsigned long flags;
  909. if (intr_info->idl == NULL)
  910. return;
  911. spin_lock_irqsave(&bnad->bna_lock, flags);
  912. bnad_disable_mbox_irq(bnad);
  913. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  914. irq = BNAD_GET_MBOX_IRQ(bnad);
  915. free_irq(irq, bnad);
  916. kfree(intr_info->idl);
  917. }
  918. /*
  919. * Allocates IRQ for Mailbox, but keep it disabled
  920. * This will be enabled once we get the mbox enable callback
  921. * from bna
  922. */
  923. static int
  924. bnad_mbox_irq_alloc(struct bnad *bnad,
  925. struct bna_intr_info *intr_info)
  926. {
  927. int err = 0;
  928. unsigned long flags;
  929. u32 irq;
  930. irq_handler_t irq_handler;
  931. /* Mbox should use only 1 vector */
  932. intr_info->idl = kzalloc(sizeof(*(intr_info->idl)), GFP_KERNEL);
  933. if (!intr_info->idl)
  934. return -ENOMEM;
  935. spin_lock_irqsave(&bnad->bna_lock, flags);
  936. if (bnad->cfg_flags & BNAD_CF_MSIX) {
  937. irq_handler = (irq_handler_t)bnad_msix_mbox_handler;
  938. irq = bnad->msix_table[bnad->msix_num - 1].vector;
  939. flags = 0;
  940. intr_info->intr_type = BNA_INTR_T_MSIX;
  941. intr_info->idl[0].vector = bnad->msix_num - 1;
  942. } else {
  943. irq_handler = (irq_handler_t)bnad_isr;
  944. irq = bnad->pcidev->irq;
  945. flags = IRQF_SHARED;
  946. intr_info->intr_type = BNA_INTR_T_INTX;
  947. /* intr_info->idl.vector = 0 ? */
  948. }
  949. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  950. sprintf(bnad->mbox_irq_name, "%s", BNAD_NAME);
  951. /*
  952. * Set the Mbox IRQ disable flag, so that the IRQ handler
  953. * called from request_irq() for SHARED IRQs do not execute
  954. */
  955. set_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags);
  956. BNAD_UPDATE_CTR(bnad, mbox_intr_disabled);
  957. err = request_irq(irq, irq_handler, flags,
  958. bnad->mbox_irq_name, bnad);
  959. if (err) {
  960. kfree(intr_info->idl);
  961. intr_info->idl = NULL;
  962. }
  963. return err;
  964. }
  965. static void
  966. bnad_txrx_irq_free(struct bnad *bnad, struct bna_intr_info *intr_info)
  967. {
  968. kfree(intr_info->idl);
  969. intr_info->idl = NULL;
  970. }
  971. /* Allocates Interrupt Descriptor List for MSIX/INT-X vectors */
  972. static int
  973. bnad_txrx_irq_alloc(struct bnad *bnad, enum bnad_intr_source src,
  974. uint txrx_id, struct bna_intr_info *intr_info)
  975. {
  976. int i, vector_start = 0;
  977. u32 cfg_flags;
  978. unsigned long flags;
  979. spin_lock_irqsave(&bnad->bna_lock, flags);
  980. cfg_flags = bnad->cfg_flags;
  981. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  982. if (cfg_flags & BNAD_CF_MSIX) {
  983. intr_info->intr_type = BNA_INTR_T_MSIX;
  984. intr_info->idl = kcalloc(intr_info->num,
  985. sizeof(struct bna_intr_descr),
  986. GFP_KERNEL);
  987. if (!intr_info->idl)
  988. return -ENOMEM;
  989. switch (src) {
  990. case BNAD_INTR_TX:
  991. vector_start = txrx_id;
  992. break;
  993. case BNAD_INTR_RX:
  994. vector_start = bnad->num_tx * bnad->num_txq_per_tx +
  995. txrx_id;
  996. break;
  997. default:
  998. BUG();
  999. }
  1000. for (i = 0; i < intr_info->num; i++)
  1001. intr_info->idl[i].vector = vector_start + i;
  1002. } else {
  1003. intr_info->intr_type = BNA_INTR_T_INTX;
  1004. intr_info->num = 1;
  1005. intr_info->idl = kcalloc(intr_info->num,
  1006. sizeof(struct bna_intr_descr),
  1007. GFP_KERNEL);
  1008. if (!intr_info->idl)
  1009. return -ENOMEM;
  1010. switch (src) {
  1011. case BNAD_INTR_TX:
  1012. intr_info->idl[0].vector = 0x1; /* Bit mask : Tx IB */
  1013. break;
  1014. case BNAD_INTR_RX:
  1015. intr_info->idl[0].vector = 0x2; /* Bit mask : Rx IB */
  1016. break;
  1017. }
  1018. }
  1019. return 0;
  1020. }
  1021. /**
  1022. * NOTE: Should be called for MSIX only
  1023. * Unregisters Tx MSIX vector(s) from the kernel
  1024. */
  1025. static void
  1026. bnad_tx_msix_unregister(struct bnad *bnad, struct bnad_tx_info *tx_info,
  1027. int num_txqs)
  1028. {
  1029. int i;
  1030. int vector_num;
  1031. for (i = 0; i < num_txqs; i++) {
  1032. if (tx_info->tcb[i] == NULL)
  1033. continue;
  1034. vector_num = tx_info->tcb[i]->intr_vector;
  1035. free_irq(bnad->msix_table[vector_num].vector, tx_info->tcb[i]);
  1036. }
  1037. }
  1038. /**
  1039. * NOTE: Should be called for MSIX only
  1040. * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel
  1041. */
  1042. static int
  1043. bnad_tx_msix_register(struct bnad *bnad, struct bnad_tx_info *tx_info,
  1044. uint tx_id, int num_txqs)
  1045. {
  1046. int i;
  1047. int err;
  1048. int vector_num;
  1049. for (i = 0; i < num_txqs; i++) {
  1050. vector_num = tx_info->tcb[i]->intr_vector;
  1051. sprintf(tx_info->tcb[i]->name, "%s TXQ %d", bnad->netdev->name,
  1052. tx_id + tx_info->tcb[i]->id);
  1053. err = request_irq(bnad->msix_table[vector_num].vector,
  1054. (irq_handler_t)bnad_msix_tx, 0,
  1055. tx_info->tcb[i]->name,
  1056. tx_info->tcb[i]);
  1057. if (err)
  1058. goto err_return;
  1059. }
  1060. return 0;
  1061. err_return:
  1062. if (i > 0)
  1063. bnad_tx_msix_unregister(bnad, tx_info, (i - 1));
  1064. return -1;
  1065. }
  1066. /**
  1067. * NOTE: Should be called for MSIX only
  1068. * Unregisters Rx MSIX vector(s) from the kernel
  1069. */
  1070. static void
  1071. bnad_rx_msix_unregister(struct bnad *bnad, struct bnad_rx_info *rx_info,
  1072. int num_rxps)
  1073. {
  1074. int i;
  1075. int vector_num;
  1076. for (i = 0; i < num_rxps; i++) {
  1077. if (rx_info->rx_ctrl[i].ccb == NULL)
  1078. continue;
  1079. vector_num = rx_info->rx_ctrl[i].ccb->intr_vector;
  1080. free_irq(bnad->msix_table[vector_num].vector,
  1081. rx_info->rx_ctrl[i].ccb);
  1082. }
  1083. }
  1084. /**
  1085. * NOTE: Should be called for MSIX only
  1086. * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel
  1087. */
  1088. static int
  1089. bnad_rx_msix_register(struct bnad *bnad, struct bnad_rx_info *rx_info,
  1090. uint rx_id, int num_rxps)
  1091. {
  1092. int i;
  1093. int err;
  1094. int vector_num;
  1095. for (i = 0; i < num_rxps; i++) {
  1096. vector_num = rx_info->rx_ctrl[i].ccb->intr_vector;
  1097. sprintf(rx_info->rx_ctrl[i].ccb->name, "%s CQ %d",
  1098. bnad->netdev->name,
  1099. rx_id + rx_info->rx_ctrl[i].ccb->id);
  1100. err = request_irq(bnad->msix_table[vector_num].vector,
  1101. (irq_handler_t)bnad_msix_rx, 0,
  1102. rx_info->rx_ctrl[i].ccb->name,
  1103. rx_info->rx_ctrl[i].ccb);
  1104. if (err)
  1105. goto err_return;
  1106. }
  1107. return 0;
  1108. err_return:
  1109. if (i > 0)
  1110. bnad_rx_msix_unregister(bnad, rx_info, (i - 1));
  1111. return -1;
  1112. }
  1113. /* Free Tx object Resources */
  1114. static void
  1115. bnad_tx_res_free(struct bnad *bnad, struct bna_res_info *res_info)
  1116. {
  1117. int i;
  1118. for (i = 0; i < BNA_TX_RES_T_MAX; i++) {
  1119. if (res_info[i].res_type == BNA_RES_T_MEM)
  1120. bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
  1121. else if (res_info[i].res_type == BNA_RES_T_INTR)
  1122. bnad_txrx_irq_free(bnad, &res_info[i].res_u.intr_info);
  1123. }
  1124. }
  1125. /* Allocates memory and interrupt resources for Tx object */
  1126. static int
  1127. bnad_tx_res_alloc(struct bnad *bnad, struct bna_res_info *res_info,
  1128. uint tx_id)
  1129. {
  1130. int i, err = 0;
  1131. for (i = 0; i < BNA_TX_RES_T_MAX; i++) {
  1132. if (res_info[i].res_type == BNA_RES_T_MEM)
  1133. err = bnad_mem_alloc(bnad,
  1134. &res_info[i].res_u.mem_info);
  1135. else if (res_info[i].res_type == BNA_RES_T_INTR)
  1136. err = bnad_txrx_irq_alloc(bnad, BNAD_INTR_TX, tx_id,
  1137. &res_info[i].res_u.intr_info);
  1138. if (err)
  1139. goto err_return;
  1140. }
  1141. return 0;
  1142. err_return:
  1143. bnad_tx_res_free(bnad, res_info);
  1144. return err;
  1145. }
  1146. /* Free Rx object Resources */
  1147. static void
  1148. bnad_rx_res_free(struct bnad *bnad, struct bna_res_info *res_info)
  1149. {
  1150. int i;
  1151. for (i = 0; i < BNA_RX_RES_T_MAX; i++) {
  1152. if (res_info[i].res_type == BNA_RES_T_MEM)
  1153. bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
  1154. else if (res_info[i].res_type == BNA_RES_T_INTR)
  1155. bnad_txrx_irq_free(bnad, &res_info[i].res_u.intr_info);
  1156. }
  1157. }
  1158. /* Allocates memory and interrupt resources for Rx object */
  1159. static int
  1160. bnad_rx_res_alloc(struct bnad *bnad, struct bna_res_info *res_info,
  1161. uint rx_id)
  1162. {
  1163. int i, err = 0;
  1164. /* All memory needs to be allocated before setup_ccbs */
  1165. for (i = 0; i < BNA_RX_RES_T_MAX; i++) {
  1166. if (res_info[i].res_type == BNA_RES_T_MEM)
  1167. err = bnad_mem_alloc(bnad,
  1168. &res_info[i].res_u.mem_info);
  1169. else if (res_info[i].res_type == BNA_RES_T_INTR)
  1170. err = bnad_txrx_irq_alloc(bnad, BNAD_INTR_RX, rx_id,
  1171. &res_info[i].res_u.intr_info);
  1172. if (err)
  1173. goto err_return;
  1174. }
  1175. return 0;
  1176. err_return:
  1177. bnad_rx_res_free(bnad, res_info);
  1178. return err;
  1179. }
  1180. /* Timer callbacks */
  1181. /* a) IOC timer */
  1182. static void
  1183. bnad_ioc_timeout(unsigned long data)
  1184. {
  1185. struct bnad *bnad = (struct bnad *)data;
  1186. unsigned long flags;
  1187. spin_lock_irqsave(&bnad->bna_lock, flags);
  1188. bfa_nw_ioc_timeout((void *) &bnad->bna.device.ioc);
  1189. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1190. }
  1191. static void
  1192. bnad_ioc_hb_check(unsigned long data)
  1193. {
  1194. struct bnad *bnad = (struct bnad *)data;
  1195. unsigned long flags;
  1196. spin_lock_irqsave(&bnad->bna_lock, flags);
  1197. bfa_nw_ioc_hb_check((void *) &bnad->bna.device.ioc);
  1198. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1199. }
  1200. static void
  1201. bnad_iocpf_timeout(unsigned long data)
  1202. {
  1203. struct bnad *bnad = (struct bnad *)data;
  1204. unsigned long flags;
  1205. spin_lock_irqsave(&bnad->bna_lock, flags);
  1206. bfa_nw_iocpf_timeout((void *) &bnad->bna.device.ioc);
  1207. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1208. }
  1209. static void
  1210. bnad_iocpf_sem_timeout(unsigned long data)
  1211. {
  1212. struct bnad *bnad = (struct bnad *)data;
  1213. unsigned long flags;
  1214. spin_lock_irqsave(&bnad->bna_lock, flags);
  1215. bfa_nw_iocpf_sem_timeout((void *) &bnad->bna.device.ioc);
  1216. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1217. }
  1218. /*
  1219. * All timer routines use bnad->bna_lock to protect against
  1220. * the following race, which may occur in case of no locking:
  1221. * Time CPU m CPU n
  1222. * 0 1 = test_bit
  1223. * 1 clear_bit
  1224. * 2 del_timer_sync
  1225. * 3 mod_timer
  1226. */
  1227. /* b) Dynamic Interrupt Moderation Timer */
  1228. static void
  1229. bnad_dim_timeout(unsigned long data)
  1230. {
  1231. struct bnad *bnad = (struct bnad *)data;
  1232. struct bnad_rx_info *rx_info;
  1233. struct bnad_rx_ctrl *rx_ctrl;
  1234. int i, j;
  1235. unsigned long flags;
  1236. if (!netif_carrier_ok(bnad->netdev))
  1237. return;
  1238. spin_lock_irqsave(&bnad->bna_lock, flags);
  1239. for (i = 0; i < bnad->num_rx; i++) {
  1240. rx_info = &bnad->rx_info[i];
  1241. if (!rx_info->rx)
  1242. continue;
  1243. for (j = 0; j < bnad->num_rxp_per_rx; j++) {
  1244. rx_ctrl = &rx_info->rx_ctrl[j];
  1245. if (!rx_ctrl->ccb)
  1246. continue;
  1247. bna_rx_dim_update(rx_ctrl->ccb);
  1248. }
  1249. }
  1250. /* Check for BNAD_CF_DIM_ENABLED, does not eleminate a race */
  1251. if (test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags))
  1252. mod_timer(&bnad->dim_timer,
  1253. jiffies + msecs_to_jiffies(BNAD_DIM_TIMER_FREQ));
  1254. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1255. }
  1256. /* c) Statistics Timer */
  1257. static void
  1258. bnad_stats_timeout(unsigned long data)
  1259. {
  1260. struct bnad *bnad = (struct bnad *)data;
  1261. unsigned long flags;
  1262. if (!netif_running(bnad->netdev) ||
  1263. !test_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
  1264. return;
  1265. spin_lock_irqsave(&bnad->bna_lock, flags);
  1266. bna_stats_get(&bnad->bna);
  1267. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1268. }
  1269. /*
  1270. * Set up timer for DIM
  1271. * Called with bnad->bna_lock held
  1272. */
  1273. void
  1274. bnad_dim_timer_start(struct bnad *bnad)
  1275. {
  1276. if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED &&
  1277. !test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags)) {
  1278. setup_timer(&bnad->dim_timer, bnad_dim_timeout,
  1279. (unsigned long)bnad);
  1280. set_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags);
  1281. mod_timer(&bnad->dim_timer,
  1282. jiffies + msecs_to_jiffies(BNAD_DIM_TIMER_FREQ));
  1283. }
  1284. }
  1285. /*
  1286. * Set up timer for statistics
  1287. * Called with mutex_lock(&bnad->conf_mutex) held
  1288. */
  1289. static void
  1290. bnad_stats_timer_start(struct bnad *bnad)
  1291. {
  1292. unsigned long flags;
  1293. spin_lock_irqsave(&bnad->bna_lock, flags);
  1294. if (!test_and_set_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags)) {
  1295. setup_timer(&bnad->stats_timer, bnad_stats_timeout,
  1296. (unsigned long)bnad);
  1297. mod_timer(&bnad->stats_timer,
  1298. jiffies + msecs_to_jiffies(BNAD_STATS_TIMER_FREQ));
  1299. }
  1300. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1301. }
  1302. /*
  1303. * Stops the stats timer
  1304. * Called with mutex_lock(&bnad->conf_mutex) held
  1305. */
  1306. static void
  1307. bnad_stats_timer_stop(struct bnad *bnad)
  1308. {
  1309. int to_del = 0;
  1310. unsigned long flags;
  1311. spin_lock_irqsave(&bnad->bna_lock, flags);
  1312. if (test_and_clear_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
  1313. to_del = 1;
  1314. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1315. if (to_del)
  1316. del_timer_sync(&bnad->stats_timer);
  1317. }
  1318. /* Utilities */
  1319. static void
  1320. bnad_netdev_mc_list_get(struct net_device *netdev, u8 *mc_list)
  1321. {
  1322. int i = 1; /* Index 0 has broadcast address */
  1323. struct netdev_hw_addr *mc_addr;
  1324. netdev_for_each_mc_addr(mc_addr, netdev) {
  1325. memcpy(&mc_list[i * ETH_ALEN], &mc_addr->addr[0],
  1326. ETH_ALEN);
  1327. i++;
  1328. }
  1329. }
  1330. static int
  1331. bnad_napi_poll_rx(struct napi_struct *napi, int budget)
  1332. {
  1333. struct bnad_rx_ctrl *rx_ctrl =
  1334. container_of(napi, struct bnad_rx_ctrl, napi);
  1335. struct bna_ccb *ccb;
  1336. struct bnad *bnad;
  1337. int rcvd = 0;
  1338. ccb = rx_ctrl->ccb;
  1339. bnad = ccb->bnad;
  1340. if (!netif_carrier_ok(bnad->netdev))
  1341. goto poll_exit;
  1342. rcvd = bnad_poll_cq(bnad, ccb, budget);
  1343. if (rcvd == budget)
  1344. return rcvd;
  1345. poll_exit:
  1346. napi_complete((napi));
  1347. BNAD_UPDATE_CTR(bnad, netif_rx_complete);
  1348. bnad_enable_rx_irq(bnad, ccb);
  1349. return rcvd;
  1350. }
  1351. static void
  1352. bnad_napi_enable(struct bnad *bnad, u32 rx_id)
  1353. {
  1354. struct bnad_rx_ctrl *rx_ctrl;
  1355. int i;
  1356. /* Initialize & enable NAPI */
  1357. for (i = 0; i < bnad->num_rxp_per_rx; i++) {
  1358. rx_ctrl = &bnad->rx_info[rx_id].rx_ctrl[i];
  1359. netif_napi_add(bnad->netdev, &rx_ctrl->napi,
  1360. bnad_napi_poll_rx, 64);
  1361. napi_enable(&rx_ctrl->napi);
  1362. }
  1363. }
  1364. static void
  1365. bnad_napi_disable(struct bnad *bnad, u32 rx_id)
  1366. {
  1367. int i;
  1368. /* First disable and then clean up */
  1369. for (i = 0; i < bnad->num_rxp_per_rx; i++) {
  1370. napi_disable(&bnad->rx_info[rx_id].rx_ctrl[i].napi);
  1371. netif_napi_del(&bnad->rx_info[rx_id].rx_ctrl[i].napi);
  1372. }
  1373. }
  1374. /* Should be held with conf_lock held */
  1375. void
  1376. bnad_cleanup_tx(struct bnad *bnad, uint tx_id)
  1377. {
  1378. struct bnad_tx_info *tx_info = &bnad->tx_info[tx_id];
  1379. struct bna_res_info *res_info = &bnad->tx_res_info[tx_id].res_info[0];
  1380. unsigned long flags;
  1381. if (!tx_info->tx)
  1382. return;
  1383. init_completion(&bnad->bnad_completions.tx_comp);
  1384. spin_lock_irqsave(&bnad->bna_lock, flags);
  1385. bna_tx_disable(tx_info->tx, BNA_HARD_CLEANUP, bnad_cb_tx_disabled);
  1386. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1387. wait_for_completion(&bnad->bnad_completions.tx_comp);
  1388. if (tx_info->tcb[0]->intr_type == BNA_INTR_T_MSIX)
  1389. bnad_tx_msix_unregister(bnad, tx_info,
  1390. bnad->num_txq_per_tx);
  1391. spin_lock_irqsave(&bnad->bna_lock, flags);
  1392. bna_tx_destroy(tx_info->tx);
  1393. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1394. tx_info->tx = NULL;
  1395. if (0 == tx_id)
  1396. tasklet_kill(&bnad->tx_free_tasklet);
  1397. bnad_tx_res_free(bnad, res_info);
  1398. }
  1399. /* Should be held with conf_lock held */
  1400. int
  1401. bnad_setup_tx(struct bnad *bnad, uint tx_id)
  1402. {
  1403. int err;
  1404. struct bnad_tx_info *tx_info = &bnad->tx_info[tx_id];
  1405. struct bna_res_info *res_info = &bnad->tx_res_info[tx_id].res_info[0];
  1406. struct bna_intr_info *intr_info =
  1407. &res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info;
  1408. struct bna_tx_config *tx_config = &bnad->tx_config[tx_id];
  1409. struct bna_tx_event_cbfn tx_cbfn;
  1410. struct bna_tx *tx;
  1411. unsigned long flags;
  1412. /* Initialize the Tx object configuration */
  1413. tx_config->num_txq = bnad->num_txq_per_tx;
  1414. tx_config->txq_depth = bnad->txq_depth;
  1415. tx_config->tx_type = BNA_TX_T_REGULAR;
  1416. /* Initialize the tx event handlers */
  1417. tx_cbfn.tcb_setup_cbfn = bnad_cb_tcb_setup;
  1418. tx_cbfn.tcb_destroy_cbfn = bnad_cb_tcb_destroy;
  1419. tx_cbfn.tx_stall_cbfn = bnad_cb_tx_stall;
  1420. tx_cbfn.tx_resume_cbfn = bnad_cb_tx_resume;
  1421. tx_cbfn.tx_cleanup_cbfn = bnad_cb_tx_cleanup;
  1422. /* Get BNA's resource requirement for one tx object */
  1423. spin_lock_irqsave(&bnad->bna_lock, flags);
  1424. bna_tx_res_req(bnad->num_txq_per_tx,
  1425. bnad->txq_depth, res_info);
  1426. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1427. /* Fill Unmap Q memory requirements */
  1428. BNAD_FILL_UNMAPQ_MEM_REQ(
  1429. &res_info[BNA_TX_RES_MEM_T_UNMAPQ],
  1430. bnad->num_txq_per_tx,
  1431. BNAD_TX_UNMAPQ_DEPTH);
  1432. /* Allocate resources */
  1433. err = bnad_tx_res_alloc(bnad, res_info, tx_id);
  1434. if (err)
  1435. return err;
  1436. /* Ask BNA to create one Tx object, supplying required resources */
  1437. spin_lock_irqsave(&bnad->bna_lock, flags);
  1438. tx = bna_tx_create(&bnad->bna, bnad, tx_config, &tx_cbfn, res_info,
  1439. tx_info);
  1440. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1441. if (!tx)
  1442. goto err_return;
  1443. tx_info->tx = tx;
  1444. /* Register ISR for the Tx object */
  1445. if (intr_info->intr_type == BNA_INTR_T_MSIX) {
  1446. err = bnad_tx_msix_register(bnad, tx_info,
  1447. tx_id, bnad->num_txq_per_tx);
  1448. if (err)
  1449. goto err_return;
  1450. }
  1451. spin_lock_irqsave(&bnad->bna_lock, flags);
  1452. bna_tx_enable(tx);
  1453. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1454. return 0;
  1455. err_return:
  1456. bnad_tx_res_free(bnad, res_info);
  1457. return err;
  1458. }
  1459. /* Setup the rx config for bna_rx_create */
  1460. /* bnad decides the configuration */
  1461. static void
  1462. bnad_init_rx_config(struct bnad *bnad, struct bna_rx_config *rx_config)
  1463. {
  1464. rx_config->rx_type = BNA_RX_T_REGULAR;
  1465. rx_config->num_paths = bnad->num_rxp_per_rx;
  1466. if (bnad->num_rxp_per_rx > 1) {
  1467. rx_config->rss_status = BNA_STATUS_T_ENABLED;
  1468. rx_config->rss_config.hash_type =
  1469. (BFI_RSS_T_V4_TCP |
  1470. BFI_RSS_T_V6_TCP |
  1471. BFI_RSS_T_V4_IP |
  1472. BFI_RSS_T_V6_IP);
  1473. rx_config->rss_config.hash_mask =
  1474. bnad->num_rxp_per_rx - 1;
  1475. get_random_bytes(rx_config->rss_config.toeplitz_hash_key,
  1476. sizeof(rx_config->rss_config.toeplitz_hash_key));
  1477. } else {
  1478. rx_config->rss_status = BNA_STATUS_T_DISABLED;
  1479. memset(&rx_config->rss_config, 0,
  1480. sizeof(rx_config->rss_config));
  1481. }
  1482. rx_config->rxp_type = BNA_RXP_SLR;
  1483. rx_config->q_depth = bnad->rxq_depth;
  1484. rx_config->small_buff_size = BFI_SMALL_RXBUF_SIZE;
  1485. rx_config->vlan_strip_status = BNA_STATUS_T_ENABLED;
  1486. }
  1487. /* Called with mutex_lock(&bnad->conf_mutex) held */
  1488. void
  1489. bnad_cleanup_rx(struct bnad *bnad, uint rx_id)
  1490. {
  1491. struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id];
  1492. struct bna_rx_config *rx_config = &bnad->rx_config[rx_id];
  1493. struct bna_res_info *res_info = &bnad->rx_res_info[rx_id].res_info[0];
  1494. unsigned long flags;
  1495. int dim_timer_del = 0;
  1496. if (!rx_info->rx)
  1497. return;
  1498. if (0 == rx_id) {
  1499. spin_lock_irqsave(&bnad->bna_lock, flags);
  1500. dim_timer_del = bnad_dim_timer_running(bnad);
  1501. if (dim_timer_del)
  1502. clear_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags);
  1503. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1504. if (dim_timer_del)
  1505. del_timer_sync(&bnad->dim_timer);
  1506. }
  1507. bnad_napi_disable(bnad, rx_id);
  1508. init_completion(&bnad->bnad_completions.rx_comp);
  1509. spin_lock_irqsave(&bnad->bna_lock, flags);
  1510. bna_rx_disable(rx_info->rx, BNA_HARD_CLEANUP, bnad_cb_rx_disabled);
  1511. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1512. wait_for_completion(&bnad->bnad_completions.rx_comp);
  1513. if (rx_info->rx_ctrl[0].ccb->intr_type == BNA_INTR_T_MSIX)
  1514. bnad_rx_msix_unregister(bnad, rx_info, rx_config->num_paths);
  1515. spin_lock_irqsave(&bnad->bna_lock, flags);
  1516. bna_rx_destroy(rx_info->rx);
  1517. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1518. rx_info->rx = NULL;
  1519. bnad_rx_res_free(bnad, res_info);
  1520. }
  1521. /* Called with mutex_lock(&bnad->conf_mutex) held */
  1522. int
  1523. bnad_setup_rx(struct bnad *bnad, uint rx_id)
  1524. {
  1525. int err;
  1526. struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id];
  1527. struct bna_res_info *res_info = &bnad->rx_res_info[rx_id].res_info[0];
  1528. struct bna_intr_info *intr_info =
  1529. &res_info[BNA_RX_RES_T_INTR].res_u.intr_info;
  1530. struct bna_rx_config *rx_config = &bnad->rx_config[rx_id];
  1531. struct bna_rx_event_cbfn rx_cbfn;
  1532. struct bna_rx *rx;
  1533. unsigned long flags;
  1534. /* Initialize the Rx object configuration */
  1535. bnad_init_rx_config(bnad, rx_config);
  1536. /* Initialize the Rx event handlers */
  1537. rx_cbfn.rcb_setup_cbfn = bnad_cb_rcb_setup;
  1538. rx_cbfn.rcb_destroy_cbfn = bnad_cb_rcb_destroy;
  1539. rx_cbfn.ccb_setup_cbfn = bnad_cb_ccb_setup;
  1540. rx_cbfn.ccb_destroy_cbfn = bnad_cb_ccb_destroy;
  1541. rx_cbfn.rx_cleanup_cbfn = bnad_cb_rx_cleanup;
  1542. rx_cbfn.rx_post_cbfn = bnad_cb_rx_post;
  1543. /* Get BNA's resource requirement for one Rx object */
  1544. spin_lock_irqsave(&bnad->bna_lock, flags);
  1545. bna_rx_res_req(rx_config, res_info);
  1546. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1547. /* Fill Unmap Q memory requirements */
  1548. BNAD_FILL_UNMAPQ_MEM_REQ(
  1549. &res_info[BNA_RX_RES_MEM_T_UNMAPQ],
  1550. rx_config->num_paths +
  1551. ((rx_config->rxp_type == BNA_RXP_SINGLE) ? 0 :
  1552. rx_config->num_paths), BNAD_RX_UNMAPQ_DEPTH);
  1553. /* Allocate resource */
  1554. err = bnad_rx_res_alloc(bnad, res_info, rx_id);
  1555. if (err)
  1556. return err;
  1557. /* Ask BNA to create one Rx object, supplying required resources */
  1558. spin_lock_irqsave(&bnad->bna_lock, flags);
  1559. rx = bna_rx_create(&bnad->bna, bnad, rx_config, &rx_cbfn, res_info,
  1560. rx_info);
  1561. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1562. if (!rx)
  1563. goto err_return;
  1564. rx_info->rx = rx;
  1565. /* Register ISR for the Rx object */
  1566. if (intr_info->intr_type == BNA_INTR_T_MSIX) {
  1567. err = bnad_rx_msix_register(bnad, rx_info, rx_id,
  1568. rx_config->num_paths);
  1569. if (err)
  1570. goto err_return;
  1571. }
  1572. /* Enable NAPI */
  1573. bnad_napi_enable(bnad, rx_id);
  1574. spin_lock_irqsave(&bnad->bna_lock, flags);
  1575. if (0 == rx_id) {
  1576. /* Set up Dynamic Interrupt Moderation Vector */
  1577. if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED)
  1578. bna_rx_dim_reconfig(&bnad->bna, bna_napi_dim_vector);
  1579. /* Enable VLAN filtering only on the default Rx */
  1580. bna_rx_vlanfilter_enable(rx);
  1581. /* Start the DIM timer */
  1582. bnad_dim_timer_start(bnad);
  1583. }
  1584. bna_rx_enable(rx);
  1585. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1586. return 0;
  1587. err_return:
  1588. bnad_cleanup_rx(bnad, rx_id);
  1589. return err;
  1590. }
  1591. /* Called with conf_lock & bnad->bna_lock held */
  1592. void
  1593. bnad_tx_coalescing_timeo_set(struct bnad *bnad)
  1594. {
  1595. struct bnad_tx_info *tx_info;
  1596. tx_info = &bnad->tx_info[0];
  1597. if (!tx_info->tx)
  1598. return;
  1599. bna_tx_coalescing_timeo_set(tx_info->tx, bnad->tx_coalescing_timeo);
  1600. }
  1601. /* Called with conf_lock & bnad->bna_lock held */
  1602. void
  1603. bnad_rx_coalescing_timeo_set(struct bnad *bnad)
  1604. {
  1605. struct bnad_rx_info *rx_info;
  1606. int i;
  1607. for (i = 0; i < bnad->num_rx; i++) {
  1608. rx_info = &bnad->rx_info[i];
  1609. if (!rx_info->rx)
  1610. continue;
  1611. bna_rx_coalescing_timeo_set(rx_info->rx,
  1612. bnad->rx_coalescing_timeo);
  1613. }
  1614. }
  1615. /*
  1616. * Called with bnad->bna_lock held
  1617. */
  1618. static int
  1619. bnad_mac_addr_set_locked(struct bnad *bnad, u8 *mac_addr)
  1620. {
  1621. int ret;
  1622. if (!is_valid_ether_addr(mac_addr))
  1623. return -EADDRNOTAVAIL;
  1624. /* If datapath is down, pretend everything went through */
  1625. if (!bnad->rx_info[0].rx)
  1626. return 0;
  1627. ret = bna_rx_ucast_set(bnad->rx_info[0].rx, mac_addr, NULL);
  1628. if (ret != BNA_CB_SUCCESS)
  1629. return -EADDRNOTAVAIL;
  1630. return 0;
  1631. }
  1632. /* Should be called with conf_lock held */
  1633. static int
  1634. bnad_enable_default_bcast(struct bnad *bnad)
  1635. {
  1636. struct bnad_rx_info *rx_info = &bnad->rx_info[0];
  1637. int ret;
  1638. unsigned long flags;
  1639. init_completion(&bnad->bnad_completions.mcast_comp);
  1640. spin_lock_irqsave(&bnad->bna_lock, flags);
  1641. ret = bna_rx_mcast_add(rx_info->rx, (u8 *)bnad_bcast_addr,
  1642. bnad_cb_rx_mcast_add);
  1643. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1644. if (ret == BNA_CB_SUCCESS)
  1645. wait_for_completion(&bnad->bnad_completions.mcast_comp);
  1646. else
  1647. return -ENODEV;
  1648. if (bnad->bnad_completions.mcast_comp_status != BNA_CB_SUCCESS)
  1649. return -ENODEV;
  1650. return 0;
  1651. }
  1652. /* Called with bnad_conf_lock() held */
  1653. static void
  1654. bnad_restore_vlans(struct bnad *bnad, u32 rx_id)
  1655. {
  1656. u16 vlan_id;
  1657. unsigned long flags;
  1658. if (!bnad->vlan_grp)
  1659. return;
  1660. BUG_ON(!(VLAN_N_VID == (BFI_MAX_VLAN + 1)));
  1661. for (vlan_id = 0; vlan_id < VLAN_N_VID; vlan_id++) {
  1662. if (!vlan_group_get_device(bnad->vlan_grp, vlan_id))
  1663. continue;
  1664. spin_lock_irqsave(&bnad->bna_lock, flags);
  1665. bna_rx_vlan_add(bnad->rx_info[rx_id].rx, vlan_id);
  1666. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1667. }
  1668. }
  1669. /* Statistics utilities */
  1670. void
  1671. bnad_netdev_qstats_fill(struct bnad *bnad, struct rtnl_link_stats64 *stats)
  1672. {
  1673. int i, j;
  1674. for (i = 0; i < bnad->num_rx; i++) {
  1675. for (j = 0; j < bnad->num_rxp_per_rx; j++) {
  1676. if (bnad->rx_info[i].rx_ctrl[j].ccb) {
  1677. stats->rx_packets += bnad->rx_info[i].
  1678. rx_ctrl[j].ccb->rcb[0]->rxq->rx_packets;
  1679. stats->rx_bytes += bnad->rx_info[i].
  1680. rx_ctrl[j].ccb->rcb[0]->rxq->rx_bytes;
  1681. if (bnad->rx_info[i].rx_ctrl[j].ccb->rcb[1] &&
  1682. bnad->rx_info[i].rx_ctrl[j].ccb->
  1683. rcb[1]->rxq) {
  1684. stats->rx_packets +=
  1685. bnad->rx_info[i].rx_ctrl[j].
  1686. ccb->rcb[1]->rxq->rx_packets;
  1687. stats->rx_bytes +=
  1688. bnad->rx_info[i].rx_ctrl[j].
  1689. ccb->rcb[1]->rxq->rx_bytes;
  1690. }
  1691. }
  1692. }
  1693. }
  1694. for (i = 0; i < bnad->num_tx; i++) {
  1695. for (j = 0; j < bnad->num_txq_per_tx; j++) {
  1696. if (bnad->tx_info[i].tcb[j]) {
  1697. stats->tx_packets +=
  1698. bnad->tx_info[i].tcb[j]->txq->tx_packets;
  1699. stats->tx_bytes +=
  1700. bnad->tx_info[i].tcb[j]->txq->tx_bytes;
  1701. }
  1702. }
  1703. }
  1704. }
  1705. /*
  1706. * Must be called with the bna_lock held.
  1707. */
  1708. void
  1709. bnad_netdev_hwstats_fill(struct bnad *bnad, struct rtnl_link_stats64 *stats)
  1710. {
  1711. struct bfi_ll_stats_mac *mac_stats;
  1712. u64 bmap;
  1713. int i;
  1714. mac_stats = &bnad->stats.bna_stats->hw_stats->mac_stats;
  1715. stats->rx_errors =
  1716. mac_stats->rx_fcs_error + mac_stats->rx_alignment_error +
  1717. mac_stats->rx_frame_length_error + mac_stats->rx_code_error +
  1718. mac_stats->rx_undersize;
  1719. stats->tx_errors = mac_stats->tx_fcs_error +
  1720. mac_stats->tx_undersize;
  1721. stats->rx_dropped = mac_stats->rx_drop;
  1722. stats->tx_dropped = mac_stats->tx_drop;
  1723. stats->multicast = mac_stats->rx_multicast;
  1724. stats->collisions = mac_stats->tx_total_collision;
  1725. stats->rx_length_errors = mac_stats->rx_frame_length_error;
  1726. /* receive ring buffer overflow ?? */
  1727. stats->rx_crc_errors = mac_stats->rx_fcs_error;
  1728. stats->rx_frame_errors = mac_stats->rx_alignment_error;
  1729. /* recv'r fifo overrun */
  1730. bmap = (u64)bnad->stats.bna_stats->rxf_bmap[0] |
  1731. ((u64)bnad->stats.bna_stats->rxf_bmap[1] << 32);
  1732. for (i = 0; bmap && (i < BFI_LL_RXF_ID_MAX); i++) {
  1733. if (bmap & 1) {
  1734. stats->rx_fifo_errors +=
  1735. bnad->stats.bna_stats->
  1736. hw_stats->rxf_stats[i].frame_drops;
  1737. break;
  1738. }
  1739. bmap >>= 1;
  1740. }
  1741. }
  1742. static void
  1743. bnad_mbox_irq_sync(struct bnad *bnad)
  1744. {
  1745. u32 irq;
  1746. unsigned long flags;
  1747. spin_lock_irqsave(&bnad->bna_lock, flags);
  1748. if (bnad->cfg_flags & BNAD_CF_MSIX)
  1749. irq = bnad->msix_table[bnad->msix_num - 1].vector;
  1750. else
  1751. irq = bnad->pcidev->irq;
  1752. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1753. synchronize_irq(irq);
  1754. }
  1755. /* Utility used by bnad_start_xmit, for doing TSO */
  1756. static int
  1757. bnad_tso_prepare(struct bnad *bnad, struct sk_buff *skb)
  1758. {
  1759. int err;
  1760. /* SKB_GSO_TCPV4 and SKB_GSO_TCPV6 is defined since 2.6.18. */
  1761. BUG_ON(!(skb_shinfo(skb)->gso_type == SKB_GSO_TCPV4 ||
  1762. skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6));
  1763. if (skb_header_cloned(skb)) {
  1764. err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
  1765. if (err) {
  1766. BNAD_UPDATE_CTR(bnad, tso_err);
  1767. return err;
  1768. }
  1769. }
  1770. /*
  1771. * For TSO, the TCP checksum field is seeded with pseudo-header sum
  1772. * excluding the length field.
  1773. */
  1774. if (skb->protocol == htons(ETH_P_IP)) {
  1775. struct iphdr *iph = ip_hdr(skb);
  1776. /* Do we really need these? */
  1777. iph->tot_len = 0;
  1778. iph->check = 0;
  1779. tcp_hdr(skb)->check =
  1780. ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
  1781. IPPROTO_TCP, 0);
  1782. BNAD_UPDATE_CTR(bnad, tso4);
  1783. } else {
  1784. struct ipv6hdr *ipv6h = ipv6_hdr(skb);
  1785. BUG_ON(!(skb->protocol == htons(ETH_P_IPV6)));
  1786. ipv6h->payload_len = 0;
  1787. tcp_hdr(skb)->check =
  1788. ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr, 0,
  1789. IPPROTO_TCP, 0);
  1790. BNAD_UPDATE_CTR(bnad, tso6);
  1791. }
  1792. return 0;
  1793. }
  1794. /*
  1795. * Initialize Q numbers depending on Rx Paths
  1796. * Called with bnad->bna_lock held, because of cfg_flags
  1797. * access.
  1798. */
  1799. static void
  1800. bnad_q_num_init(struct bnad *bnad)
  1801. {
  1802. int rxps;
  1803. rxps = min((uint)num_online_cpus(),
  1804. (uint)(BNAD_MAX_RXS * BNAD_MAX_RXPS_PER_RX));
  1805. if (!(bnad->cfg_flags & BNAD_CF_MSIX))
  1806. rxps = 1; /* INTx */
  1807. bnad->num_rx = 1;
  1808. bnad->num_tx = 1;
  1809. bnad->num_rxp_per_rx = rxps;
  1810. bnad->num_txq_per_tx = BNAD_TXQ_NUM;
  1811. }
  1812. /*
  1813. * Adjusts the Q numbers, given a number of msix vectors
  1814. * Give preference to RSS as opposed to Tx priority Queues,
  1815. * in such a case, just use 1 Tx Q
  1816. * Called with bnad->bna_lock held b'cos of cfg_flags access
  1817. */
  1818. static void
  1819. bnad_q_num_adjust(struct bnad *bnad, int msix_vectors)
  1820. {
  1821. bnad->num_txq_per_tx = 1;
  1822. if ((msix_vectors >= (bnad->num_tx * bnad->num_txq_per_tx) +
  1823. bnad_rxqs_per_cq + BNAD_MAILBOX_MSIX_VECTORS) &&
  1824. (bnad->cfg_flags & BNAD_CF_MSIX)) {
  1825. bnad->num_rxp_per_rx = msix_vectors -
  1826. (bnad->num_tx * bnad->num_txq_per_tx) -
  1827. BNAD_MAILBOX_MSIX_VECTORS;
  1828. } else
  1829. bnad->num_rxp_per_rx = 1;
  1830. }
  1831. /* Enable / disable device */
  1832. static void
  1833. bnad_device_disable(struct bnad *bnad)
  1834. {
  1835. unsigned long flags;
  1836. init_completion(&bnad->bnad_completions.ioc_comp);
  1837. spin_lock_irqsave(&bnad->bna_lock, flags);
  1838. bna_device_disable(&bnad->bna.device, BNA_HARD_CLEANUP);
  1839. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1840. wait_for_completion(&bnad->bnad_completions.ioc_comp);
  1841. }
  1842. static int
  1843. bnad_device_enable(struct bnad *bnad)
  1844. {
  1845. int err = 0;
  1846. unsigned long flags;
  1847. init_completion(&bnad->bnad_completions.ioc_comp);
  1848. spin_lock_irqsave(&bnad->bna_lock, flags);
  1849. bna_device_enable(&bnad->bna.device);
  1850. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1851. wait_for_completion(&bnad->bnad_completions.ioc_comp);
  1852. if (bnad->bnad_completions.ioc_comp_status)
  1853. err = bnad->bnad_completions.ioc_comp_status;
  1854. return err;
  1855. }
  1856. /* Free BNA resources */
  1857. static void
  1858. bnad_res_free(struct bnad *bnad)
  1859. {
  1860. int i;
  1861. struct bna_res_info *res_info = &bnad->res_info[0];
  1862. for (i = 0; i < BNA_RES_T_MAX; i++) {
  1863. if (res_info[i].res_type == BNA_RES_T_MEM)
  1864. bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
  1865. else
  1866. bnad_mbox_irq_free(bnad, &res_info[i].res_u.intr_info);
  1867. }
  1868. }
  1869. /* Allocates memory and interrupt resources for BNA */
  1870. static int
  1871. bnad_res_alloc(struct bnad *bnad)
  1872. {
  1873. int i, err;
  1874. struct bna_res_info *res_info = &bnad->res_info[0];
  1875. for (i = 0; i < BNA_RES_T_MAX; i++) {
  1876. if (res_info[i].res_type == BNA_RES_T_MEM)
  1877. err = bnad_mem_alloc(bnad, &res_info[i].res_u.mem_info);
  1878. else
  1879. err = bnad_mbox_irq_alloc(bnad,
  1880. &res_info[i].res_u.intr_info);
  1881. if (err)
  1882. goto err_return;
  1883. }
  1884. return 0;
  1885. err_return:
  1886. bnad_res_free(bnad);
  1887. return err;
  1888. }
  1889. /* Interrupt enable / disable */
  1890. static void
  1891. bnad_enable_msix(struct bnad *bnad)
  1892. {
  1893. int i, ret;
  1894. unsigned long flags;
  1895. spin_lock_irqsave(&bnad->bna_lock, flags);
  1896. if (!(bnad->cfg_flags & BNAD_CF_MSIX)) {
  1897. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1898. return;
  1899. }
  1900. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1901. if (bnad->msix_table)
  1902. return;
  1903. bnad->msix_table =
  1904. kcalloc(bnad->msix_num, sizeof(struct msix_entry), GFP_KERNEL);
  1905. if (!bnad->msix_table)
  1906. goto intx_mode;
  1907. for (i = 0; i < bnad->msix_num; i++)
  1908. bnad->msix_table[i].entry = i;
  1909. ret = pci_enable_msix(bnad->pcidev, bnad->msix_table, bnad->msix_num);
  1910. if (ret > 0) {
  1911. /* Not enough MSI-X vectors. */
  1912. spin_lock_irqsave(&bnad->bna_lock, flags);
  1913. /* ret = #of vectors that we got */
  1914. bnad_q_num_adjust(bnad, ret);
  1915. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1916. bnad->msix_num = (bnad->num_tx * bnad->num_txq_per_tx)
  1917. + (bnad->num_rx
  1918. * bnad->num_rxp_per_rx) +
  1919. BNAD_MAILBOX_MSIX_VECTORS;
  1920. /* Try once more with adjusted numbers */
  1921. /* If this fails, fall back to INTx */
  1922. ret = pci_enable_msix(bnad->pcidev, bnad->msix_table,
  1923. bnad->msix_num);
  1924. if (ret)
  1925. goto intx_mode;
  1926. } else if (ret < 0)
  1927. goto intx_mode;
  1928. return;
  1929. intx_mode:
  1930. kfree(bnad->msix_table);
  1931. bnad->msix_table = NULL;
  1932. bnad->msix_num = 0;
  1933. spin_lock_irqsave(&bnad->bna_lock, flags);
  1934. bnad->cfg_flags &= ~BNAD_CF_MSIX;
  1935. bnad_q_num_init(bnad);
  1936. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1937. }
  1938. static void
  1939. bnad_disable_msix(struct bnad *bnad)
  1940. {
  1941. u32 cfg_flags;
  1942. unsigned long flags;
  1943. spin_lock_irqsave(&bnad->bna_lock, flags);
  1944. cfg_flags = bnad->cfg_flags;
  1945. if (bnad->cfg_flags & BNAD_CF_MSIX)
  1946. bnad->cfg_flags &= ~BNAD_CF_MSIX;
  1947. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1948. if (cfg_flags & BNAD_CF_MSIX) {
  1949. pci_disable_msix(bnad->pcidev);
  1950. kfree(bnad->msix_table);
  1951. bnad->msix_table = NULL;
  1952. }
  1953. }
  1954. /* Netdev entry points */
  1955. static int
  1956. bnad_open(struct net_device *netdev)
  1957. {
  1958. int err;
  1959. struct bnad *bnad = netdev_priv(netdev);
  1960. struct bna_pause_config pause_config;
  1961. int mtu;
  1962. unsigned long flags;
  1963. mutex_lock(&bnad->conf_mutex);
  1964. /* Tx */
  1965. err = bnad_setup_tx(bnad, 0);
  1966. if (err)
  1967. goto err_return;
  1968. /* Rx */
  1969. err = bnad_setup_rx(bnad, 0);
  1970. if (err)
  1971. goto cleanup_tx;
  1972. /* Port */
  1973. pause_config.tx_pause = 0;
  1974. pause_config.rx_pause = 0;
  1975. mtu = ETH_HLEN + bnad->netdev->mtu + ETH_FCS_LEN;
  1976. spin_lock_irqsave(&bnad->bna_lock, flags);
  1977. bna_port_mtu_set(&bnad->bna.port, mtu, NULL);
  1978. bna_port_pause_config(&bnad->bna.port, &pause_config, NULL);
  1979. bna_port_enable(&bnad->bna.port);
  1980. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1981. /* Enable broadcast */
  1982. bnad_enable_default_bcast(bnad);
  1983. /* Restore VLANs, if any */
  1984. bnad_restore_vlans(bnad, 0);
  1985. /* Set the UCAST address */
  1986. spin_lock_irqsave(&bnad->bna_lock, flags);
  1987. bnad_mac_addr_set_locked(bnad, netdev->dev_addr);
  1988. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  1989. /* Start the stats timer */
  1990. bnad_stats_timer_start(bnad);
  1991. mutex_unlock(&bnad->conf_mutex);
  1992. return 0;
  1993. cleanup_tx:
  1994. bnad_cleanup_tx(bnad, 0);
  1995. err_return:
  1996. mutex_unlock(&bnad->conf_mutex);
  1997. return err;
  1998. }
  1999. static int
  2000. bnad_stop(struct net_device *netdev)
  2001. {
  2002. struct bnad *bnad = netdev_priv(netdev);
  2003. unsigned long flags;
  2004. mutex_lock(&bnad->conf_mutex);
  2005. /* Stop the stats timer */
  2006. bnad_stats_timer_stop(bnad);
  2007. init_completion(&bnad->bnad_completions.port_comp);
  2008. spin_lock_irqsave(&bnad->bna_lock, flags);
  2009. bna_port_disable(&bnad->bna.port, BNA_HARD_CLEANUP,
  2010. bnad_cb_port_disabled);
  2011. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  2012. wait_for_completion(&bnad->bnad_completions.port_comp);
  2013. bnad_cleanup_tx(bnad, 0);
  2014. bnad_cleanup_rx(bnad, 0);
  2015. /* Synchronize mailbox IRQ */
  2016. bnad_mbox_irq_sync(bnad);
  2017. mutex_unlock(&bnad->conf_mutex);
  2018. return 0;
  2019. }
  2020. /* TX */
  2021. /*
  2022. * bnad_start_xmit : Netdev entry point for Transmit
  2023. * Called under lock held by net_device
  2024. */
  2025. static netdev_tx_t
  2026. bnad_start_xmit(struct sk_buff *skb, struct net_device *netdev)
  2027. {
  2028. struct bnad *bnad = netdev_priv(netdev);
  2029. u16 txq_prod, vlan_tag = 0;
  2030. u32 unmap_prod, wis, wis_used, wi_range;
  2031. u32 vectors, vect_id, i, acked;
  2032. u32 tx_id;
  2033. int err;
  2034. struct bnad_tx_info *tx_info;
  2035. struct bna_tcb *tcb;
  2036. struct bnad_unmap_q *unmap_q;
  2037. dma_addr_t dma_addr;
  2038. struct bna_txq_entry *txqent;
  2039. bna_txq_wi_ctrl_flag_t flags;
  2040. if (unlikely
  2041. (skb->len <= ETH_HLEN || skb->len > BFI_TX_MAX_DATA_PER_PKT)) {
  2042. dev_kfree_skb(skb);
  2043. return NETDEV_TX_OK;
  2044. }
  2045. tx_id = 0;
  2046. tx_info = &bnad->tx_info[tx_id];
  2047. tcb = tx_info->tcb[tx_id];
  2048. unmap_q = tcb->unmap_q;
  2049. /*
  2050. * Takes care of the Tx that is scheduled between clearing the flag
  2051. * and the netif_stop_queue() call.
  2052. */
  2053. if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))) {
  2054. dev_kfree_skb(skb);
  2055. return NETDEV_TX_OK;
  2056. }
  2057. vectors = 1 + skb_shinfo(skb)->nr_frags;
  2058. if (vectors > BFI_TX_MAX_VECTORS_PER_PKT) {
  2059. dev_kfree_skb(skb);
  2060. return NETDEV_TX_OK;
  2061. }
  2062. wis = BNA_TXQ_WI_NEEDED(vectors); /* 4 vectors per work item */
  2063. acked = 0;
  2064. if (unlikely
  2065. (wis > BNA_QE_FREE_CNT(tcb, tcb->q_depth) ||
  2066. vectors > BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth))) {
  2067. if ((u16) (*tcb->hw_consumer_index) !=
  2068. tcb->consumer_index &&
  2069. !test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags)) {
  2070. acked = bnad_free_txbufs(bnad, tcb);
  2071. if (likely(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)))
  2072. bna_ib_ack(tcb->i_dbell, acked);
  2073. smp_mb__before_clear_bit();
  2074. clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
  2075. } else {
  2076. netif_stop_queue(netdev);
  2077. BNAD_UPDATE_CTR(bnad, netif_queue_stop);
  2078. }
  2079. smp_mb();
  2080. /*
  2081. * Check again to deal with race condition between
  2082. * netif_stop_queue here, and netif_wake_queue in
  2083. * interrupt handler which is not inside netif tx lock.
  2084. */
  2085. if (likely
  2086. (wis > BNA_QE_FREE_CNT(tcb, tcb->q_depth) ||
  2087. vectors > BNA_QE_FREE_CNT(unmap_q, unmap_q->q_depth))) {
  2088. BNAD_UPDATE_CTR(bnad, netif_queue_stop);
  2089. return NETDEV_TX_BUSY;
  2090. } else {
  2091. netif_wake_queue(netdev);
  2092. BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
  2093. }
  2094. }
  2095. unmap_prod = unmap_q->producer_index;
  2096. wis_used = 1;
  2097. vect_id = 0;
  2098. flags = 0;
  2099. txq_prod = tcb->producer_index;
  2100. BNA_TXQ_QPGE_PTR_GET(txq_prod, tcb->sw_qpt, txqent, wi_range);
  2101. BUG_ON(!(wi_range <= tcb->q_depth));
  2102. txqent->hdr.wi.reserved = 0;
  2103. txqent->hdr.wi.num_vectors = vectors;
  2104. txqent->hdr.wi.opcode =
  2105. htons((skb_is_gso(skb) ? BNA_TXQ_WI_SEND_LSO :
  2106. BNA_TXQ_WI_SEND));
  2107. if (vlan_tx_tag_present(skb)) {
  2108. vlan_tag = (u16) vlan_tx_tag_get(skb);
  2109. flags |= (BNA_TXQ_WI_CF_INS_PRIO | BNA_TXQ_WI_CF_INS_VLAN);
  2110. }
  2111. if (test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags)) {
  2112. vlan_tag =
  2113. (tcb->priority & 0x7) << 13 | (vlan_tag & 0x1fff);
  2114. flags |= (BNA_TXQ_WI_CF_INS_PRIO | BNA_TXQ_WI_CF_INS_VLAN);
  2115. }
  2116. txqent->hdr.wi.vlan_tag = htons(vlan_tag);
  2117. if (skb_is_gso(skb)) {
  2118. err = bnad_tso_prepare(bnad, skb);
  2119. if (err) {
  2120. dev_kfree_skb(skb);
  2121. return NETDEV_TX_OK;
  2122. }
  2123. txqent->hdr.wi.lso_mss = htons(skb_is_gso(skb));
  2124. flags |= (BNA_TXQ_WI_CF_IP_CKSUM | BNA_TXQ_WI_CF_TCP_CKSUM);
  2125. txqent->hdr.wi.l4_hdr_size_n_offset =
  2126. htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
  2127. (tcp_hdrlen(skb) >> 2,
  2128. skb_transport_offset(skb)));
  2129. } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
  2130. u8 proto = 0;
  2131. txqent->hdr.wi.lso_mss = 0;
  2132. if (skb->protocol == htons(ETH_P_IP))
  2133. proto = ip_hdr(skb)->protocol;
  2134. else if (skb->protocol == htons(ETH_P_IPV6)) {
  2135. /* nexthdr may not be TCP immediately. */
  2136. proto = ipv6_hdr(skb)->nexthdr;
  2137. }
  2138. if (proto == IPPROTO_TCP) {
  2139. flags |= BNA_TXQ_WI_CF_TCP_CKSUM;
  2140. txqent->hdr.wi.l4_hdr_size_n_offset =
  2141. htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
  2142. (0, skb_transport_offset(skb)));
  2143. BNAD_UPDATE_CTR(bnad, tcpcsum_offload);
  2144. BUG_ON(!(skb_headlen(skb) >=
  2145. skb_transport_offset(skb) + tcp_hdrlen(skb)));
  2146. } else if (proto == IPPROTO_UDP) {
  2147. flags |= BNA_TXQ_WI_CF_UDP_CKSUM;
  2148. txqent->hdr.wi.l4_hdr_size_n_offset =
  2149. htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
  2150. (0, skb_transport_offset(skb)));
  2151. BNAD_UPDATE_CTR(bnad, udpcsum_offload);
  2152. BUG_ON(!(skb_headlen(skb) >=
  2153. skb_transport_offset(skb) +
  2154. sizeof(struct udphdr)));
  2155. } else {
  2156. err = skb_checksum_help(skb);
  2157. BNAD_UPDATE_CTR(bnad, csum_help);
  2158. if (err) {
  2159. dev_kfree_skb(skb);
  2160. BNAD_UPDATE_CTR(bnad, csum_help_err);
  2161. return NETDEV_TX_OK;
  2162. }
  2163. }
  2164. } else {
  2165. txqent->hdr.wi.lso_mss = 0;
  2166. txqent->hdr.wi.l4_hdr_size_n_offset = 0;
  2167. }
  2168. txqent->hdr.wi.flags = htons(flags);
  2169. txqent->hdr.wi.frame_length = htonl(skb->len);
  2170. unmap_q->unmap_array[unmap_prod].skb = skb;
  2171. BUG_ON(!(skb_headlen(skb) <= BFI_TX_MAX_DATA_PER_VECTOR));
  2172. txqent->vector[vect_id].length = htons(skb_headlen(skb));
  2173. dma_addr = dma_map_single(&bnad->pcidev->dev, skb->data,
  2174. skb_headlen(skb), DMA_TO_DEVICE);
  2175. dma_unmap_addr_set(&unmap_q->unmap_array[unmap_prod], dma_addr,
  2176. dma_addr);
  2177. BNA_SET_DMA_ADDR(dma_addr, &txqent->vector[vect_id].host_addr);
  2178. BNA_QE_INDX_ADD(unmap_prod, 1, unmap_q->q_depth);
  2179. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  2180. struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
  2181. u32 size = frag->size;
  2182. if (++vect_id == BFI_TX_MAX_VECTORS_PER_WI) {
  2183. vect_id = 0;
  2184. if (--wi_range)
  2185. txqent++;
  2186. else {
  2187. BNA_QE_INDX_ADD(txq_prod, wis_used,
  2188. tcb->q_depth);
  2189. wis_used = 0;
  2190. BNA_TXQ_QPGE_PTR_GET(txq_prod, tcb->sw_qpt,
  2191. txqent, wi_range);
  2192. BUG_ON(!(wi_range <= tcb->q_depth));
  2193. }
  2194. wis_used++;
  2195. txqent->hdr.wi_ext.opcode = htons(BNA_TXQ_WI_EXTENSION);
  2196. }
  2197. BUG_ON(!(size <= BFI_TX_MAX_DATA_PER_VECTOR));
  2198. txqent->vector[vect_id].length = htons(size);
  2199. dma_addr = dma_map_page(&bnad->pcidev->dev, frag->page,
  2200. frag->page_offset, size, DMA_TO_DEVICE);
  2201. dma_unmap_addr_set(&unmap_q->unmap_array[unmap_prod], dma_addr,
  2202. dma_addr);
  2203. BNA_SET_DMA_ADDR(dma_addr, &txqent->vector[vect_id].host_addr);
  2204. BNA_QE_INDX_ADD(unmap_prod, 1, unmap_q->q_depth);
  2205. }
  2206. unmap_q->producer_index = unmap_prod;
  2207. BNA_QE_INDX_ADD(txq_prod, wis_used, tcb->q_depth);
  2208. tcb->producer_index = txq_prod;
  2209. smp_mb();
  2210. if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)))
  2211. return NETDEV_TX_OK;
  2212. bna_txq_prod_indx_doorbell(tcb);
  2213. if ((u16) (*tcb->hw_consumer_index) != tcb->consumer_index)
  2214. tasklet_schedule(&bnad->tx_free_tasklet);
  2215. return NETDEV_TX_OK;
  2216. }
  2217. /*
  2218. * Used spin_lock to synchronize reading of stats structures, which
  2219. * is written by BNA under the same lock.
  2220. */
  2221. static struct rtnl_link_stats64 *
  2222. bnad_get_stats64(struct net_device *netdev, struct rtnl_link_stats64 *stats)
  2223. {
  2224. struct bnad *bnad = netdev_priv(netdev);
  2225. unsigned long flags;
  2226. spin_lock_irqsave(&bnad->bna_lock, flags);
  2227. bnad_netdev_qstats_fill(bnad, stats);
  2228. bnad_netdev_hwstats_fill(bnad, stats);
  2229. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  2230. return stats;
  2231. }
  2232. static void
  2233. bnad_set_rx_mode(struct net_device *netdev)
  2234. {
  2235. struct bnad *bnad = netdev_priv(netdev);
  2236. u32 new_mask, valid_mask;
  2237. unsigned long flags;
  2238. spin_lock_irqsave(&bnad->bna_lock, flags);
  2239. new_mask = valid_mask = 0;
  2240. if (netdev->flags & IFF_PROMISC) {
  2241. if (!(bnad->cfg_flags & BNAD_CF_PROMISC)) {
  2242. new_mask = BNAD_RXMODE_PROMISC_DEFAULT;
  2243. valid_mask = BNAD_RXMODE_PROMISC_DEFAULT;
  2244. bnad->cfg_flags |= BNAD_CF_PROMISC;
  2245. }
  2246. } else {
  2247. if (bnad->cfg_flags & BNAD_CF_PROMISC) {
  2248. new_mask = ~BNAD_RXMODE_PROMISC_DEFAULT;
  2249. valid_mask = BNAD_RXMODE_PROMISC_DEFAULT;
  2250. bnad->cfg_flags &= ~BNAD_CF_PROMISC;
  2251. }
  2252. }
  2253. if (netdev->flags & IFF_ALLMULTI) {
  2254. if (!(bnad->cfg_flags & BNAD_CF_ALLMULTI)) {
  2255. new_mask |= BNA_RXMODE_ALLMULTI;
  2256. valid_mask |= BNA_RXMODE_ALLMULTI;
  2257. bnad->cfg_flags |= BNAD_CF_ALLMULTI;
  2258. }
  2259. } else {
  2260. if (bnad->cfg_flags & BNAD_CF_ALLMULTI) {
  2261. new_mask &= ~BNA_RXMODE_ALLMULTI;
  2262. valid_mask |= BNA_RXMODE_ALLMULTI;
  2263. bnad->cfg_flags &= ~BNAD_CF_ALLMULTI;
  2264. }
  2265. }
  2266. bna_rx_mode_set(bnad->rx_info[0].rx, new_mask, valid_mask, NULL);
  2267. if (!netdev_mc_empty(netdev)) {
  2268. u8 *mcaddr_list;
  2269. int mc_count = netdev_mc_count(netdev);
  2270. /* Index 0 holds the broadcast address */
  2271. mcaddr_list =
  2272. kzalloc((mc_count + 1) * ETH_ALEN,
  2273. GFP_ATOMIC);
  2274. if (!mcaddr_list)
  2275. goto unlock;
  2276. memcpy(&mcaddr_list[0], &bnad_bcast_addr[0], ETH_ALEN);
  2277. /* Copy rest of the MC addresses */
  2278. bnad_netdev_mc_list_get(netdev, mcaddr_list);
  2279. bna_rx_mcast_listset(bnad->rx_info[0].rx, mc_count + 1,
  2280. mcaddr_list, NULL);
  2281. /* Should we enable BNAD_CF_ALLMULTI for err != 0 ? */
  2282. kfree(mcaddr_list);
  2283. }
  2284. unlock:
  2285. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  2286. }
  2287. /*
  2288. * bna_lock is used to sync writes to netdev->addr
  2289. * conf_lock cannot be used since this call may be made
  2290. * in a non-blocking context.
  2291. */
  2292. static int
  2293. bnad_set_mac_address(struct net_device *netdev, void *mac_addr)
  2294. {
  2295. int err;
  2296. struct bnad *bnad = netdev_priv(netdev);
  2297. struct sockaddr *sa = (struct sockaddr *)mac_addr;
  2298. unsigned long flags;
  2299. spin_lock_irqsave(&bnad->bna_lock, flags);
  2300. err = bnad_mac_addr_set_locked(bnad, sa->sa_data);
  2301. if (!err)
  2302. memcpy(netdev->dev_addr, sa->sa_data, netdev->addr_len);
  2303. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  2304. return err;
  2305. }
  2306. static int
  2307. bnad_change_mtu(struct net_device *netdev, int new_mtu)
  2308. {
  2309. int mtu, err = 0;
  2310. unsigned long flags;
  2311. struct bnad *bnad = netdev_priv(netdev);
  2312. if (new_mtu + ETH_HLEN < ETH_ZLEN || new_mtu > BNAD_JUMBO_MTU)
  2313. return -EINVAL;
  2314. mutex_lock(&bnad->conf_mutex);
  2315. netdev->mtu = new_mtu;
  2316. mtu = ETH_HLEN + new_mtu + ETH_FCS_LEN;
  2317. spin_lock_irqsave(&bnad->bna_lock, flags);
  2318. bna_port_mtu_set(&bnad->bna.port, mtu, NULL);
  2319. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  2320. mutex_unlock(&bnad->conf_mutex);
  2321. return err;
  2322. }
  2323. static void
  2324. bnad_vlan_rx_register(struct net_device *netdev,
  2325. struct vlan_group *vlan_grp)
  2326. {
  2327. struct bnad *bnad = netdev_priv(netdev);
  2328. mutex_lock(&bnad->conf_mutex);
  2329. bnad->vlan_grp = vlan_grp;
  2330. mutex_unlock(&bnad->conf_mutex);
  2331. }
  2332. static void
  2333. bnad_vlan_rx_add_vid(struct net_device *netdev,
  2334. unsigned short vid)
  2335. {
  2336. struct bnad *bnad = netdev_priv(netdev);
  2337. unsigned long flags;
  2338. if (!bnad->rx_info[0].rx)
  2339. return;
  2340. mutex_lock(&bnad->conf_mutex);
  2341. spin_lock_irqsave(&bnad->bna_lock, flags);
  2342. bna_rx_vlan_add(bnad->rx_info[0].rx, vid);
  2343. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  2344. mutex_unlock(&bnad->conf_mutex);
  2345. }
  2346. static void
  2347. bnad_vlan_rx_kill_vid(struct net_device *netdev,
  2348. unsigned short vid)
  2349. {
  2350. struct bnad *bnad = netdev_priv(netdev);
  2351. unsigned long flags;
  2352. if (!bnad->rx_info[0].rx)
  2353. return;
  2354. mutex_lock(&bnad->conf_mutex);
  2355. spin_lock_irqsave(&bnad->bna_lock, flags);
  2356. bna_rx_vlan_del(bnad->rx_info[0].rx, vid);
  2357. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  2358. mutex_unlock(&bnad->conf_mutex);
  2359. }
  2360. #ifdef CONFIG_NET_POLL_CONTROLLER
  2361. static void
  2362. bnad_netpoll(struct net_device *netdev)
  2363. {
  2364. struct bnad *bnad = netdev_priv(netdev);
  2365. struct bnad_rx_info *rx_info;
  2366. struct bnad_rx_ctrl *rx_ctrl;
  2367. u32 curr_mask;
  2368. int i, j;
  2369. if (!(bnad->cfg_flags & BNAD_CF_MSIX)) {
  2370. bna_intx_disable(&bnad->bna, curr_mask);
  2371. bnad_isr(bnad->pcidev->irq, netdev);
  2372. bna_intx_enable(&bnad->bna, curr_mask);
  2373. } else {
  2374. for (i = 0; i < bnad->num_rx; i++) {
  2375. rx_info = &bnad->rx_info[i];
  2376. if (!rx_info->rx)
  2377. continue;
  2378. for (j = 0; j < bnad->num_rxp_per_rx; j++) {
  2379. rx_ctrl = &rx_info->rx_ctrl[j];
  2380. if (rx_ctrl->ccb) {
  2381. bnad_disable_rx_irq(bnad,
  2382. rx_ctrl->ccb);
  2383. bnad_netif_rx_schedule_poll(bnad,
  2384. rx_ctrl->ccb);
  2385. }
  2386. }
  2387. }
  2388. }
  2389. }
  2390. #endif
  2391. static const struct net_device_ops bnad_netdev_ops = {
  2392. .ndo_open = bnad_open,
  2393. .ndo_stop = bnad_stop,
  2394. .ndo_start_xmit = bnad_start_xmit,
  2395. .ndo_get_stats64 = bnad_get_stats64,
  2396. .ndo_set_rx_mode = bnad_set_rx_mode,
  2397. .ndo_set_multicast_list = bnad_set_rx_mode,
  2398. .ndo_validate_addr = eth_validate_addr,
  2399. .ndo_set_mac_address = bnad_set_mac_address,
  2400. .ndo_change_mtu = bnad_change_mtu,
  2401. .ndo_vlan_rx_register = bnad_vlan_rx_register,
  2402. .ndo_vlan_rx_add_vid = bnad_vlan_rx_add_vid,
  2403. .ndo_vlan_rx_kill_vid = bnad_vlan_rx_kill_vid,
  2404. #ifdef CONFIG_NET_POLL_CONTROLLER
  2405. .ndo_poll_controller = bnad_netpoll
  2406. #endif
  2407. };
  2408. static void
  2409. bnad_netdev_init(struct bnad *bnad, bool using_dac)
  2410. {
  2411. struct net_device *netdev = bnad->netdev;
  2412. netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM |
  2413. NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
  2414. NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_HW_VLAN_TX;
  2415. netdev->vlan_features = NETIF_F_SG | NETIF_F_HIGHDMA |
  2416. NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
  2417. NETIF_F_TSO | NETIF_F_TSO6;
  2418. netdev->features |= netdev->hw_features |
  2419. NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER;
  2420. if (using_dac)
  2421. netdev->features |= NETIF_F_HIGHDMA;
  2422. netdev->mem_start = bnad->mmio_start;
  2423. netdev->mem_end = bnad->mmio_start + bnad->mmio_len - 1;
  2424. netdev->netdev_ops = &bnad_netdev_ops;
  2425. bnad_set_ethtool_ops(netdev);
  2426. }
  2427. /*
  2428. * 1. Initialize the bnad structure
  2429. * 2. Setup netdev pointer in pci_dev
  2430. * 3. Initialze Tx free tasklet
  2431. * 4. Initialize no. of TxQ & CQs & MSIX vectors
  2432. */
  2433. static int
  2434. bnad_init(struct bnad *bnad,
  2435. struct pci_dev *pdev, struct net_device *netdev)
  2436. {
  2437. unsigned long flags;
  2438. SET_NETDEV_DEV(netdev, &pdev->dev);
  2439. pci_set_drvdata(pdev, netdev);
  2440. bnad->netdev = netdev;
  2441. bnad->pcidev = pdev;
  2442. bnad->mmio_start = pci_resource_start(pdev, 0);
  2443. bnad->mmio_len = pci_resource_len(pdev, 0);
  2444. bnad->bar0 = ioremap_nocache(bnad->mmio_start, bnad->mmio_len);
  2445. if (!bnad->bar0) {
  2446. dev_err(&pdev->dev, "ioremap for bar0 failed\n");
  2447. pci_set_drvdata(pdev, NULL);
  2448. return -ENOMEM;
  2449. }
  2450. pr_info("bar0 mapped to %p, len %llu\n", bnad->bar0,
  2451. (unsigned long long) bnad->mmio_len);
  2452. spin_lock_irqsave(&bnad->bna_lock, flags);
  2453. if (!bnad_msix_disable)
  2454. bnad->cfg_flags = BNAD_CF_MSIX;
  2455. bnad->cfg_flags |= BNAD_CF_DIM_ENABLED;
  2456. bnad_q_num_init(bnad);
  2457. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  2458. bnad->msix_num = (bnad->num_tx * bnad->num_txq_per_tx) +
  2459. (bnad->num_rx * bnad->num_rxp_per_rx) +
  2460. BNAD_MAILBOX_MSIX_VECTORS;
  2461. bnad->txq_depth = BNAD_TXQ_DEPTH;
  2462. bnad->rxq_depth = BNAD_RXQ_DEPTH;
  2463. bnad->tx_coalescing_timeo = BFI_TX_COALESCING_TIMEO;
  2464. bnad->rx_coalescing_timeo = BFI_RX_COALESCING_TIMEO;
  2465. tasklet_init(&bnad->tx_free_tasklet, bnad_tx_free_tasklet,
  2466. (unsigned long)bnad);
  2467. return 0;
  2468. }
  2469. /*
  2470. * Must be called after bnad_pci_uninit()
  2471. * so that iounmap() and pci_set_drvdata(NULL)
  2472. * happens only after PCI uninitialization.
  2473. */
  2474. static void
  2475. bnad_uninit(struct bnad *bnad)
  2476. {
  2477. if (bnad->bar0)
  2478. iounmap(bnad->bar0);
  2479. pci_set_drvdata(bnad->pcidev, NULL);
  2480. }
  2481. /*
  2482. * Initialize locks
  2483. a) Per device mutes used for serializing configuration
  2484. changes from OS interface
  2485. b) spin lock used to protect bna state machine
  2486. */
  2487. static void
  2488. bnad_lock_init(struct bnad *bnad)
  2489. {
  2490. spin_lock_init(&bnad->bna_lock);
  2491. mutex_init(&bnad->conf_mutex);
  2492. }
  2493. static void
  2494. bnad_lock_uninit(struct bnad *bnad)
  2495. {
  2496. mutex_destroy(&bnad->conf_mutex);
  2497. }
  2498. /* PCI Initialization */
  2499. static int
  2500. bnad_pci_init(struct bnad *bnad,
  2501. struct pci_dev *pdev, bool *using_dac)
  2502. {
  2503. int err;
  2504. err = pci_enable_device(pdev);
  2505. if (err)
  2506. return err;
  2507. err = pci_request_regions(pdev, BNAD_NAME);
  2508. if (err)
  2509. goto disable_device;
  2510. if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
  2511. !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
  2512. *using_dac = 1;
  2513. } else {
  2514. err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
  2515. if (err) {
  2516. err = dma_set_coherent_mask(&pdev->dev,
  2517. DMA_BIT_MASK(32));
  2518. if (err)
  2519. goto release_regions;
  2520. }
  2521. *using_dac = 0;
  2522. }
  2523. pci_set_master(pdev);
  2524. return 0;
  2525. release_regions:
  2526. pci_release_regions(pdev);
  2527. disable_device:
  2528. pci_disable_device(pdev);
  2529. return err;
  2530. }
  2531. static void
  2532. bnad_pci_uninit(struct pci_dev *pdev)
  2533. {
  2534. pci_release_regions(pdev);
  2535. pci_disable_device(pdev);
  2536. }
  2537. static int __devinit
  2538. bnad_pci_probe(struct pci_dev *pdev,
  2539. const struct pci_device_id *pcidev_id)
  2540. {
  2541. bool using_dac = false;
  2542. int err;
  2543. struct bnad *bnad;
  2544. struct bna *bna;
  2545. struct net_device *netdev;
  2546. struct bfa_pcidev pcidev_info;
  2547. unsigned long flags;
  2548. pr_info("bnad_pci_probe : (0x%p, 0x%p) PCI Func : (%d)\n",
  2549. pdev, pcidev_id, PCI_FUNC(pdev->devfn));
  2550. mutex_lock(&bnad_fwimg_mutex);
  2551. if (!cna_get_firmware_buf(pdev)) {
  2552. mutex_unlock(&bnad_fwimg_mutex);
  2553. pr_warn("Failed to load Firmware Image!\n");
  2554. return -ENODEV;
  2555. }
  2556. mutex_unlock(&bnad_fwimg_mutex);
  2557. /*
  2558. * Allocates sizeof(struct net_device + struct bnad)
  2559. * bnad = netdev->priv
  2560. */
  2561. netdev = alloc_etherdev(sizeof(struct bnad));
  2562. if (!netdev) {
  2563. dev_err(&pdev->dev, "alloc_etherdev failed\n");
  2564. err = -ENOMEM;
  2565. return err;
  2566. }
  2567. bnad = netdev_priv(netdev);
  2568. /*
  2569. * PCI initialization
  2570. * Output : using_dac = 1 for 64 bit DMA
  2571. * = 0 for 32 bit DMA
  2572. */
  2573. err = bnad_pci_init(bnad, pdev, &using_dac);
  2574. if (err)
  2575. goto free_netdev;
  2576. bnad_lock_init(bnad);
  2577. /*
  2578. * Initialize bnad structure
  2579. * Setup relation between pci_dev & netdev
  2580. * Init Tx free tasklet
  2581. */
  2582. err = bnad_init(bnad, pdev, netdev);
  2583. if (err)
  2584. goto pci_uninit;
  2585. /* Initialize netdev structure, set up ethtool ops */
  2586. bnad_netdev_init(bnad, using_dac);
  2587. /* Set link to down state */
  2588. netif_carrier_off(netdev);
  2589. bnad_enable_msix(bnad);
  2590. /* Get resource requirement form bna */
  2591. bna_res_req(&bnad->res_info[0]);
  2592. /* Allocate resources from bna */
  2593. err = bnad_res_alloc(bnad);
  2594. if (err)
  2595. goto free_netdev;
  2596. bna = &bnad->bna;
  2597. /* Setup pcidev_info for bna_init() */
  2598. pcidev_info.pci_slot = PCI_SLOT(bnad->pcidev->devfn);
  2599. pcidev_info.pci_func = PCI_FUNC(bnad->pcidev->devfn);
  2600. pcidev_info.device_id = bnad->pcidev->device;
  2601. pcidev_info.pci_bar_kva = bnad->bar0;
  2602. mutex_lock(&bnad->conf_mutex);
  2603. spin_lock_irqsave(&bnad->bna_lock, flags);
  2604. bna_init(bna, bnad, &pcidev_info, &bnad->res_info[0]);
  2605. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  2606. bnad->stats.bna_stats = &bna->stats;
  2607. /* Set up timers */
  2608. setup_timer(&bnad->bna.device.ioc.ioc_timer, bnad_ioc_timeout,
  2609. ((unsigned long)bnad));
  2610. setup_timer(&bnad->bna.device.ioc.hb_timer, bnad_ioc_hb_check,
  2611. ((unsigned long)bnad));
  2612. setup_timer(&bnad->bna.device.ioc.iocpf_timer, bnad_iocpf_timeout,
  2613. ((unsigned long)bnad));
  2614. setup_timer(&bnad->bna.device.ioc.sem_timer, bnad_iocpf_sem_timeout,
  2615. ((unsigned long)bnad));
  2616. /* Now start the timer before calling IOC */
  2617. mod_timer(&bnad->bna.device.ioc.iocpf_timer,
  2618. jiffies + msecs_to_jiffies(BNA_IOC_TIMER_FREQ));
  2619. /*
  2620. * Start the chip
  2621. * Don't care even if err != 0, bna state machine will
  2622. * deal with it
  2623. */
  2624. err = bnad_device_enable(bnad);
  2625. /* Get the burnt-in mac */
  2626. spin_lock_irqsave(&bnad->bna_lock, flags);
  2627. bna_port_mac_get(&bna->port, &bnad->perm_addr);
  2628. bnad_set_netdev_perm_addr(bnad);
  2629. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  2630. mutex_unlock(&bnad->conf_mutex);
  2631. /* Finally, reguister with net_device layer */
  2632. err = register_netdev(netdev);
  2633. if (err) {
  2634. pr_err("BNA : Registering with netdev failed\n");
  2635. goto disable_device;
  2636. }
  2637. return 0;
  2638. disable_device:
  2639. mutex_lock(&bnad->conf_mutex);
  2640. bnad_device_disable(bnad);
  2641. del_timer_sync(&bnad->bna.device.ioc.ioc_timer);
  2642. del_timer_sync(&bnad->bna.device.ioc.sem_timer);
  2643. del_timer_sync(&bnad->bna.device.ioc.hb_timer);
  2644. spin_lock_irqsave(&bnad->bna_lock, flags);
  2645. bna_uninit(bna);
  2646. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  2647. mutex_unlock(&bnad->conf_mutex);
  2648. bnad_res_free(bnad);
  2649. bnad_disable_msix(bnad);
  2650. pci_uninit:
  2651. bnad_pci_uninit(pdev);
  2652. bnad_lock_uninit(bnad);
  2653. bnad_uninit(bnad);
  2654. free_netdev:
  2655. free_netdev(netdev);
  2656. return err;
  2657. }
  2658. static void __devexit
  2659. bnad_pci_remove(struct pci_dev *pdev)
  2660. {
  2661. struct net_device *netdev = pci_get_drvdata(pdev);
  2662. struct bnad *bnad;
  2663. struct bna *bna;
  2664. unsigned long flags;
  2665. if (!netdev)
  2666. return;
  2667. pr_info("%s bnad_pci_remove\n", netdev->name);
  2668. bnad = netdev_priv(netdev);
  2669. bna = &bnad->bna;
  2670. unregister_netdev(netdev);
  2671. mutex_lock(&bnad->conf_mutex);
  2672. bnad_device_disable(bnad);
  2673. del_timer_sync(&bnad->bna.device.ioc.ioc_timer);
  2674. del_timer_sync(&bnad->bna.device.ioc.sem_timer);
  2675. del_timer_sync(&bnad->bna.device.ioc.hb_timer);
  2676. spin_lock_irqsave(&bnad->bna_lock, flags);
  2677. bna_uninit(bna);
  2678. spin_unlock_irqrestore(&bnad->bna_lock, flags);
  2679. mutex_unlock(&bnad->conf_mutex);
  2680. bnad_res_free(bnad);
  2681. bnad_disable_msix(bnad);
  2682. bnad_pci_uninit(pdev);
  2683. bnad_lock_uninit(bnad);
  2684. bnad_uninit(bnad);
  2685. free_netdev(netdev);
  2686. }
  2687. static const struct pci_device_id bnad_pci_id_table[] = {
  2688. {
  2689. PCI_DEVICE(PCI_VENDOR_ID_BROCADE,
  2690. PCI_DEVICE_ID_BROCADE_CT),
  2691. .class = PCI_CLASS_NETWORK_ETHERNET << 8,
  2692. .class_mask = 0xffff00
  2693. }, {0, }
  2694. };
  2695. MODULE_DEVICE_TABLE(pci, bnad_pci_id_table);
  2696. static struct pci_driver bnad_pci_driver = {
  2697. .name = BNAD_NAME,
  2698. .id_table = bnad_pci_id_table,
  2699. .probe = bnad_pci_probe,
  2700. .remove = __devexit_p(bnad_pci_remove),
  2701. };
  2702. static int __init
  2703. bnad_module_init(void)
  2704. {
  2705. int err;
  2706. pr_info("Brocade 10G Ethernet driver\n");
  2707. bfa_nw_ioc_auto_recover(bnad_ioc_auto_recover);
  2708. err = pci_register_driver(&bnad_pci_driver);
  2709. if (err < 0) {
  2710. pr_err("bna : PCI registration failed in module init "
  2711. "(%d)\n", err);
  2712. return err;
  2713. }
  2714. return 0;
  2715. }
  2716. static void __exit
  2717. bnad_module_exit(void)
  2718. {
  2719. pci_unregister_driver(&bnad_pci_driver);
  2720. if (bfi_fw)
  2721. release_firmware(bfi_fw);
  2722. }
  2723. module_init(bnad_module_init);
  2724. module_exit(bnad_module_exit);
  2725. MODULE_AUTHOR("Brocade");
  2726. MODULE_LICENSE("GPL");
  2727. MODULE_DESCRIPTION("Brocade 10G PCIe Ethernet driver");
  2728. MODULE_VERSION(BNAD_VERSION);
  2729. MODULE_FIRMWARE(CNA_FW_FILE_CT);