adg.c 4.7 KB

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  1. /*
  2. * Helper routines for R-Car sound ADG.
  3. *
  4. * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file "COPYING" in the main directory of this archive
  8. * for more details.
  9. */
  10. #include <linux/sh_clk.h>
  11. #include "rsnd.h"
  12. #define CLKA 0
  13. #define CLKB 1
  14. #define CLKC 2
  15. #define CLKI 3
  16. #define CLKMAX 4
  17. struct rsnd_adg {
  18. struct clk *clk[CLKMAX];
  19. int rate_of_441khz_div_6;
  20. int rate_of_48khz_div_6;
  21. u32 ckr;
  22. };
  23. #define for_each_rsnd_clk(pos, adg, i) \
  24. for (i = 0, (pos) = adg->clk[i]; \
  25. i < CLKMAX; \
  26. i++, (pos) = adg->clk[i])
  27. #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
  28. static enum rsnd_reg rsnd_adg_ssi_reg_get(int id)
  29. {
  30. enum rsnd_reg reg;
  31. /*
  32. * SSI 8 is not connected to ADG.
  33. * it works with SSI 7
  34. */
  35. if (id == 8)
  36. return RSND_REG_MAX;
  37. if (0 <= id && id <= 3)
  38. reg = RSND_REG_AUDIO_CLK_SEL0;
  39. else if (4 <= id && id <= 7)
  40. reg = RSND_REG_AUDIO_CLK_SEL1;
  41. else
  42. reg = RSND_REG_AUDIO_CLK_SEL2;
  43. return reg;
  44. }
  45. int rsnd_adg_ssi_clk_stop(struct rsnd_mod *mod)
  46. {
  47. struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
  48. enum rsnd_reg reg;
  49. int id;
  50. /*
  51. * "mod" = "ssi" here.
  52. * we can get "ssi id" from mod
  53. */
  54. id = rsnd_mod_id(mod);
  55. reg = rsnd_adg_ssi_reg_get(id);
  56. rsnd_write(priv, mod, reg, 0);
  57. return 0;
  58. }
  59. int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *mod, unsigned int rate)
  60. {
  61. struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
  62. struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
  63. struct device *dev = rsnd_priv_to_dev(priv);
  64. struct clk *clk;
  65. enum rsnd_reg reg;
  66. int id, shift, i;
  67. u32 data;
  68. int sel_table[] = {
  69. [CLKA] = 0x1,
  70. [CLKB] = 0x2,
  71. [CLKC] = 0x3,
  72. [CLKI] = 0x0,
  73. };
  74. dev_dbg(dev, "request clock = %d\n", rate);
  75. /*
  76. * find suitable clock from
  77. * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
  78. */
  79. data = 0;
  80. for_each_rsnd_clk(clk, adg, i) {
  81. if (rate == clk_get_rate(clk)) {
  82. data = sel_table[i];
  83. goto found_clock;
  84. }
  85. }
  86. /*
  87. * find 1/6 clock from BRGA/BRGB
  88. */
  89. if (rate == adg->rate_of_441khz_div_6) {
  90. data = 0x10;
  91. goto found_clock;
  92. }
  93. if (rate == adg->rate_of_48khz_div_6) {
  94. data = 0x20;
  95. goto found_clock;
  96. }
  97. return -EIO;
  98. found_clock:
  99. /* see rsnd_adg_ssi_clk_init() */
  100. rsnd_mod_bset(mod, SSICKR, 0x00FF0000, adg->ckr);
  101. rsnd_mod_write(mod, BRRA, 0x00000002); /* 1/6 */
  102. rsnd_mod_write(mod, BRRB, 0x00000002); /* 1/6 */
  103. /*
  104. * This "mod" = "ssi" here.
  105. * we can get "ssi id" from mod
  106. */
  107. id = rsnd_mod_id(mod);
  108. reg = rsnd_adg_ssi_reg_get(id);
  109. dev_dbg(dev, "ADG: ssi%d selects clk%d = %d", id, i, rate);
  110. /*
  111. * Enable SSIx clock
  112. */
  113. shift = (id % 4) * 8;
  114. rsnd_bset(priv, mod, reg,
  115. 0xFF << shift,
  116. data << shift);
  117. return 0;
  118. }
  119. static void rsnd_adg_ssi_clk_init(struct rsnd_priv *priv, struct rsnd_adg *adg)
  120. {
  121. struct clk *clk;
  122. unsigned long rate;
  123. u32 ckr;
  124. int i;
  125. int brg_table[] = {
  126. [CLKA] = 0x0,
  127. [CLKB] = 0x1,
  128. [CLKC] = 0x4,
  129. [CLKI] = 0x2,
  130. };
  131. /*
  132. * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
  133. * have 44.1kHz or 48kHz base clocks for now.
  134. *
  135. * SSI itself can divide parent clock by 1/1 - 1/16
  136. * So, BRGA outputs 44.1kHz base parent clock 1/32,
  137. * and, BRGB outputs 48.0kHz base parent clock 1/32 here.
  138. * see
  139. * rsnd_adg_ssi_clk_try_start()
  140. */
  141. ckr = 0;
  142. adg->rate_of_441khz_div_6 = 0;
  143. adg->rate_of_48khz_div_6 = 0;
  144. for_each_rsnd_clk(clk, adg, i) {
  145. rate = clk_get_rate(clk);
  146. if (0 == rate) /* not used */
  147. continue;
  148. /* RBGA */
  149. if (!adg->rate_of_441khz_div_6 && (0 == rate % 44100)) {
  150. adg->rate_of_441khz_div_6 = rate / 6;
  151. ckr |= brg_table[i] << 20;
  152. }
  153. /* RBGB */
  154. if (!adg->rate_of_48khz_div_6 && (0 == rate % 48000)) {
  155. adg->rate_of_48khz_div_6 = rate / 6;
  156. ckr |= brg_table[i] << 16;
  157. }
  158. }
  159. adg->ckr = ckr;
  160. }
  161. int rsnd_adg_probe(struct platform_device *pdev,
  162. struct rcar_snd_info *info,
  163. struct rsnd_priv *priv)
  164. {
  165. struct rsnd_adg *adg;
  166. struct device *dev = rsnd_priv_to_dev(priv);
  167. struct clk *clk;
  168. int i;
  169. adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL);
  170. if (!adg) {
  171. dev_err(dev, "ADG allocate failed\n");
  172. return -ENOMEM;
  173. }
  174. adg->clk[CLKA] = clk_get(NULL, "audio_clk_a");
  175. adg->clk[CLKB] = clk_get(NULL, "audio_clk_b");
  176. adg->clk[CLKC] = clk_get(NULL, "audio_clk_c");
  177. adg->clk[CLKI] = clk_get(NULL, "audio_clk_internal");
  178. for_each_rsnd_clk(clk, adg, i) {
  179. if (IS_ERR(clk)) {
  180. dev_err(dev, "Audio clock failed\n");
  181. return -EIO;
  182. }
  183. }
  184. rsnd_adg_ssi_clk_init(priv, adg);
  185. priv->adg = adg;
  186. dev_dbg(dev, "adg probed\n");
  187. return 0;
  188. }
  189. void rsnd_adg_remove(struct platform_device *pdev,
  190. struct rsnd_priv *priv)
  191. {
  192. struct rsnd_adg *adg = priv->adg;
  193. struct clk *clk;
  194. int i;
  195. for_each_rsnd_clk(clk, adg, i)
  196. clk_put(clk);
  197. }