uda1380.c 25 KB

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  1. /*
  2. * uda1380.c - Philips UDA1380 ALSA SoC audio driver
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. *
  8. * Copyright (c) 2007 Philipp Zabel <philipp.zabel@gmail.com>
  9. * Improved support for DAPM and audio routing/mixing capabilities,
  10. * added TLV support.
  11. *
  12. * Modified by Richard Purdie <richard@openedhand.com> to fit into SoC
  13. * codec model.
  14. *
  15. * Copyright (c) 2005 Giorgio Padrin <giorgio@mandarinlogiq.org>
  16. * Copyright 2005 Openedhand Ltd.
  17. */
  18. #include <linux/module.h>
  19. #include <linux/init.h>
  20. #include <linux/types.h>
  21. #include <linux/string.h>
  22. #include <linux/slab.h>
  23. #include <linux/errno.h>
  24. #include <linux/ioctl.h>
  25. #include <linux/delay.h>
  26. #include <linux/i2c.h>
  27. #include <linux/workqueue.h>
  28. #include <sound/core.h>
  29. #include <sound/control.h>
  30. #include <sound/initval.h>
  31. #include <sound/info.h>
  32. #include <sound/soc.h>
  33. #include <sound/soc-dapm.h>
  34. #include <sound/tlv.h>
  35. #include "uda1380.h"
  36. static struct work_struct uda1380_work;
  37. static struct snd_soc_codec *uda1380_codec;
  38. /*
  39. * uda1380 register cache
  40. */
  41. static const u16 uda1380_reg[UDA1380_CACHEREGNUM] = {
  42. 0x0502, 0x0000, 0x0000, 0x3f3f,
  43. 0x0202, 0x0000, 0x0000, 0x0000,
  44. 0x0000, 0x0000, 0x0000, 0x0000,
  45. 0x0000, 0x0000, 0x0000, 0x0000,
  46. 0x0000, 0xff00, 0x0000, 0x4800,
  47. 0x0000, 0x0000, 0x0000, 0x0000,
  48. 0x0000, 0x0000, 0x0000, 0x0000,
  49. 0x0000, 0x0000, 0x0000, 0x0000,
  50. 0x0000, 0x8000, 0x0002, 0x0000,
  51. };
  52. static unsigned long uda1380_cache_dirty;
  53. /*
  54. * read uda1380 register cache
  55. */
  56. static inline unsigned int uda1380_read_reg_cache(struct snd_soc_codec *codec,
  57. unsigned int reg)
  58. {
  59. u16 *cache = codec->reg_cache;
  60. if (reg == UDA1380_RESET)
  61. return 0;
  62. if (reg >= UDA1380_CACHEREGNUM)
  63. return -1;
  64. return cache[reg];
  65. }
  66. /*
  67. * write uda1380 register cache
  68. */
  69. static inline void uda1380_write_reg_cache(struct snd_soc_codec *codec,
  70. u16 reg, unsigned int value)
  71. {
  72. u16 *cache = codec->reg_cache;
  73. if (reg >= UDA1380_CACHEREGNUM)
  74. return;
  75. if ((reg >= 0x10) && (cache[reg] != value))
  76. set_bit(reg - 0x10, &uda1380_cache_dirty);
  77. cache[reg] = value;
  78. }
  79. /*
  80. * write to the UDA1380 register space
  81. */
  82. static int uda1380_write(struct snd_soc_codec *codec, unsigned int reg,
  83. unsigned int value)
  84. {
  85. u8 data[3];
  86. /* data is
  87. * data[0] is register offset
  88. * data[1] is MS byte
  89. * data[2] is LS byte
  90. */
  91. data[0] = reg;
  92. data[1] = (value & 0xff00) >> 8;
  93. data[2] = value & 0x00ff;
  94. uda1380_write_reg_cache(codec, reg, value);
  95. /* the interpolator & decimator regs must only be written when the
  96. * codec DAI is active.
  97. */
  98. if (!codec->active && (reg >= UDA1380_MVOL))
  99. return 0;
  100. pr_debug("uda1380: hw write %x val %x\n", reg, value);
  101. if (codec->hw_write(codec->control_data, data, 3) == 3) {
  102. unsigned int val;
  103. i2c_master_send(codec->control_data, data, 1);
  104. i2c_master_recv(codec->control_data, data, 2);
  105. val = (data[0]<<8) | data[1];
  106. if (val != value) {
  107. pr_debug("uda1380: READ BACK VAL %x\n",
  108. (data[0]<<8) | data[1]);
  109. return -EIO;
  110. }
  111. if (reg >= 0x10)
  112. clear_bit(reg - 0x10, &uda1380_cache_dirty);
  113. return 0;
  114. } else
  115. return -EIO;
  116. }
  117. #define uda1380_reset(c) uda1380_write(c, UDA1380_RESET, 0)
  118. static void uda1380_flush_work(struct work_struct *work)
  119. {
  120. int bit, reg;
  121. for_each_bit(bit, &uda1380_cache_dirty, UDA1380_CACHEREGNUM - 0x10) {
  122. reg = 0x10 + bit;
  123. pr_debug("uda1380: flush reg %x val %x:\n", reg,
  124. uda1380_read_reg_cache(uda1380_codec, reg));
  125. uda1380_write(uda1380_codec, reg,
  126. uda1380_read_reg_cache(uda1380_codec, reg));
  127. clear_bit(bit, &uda1380_cache_dirty);
  128. }
  129. }
  130. /* declarations of ALSA reg_elem_REAL controls */
  131. static const char *uda1380_deemp[] = {
  132. "None",
  133. "32kHz",
  134. "44.1kHz",
  135. "48kHz",
  136. "96kHz",
  137. };
  138. static const char *uda1380_input_sel[] = {
  139. "Line",
  140. "Mic + Line R",
  141. "Line L",
  142. "Mic",
  143. };
  144. static const char *uda1380_output_sel[] = {
  145. "DAC",
  146. "Analog Mixer",
  147. };
  148. static const char *uda1380_spf_mode[] = {
  149. "Flat",
  150. "Minimum1",
  151. "Minimum2",
  152. "Maximum"
  153. };
  154. static const char *uda1380_capture_sel[] = {
  155. "ADC",
  156. "Digital Mixer"
  157. };
  158. static const char *uda1380_sel_ns[] = {
  159. "3rd-order",
  160. "5th-order"
  161. };
  162. static const char *uda1380_mix_control[] = {
  163. "off",
  164. "PCM only",
  165. "before sound processing",
  166. "after sound processing"
  167. };
  168. static const char *uda1380_sdet_setting[] = {
  169. "3200",
  170. "4800",
  171. "9600",
  172. "19200"
  173. };
  174. static const char *uda1380_os_setting[] = {
  175. "single-speed",
  176. "double-speed (no mixing)",
  177. "quad-speed (no mixing)"
  178. };
  179. static const struct soc_enum uda1380_deemp_enum[] = {
  180. SOC_ENUM_SINGLE(UDA1380_DEEMP, 8, 5, uda1380_deemp),
  181. SOC_ENUM_SINGLE(UDA1380_DEEMP, 0, 5, uda1380_deemp),
  182. };
  183. static const struct soc_enum uda1380_input_sel_enum =
  184. SOC_ENUM_SINGLE(UDA1380_ADC, 2, 4, uda1380_input_sel); /* SEL_MIC, SEL_LNA */
  185. static const struct soc_enum uda1380_output_sel_enum =
  186. SOC_ENUM_SINGLE(UDA1380_PM, 7, 2, uda1380_output_sel); /* R02_EN_AVC */
  187. static const struct soc_enum uda1380_spf_enum =
  188. SOC_ENUM_SINGLE(UDA1380_MODE, 14, 4, uda1380_spf_mode); /* M */
  189. static const struct soc_enum uda1380_capture_sel_enum =
  190. SOC_ENUM_SINGLE(UDA1380_IFACE, 6, 2, uda1380_capture_sel); /* SEL_SOURCE */
  191. static const struct soc_enum uda1380_sel_ns_enum =
  192. SOC_ENUM_SINGLE(UDA1380_MIXER, 14, 2, uda1380_sel_ns); /* SEL_NS */
  193. static const struct soc_enum uda1380_mix_enum =
  194. SOC_ENUM_SINGLE(UDA1380_MIXER, 12, 4, uda1380_mix_control); /* MIX, MIX_POS */
  195. static const struct soc_enum uda1380_sdet_enum =
  196. SOC_ENUM_SINGLE(UDA1380_MIXER, 4, 4, uda1380_sdet_setting); /* SD_VALUE */
  197. static const struct soc_enum uda1380_os_enum =
  198. SOC_ENUM_SINGLE(UDA1380_MIXER, 0, 3, uda1380_os_setting); /* OS */
  199. /*
  200. * from -48 dB in 1.5 dB steps (mute instead of -49.5 dB)
  201. */
  202. static DECLARE_TLV_DB_SCALE(amix_tlv, -4950, 150, 1);
  203. /*
  204. * from -78 dB in 1 dB steps (3 dB steps, really. LSB are ignored),
  205. * from -66 dB in 0.5 dB steps (2 dB steps, really) and
  206. * from -52 dB in 0.25 dB steps
  207. */
  208. static const unsigned int mvol_tlv[] = {
  209. TLV_DB_RANGE_HEAD(3),
  210. 0, 15, TLV_DB_SCALE_ITEM(-8200, 100, 1),
  211. 16, 43, TLV_DB_SCALE_ITEM(-6600, 50, 0),
  212. 44, 252, TLV_DB_SCALE_ITEM(-5200, 25, 0),
  213. };
  214. /*
  215. * from -72 dB in 1.5 dB steps (6 dB steps really),
  216. * from -66 dB in 0.75 dB steps (3 dB steps really),
  217. * from -60 dB in 0.5 dB steps (2 dB steps really) and
  218. * from -46 dB in 0.25 dB steps
  219. */
  220. static const unsigned int vc_tlv[] = {
  221. TLV_DB_RANGE_HEAD(4),
  222. 0, 7, TLV_DB_SCALE_ITEM(-7800, 150, 1),
  223. 8, 15, TLV_DB_SCALE_ITEM(-6600, 75, 0),
  224. 16, 43, TLV_DB_SCALE_ITEM(-6000, 50, 0),
  225. 44, 228, TLV_DB_SCALE_ITEM(-4600, 25, 0),
  226. };
  227. /* from 0 to 6 dB in 2 dB steps if SPF mode != flat */
  228. static DECLARE_TLV_DB_SCALE(tr_tlv, 0, 200, 0);
  229. /* from 0 to 24 dB in 2 dB steps, if SPF mode == maximum, otherwise cuts
  230. * off at 18 dB max) */
  231. static DECLARE_TLV_DB_SCALE(bb_tlv, 0, 200, 0);
  232. /* from -63 to 24 dB in 0.5 dB steps (-128...48) */
  233. static DECLARE_TLV_DB_SCALE(dec_tlv, -6400, 50, 1);
  234. /* from 0 to 24 dB in 3 dB steps */
  235. static DECLARE_TLV_DB_SCALE(pga_tlv, 0, 300, 0);
  236. /* from 0 to 30 dB in 2 dB steps */
  237. static DECLARE_TLV_DB_SCALE(vga_tlv, 0, 200, 0);
  238. static const struct snd_kcontrol_new uda1380_snd_controls[] = {
  239. SOC_DOUBLE_TLV("Analog Mixer Volume", UDA1380_AMIX, 0, 8, 44, 1, amix_tlv), /* AVCR, AVCL */
  240. SOC_DOUBLE_TLV("Master Playback Volume", UDA1380_MVOL, 0, 8, 252, 1, mvol_tlv), /* MVCL, MVCR */
  241. SOC_SINGLE_TLV("ADC Playback Volume", UDA1380_MIXVOL, 8, 228, 1, vc_tlv), /* VC2 */
  242. SOC_SINGLE_TLV("PCM Playback Volume", UDA1380_MIXVOL, 0, 228, 1, vc_tlv), /* VC1 */
  243. SOC_ENUM("Sound Processing Filter", uda1380_spf_enum), /* M */
  244. SOC_DOUBLE_TLV("Tone Control - Treble", UDA1380_MODE, 4, 12, 3, 0, tr_tlv), /* TRL, TRR */
  245. SOC_DOUBLE_TLV("Tone Control - Bass", UDA1380_MODE, 0, 8, 15, 0, bb_tlv), /* BBL, BBR */
  246. /**/ SOC_SINGLE("Master Playback Switch", UDA1380_DEEMP, 14, 1, 1), /* MTM */
  247. SOC_SINGLE("ADC Playback Switch", UDA1380_DEEMP, 11, 1, 1), /* MT2 from decimation filter */
  248. SOC_ENUM("ADC Playback De-emphasis", uda1380_deemp_enum[0]), /* DE2 */
  249. SOC_SINGLE("PCM Playback Switch", UDA1380_DEEMP, 3, 1, 1), /* MT1, from digital data input */
  250. SOC_ENUM("PCM Playback De-emphasis", uda1380_deemp_enum[1]), /* DE1 */
  251. SOC_SINGLE("DAC Polarity inverting Switch", UDA1380_MIXER, 15, 1, 0), /* DA_POL_INV */
  252. SOC_ENUM("Noise Shaper", uda1380_sel_ns_enum), /* SEL_NS */
  253. SOC_ENUM("Digital Mixer Signal Control", uda1380_mix_enum), /* MIX_POS, MIX */
  254. SOC_SINGLE("Silence Detector Switch", UDA1380_MIXER, 6, 1, 0), /* SDET_ON */
  255. SOC_ENUM("Silence Detector Setting", uda1380_sdet_enum), /* SD_VALUE */
  256. SOC_ENUM("Oversampling Input", uda1380_os_enum), /* OS */
  257. SOC_DOUBLE_S8_TLV("ADC Capture Volume", UDA1380_DEC, -128, 48, dec_tlv), /* ML_DEC, MR_DEC */
  258. /**/ SOC_SINGLE("ADC Capture Switch", UDA1380_PGA, 15, 1, 1), /* MT_ADC */
  259. SOC_DOUBLE_TLV("Line Capture Volume", UDA1380_PGA, 0, 8, 8, 0, pga_tlv), /* PGA_GAINCTRLL, PGA_GAINCTRLR */
  260. SOC_SINGLE("ADC Polarity inverting Switch", UDA1380_ADC, 12, 1, 0), /* ADCPOL_INV */
  261. SOC_SINGLE_TLV("Mic Capture Volume", UDA1380_ADC, 8, 15, 0, vga_tlv), /* VGA_CTRL */
  262. SOC_SINGLE("DC Filter Bypass Switch", UDA1380_ADC, 1, 1, 0), /* SKIP_DCFIL (before decimator) */
  263. SOC_SINGLE("DC Filter Enable Switch", UDA1380_ADC, 0, 1, 0), /* EN_DCFIL (at output of decimator) */
  264. SOC_SINGLE("AGC Timing", UDA1380_AGC, 8, 7, 0), /* TODO: enum, see table 62 */
  265. SOC_SINGLE("AGC Target level", UDA1380_AGC, 2, 3, 1), /* AGC_LEVEL */
  266. /* -5.5, -8, -11.5, -14 dBFS */
  267. SOC_SINGLE("AGC Switch", UDA1380_AGC, 0, 1, 0),
  268. };
  269. /* Input mux */
  270. static const struct snd_kcontrol_new uda1380_input_mux_control =
  271. SOC_DAPM_ENUM("Route", uda1380_input_sel_enum);
  272. /* Output mux */
  273. static const struct snd_kcontrol_new uda1380_output_mux_control =
  274. SOC_DAPM_ENUM("Route", uda1380_output_sel_enum);
  275. /* Capture mux */
  276. static const struct snd_kcontrol_new uda1380_capture_mux_control =
  277. SOC_DAPM_ENUM("Route", uda1380_capture_sel_enum);
  278. static const struct snd_soc_dapm_widget uda1380_dapm_widgets[] = {
  279. SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM, 0, 0,
  280. &uda1380_input_mux_control),
  281. SND_SOC_DAPM_MUX("Output Mux", SND_SOC_NOPM, 0, 0,
  282. &uda1380_output_mux_control),
  283. SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0,
  284. &uda1380_capture_mux_control),
  285. SND_SOC_DAPM_PGA("Left PGA", UDA1380_PM, 3, 0, NULL, 0),
  286. SND_SOC_DAPM_PGA("Right PGA", UDA1380_PM, 1, 0, NULL, 0),
  287. SND_SOC_DAPM_PGA("Mic LNA", UDA1380_PM, 4, 0, NULL, 0),
  288. SND_SOC_DAPM_ADC("Left ADC", "Left Capture", UDA1380_PM, 2, 0),
  289. SND_SOC_DAPM_ADC("Right ADC", "Right Capture", UDA1380_PM, 0, 0),
  290. SND_SOC_DAPM_INPUT("VINM"),
  291. SND_SOC_DAPM_INPUT("VINL"),
  292. SND_SOC_DAPM_INPUT("VINR"),
  293. SND_SOC_DAPM_MIXER("Analog Mixer", UDA1380_PM, 6, 0, NULL, 0),
  294. SND_SOC_DAPM_OUTPUT("VOUTLHP"),
  295. SND_SOC_DAPM_OUTPUT("VOUTRHP"),
  296. SND_SOC_DAPM_OUTPUT("VOUTL"),
  297. SND_SOC_DAPM_OUTPUT("VOUTR"),
  298. SND_SOC_DAPM_DAC("DAC", "Playback", UDA1380_PM, 10, 0),
  299. SND_SOC_DAPM_PGA("HeadPhone Driver", UDA1380_PM, 13, 0, NULL, 0),
  300. };
  301. static const struct snd_soc_dapm_route audio_map[] = {
  302. /* output mux */
  303. {"HeadPhone Driver", NULL, "Output Mux"},
  304. {"VOUTR", NULL, "Output Mux"},
  305. {"VOUTL", NULL, "Output Mux"},
  306. {"Analog Mixer", NULL, "VINR"},
  307. {"Analog Mixer", NULL, "VINL"},
  308. {"Analog Mixer", NULL, "DAC"},
  309. {"Output Mux", "DAC", "DAC"},
  310. {"Output Mux", "Analog Mixer", "Analog Mixer"},
  311. /* {"DAC", "Digital Mixer", "I2S" } */
  312. /* headphone driver */
  313. {"VOUTLHP", NULL, "HeadPhone Driver"},
  314. {"VOUTRHP", NULL, "HeadPhone Driver"},
  315. /* input mux */
  316. {"Left ADC", NULL, "Input Mux"},
  317. {"Input Mux", "Mic", "Mic LNA"},
  318. {"Input Mux", "Mic + Line R", "Mic LNA"},
  319. {"Input Mux", "Line L", "Left PGA"},
  320. {"Input Mux", "Line", "Left PGA"},
  321. /* right input */
  322. {"Right ADC", "Mic + Line R", "Right PGA"},
  323. {"Right ADC", "Line", "Right PGA"},
  324. /* inputs */
  325. {"Mic LNA", NULL, "VINM"},
  326. {"Left PGA", NULL, "VINL"},
  327. {"Right PGA", NULL, "VINR"},
  328. };
  329. static int uda1380_add_widgets(struct snd_soc_codec *codec)
  330. {
  331. snd_soc_dapm_new_controls(codec, uda1380_dapm_widgets,
  332. ARRAY_SIZE(uda1380_dapm_widgets));
  333. snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
  334. snd_soc_dapm_new_widgets(codec);
  335. return 0;
  336. }
  337. static int uda1380_set_dai_fmt_both(struct snd_soc_dai *codec_dai,
  338. unsigned int fmt)
  339. {
  340. struct snd_soc_codec *codec = codec_dai->codec;
  341. int iface;
  342. /* set up DAI based upon fmt */
  343. iface = uda1380_read_reg_cache(codec, UDA1380_IFACE);
  344. iface &= ~(R01_SFORI_MASK | R01_SIM | R01_SFORO_MASK);
  345. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  346. case SND_SOC_DAIFMT_I2S:
  347. iface |= R01_SFORI_I2S | R01_SFORO_I2S;
  348. break;
  349. case SND_SOC_DAIFMT_LSB:
  350. iface |= R01_SFORI_LSB16 | R01_SFORO_LSB16;
  351. break;
  352. case SND_SOC_DAIFMT_MSB:
  353. iface |= R01_SFORI_MSB | R01_SFORO_MSB;
  354. }
  355. /* DATAI is slave only, so in single-link mode, this has to be slave */
  356. if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS)
  357. return -EINVAL;
  358. uda1380_write(codec, UDA1380_IFACE, iface);
  359. return 0;
  360. }
  361. static int uda1380_set_dai_fmt_playback(struct snd_soc_dai *codec_dai,
  362. unsigned int fmt)
  363. {
  364. struct snd_soc_codec *codec = codec_dai->codec;
  365. int iface;
  366. /* set up DAI based upon fmt */
  367. iface = uda1380_read_reg_cache(codec, UDA1380_IFACE);
  368. iface &= ~R01_SFORI_MASK;
  369. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  370. case SND_SOC_DAIFMT_I2S:
  371. iface |= R01_SFORI_I2S;
  372. break;
  373. case SND_SOC_DAIFMT_LSB:
  374. iface |= R01_SFORI_LSB16;
  375. break;
  376. case SND_SOC_DAIFMT_MSB:
  377. iface |= R01_SFORI_MSB;
  378. }
  379. /* DATAI is slave only, so this has to be slave */
  380. if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS)
  381. return -EINVAL;
  382. uda1380_write(codec, UDA1380_IFACE, iface);
  383. return 0;
  384. }
  385. static int uda1380_set_dai_fmt_capture(struct snd_soc_dai *codec_dai,
  386. unsigned int fmt)
  387. {
  388. struct snd_soc_codec *codec = codec_dai->codec;
  389. int iface;
  390. /* set up DAI based upon fmt */
  391. iface = uda1380_read_reg_cache(codec, UDA1380_IFACE);
  392. iface &= ~(R01_SIM | R01_SFORO_MASK);
  393. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  394. case SND_SOC_DAIFMT_I2S:
  395. iface |= R01_SFORO_I2S;
  396. break;
  397. case SND_SOC_DAIFMT_LSB:
  398. iface |= R01_SFORO_LSB16;
  399. break;
  400. case SND_SOC_DAIFMT_MSB:
  401. iface |= R01_SFORO_MSB;
  402. }
  403. if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) == SND_SOC_DAIFMT_CBM_CFM)
  404. iface |= R01_SIM;
  405. uda1380_write(codec, UDA1380_IFACE, iface);
  406. return 0;
  407. }
  408. static int uda1380_trigger(struct snd_pcm_substream *substream, int cmd,
  409. struct snd_soc_dai *dai)
  410. {
  411. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  412. struct snd_soc_device *socdev = rtd->socdev;
  413. struct snd_soc_codec *codec = socdev->card->codec;
  414. int mixer = uda1380_read_reg_cache(codec, UDA1380_MIXER);
  415. switch (cmd) {
  416. case SNDRV_PCM_TRIGGER_START:
  417. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  418. uda1380_write_reg_cache(codec, UDA1380_MIXER,
  419. mixer & ~R14_SILENCE);
  420. schedule_work(&uda1380_work);
  421. break;
  422. case SNDRV_PCM_TRIGGER_STOP:
  423. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  424. uda1380_write_reg_cache(codec, UDA1380_MIXER,
  425. mixer | R14_SILENCE);
  426. schedule_work(&uda1380_work);
  427. break;
  428. }
  429. return 0;
  430. }
  431. static int uda1380_pcm_hw_params(struct snd_pcm_substream *substream,
  432. struct snd_pcm_hw_params *params,
  433. struct snd_soc_dai *dai)
  434. {
  435. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  436. struct snd_soc_device *socdev = rtd->socdev;
  437. struct snd_soc_codec *codec = socdev->card->codec;
  438. u16 clk = uda1380_read_reg_cache(codec, UDA1380_CLK);
  439. /* set WSPLL power and divider if running from this clock */
  440. if (clk & R00_DAC_CLK) {
  441. int rate = params_rate(params);
  442. u16 pm = uda1380_read_reg_cache(codec, UDA1380_PM);
  443. clk &= ~0x3; /* clear SEL_LOOP_DIV */
  444. switch (rate) {
  445. case 6250 ... 12500:
  446. clk |= 0x0;
  447. break;
  448. case 12501 ... 25000:
  449. clk |= 0x1;
  450. break;
  451. case 25001 ... 50000:
  452. clk |= 0x2;
  453. break;
  454. case 50001 ... 100000:
  455. clk |= 0x3;
  456. break;
  457. }
  458. uda1380_write(codec, UDA1380_PM, R02_PON_PLL | pm);
  459. }
  460. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  461. clk |= R00_EN_DAC | R00_EN_INT;
  462. else
  463. clk |= R00_EN_ADC | R00_EN_DEC;
  464. uda1380_write(codec, UDA1380_CLK, clk);
  465. return 0;
  466. }
  467. static void uda1380_pcm_shutdown(struct snd_pcm_substream *substream,
  468. struct snd_soc_dai *dai)
  469. {
  470. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  471. struct snd_soc_device *socdev = rtd->socdev;
  472. struct snd_soc_codec *codec = socdev->card->codec;
  473. u16 clk = uda1380_read_reg_cache(codec, UDA1380_CLK);
  474. /* shut down WSPLL power if running from this clock */
  475. if (clk & R00_DAC_CLK) {
  476. u16 pm = uda1380_read_reg_cache(codec, UDA1380_PM);
  477. uda1380_write(codec, UDA1380_PM, ~R02_PON_PLL & pm);
  478. }
  479. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  480. clk &= ~(R00_EN_DAC | R00_EN_INT);
  481. else
  482. clk &= ~(R00_EN_ADC | R00_EN_DEC);
  483. uda1380_write(codec, UDA1380_CLK, clk);
  484. }
  485. static int uda1380_set_bias_level(struct snd_soc_codec *codec,
  486. enum snd_soc_bias_level level)
  487. {
  488. int pm = uda1380_read_reg_cache(codec, UDA1380_PM);
  489. switch (level) {
  490. case SND_SOC_BIAS_ON:
  491. case SND_SOC_BIAS_PREPARE:
  492. uda1380_write(codec, UDA1380_PM, R02_PON_BIAS | pm);
  493. break;
  494. case SND_SOC_BIAS_STANDBY:
  495. uda1380_write(codec, UDA1380_PM, R02_PON_BIAS);
  496. break;
  497. case SND_SOC_BIAS_OFF:
  498. uda1380_write(codec, UDA1380_PM, 0x0);
  499. break;
  500. }
  501. codec->bias_level = level;
  502. return 0;
  503. }
  504. #define UDA1380_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
  505. SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
  506. SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
  507. static struct snd_soc_dai_ops uda1380_dai_ops = {
  508. .hw_params = uda1380_pcm_hw_params,
  509. .shutdown = uda1380_pcm_shutdown,
  510. .trigger = uda1380_trigger,
  511. .set_fmt = uda1380_set_dai_fmt_both,
  512. };
  513. static struct snd_soc_dai_ops uda1380_dai_ops_playback = {
  514. .hw_params = uda1380_pcm_hw_params,
  515. .shutdown = uda1380_pcm_shutdown,
  516. .trigger = uda1380_trigger,
  517. .set_fmt = uda1380_set_dai_fmt_playback,
  518. };
  519. static struct snd_soc_dai_ops uda1380_dai_ops_capture = {
  520. .hw_params = uda1380_pcm_hw_params,
  521. .shutdown = uda1380_pcm_shutdown,
  522. .trigger = uda1380_trigger,
  523. .set_fmt = uda1380_set_dai_fmt_capture,
  524. };
  525. struct snd_soc_dai uda1380_dai[] = {
  526. {
  527. .name = "UDA1380",
  528. .playback = {
  529. .stream_name = "Playback",
  530. .channels_min = 1,
  531. .channels_max = 2,
  532. .rates = UDA1380_RATES,
  533. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  534. .capture = {
  535. .stream_name = "Capture",
  536. .channels_min = 1,
  537. .channels_max = 2,
  538. .rates = UDA1380_RATES,
  539. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  540. .ops = &uda1380_dai_ops,
  541. },
  542. { /* playback only - dual interface */
  543. .name = "UDA1380",
  544. .playback = {
  545. .stream_name = "Playback",
  546. .channels_min = 1,
  547. .channels_max = 2,
  548. .rates = UDA1380_RATES,
  549. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  550. },
  551. .ops = &uda1380_dai_ops_playback,
  552. },
  553. { /* capture only - dual interface*/
  554. .name = "UDA1380",
  555. .capture = {
  556. .stream_name = "Capture",
  557. .channels_min = 1,
  558. .channels_max = 2,
  559. .rates = UDA1380_RATES,
  560. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  561. },
  562. .ops = &uda1380_dai_ops_capture,
  563. },
  564. };
  565. EXPORT_SYMBOL_GPL(uda1380_dai);
  566. static int uda1380_suspend(struct platform_device *pdev, pm_message_t state)
  567. {
  568. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  569. struct snd_soc_codec *codec = socdev->card->codec;
  570. uda1380_set_bias_level(codec, SND_SOC_BIAS_OFF);
  571. return 0;
  572. }
  573. static int uda1380_resume(struct platform_device *pdev)
  574. {
  575. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  576. struct snd_soc_codec *codec = socdev->card->codec;
  577. int i;
  578. u8 data[2];
  579. u16 *cache = codec->reg_cache;
  580. /* Sync reg_cache with the hardware */
  581. for (i = 0; i < ARRAY_SIZE(uda1380_reg); i++) {
  582. data[0] = (i << 1) | ((cache[i] >> 8) & 0x0001);
  583. data[1] = cache[i] & 0x00ff;
  584. codec->hw_write(codec->control_data, data, 2);
  585. }
  586. uda1380_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  587. uda1380_set_bias_level(codec, codec->suspend_bias_level);
  588. return 0;
  589. }
  590. /*
  591. * initialise the UDA1380 driver
  592. * register mixer and dsp interfaces with the kernel
  593. */
  594. static int uda1380_init(struct snd_soc_device *socdev, int dac_clk)
  595. {
  596. struct snd_soc_codec *codec = socdev->card->codec;
  597. int ret = 0;
  598. codec->name = "UDA1380";
  599. codec->owner = THIS_MODULE;
  600. codec->read = uda1380_read_reg_cache;
  601. codec->write = uda1380_write;
  602. codec->set_bias_level = uda1380_set_bias_level;
  603. codec->dai = uda1380_dai;
  604. codec->num_dai = ARRAY_SIZE(uda1380_dai);
  605. codec->reg_cache = kmemdup(uda1380_reg, sizeof(uda1380_reg),
  606. GFP_KERNEL);
  607. if (codec->reg_cache == NULL)
  608. return -ENOMEM;
  609. codec->reg_cache_size = ARRAY_SIZE(uda1380_reg);
  610. codec->reg_cache_step = 1;
  611. uda1380_reset(codec);
  612. uda1380_codec = codec;
  613. INIT_WORK(&uda1380_work, uda1380_flush_work);
  614. /* register pcms */
  615. ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
  616. if (ret < 0) {
  617. pr_err("uda1380: failed to create pcms\n");
  618. goto pcm_err;
  619. }
  620. /* power on device */
  621. uda1380_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  622. /* set clock input */
  623. switch (dac_clk) {
  624. case UDA1380_DAC_CLK_SYSCLK:
  625. uda1380_write(codec, UDA1380_CLK, 0);
  626. break;
  627. case UDA1380_DAC_CLK_WSPLL:
  628. uda1380_write(codec, UDA1380_CLK, R00_DAC_CLK);
  629. break;
  630. }
  631. /* uda1380 init */
  632. snd_soc_add_controls(codec, uda1380_snd_controls,
  633. ARRAY_SIZE(uda1380_snd_controls));
  634. uda1380_add_widgets(codec);
  635. ret = snd_soc_init_card(socdev);
  636. if (ret < 0) {
  637. pr_err("uda1380: failed to register card\n");
  638. goto card_err;
  639. }
  640. return ret;
  641. card_err:
  642. snd_soc_free_pcms(socdev);
  643. snd_soc_dapm_free(socdev);
  644. pcm_err:
  645. kfree(codec->reg_cache);
  646. return ret;
  647. }
  648. static struct snd_soc_device *uda1380_socdev;
  649. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  650. static int uda1380_i2c_probe(struct i2c_client *i2c,
  651. const struct i2c_device_id *id)
  652. {
  653. struct snd_soc_device *socdev = uda1380_socdev;
  654. struct uda1380_setup_data *setup = socdev->codec_data;
  655. struct snd_soc_codec *codec = socdev->card->codec;
  656. int ret;
  657. i2c_set_clientdata(i2c, codec);
  658. codec->control_data = i2c;
  659. ret = uda1380_init(socdev, setup->dac_clk);
  660. if (ret < 0)
  661. pr_err("uda1380: failed to initialise UDA1380\n");
  662. return ret;
  663. }
  664. static int uda1380_i2c_remove(struct i2c_client *client)
  665. {
  666. struct snd_soc_codec *codec = i2c_get_clientdata(client);
  667. kfree(codec->reg_cache);
  668. return 0;
  669. }
  670. static const struct i2c_device_id uda1380_i2c_id[] = {
  671. { "uda1380", 0 },
  672. { }
  673. };
  674. MODULE_DEVICE_TABLE(i2c, uda1380_i2c_id);
  675. static struct i2c_driver uda1380_i2c_driver = {
  676. .driver = {
  677. .name = "UDA1380 I2C Codec",
  678. .owner = THIS_MODULE,
  679. },
  680. .probe = uda1380_i2c_probe,
  681. .remove = uda1380_i2c_remove,
  682. .id_table = uda1380_i2c_id,
  683. };
  684. static int uda1380_add_i2c_device(struct platform_device *pdev,
  685. const struct uda1380_setup_data *setup)
  686. {
  687. struct i2c_board_info info;
  688. struct i2c_adapter *adapter;
  689. struct i2c_client *client;
  690. int ret;
  691. ret = i2c_add_driver(&uda1380_i2c_driver);
  692. if (ret != 0) {
  693. dev_err(&pdev->dev, "can't add i2c driver\n");
  694. return ret;
  695. }
  696. memset(&info, 0, sizeof(struct i2c_board_info));
  697. info.addr = setup->i2c_address;
  698. strlcpy(info.type, "uda1380", I2C_NAME_SIZE);
  699. adapter = i2c_get_adapter(setup->i2c_bus);
  700. if (!adapter) {
  701. dev_err(&pdev->dev, "can't get i2c adapter %d\n",
  702. setup->i2c_bus);
  703. goto err_driver;
  704. }
  705. client = i2c_new_device(adapter, &info);
  706. i2c_put_adapter(adapter);
  707. if (!client) {
  708. dev_err(&pdev->dev, "can't add i2c device at 0x%x\n",
  709. (unsigned int)info.addr);
  710. goto err_driver;
  711. }
  712. return 0;
  713. err_driver:
  714. i2c_del_driver(&uda1380_i2c_driver);
  715. return -ENODEV;
  716. }
  717. #endif
  718. static int uda1380_probe(struct platform_device *pdev)
  719. {
  720. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  721. struct uda1380_setup_data *setup;
  722. struct snd_soc_codec *codec;
  723. int ret;
  724. setup = socdev->codec_data;
  725. codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
  726. if (codec == NULL)
  727. return -ENOMEM;
  728. socdev->card->codec = codec;
  729. mutex_init(&codec->mutex);
  730. INIT_LIST_HEAD(&codec->dapm_widgets);
  731. INIT_LIST_HEAD(&codec->dapm_paths);
  732. uda1380_socdev = socdev;
  733. ret = -ENODEV;
  734. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  735. if (setup->i2c_address) {
  736. codec->hw_write = (hw_write_t)i2c_master_send;
  737. ret = uda1380_add_i2c_device(pdev, setup);
  738. }
  739. #endif
  740. if (ret != 0)
  741. kfree(codec);
  742. return ret;
  743. }
  744. /* power down chip */
  745. static int uda1380_remove(struct platform_device *pdev)
  746. {
  747. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  748. struct snd_soc_codec *codec = socdev->card->codec;
  749. if (codec->control_data)
  750. uda1380_set_bias_level(codec, SND_SOC_BIAS_OFF);
  751. snd_soc_free_pcms(socdev);
  752. snd_soc_dapm_free(socdev);
  753. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  754. i2c_unregister_device(codec->control_data);
  755. i2c_del_driver(&uda1380_i2c_driver);
  756. #endif
  757. kfree(codec);
  758. return 0;
  759. }
  760. struct snd_soc_codec_device soc_codec_dev_uda1380 = {
  761. .probe = uda1380_probe,
  762. .remove = uda1380_remove,
  763. .suspend = uda1380_suspend,
  764. .resume = uda1380_resume,
  765. };
  766. EXPORT_SYMBOL_GPL(soc_codec_dev_uda1380);
  767. static int __init uda1380_modinit(void)
  768. {
  769. return snd_soc_register_dais(uda1380_dai, ARRAY_SIZE(uda1380_dai));
  770. }
  771. module_init(uda1380_modinit);
  772. static void __exit uda1380_exit(void)
  773. {
  774. snd_soc_unregister_dais(uda1380_dai, ARRAY_SIZE(uda1380_dai));
  775. }
  776. module_exit(uda1380_exit);
  777. MODULE_AUTHOR("Giorgio Padrin");
  778. MODULE_DESCRIPTION("Audio support for codec Philips UDA1380");
  779. MODULE_LICENSE("GPL");