phy_common.c 9.9 KB

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  1. /*
  2. Broadcom B43 wireless driver
  3. Common PHY routines
  4. Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
  5. Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
  6. Copyright (c) 2005-2008 Michael Buesch <mb@bu3sch.de>
  7. Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
  8. Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  9. This program is free software; you can redistribute it and/or modify
  10. it under the terms of the GNU General Public License as published by
  11. the Free Software Foundation; either version 2 of the License, or
  12. (at your option) any later version.
  13. This program is distributed in the hope that it will be useful,
  14. but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. GNU General Public License for more details.
  17. You should have received a copy of the GNU General Public License
  18. along with this program; see the file COPYING. If not, write to
  19. the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  20. Boston, MA 02110-1301, USA.
  21. */
  22. #include "phy_common.h"
  23. #include "phy_g.h"
  24. #include "phy_a.h"
  25. #include "phy_n.h"
  26. #include "phy_lp.h"
  27. #include "b43.h"
  28. #include "main.h"
  29. int b43_phy_allocate(struct b43_wldev *dev)
  30. {
  31. struct b43_phy *phy = &(dev->phy);
  32. int err;
  33. phy->ops = NULL;
  34. switch (phy->type) {
  35. case B43_PHYTYPE_A:
  36. phy->ops = &b43_phyops_a;
  37. break;
  38. case B43_PHYTYPE_G:
  39. phy->ops = &b43_phyops_g;
  40. break;
  41. case B43_PHYTYPE_N:
  42. #ifdef CONFIG_B43_NPHY
  43. phy->ops = &b43_phyops_n;
  44. #endif
  45. break;
  46. case B43_PHYTYPE_LP:
  47. #ifdef CONFIG_B43_PHY_LP
  48. phy->ops = &b43_phyops_lp;
  49. #endif
  50. break;
  51. }
  52. if (B43_WARN_ON(!phy->ops))
  53. return -ENODEV;
  54. err = phy->ops->allocate(dev);
  55. if (err)
  56. phy->ops = NULL;
  57. return err;
  58. }
  59. void b43_phy_free(struct b43_wldev *dev)
  60. {
  61. dev->phy.ops->free(dev);
  62. dev->phy.ops = NULL;
  63. }
  64. int b43_phy_init(struct b43_wldev *dev)
  65. {
  66. struct b43_phy *phy = &dev->phy;
  67. const struct b43_phy_operations *ops = phy->ops;
  68. int err;
  69. phy->channel = ops->get_default_chan(dev);
  70. ops->software_rfkill(dev, RFKILL_STATE_UNBLOCKED);
  71. err = ops->init(dev);
  72. if (err) {
  73. b43err(dev->wl, "PHY init failed\n");
  74. goto err_block_rf;
  75. }
  76. /* Make sure to switch hardware and firmware (SHM) to
  77. * the default channel. */
  78. err = b43_switch_channel(dev, ops->get_default_chan(dev));
  79. if (err) {
  80. b43err(dev->wl, "PHY init: Channel switch to default failed\n");
  81. goto err_phy_exit;
  82. }
  83. return 0;
  84. err_phy_exit:
  85. if (ops->exit)
  86. ops->exit(dev);
  87. err_block_rf:
  88. ops->software_rfkill(dev, RFKILL_STATE_SOFT_BLOCKED);
  89. return err;
  90. }
  91. void b43_phy_exit(struct b43_wldev *dev)
  92. {
  93. const struct b43_phy_operations *ops = dev->phy.ops;
  94. ops->software_rfkill(dev, RFKILL_STATE_SOFT_BLOCKED);
  95. if (ops->exit)
  96. ops->exit(dev);
  97. }
  98. bool b43_has_hardware_pctl(struct b43_wldev *dev)
  99. {
  100. if (!dev->phy.hardware_power_control)
  101. return 0;
  102. if (!dev->phy.ops->supports_hwpctl)
  103. return 0;
  104. return dev->phy.ops->supports_hwpctl(dev);
  105. }
  106. void b43_radio_lock(struct b43_wldev *dev)
  107. {
  108. u32 macctl;
  109. #if B43_DEBUG
  110. B43_WARN_ON(dev->phy.radio_locked);
  111. dev->phy.radio_locked = 1;
  112. #endif
  113. macctl = b43_read32(dev, B43_MMIO_MACCTL);
  114. macctl |= B43_MACCTL_RADIOLOCK;
  115. b43_write32(dev, B43_MMIO_MACCTL, macctl);
  116. /* Commit the write and wait for the firmware
  117. * to finish any radio register access. */
  118. b43_read32(dev, B43_MMIO_MACCTL);
  119. udelay(10);
  120. }
  121. void b43_radio_unlock(struct b43_wldev *dev)
  122. {
  123. u32 macctl;
  124. #if B43_DEBUG
  125. B43_WARN_ON(!dev->phy.radio_locked);
  126. dev->phy.radio_locked = 0;
  127. #endif
  128. /* Commit any write */
  129. b43_read16(dev, B43_MMIO_PHY_VER);
  130. /* unlock */
  131. macctl = b43_read32(dev, B43_MMIO_MACCTL);
  132. macctl &= ~B43_MACCTL_RADIOLOCK;
  133. b43_write32(dev, B43_MMIO_MACCTL, macctl);
  134. }
  135. void b43_phy_lock(struct b43_wldev *dev)
  136. {
  137. #if B43_DEBUG
  138. B43_WARN_ON(dev->phy.phy_locked);
  139. dev->phy.phy_locked = 1;
  140. #endif
  141. B43_WARN_ON(dev->dev->id.revision < 3);
  142. if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
  143. b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
  144. }
  145. void b43_phy_unlock(struct b43_wldev *dev)
  146. {
  147. #if B43_DEBUG
  148. B43_WARN_ON(!dev->phy.phy_locked);
  149. dev->phy.phy_locked = 0;
  150. #endif
  151. B43_WARN_ON(dev->dev->id.revision < 3);
  152. if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
  153. b43_power_saving_ctl_bits(dev, 0);
  154. }
  155. static inline void assert_mac_suspended(struct b43_wldev *dev)
  156. {
  157. if (!B43_DEBUG)
  158. return;
  159. if ((b43_status(dev) >= B43_STAT_INITIALIZED) &&
  160. (dev->mac_suspended <= 0)) {
  161. b43dbg(dev->wl, "PHY/RADIO register access with "
  162. "enabled MAC.\n");
  163. dump_stack();
  164. }
  165. }
  166. u16 b43_radio_read(struct b43_wldev *dev, u16 reg)
  167. {
  168. assert_mac_suspended(dev);
  169. return dev->phy.ops->radio_read(dev, reg);
  170. }
  171. void b43_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
  172. {
  173. assert_mac_suspended(dev);
  174. dev->phy.ops->radio_write(dev, reg, value);
  175. }
  176. void b43_radio_mask(struct b43_wldev *dev, u16 offset, u16 mask)
  177. {
  178. b43_radio_write16(dev, offset,
  179. b43_radio_read16(dev, offset) & mask);
  180. }
  181. void b43_radio_set(struct b43_wldev *dev, u16 offset, u16 set)
  182. {
  183. b43_radio_write16(dev, offset,
  184. b43_radio_read16(dev, offset) | set);
  185. }
  186. void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
  187. {
  188. b43_radio_write16(dev, offset,
  189. (b43_radio_read16(dev, offset) & mask) | set);
  190. }
  191. u16 b43_phy_read(struct b43_wldev *dev, u16 reg)
  192. {
  193. assert_mac_suspended(dev);
  194. return dev->phy.ops->phy_read(dev, reg);
  195. }
  196. void b43_phy_write(struct b43_wldev *dev, u16 reg, u16 value)
  197. {
  198. assert_mac_suspended(dev);
  199. dev->phy.ops->phy_write(dev, reg, value);
  200. }
  201. void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask)
  202. {
  203. b43_phy_write(dev, offset,
  204. b43_phy_read(dev, offset) & mask);
  205. }
  206. void b43_phy_set(struct b43_wldev *dev, u16 offset, u16 set)
  207. {
  208. b43_phy_write(dev, offset,
  209. b43_phy_read(dev, offset) | set);
  210. }
  211. void b43_phy_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
  212. {
  213. b43_phy_write(dev, offset,
  214. (b43_phy_read(dev, offset) & mask) | set);
  215. }
  216. int b43_switch_channel(struct b43_wldev *dev, unsigned int new_channel)
  217. {
  218. struct b43_phy *phy = &(dev->phy);
  219. u16 channelcookie, savedcookie;
  220. int err;
  221. if (new_channel == B43_DEFAULT_CHANNEL)
  222. new_channel = phy->ops->get_default_chan(dev);
  223. /* First we set the channel radio code to prevent the
  224. * firmware from sending ghost packets.
  225. */
  226. channelcookie = new_channel;
  227. if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
  228. channelcookie |= 0x100;
  229. //FIXME set 40Mhz flag if required
  230. savedcookie = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN);
  231. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN, channelcookie);
  232. /* Now try to switch the PHY hardware channel. */
  233. err = phy->ops->switch_channel(dev, new_channel);
  234. if (err)
  235. goto err_restore_cookie;
  236. dev->phy.channel = new_channel;
  237. /* Wait for the radio to tune to the channel and stabilize. */
  238. msleep(8);
  239. return 0;
  240. err_restore_cookie:
  241. b43_shm_write16(dev, B43_SHM_SHARED,
  242. B43_SHM_SH_CHAN, savedcookie);
  243. return err;
  244. }
  245. void b43_software_rfkill(struct b43_wldev *dev, enum rfkill_state state)
  246. {
  247. struct b43_phy *phy = &dev->phy;
  248. if (state == RFKILL_STATE_HARD_BLOCKED) {
  249. /* We cannot hardware-block the device */
  250. state = RFKILL_STATE_SOFT_BLOCKED;
  251. }
  252. b43_mac_suspend(dev);
  253. phy->ops->software_rfkill(dev, state);
  254. phy->radio_on = (state == RFKILL_STATE_UNBLOCKED);
  255. b43_mac_enable(dev);
  256. }
  257. /**
  258. * b43_phy_txpower_adjust_work - TX power workqueue.
  259. *
  260. * Workqueue for updating the TX power parameters in hardware.
  261. */
  262. void b43_phy_txpower_adjust_work(struct work_struct *work)
  263. {
  264. struct b43_wl *wl = container_of(work, struct b43_wl,
  265. txpower_adjust_work);
  266. struct b43_wldev *dev;
  267. mutex_lock(&wl->mutex);
  268. dev = wl->current_dev;
  269. if (likely(dev && (b43_status(dev) >= B43_STAT_STARTED)))
  270. dev->phy.ops->adjust_txpower(dev);
  271. mutex_unlock(&wl->mutex);
  272. }
  273. /* Called with wl->irq_lock locked */
  274. void b43_phy_txpower_check(struct b43_wldev *dev, unsigned int flags)
  275. {
  276. struct b43_phy *phy = &dev->phy;
  277. unsigned long now = jiffies;
  278. enum b43_txpwr_result result;
  279. if (!(flags & B43_TXPWR_IGNORE_TIME)) {
  280. /* Check if it's time for a TXpower check. */
  281. if (time_before(now, phy->next_txpwr_check_time))
  282. return; /* Not yet */
  283. }
  284. /* The next check will be needed in two seconds, or later. */
  285. phy->next_txpwr_check_time = round_jiffies(now + (HZ * 2));
  286. if ((dev->dev->bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
  287. (dev->dev->bus->boardinfo.type == SSB_BOARD_BU4306))
  288. return; /* No software txpower adjustment needed */
  289. result = phy->ops->recalc_txpower(dev, !!(flags & B43_TXPWR_IGNORE_TSSI));
  290. if (result == B43_TXPWR_RES_DONE)
  291. return; /* We are done. */
  292. B43_WARN_ON(result != B43_TXPWR_RES_NEED_ADJUST);
  293. B43_WARN_ON(phy->ops->adjust_txpower == NULL);
  294. /* We must adjust the transmission power in hardware.
  295. * Schedule b43_phy_txpower_adjust_work(). */
  296. queue_work(dev->wl->hw->workqueue, &dev->wl->txpower_adjust_work);
  297. }
  298. int b43_phy_shm_tssi_read(struct b43_wldev *dev, u16 shm_offset)
  299. {
  300. const bool is_ofdm = (shm_offset != B43_SHM_SH_TSSI_CCK);
  301. unsigned int a, b, c, d;
  302. unsigned int average;
  303. u32 tmp;
  304. tmp = b43_shm_read32(dev, B43_SHM_SHARED, shm_offset);
  305. a = tmp & 0xFF;
  306. b = (tmp >> 8) & 0xFF;
  307. c = (tmp >> 16) & 0xFF;
  308. d = (tmp >> 24) & 0xFF;
  309. if (a == 0 || a == B43_TSSI_MAX ||
  310. b == 0 || b == B43_TSSI_MAX ||
  311. c == 0 || c == B43_TSSI_MAX ||
  312. d == 0 || d == B43_TSSI_MAX)
  313. return -ENOENT;
  314. /* The values are OK. Clear them. */
  315. tmp = B43_TSSI_MAX | (B43_TSSI_MAX << 8) |
  316. (B43_TSSI_MAX << 16) | (B43_TSSI_MAX << 24);
  317. b43_shm_write32(dev, B43_SHM_SHARED, shm_offset, tmp);
  318. if (is_ofdm) {
  319. a = (a + 32) & 0x3F;
  320. b = (b + 32) & 0x3F;
  321. c = (c + 32) & 0x3F;
  322. d = (d + 32) & 0x3F;
  323. }
  324. /* Get the average of the values with 0.5 added to each value. */
  325. average = (a + b + c + d + 2) / 4;
  326. if (is_ofdm) {
  327. /* Adjust for CCK-boost */
  328. if (b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO)
  329. & B43_HF_CCKBOOST)
  330. average = (average >= 13) ? (average - 13) : 0;
  331. }
  332. return average;
  333. }
  334. void b43_phyop_switch_analog_generic(struct b43_wldev *dev, bool on)
  335. {
  336. b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
  337. }