c2.c 33 KB

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  1. /*
  2. * Copyright (c) 2005 Ammasso, Inc. All rights reserved.
  3. * Copyright (c) 2005 Open Grid Computing, Inc. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenIB.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. */
  33. #include <linux/module.h>
  34. #include <linux/moduleparam.h>
  35. #include <linux/pci.h>
  36. #include <linux/netdevice.h>
  37. #include <linux/etherdevice.h>
  38. #include <linux/inetdevice.h>
  39. #include <linux/delay.h>
  40. #include <linux/ethtool.h>
  41. #include <linux/mii.h>
  42. #include <linux/if_vlan.h>
  43. #include <linux/crc32.h>
  44. #include <linux/in.h>
  45. #include <linux/ip.h>
  46. #include <linux/tcp.h>
  47. #include <linux/init.h>
  48. #include <linux/dma-mapping.h>
  49. #include <asm/io.h>
  50. #include <asm/irq.h>
  51. #include <asm/byteorder.h>
  52. #include <rdma/ib_smi.h>
  53. #include "c2.h"
  54. #include "c2_provider.h"
  55. MODULE_AUTHOR("Tom Tucker <tom@opengridcomputing.com>");
  56. MODULE_DESCRIPTION("Ammasso AMSO1100 Low-level iWARP Driver");
  57. MODULE_LICENSE("Dual BSD/GPL");
  58. MODULE_VERSION(DRV_VERSION);
  59. static const u32 default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
  60. | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
  61. static int debug = -1; /* defaults above */
  62. module_param(debug, int, 0);
  63. MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  64. static int c2_up(struct net_device *netdev);
  65. static int c2_down(struct net_device *netdev);
  66. static int c2_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
  67. static void c2_tx_interrupt(struct net_device *netdev);
  68. static void c2_rx_interrupt(struct net_device *netdev);
  69. static irqreturn_t c2_interrupt(int irq, void *dev_id);
  70. static void c2_tx_timeout(struct net_device *netdev);
  71. static int c2_change_mtu(struct net_device *netdev, int new_mtu);
  72. static void c2_reset(struct c2_port *c2_port);
  73. static struct pci_device_id c2_pci_table[] = {
  74. { PCI_DEVICE(0x18b8, 0xb001) },
  75. { 0 }
  76. };
  77. MODULE_DEVICE_TABLE(pci, c2_pci_table);
  78. static void c2_print_macaddr(struct net_device *netdev)
  79. {
  80. pr_debug("%s: MAC %02X:%02X:%02X:%02X:%02X:%02X, "
  81. "IRQ %u\n", netdev->name,
  82. netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
  83. netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5],
  84. netdev->irq);
  85. }
  86. static void c2_set_rxbufsize(struct c2_port *c2_port)
  87. {
  88. struct net_device *netdev = c2_port->netdev;
  89. if (netdev->mtu > RX_BUF_SIZE)
  90. c2_port->rx_buf_size =
  91. netdev->mtu + ETH_HLEN + sizeof(struct c2_rxp_hdr) +
  92. NET_IP_ALIGN;
  93. else
  94. c2_port->rx_buf_size = sizeof(struct c2_rxp_hdr) + RX_BUF_SIZE;
  95. }
  96. /*
  97. * Allocate TX ring elements and chain them together.
  98. * One-to-one association of adapter descriptors with ring elements.
  99. */
  100. static int c2_tx_ring_alloc(struct c2_ring *tx_ring, void *vaddr,
  101. dma_addr_t base, void __iomem * mmio_txp_ring)
  102. {
  103. struct c2_tx_desc *tx_desc;
  104. struct c2_txp_desc __iomem *txp_desc;
  105. struct c2_element *elem;
  106. int i;
  107. tx_ring->start = kmalloc(sizeof(*elem) * tx_ring->count, GFP_KERNEL);
  108. if (!tx_ring->start)
  109. return -ENOMEM;
  110. elem = tx_ring->start;
  111. tx_desc = vaddr;
  112. txp_desc = mmio_txp_ring;
  113. for (i = 0; i < tx_ring->count; i++, elem++, tx_desc++, txp_desc++) {
  114. tx_desc->len = 0;
  115. tx_desc->status = 0;
  116. /* Set TXP_HTXD_UNINIT */
  117. __raw_writeq((__force u64) cpu_to_be64(0x1122334455667788ULL),
  118. (void __iomem *) txp_desc + C2_TXP_ADDR);
  119. __raw_writew(0, (void __iomem *) txp_desc + C2_TXP_LEN);
  120. __raw_writew((__force u16) cpu_to_be16(TXP_HTXD_UNINIT),
  121. (void __iomem *) txp_desc + C2_TXP_FLAGS);
  122. elem->skb = NULL;
  123. elem->ht_desc = tx_desc;
  124. elem->hw_desc = txp_desc;
  125. if (i == tx_ring->count - 1) {
  126. elem->next = tx_ring->start;
  127. tx_desc->next_offset = base;
  128. } else {
  129. elem->next = elem + 1;
  130. tx_desc->next_offset =
  131. base + (i + 1) * sizeof(*tx_desc);
  132. }
  133. }
  134. tx_ring->to_use = tx_ring->to_clean = tx_ring->start;
  135. return 0;
  136. }
  137. /*
  138. * Allocate RX ring elements and chain them together.
  139. * One-to-one association of adapter descriptors with ring elements.
  140. */
  141. static int c2_rx_ring_alloc(struct c2_ring *rx_ring, void *vaddr,
  142. dma_addr_t base, void __iomem * mmio_rxp_ring)
  143. {
  144. struct c2_rx_desc *rx_desc;
  145. struct c2_rxp_desc __iomem *rxp_desc;
  146. struct c2_element *elem;
  147. int i;
  148. rx_ring->start = kmalloc(sizeof(*elem) * rx_ring->count, GFP_KERNEL);
  149. if (!rx_ring->start)
  150. return -ENOMEM;
  151. elem = rx_ring->start;
  152. rx_desc = vaddr;
  153. rxp_desc = mmio_rxp_ring;
  154. for (i = 0; i < rx_ring->count; i++, elem++, rx_desc++, rxp_desc++) {
  155. rx_desc->len = 0;
  156. rx_desc->status = 0;
  157. /* Set RXP_HRXD_UNINIT */
  158. __raw_writew((__force u16) cpu_to_be16(RXP_HRXD_OK),
  159. (void __iomem *) rxp_desc + C2_RXP_STATUS);
  160. __raw_writew(0, (void __iomem *) rxp_desc + C2_RXP_COUNT);
  161. __raw_writew(0, (void __iomem *) rxp_desc + C2_RXP_LEN);
  162. __raw_writeq((__force u64) cpu_to_be64(0x99aabbccddeeffULL),
  163. (void __iomem *) rxp_desc + C2_RXP_ADDR);
  164. __raw_writew((__force u16) cpu_to_be16(RXP_HRXD_UNINIT),
  165. (void __iomem *) rxp_desc + C2_RXP_FLAGS);
  166. elem->skb = NULL;
  167. elem->ht_desc = rx_desc;
  168. elem->hw_desc = rxp_desc;
  169. if (i == rx_ring->count - 1) {
  170. elem->next = rx_ring->start;
  171. rx_desc->next_offset = base;
  172. } else {
  173. elem->next = elem + 1;
  174. rx_desc->next_offset =
  175. base + (i + 1) * sizeof(*rx_desc);
  176. }
  177. }
  178. rx_ring->to_use = rx_ring->to_clean = rx_ring->start;
  179. return 0;
  180. }
  181. /* Setup buffer for receiving */
  182. static inline int c2_rx_alloc(struct c2_port *c2_port, struct c2_element *elem)
  183. {
  184. struct c2_dev *c2dev = c2_port->c2dev;
  185. struct c2_rx_desc *rx_desc = elem->ht_desc;
  186. struct sk_buff *skb;
  187. dma_addr_t mapaddr;
  188. u32 maplen;
  189. struct c2_rxp_hdr *rxp_hdr;
  190. skb = dev_alloc_skb(c2_port->rx_buf_size);
  191. if (unlikely(!skb)) {
  192. pr_debug("%s: out of memory for receive\n",
  193. c2_port->netdev->name);
  194. return -ENOMEM;
  195. }
  196. /* Zero out the rxp hdr in the sk_buff */
  197. memset(skb->data, 0, sizeof(*rxp_hdr));
  198. skb->dev = c2_port->netdev;
  199. maplen = c2_port->rx_buf_size;
  200. mapaddr =
  201. pci_map_single(c2dev->pcidev, skb->data, maplen,
  202. PCI_DMA_FROMDEVICE);
  203. /* Set the sk_buff RXP_header to RXP_HRXD_READY */
  204. rxp_hdr = (struct c2_rxp_hdr *) skb->data;
  205. rxp_hdr->flags = RXP_HRXD_READY;
  206. __raw_writew(0, elem->hw_desc + C2_RXP_STATUS);
  207. __raw_writew((__force u16) cpu_to_be16((u16) maplen - sizeof(*rxp_hdr)),
  208. elem->hw_desc + C2_RXP_LEN);
  209. __raw_writeq((__force u64) cpu_to_be64(mapaddr), elem->hw_desc + C2_RXP_ADDR);
  210. __raw_writew((__force u16) cpu_to_be16(RXP_HRXD_READY),
  211. elem->hw_desc + C2_RXP_FLAGS);
  212. elem->skb = skb;
  213. elem->mapaddr = mapaddr;
  214. elem->maplen = maplen;
  215. rx_desc->len = maplen;
  216. return 0;
  217. }
  218. /*
  219. * Allocate buffers for the Rx ring
  220. * For receive: rx_ring.to_clean is next received frame
  221. */
  222. static int c2_rx_fill(struct c2_port *c2_port)
  223. {
  224. struct c2_ring *rx_ring = &c2_port->rx_ring;
  225. struct c2_element *elem;
  226. int ret = 0;
  227. elem = rx_ring->start;
  228. do {
  229. if (c2_rx_alloc(c2_port, elem)) {
  230. ret = 1;
  231. break;
  232. }
  233. } while ((elem = elem->next) != rx_ring->start);
  234. rx_ring->to_clean = rx_ring->start;
  235. return ret;
  236. }
  237. /* Free all buffers in RX ring, assumes receiver stopped */
  238. static void c2_rx_clean(struct c2_port *c2_port)
  239. {
  240. struct c2_dev *c2dev = c2_port->c2dev;
  241. struct c2_ring *rx_ring = &c2_port->rx_ring;
  242. struct c2_element *elem;
  243. struct c2_rx_desc *rx_desc;
  244. elem = rx_ring->start;
  245. do {
  246. rx_desc = elem->ht_desc;
  247. rx_desc->len = 0;
  248. __raw_writew(0, elem->hw_desc + C2_RXP_STATUS);
  249. __raw_writew(0, elem->hw_desc + C2_RXP_COUNT);
  250. __raw_writew(0, elem->hw_desc + C2_RXP_LEN);
  251. __raw_writeq((__force u64) cpu_to_be64(0x99aabbccddeeffULL),
  252. elem->hw_desc + C2_RXP_ADDR);
  253. __raw_writew((__force u16) cpu_to_be16(RXP_HRXD_UNINIT),
  254. elem->hw_desc + C2_RXP_FLAGS);
  255. if (elem->skb) {
  256. pci_unmap_single(c2dev->pcidev, elem->mapaddr,
  257. elem->maplen, PCI_DMA_FROMDEVICE);
  258. dev_kfree_skb(elem->skb);
  259. elem->skb = NULL;
  260. }
  261. } while ((elem = elem->next) != rx_ring->start);
  262. }
  263. static inline int c2_tx_free(struct c2_dev *c2dev, struct c2_element *elem)
  264. {
  265. struct c2_tx_desc *tx_desc = elem->ht_desc;
  266. tx_desc->len = 0;
  267. pci_unmap_single(c2dev->pcidev, elem->mapaddr, elem->maplen,
  268. PCI_DMA_TODEVICE);
  269. if (elem->skb) {
  270. dev_kfree_skb_any(elem->skb);
  271. elem->skb = NULL;
  272. }
  273. return 0;
  274. }
  275. /* Free all buffers in TX ring, assumes transmitter stopped */
  276. static void c2_tx_clean(struct c2_port *c2_port)
  277. {
  278. struct c2_ring *tx_ring = &c2_port->tx_ring;
  279. struct c2_element *elem;
  280. struct c2_txp_desc txp_htxd;
  281. int retry;
  282. unsigned long flags;
  283. spin_lock_irqsave(&c2_port->tx_lock, flags);
  284. elem = tx_ring->start;
  285. do {
  286. retry = 0;
  287. do {
  288. txp_htxd.flags =
  289. readw(elem->hw_desc + C2_TXP_FLAGS);
  290. if (txp_htxd.flags == TXP_HTXD_READY) {
  291. retry = 1;
  292. __raw_writew(0,
  293. elem->hw_desc + C2_TXP_LEN);
  294. __raw_writeq(0,
  295. elem->hw_desc + C2_TXP_ADDR);
  296. __raw_writew((__force u16) cpu_to_be16(TXP_HTXD_DONE),
  297. elem->hw_desc + C2_TXP_FLAGS);
  298. c2_port->netdev->stats.tx_dropped++;
  299. break;
  300. } else {
  301. __raw_writew(0,
  302. elem->hw_desc + C2_TXP_LEN);
  303. __raw_writeq((__force u64) cpu_to_be64(0x1122334455667788ULL),
  304. elem->hw_desc + C2_TXP_ADDR);
  305. __raw_writew((__force u16) cpu_to_be16(TXP_HTXD_UNINIT),
  306. elem->hw_desc + C2_TXP_FLAGS);
  307. }
  308. c2_tx_free(c2_port->c2dev, elem);
  309. } while ((elem = elem->next) != tx_ring->start);
  310. } while (retry);
  311. c2_port->tx_avail = c2_port->tx_ring.count - 1;
  312. c2_port->c2dev->cur_tx = tx_ring->to_use - tx_ring->start;
  313. if (c2_port->tx_avail > MAX_SKB_FRAGS + 1)
  314. netif_wake_queue(c2_port->netdev);
  315. spin_unlock_irqrestore(&c2_port->tx_lock, flags);
  316. }
  317. /*
  318. * Process transmit descriptors marked 'DONE' by the firmware,
  319. * freeing up their unneeded sk_buffs.
  320. */
  321. static void c2_tx_interrupt(struct net_device *netdev)
  322. {
  323. struct c2_port *c2_port = netdev_priv(netdev);
  324. struct c2_dev *c2dev = c2_port->c2dev;
  325. struct c2_ring *tx_ring = &c2_port->tx_ring;
  326. struct c2_element *elem;
  327. struct c2_txp_desc txp_htxd;
  328. spin_lock(&c2_port->tx_lock);
  329. for (elem = tx_ring->to_clean; elem != tx_ring->to_use;
  330. elem = elem->next) {
  331. txp_htxd.flags =
  332. be16_to_cpu((__force __be16) readw(elem->hw_desc + C2_TXP_FLAGS));
  333. if (txp_htxd.flags != TXP_HTXD_DONE)
  334. break;
  335. if (netif_msg_tx_done(c2_port)) {
  336. /* PCI reads are expensive in fast path */
  337. txp_htxd.len =
  338. be16_to_cpu((__force __be16) readw(elem->hw_desc + C2_TXP_LEN));
  339. pr_debug("%s: tx done slot %3Zu status 0x%x len "
  340. "%5u bytes\n",
  341. netdev->name, elem - tx_ring->start,
  342. txp_htxd.flags, txp_htxd.len);
  343. }
  344. c2_tx_free(c2dev, elem);
  345. ++(c2_port->tx_avail);
  346. }
  347. tx_ring->to_clean = elem;
  348. if (netif_queue_stopped(netdev)
  349. && c2_port->tx_avail > MAX_SKB_FRAGS + 1)
  350. netif_wake_queue(netdev);
  351. spin_unlock(&c2_port->tx_lock);
  352. }
  353. static void c2_rx_error(struct c2_port *c2_port, struct c2_element *elem)
  354. {
  355. struct c2_rx_desc *rx_desc = elem->ht_desc;
  356. struct c2_rxp_hdr *rxp_hdr = (struct c2_rxp_hdr *) elem->skb->data;
  357. if (rxp_hdr->status != RXP_HRXD_OK ||
  358. rxp_hdr->len > (rx_desc->len - sizeof(*rxp_hdr))) {
  359. pr_debug("BAD RXP_HRXD\n");
  360. pr_debug(" rx_desc : %p\n", rx_desc);
  361. pr_debug(" index : %Zu\n",
  362. elem - c2_port->rx_ring.start);
  363. pr_debug(" len : %u\n", rx_desc->len);
  364. pr_debug(" rxp_hdr : %p [PA %p]\n", rxp_hdr,
  365. (void *) __pa((unsigned long) rxp_hdr));
  366. pr_debug(" flags : 0x%x\n", rxp_hdr->flags);
  367. pr_debug(" status: 0x%x\n", rxp_hdr->status);
  368. pr_debug(" len : %u\n", rxp_hdr->len);
  369. pr_debug(" rsvd : 0x%x\n", rxp_hdr->rsvd);
  370. }
  371. /* Setup the skb for reuse since we're dropping this pkt */
  372. elem->skb->data = elem->skb->head;
  373. skb_reset_tail_pointer(elem->skb);
  374. /* Zero out the rxp hdr in the sk_buff */
  375. memset(elem->skb->data, 0, sizeof(*rxp_hdr));
  376. /* Write the descriptor to the adapter's rx ring */
  377. __raw_writew(0, elem->hw_desc + C2_RXP_STATUS);
  378. __raw_writew(0, elem->hw_desc + C2_RXP_COUNT);
  379. __raw_writew((__force u16) cpu_to_be16((u16) elem->maplen - sizeof(*rxp_hdr)),
  380. elem->hw_desc + C2_RXP_LEN);
  381. __raw_writeq((__force u64) cpu_to_be64(elem->mapaddr),
  382. elem->hw_desc + C2_RXP_ADDR);
  383. __raw_writew((__force u16) cpu_to_be16(RXP_HRXD_READY),
  384. elem->hw_desc + C2_RXP_FLAGS);
  385. pr_debug("packet dropped\n");
  386. c2_port->netdev->stats.rx_dropped++;
  387. }
  388. static void c2_rx_interrupt(struct net_device *netdev)
  389. {
  390. struct c2_port *c2_port = netdev_priv(netdev);
  391. struct c2_dev *c2dev = c2_port->c2dev;
  392. struct c2_ring *rx_ring = &c2_port->rx_ring;
  393. struct c2_element *elem;
  394. struct c2_rx_desc *rx_desc;
  395. struct c2_rxp_hdr *rxp_hdr;
  396. struct sk_buff *skb;
  397. dma_addr_t mapaddr;
  398. u32 maplen, buflen;
  399. unsigned long flags;
  400. spin_lock_irqsave(&c2dev->lock, flags);
  401. /* Begin where we left off */
  402. rx_ring->to_clean = rx_ring->start + c2dev->cur_rx;
  403. for (elem = rx_ring->to_clean; elem->next != rx_ring->to_clean;
  404. elem = elem->next) {
  405. rx_desc = elem->ht_desc;
  406. mapaddr = elem->mapaddr;
  407. maplen = elem->maplen;
  408. skb = elem->skb;
  409. rxp_hdr = (struct c2_rxp_hdr *) skb->data;
  410. if (rxp_hdr->flags != RXP_HRXD_DONE)
  411. break;
  412. buflen = rxp_hdr->len;
  413. /* Sanity check the RXP header */
  414. if (rxp_hdr->status != RXP_HRXD_OK ||
  415. buflen > (rx_desc->len - sizeof(*rxp_hdr))) {
  416. c2_rx_error(c2_port, elem);
  417. continue;
  418. }
  419. /*
  420. * Allocate and map a new skb for replenishing the host
  421. * RX desc
  422. */
  423. if (c2_rx_alloc(c2_port, elem)) {
  424. c2_rx_error(c2_port, elem);
  425. continue;
  426. }
  427. /* Unmap the old skb */
  428. pci_unmap_single(c2dev->pcidev, mapaddr, maplen,
  429. PCI_DMA_FROMDEVICE);
  430. prefetch(skb->data);
  431. /*
  432. * Skip past the leading 8 bytes comprising of the
  433. * "struct c2_rxp_hdr", prepended by the adapter
  434. * to the usual Ethernet header ("struct ethhdr"),
  435. * to the start of the raw Ethernet packet.
  436. *
  437. * Fix up the various fields in the sk_buff before
  438. * passing it up to netif_rx(). The transfer size
  439. * (in bytes) specified by the adapter len field of
  440. * the "struct rxp_hdr_t" does NOT include the
  441. * "sizeof(struct c2_rxp_hdr)".
  442. */
  443. skb->data += sizeof(*rxp_hdr);
  444. skb_set_tail_pointer(skb, buflen);
  445. skb->len = buflen;
  446. skb->protocol = eth_type_trans(skb, netdev);
  447. netif_rx(skb);
  448. netdev->last_rx = jiffies;
  449. netdev->stats.rx_packets++;
  450. netdev->stats.rx_bytes += buflen;
  451. }
  452. /* Save where we left off */
  453. rx_ring->to_clean = elem;
  454. c2dev->cur_rx = elem - rx_ring->start;
  455. C2_SET_CUR_RX(c2dev, c2dev->cur_rx);
  456. spin_unlock_irqrestore(&c2dev->lock, flags);
  457. }
  458. /*
  459. * Handle netisr0 TX & RX interrupts.
  460. */
  461. static irqreturn_t c2_interrupt(int irq, void *dev_id)
  462. {
  463. unsigned int netisr0, dmaisr;
  464. int handled = 0;
  465. struct c2_dev *c2dev = (struct c2_dev *) dev_id;
  466. /* Process CCILNET interrupts */
  467. netisr0 = readl(c2dev->regs + C2_NISR0);
  468. if (netisr0) {
  469. /*
  470. * There is an issue with the firmware that always
  471. * provides the status of RX for both TX & RX
  472. * interrupts. So process both queues here.
  473. */
  474. c2_rx_interrupt(c2dev->netdev);
  475. c2_tx_interrupt(c2dev->netdev);
  476. /* Clear the interrupt */
  477. writel(netisr0, c2dev->regs + C2_NISR0);
  478. handled++;
  479. }
  480. /* Process RNIC interrupts */
  481. dmaisr = readl(c2dev->regs + C2_DISR);
  482. if (dmaisr) {
  483. writel(dmaisr, c2dev->regs + C2_DISR);
  484. c2_rnic_interrupt(c2dev);
  485. handled++;
  486. }
  487. if (handled) {
  488. return IRQ_HANDLED;
  489. } else {
  490. return IRQ_NONE;
  491. }
  492. }
  493. static int c2_up(struct net_device *netdev)
  494. {
  495. struct c2_port *c2_port = netdev_priv(netdev);
  496. struct c2_dev *c2dev = c2_port->c2dev;
  497. struct c2_element *elem;
  498. struct c2_rxp_hdr *rxp_hdr;
  499. struct in_device *in_dev;
  500. size_t rx_size, tx_size;
  501. int ret, i;
  502. unsigned int netimr0;
  503. if (netif_msg_ifup(c2_port))
  504. pr_debug("%s: enabling interface\n", netdev->name);
  505. /* Set the Rx buffer size based on MTU */
  506. c2_set_rxbufsize(c2_port);
  507. /* Allocate DMA'able memory for Tx/Rx host descriptor rings */
  508. rx_size = c2_port->rx_ring.count * sizeof(struct c2_rx_desc);
  509. tx_size = c2_port->tx_ring.count * sizeof(struct c2_tx_desc);
  510. c2_port->mem_size = tx_size + rx_size;
  511. c2_port->mem = pci_alloc_consistent(c2dev->pcidev, c2_port->mem_size,
  512. &c2_port->dma);
  513. if (c2_port->mem == NULL) {
  514. pr_debug("Unable to allocate memory for "
  515. "host descriptor rings\n");
  516. return -ENOMEM;
  517. }
  518. memset(c2_port->mem, 0, c2_port->mem_size);
  519. /* Create the Rx host descriptor ring */
  520. if ((ret =
  521. c2_rx_ring_alloc(&c2_port->rx_ring, c2_port->mem, c2_port->dma,
  522. c2dev->mmio_rxp_ring))) {
  523. pr_debug("Unable to create RX ring\n");
  524. goto bail0;
  525. }
  526. /* Allocate Rx buffers for the host descriptor ring */
  527. if (c2_rx_fill(c2_port)) {
  528. pr_debug("Unable to fill RX ring\n");
  529. goto bail1;
  530. }
  531. /* Create the Tx host descriptor ring */
  532. if ((ret = c2_tx_ring_alloc(&c2_port->tx_ring, c2_port->mem + rx_size,
  533. c2_port->dma + rx_size,
  534. c2dev->mmio_txp_ring))) {
  535. pr_debug("Unable to create TX ring\n");
  536. goto bail1;
  537. }
  538. /* Set the TX pointer to where we left off */
  539. c2_port->tx_avail = c2_port->tx_ring.count - 1;
  540. c2_port->tx_ring.to_use = c2_port->tx_ring.to_clean =
  541. c2_port->tx_ring.start + c2dev->cur_tx;
  542. /* missing: Initialize MAC */
  543. BUG_ON(c2_port->tx_ring.to_use != c2_port->tx_ring.to_clean);
  544. /* Reset the adapter, ensures the driver is in sync with the RXP */
  545. c2_reset(c2_port);
  546. /* Reset the READY bit in the sk_buff RXP headers & adapter HRXDQ */
  547. for (i = 0, elem = c2_port->rx_ring.start; i < c2_port->rx_ring.count;
  548. i++, elem++) {
  549. rxp_hdr = (struct c2_rxp_hdr *) elem->skb->data;
  550. rxp_hdr->flags = 0;
  551. __raw_writew((__force u16) cpu_to_be16(RXP_HRXD_READY),
  552. elem->hw_desc + C2_RXP_FLAGS);
  553. }
  554. /* Enable network packets */
  555. netif_start_queue(netdev);
  556. /* Enable IRQ */
  557. writel(0, c2dev->regs + C2_IDIS);
  558. netimr0 = readl(c2dev->regs + C2_NIMR0);
  559. netimr0 &= ~(C2_PCI_HTX_INT | C2_PCI_HRX_INT);
  560. writel(netimr0, c2dev->regs + C2_NIMR0);
  561. /* Tell the stack to ignore arp requests for ipaddrs bound to
  562. * other interfaces. This is needed to prevent the host stack
  563. * from responding to arp requests to the ipaddr bound on the
  564. * rdma interface.
  565. */
  566. in_dev = in_dev_get(netdev);
  567. IN_DEV_CONF_SET(in_dev, ARP_IGNORE, 1);
  568. in_dev_put(in_dev);
  569. return 0;
  570. bail1:
  571. c2_rx_clean(c2_port);
  572. kfree(c2_port->rx_ring.start);
  573. bail0:
  574. pci_free_consistent(c2dev->pcidev, c2_port->mem_size, c2_port->mem,
  575. c2_port->dma);
  576. return ret;
  577. }
  578. static int c2_down(struct net_device *netdev)
  579. {
  580. struct c2_port *c2_port = netdev_priv(netdev);
  581. struct c2_dev *c2dev = c2_port->c2dev;
  582. if (netif_msg_ifdown(c2_port))
  583. pr_debug("%s: disabling interface\n",
  584. netdev->name);
  585. /* Wait for all the queued packets to get sent */
  586. c2_tx_interrupt(netdev);
  587. /* Disable network packets */
  588. netif_stop_queue(netdev);
  589. /* Disable IRQs by clearing the interrupt mask */
  590. writel(1, c2dev->regs + C2_IDIS);
  591. writel(0, c2dev->regs + C2_NIMR0);
  592. /* missing: Stop transmitter */
  593. /* missing: Stop receiver */
  594. /* Reset the adapter, ensures the driver is in sync with the RXP */
  595. c2_reset(c2_port);
  596. /* missing: Turn off LEDs here */
  597. /* Free all buffers in the host descriptor rings */
  598. c2_tx_clean(c2_port);
  599. c2_rx_clean(c2_port);
  600. /* Free the host descriptor rings */
  601. kfree(c2_port->rx_ring.start);
  602. kfree(c2_port->tx_ring.start);
  603. pci_free_consistent(c2dev->pcidev, c2_port->mem_size, c2_port->mem,
  604. c2_port->dma);
  605. return 0;
  606. }
  607. static void c2_reset(struct c2_port *c2_port)
  608. {
  609. struct c2_dev *c2dev = c2_port->c2dev;
  610. unsigned int cur_rx = c2dev->cur_rx;
  611. /* Tell the hardware to quiesce */
  612. C2_SET_CUR_RX(c2dev, cur_rx | C2_PCI_HRX_QUI);
  613. /*
  614. * The hardware will reset the C2_PCI_HRX_QUI bit once
  615. * the RXP is quiesced. Wait 2 seconds for this.
  616. */
  617. ssleep(2);
  618. cur_rx = C2_GET_CUR_RX(c2dev);
  619. if (cur_rx & C2_PCI_HRX_QUI)
  620. pr_debug("c2_reset: failed to quiesce the hardware!\n");
  621. cur_rx &= ~C2_PCI_HRX_QUI;
  622. c2dev->cur_rx = cur_rx;
  623. pr_debug("Current RX: %u\n", c2dev->cur_rx);
  624. }
  625. static int c2_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
  626. {
  627. struct c2_port *c2_port = netdev_priv(netdev);
  628. struct c2_dev *c2dev = c2_port->c2dev;
  629. struct c2_ring *tx_ring = &c2_port->tx_ring;
  630. struct c2_element *elem;
  631. dma_addr_t mapaddr;
  632. u32 maplen;
  633. unsigned long flags;
  634. unsigned int i;
  635. spin_lock_irqsave(&c2_port->tx_lock, flags);
  636. if (unlikely(c2_port->tx_avail < (skb_shinfo(skb)->nr_frags + 1))) {
  637. netif_stop_queue(netdev);
  638. spin_unlock_irqrestore(&c2_port->tx_lock, flags);
  639. pr_debug("%s: Tx ring full when queue awake!\n",
  640. netdev->name);
  641. return NETDEV_TX_BUSY;
  642. }
  643. maplen = skb_headlen(skb);
  644. mapaddr =
  645. pci_map_single(c2dev->pcidev, skb->data, maplen, PCI_DMA_TODEVICE);
  646. elem = tx_ring->to_use;
  647. elem->skb = skb;
  648. elem->mapaddr = mapaddr;
  649. elem->maplen = maplen;
  650. /* Tell HW to xmit */
  651. __raw_writeq((__force u64) cpu_to_be64(mapaddr),
  652. elem->hw_desc + C2_TXP_ADDR);
  653. __raw_writew((__force u16) cpu_to_be16(maplen),
  654. elem->hw_desc + C2_TXP_LEN);
  655. __raw_writew((__force u16) cpu_to_be16(TXP_HTXD_READY),
  656. elem->hw_desc + C2_TXP_FLAGS);
  657. netdev->stats.tx_packets++;
  658. netdev->stats.tx_bytes += maplen;
  659. /* Loop thru additional data fragments and queue them */
  660. if (skb_shinfo(skb)->nr_frags) {
  661. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  662. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  663. maplen = frag->size;
  664. mapaddr =
  665. pci_map_page(c2dev->pcidev, frag->page,
  666. frag->page_offset, maplen,
  667. PCI_DMA_TODEVICE);
  668. elem = elem->next;
  669. elem->skb = NULL;
  670. elem->mapaddr = mapaddr;
  671. elem->maplen = maplen;
  672. /* Tell HW to xmit */
  673. __raw_writeq((__force u64) cpu_to_be64(mapaddr),
  674. elem->hw_desc + C2_TXP_ADDR);
  675. __raw_writew((__force u16) cpu_to_be16(maplen),
  676. elem->hw_desc + C2_TXP_LEN);
  677. __raw_writew((__force u16) cpu_to_be16(TXP_HTXD_READY),
  678. elem->hw_desc + C2_TXP_FLAGS);
  679. netdev->stats.tx_packets++;
  680. netdev->stats.tx_bytes += maplen;
  681. }
  682. }
  683. tx_ring->to_use = elem->next;
  684. c2_port->tx_avail -= (skb_shinfo(skb)->nr_frags + 1);
  685. if (c2_port->tx_avail <= MAX_SKB_FRAGS + 1) {
  686. netif_stop_queue(netdev);
  687. if (netif_msg_tx_queued(c2_port))
  688. pr_debug("%s: transmit queue full\n",
  689. netdev->name);
  690. }
  691. spin_unlock_irqrestore(&c2_port->tx_lock, flags);
  692. netdev->trans_start = jiffies;
  693. return NETDEV_TX_OK;
  694. }
  695. static void c2_tx_timeout(struct net_device *netdev)
  696. {
  697. struct c2_port *c2_port = netdev_priv(netdev);
  698. if (netif_msg_timer(c2_port))
  699. pr_debug("%s: tx timeout\n", netdev->name);
  700. c2_tx_clean(c2_port);
  701. }
  702. static int c2_change_mtu(struct net_device *netdev, int new_mtu)
  703. {
  704. int ret = 0;
  705. if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
  706. return -EINVAL;
  707. netdev->mtu = new_mtu;
  708. if (netif_running(netdev)) {
  709. c2_down(netdev);
  710. c2_up(netdev);
  711. }
  712. return ret;
  713. }
  714. static const struct net_device_ops c2_netdev = {
  715. .ndo_open = c2_up,
  716. .ndo_stop = c2_down,
  717. .ndo_start_xmit = c2_xmit_frame,
  718. .ndo_tx_timeout = c2_tx_timeout,
  719. .ndo_change_mtu = c2_change_mtu,
  720. .ndo_set_mac_address = eth_mac_addr,
  721. .ndo_validate_addr = eth_validate_addr,
  722. };
  723. /* Initialize network device */
  724. static struct net_device *c2_devinit(struct c2_dev *c2dev,
  725. void __iomem * mmio_addr)
  726. {
  727. struct c2_port *c2_port = NULL;
  728. struct net_device *netdev = alloc_etherdev(sizeof(*c2_port));
  729. if (!netdev) {
  730. pr_debug("c2_port etherdev alloc failed");
  731. return NULL;
  732. }
  733. SET_NETDEV_DEV(netdev, &c2dev->pcidev->dev);
  734. netdev->netdev_ops = &c2_netdev;
  735. netdev->watchdog_timeo = C2_TX_TIMEOUT;
  736. netdev->irq = c2dev->pcidev->irq;
  737. c2_port = netdev_priv(netdev);
  738. c2_port->netdev = netdev;
  739. c2_port->c2dev = c2dev;
  740. c2_port->msg_enable = netif_msg_init(debug, default_msg);
  741. c2_port->tx_ring.count = C2_NUM_TX_DESC;
  742. c2_port->rx_ring.count = C2_NUM_RX_DESC;
  743. spin_lock_init(&c2_port->tx_lock);
  744. /* Copy our 48-bit ethernet hardware address */
  745. memcpy_fromio(netdev->dev_addr, mmio_addr + C2_REGS_ENADDR, 6);
  746. /* Validate the MAC address */
  747. if (!is_valid_ether_addr(netdev->dev_addr)) {
  748. pr_debug("Invalid MAC Address\n");
  749. c2_print_macaddr(netdev);
  750. free_netdev(netdev);
  751. return NULL;
  752. }
  753. c2dev->netdev = netdev;
  754. return netdev;
  755. }
  756. static int __devinit c2_probe(struct pci_dev *pcidev,
  757. const struct pci_device_id *ent)
  758. {
  759. int ret = 0, i;
  760. unsigned long reg0_start, reg0_flags, reg0_len;
  761. unsigned long reg2_start, reg2_flags, reg2_len;
  762. unsigned long reg4_start, reg4_flags, reg4_len;
  763. unsigned kva_map_size;
  764. struct net_device *netdev = NULL;
  765. struct c2_dev *c2dev = NULL;
  766. void __iomem *mmio_regs = NULL;
  767. printk(KERN_INFO PFX "AMSO1100 Gigabit Ethernet driver v%s loaded\n",
  768. DRV_VERSION);
  769. /* Enable PCI device */
  770. ret = pci_enable_device(pcidev);
  771. if (ret) {
  772. printk(KERN_ERR PFX "%s: Unable to enable PCI device\n",
  773. pci_name(pcidev));
  774. goto bail0;
  775. }
  776. reg0_start = pci_resource_start(pcidev, BAR_0);
  777. reg0_len = pci_resource_len(pcidev, BAR_0);
  778. reg0_flags = pci_resource_flags(pcidev, BAR_0);
  779. reg2_start = pci_resource_start(pcidev, BAR_2);
  780. reg2_len = pci_resource_len(pcidev, BAR_2);
  781. reg2_flags = pci_resource_flags(pcidev, BAR_2);
  782. reg4_start = pci_resource_start(pcidev, BAR_4);
  783. reg4_len = pci_resource_len(pcidev, BAR_4);
  784. reg4_flags = pci_resource_flags(pcidev, BAR_4);
  785. pr_debug("BAR0 size = 0x%lX bytes\n", reg0_len);
  786. pr_debug("BAR2 size = 0x%lX bytes\n", reg2_len);
  787. pr_debug("BAR4 size = 0x%lX bytes\n", reg4_len);
  788. /* Make sure PCI base addr are MMIO */
  789. if (!(reg0_flags & IORESOURCE_MEM) ||
  790. !(reg2_flags & IORESOURCE_MEM) || !(reg4_flags & IORESOURCE_MEM)) {
  791. printk(KERN_ERR PFX "PCI regions not an MMIO resource\n");
  792. ret = -ENODEV;
  793. goto bail1;
  794. }
  795. /* Check for weird/broken PCI region reporting */
  796. if ((reg0_len < C2_REG0_SIZE) ||
  797. (reg2_len < C2_REG2_SIZE) || (reg4_len < C2_REG4_SIZE)) {
  798. printk(KERN_ERR PFX "Invalid PCI region sizes\n");
  799. ret = -ENODEV;
  800. goto bail1;
  801. }
  802. /* Reserve PCI I/O and memory resources */
  803. ret = pci_request_regions(pcidev, DRV_NAME);
  804. if (ret) {
  805. printk(KERN_ERR PFX "%s: Unable to request regions\n",
  806. pci_name(pcidev));
  807. goto bail1;
  808. }
  809. if ((sizeof(dma_addr_t) > 4)) {
  810. ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(64));
  811. if (ret < 0) {
  812. printk(KERN_ERR PFX "64b DMA configuration failed\n");
  813. goto bail2;
  814. }
  815. } else {
  816. ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(32));
  817. if (ret < 0) {
  818. printk(KERN_ERR PFX "32b DMA configuration failed\n");
  819. goto bail2;
  820. }
  821. }
  822. /* Enables bus-mastering on the device */
  823. pci_set_master(pcidev);
  824. /* Remap the adapter PCI registers in BAR4 */
  825. mmio_regs = ioremap_nocache(reg4_start + C2_PCI_REGS_OFFSET,
  826. sizeof(struct c2_adapter_pci_regs));
  827. if (!mmio_regs) {
  828. printk(KERN_ERR PFX
  829. "Unable to remap adapter PCI registers in BAR4\n");
  830. ret = -EIO;
  831. goto bail2;
  832. }
  833. /* Validate PCI regs magic */
  834. for (i = 0; i < sizeof(c2_magic); i++) {
  835. if (c2_magic[i] != readb(mmio_regs + C2_REGS_MAGIC + i)) {
  836. printk(KERN_ERR PFX "Downlevel Firmware boot loader "
  837. "[%d/%Zd: got 0x%x, exp 0x%x]. Use the cc_flash "
  838. "utility to update your boot loader\n",
  839. i + 1, sizeof(c2_magic),
  840. readb(mmio_regs + C2_REGS_MAGIC + i),
  841. c2_magic[i]);
  842. printk(KERN_ERR PFX "Adapter not claimed\n");
  843. iounmap(mmio_regs);
  844. ret = -EIO;
  845. goto bail2;
  846. }
  847. }
  848. /* Validate the adapter version */
  849. if (be32_to_cpu((__force __be32) readl(mmio_regs + C2_REGS_VERS)) != C2_VERSION) {
  850. printk(KERN_ERR PFX "Version mismatch "
  851. "[fw=%u, c2=%u], Adapter not claimed\n",
  852. be32_to_cpu((__force __be32) readl(mmio_regs + C2_REGS_VERS)),
  853. C2_VERSION);
  854. ret = -EINVAL;
  855. iounmap(mmio_regs);
  856. goto bail2;
  857. }
  858. /* Validate the adapter IVN */
  859. if (be32_to_cpu((__force __be32) readl(mmio_regs + C2_REGS_IVN)) != C2_IVN) {
  860. printk(KERN_ERR PFX "Downlevel FIrmware level. You should be using "
  861. "the OpenIB device support kit. "
  862. "[fw=0x%x, c2=0x%x], Adapter not claimed\n",
  863. be32_to_cpu((__force __be32) readl(mmio_regs + C2_REGS_IVN)),
  864. C2_IVN);
  865. ret = -EINVAL;
  866. iounmap(mmio_regs);
  867. goto bail2;
  868. }
  869. /* Allocate hardware structure */
  870. c2dev = (struct c2_dev *) ib_alloc_device(sizeof(*c2dev));
  871. if (!c2dev) {
  872. printk(KERN_ERR PFX "%s: Unable to alloc hardware struct\n",
  873. pci_name(pcidev));
  874. ret = -ENOMEM;
  875. iounmap(mmio_regs);
  876. goto bail2;
  877. }
  878. memset(c2dev, 0, sizeof(*c2dev));
  879. spin_lock_init(&c2dev->lock);
  880. c2dev->pcidev = pcidev;
  881. c2dev->cur_tx = 0;
  882. /* Get the last RX index */
  883. c2dev->cur_rx =
  884. (be32_to_cpu((__force __be32) readl(mmio_regs + C2_REGS_HRX_CUR)) -
  885. 0xffffc000) / sizeof(struct c2_rxp_desc);
  886. /* Request an interrupt line for the driver */
  887. ret = request_irq(pcidev->irq, c2_interrupt, IRQF_SHARED, DRV_NAME, c2dev);
  888. if (ret) {
  889. printk(KERN_ERR PFX "%s: requested IRQ %u is busy\n",
  890. pci_name(pcidev), pcidev->irq);
  891. iounmap(mmio_regs);
  892. goto bail3;
  893. }
  894. /* Set driver specific data */
  895. pci_set_drvdata(pcidev, c2dev);
  896. /* Initialize network device */
  897. if ((netdev = c2_devinit(c2dev, mmio_regs)) == NULL) {
  898. iounmap(mmio_regs);
  899. goto bail4;
  900. }
  901. /* Save off the actual size prior to unmapping mmio_regs */
  902. kva_map_size = be32_to_cpu((__force __be32) readl(mmio_regs + C2_REGS_PCI_WINSIZE));
  903. /* Unmap the adapter PCI registers in BAR4 */
  904. iounmap(mmio_regs);
  905. /* Register network device */
  906. ret = register_netdev(netdev);
  907. if (ret) {
  908. printk(KERN_ERR PFX "Unable to register netdev, ret = %d\n",
  909. ret);
  910. goto bail5;
  911. }
  912. /* Disable network packets */
  913. netif_stop_queue(netdev);
  914. /* Remap the adapter HRXDQ PA space to kernel VA space */
  915. c2dev->mmio_rxp_ring = ioremap_nocache(reg4_start + C2_RXP_HRXDQ_OFFSET,
  916. C2_RXP_HRXDQ_SIZE);
  917. if (!c2dev->mmio_rxp_ring) {
  918. printk(KERN_ERR PFX "Unable to remap MMIO HRXDQ region\n");
  919. ret = -EIO;
  920. goto bail6;
  921. }
  922. /* Remap the adapter HTXDQ PA space to kernel VA space */
  923. c2dev->mmio_txp_ring = ioremap_nocache(reg4_start + C2_TXP_HTXDQ_OFFSET,
  924. C2_TXP_HTXDQ_SIZE);
  925. if (!c2dev->mmio_txp_ring) {
  926. printk(KERN_ERR PFX "Unable to remap MMIO HTXDQ region\n");
  927. ret = -EIO;
  928. goto bail7;
  929. }
  930. /* Save off the current RX index in the last 4 bytes of the TXP Ring */
  931. C2_SET_CUR_RX(c2dev, c2dev->cur_rx);
  932. /* Remap the PCI registers in adapter BAR0 to kernel VA space */
  933. c2dev->regs = ioremap_nocache(reg0_start, reg0_len);
  934. if (!c2dev->regs) {
  935. printk(KERN_ERR PFX "Unable to remap BAR0\n");
  936. ret = -EIO;
  937. goto bail8;
  938. }
  939. /* Remap the PCI registers in adapter BAR4 to kernel VA space */
  940. c2dev->pa = reg4_start + C2_PCI_REGS_OFFSET;
  941. c2dev->kva = ioremap_nocache(reg4_start + C2_PCI_REGS_OFFSET,
  942. kva_map_size);
  943. if (!c2dev->kva) {
  944. printk(KERN_ERR PFX "Unable to remap BAR4\n");
  945. ret = -EIO;
  946. goto bail9;
  947. }
  948. /* Print out the MAC address */
  949. c2_print_macaddr(netdev);
  950. ret = c2_rnic_init(c2dev);
  951. if (ret) {
  952. printk(KERN_ERR PFX "c2_rnic_init failed: %d\n", ret);
  953. goto bail10;
  954. }
  955. if (c2_register_device(c2dev))
  956. goto bail10;
  957. return 0;
  958. bail10:
  959. iounmap(c2dev->kva);
  960. bail9:
  961. iounmap(c2dev->regs);
  962. bail8:
  963. iounmap(c2dev->mmio_txp_ring);
  964. bail7:
  965. iounmap(c2dev->mmio_rxp_ring);
  966. bail6:
  967. unregister_netdev(netdev);
  968. bail5:
  969. free_netdev(netdev);
  970. bail4:
  971. free_irq(pcidev->irq, c2dev);
  972. bail3:
  973. ib_dealloc_device(&c2dev->ibdev);
  974. bail2:
  975. pci_release_regions(pcidev);
  976. bail1:
  977. pci_disable_device(pcidev);
  978. bail0:
  979. return ret;
  980. }
  981. static void __devexit c2_remove(struct pci_dev *pcidev)
  982. {
  983. struct c2_dev *c2dev = pci_get_drvdata(pcidev);
  984. struct net_device *netdev = c2dev->netdev;
  985. /* Unregister with OpenIB */
  986. c2_unregister_device(c2dev);
  987. /* Clean up the RNIC resources */
  988. c2_rnic_term(c2dev);
  989. /* Remove network device from the kernel */
  990. unregister_netdev(netdev);
  991. /* Free network device */
  992. free_netdev(netdev);
  993. /* Free the interrupt line */
  994. free_irq(pcidev->irq, c2dev);
  995. /* missing: Turn LEDs off here */
  996. /* Unmap adapter PA space */
  997. iounmap(c2dev->kva);
  998. iounmap(c2dev->regs);
  999. iounmap(c2dev->mmio_txp_ring);
  1000. iounmap(c2dev->mmio_rxp_ring);
  1001. /* Free the hardware structure */
  1002. ib_dealloc_device(&c2dev->ibdev);
  1003. /* Release reserved PCI I/O and memory resources */
  1004. pci_release_regions(pcidev);
  1005. /* Disable PCI device */
  1006. pci_disable_device(pcidev);
  1007. /* Clear driver specific data */
  1008. pci_set_drvdata(pcidev, NULL);
  1009. }
  1010. static struct pci_driver c2_pci_driver = {
  1011. .name = DRV_NAME,
  1012. .id_table = c2_pci_table,
  1013. .probe = c2_probe,
  1014. .remove = __devexit_p(c2_remove),
  1015. };
  1016. static int __init c2_init_module(void)
  1017. {
  1018. return pci_register_driver(&c2_pci_driver);
  1019. }
  1020. static void __exit c2_exit_module(void)
  1021. {
  1022. pci_unregister_driver(&c2_pci_driver);
  1023. }
  1024. module_init(c2_init_module);
  1025. module_exit(c2_exit_module);