hwregs.c 14 KB

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  1. /*******************************************************************************
  2. *
  3. * Module Name: hwregs - Read/write access functions for the various ACPI
  4. * control and status registers.
  5. *
  6. ******************************************************************************/
  7. /*
  8. * Copyright (C) 2000 - 2008, Intel Corp.
  9. * All rights reserved.
  10. *
  11. * Redistribution and use in source and binary forms, with or without
  12. * modification, are permitted provided that the following conditions
  13. * are met:
  14. * 1. Redistributions of source code must retain the above copyright
  15. * notice, this list of conditions, and the following disclaimer,
  16. * without modification.
  17. * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  18. * substantially similar to the "NO WARRANTY" disclaimer below
  19. * ("Disclaimer") and any redistribution must be conditioned upon
  20. * including a substantially similar Disclaimer requirement for further
  21. * binary redistribution.
  22. * 3. Neither the names of the above-listed copyright holders nor the names
  23. * of any contributors may be used to endorse or promote products derived
  24. * from this software without specific prior written permission.
  25. *
  26. * Alternatively, this software may be distributed under the terms of the
  27. * GNU General Public License ("GPL") version 2 as published by the Free
  28. * Software Foundation.
  29. *
  30. * NO WARRANTY
  31. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  32. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  33. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  34. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  35. * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  36. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  37. * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  38. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  39. * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  40. * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  41. * POSSIBILITY OF SUCH DAMAGES.
  42. */
  43. #include <acpi/acpi.h>
  44. #include "accommon.h"
  45. #include "acnamesp.h"
  46. #include "acevents.h"
  47. #define _COMPONENT ACPI_HARDWARE
  48. ACPI_MODULE_NAME("hwregs")
  49. /* Local Prototypes */
  50. static acpi_status
  51. acpi_hw_read_multiple(u32 *value,
  52. struct acpi_generic_address *register_a,
  53. struct acpi_generic_address *register_b);
  54. static acpi_status
  55. acpi_hw_write_multiple(u32 value,
  56. struct acpi_generic_address *register_a,
  57. struct acpi_generic_address *register_b);
  58. /*******************************************************************************
  59. *
  60. * FUNCTION: acpi_hw_clear_acpi_status
  61. *
  62. * PARAMETERS: None
  63. *
  64. * RETURN: Status
  65. *
  66. * DESCRIPTION: Clears all fixed and general purpose status bits
  67. *
  68. ******************************************************************************/
  69. acpi_status acpi_hw_clear_acpi_status(void)
  70. {
  71. acpi_status status;
  72. acpi_cpu_flags lock_flags = 0;
  73. ACPI_FUNCTION_TRACE(hw_clear_acpi_status);
  74. ACPI_DEBUG_PRINT((ACPI_DB_IO, "About to write %04X to %0llX\n",
  75. ACPI_BITMASK_ALL_FIXED_STATUS,
  76. acpi_gbl_xpm1a_status.address));
  77. lock_flags = acpi_os_acquire_lock(acpi_gbl_hardware_lock);
  78. /* Clear the fixed events in PM1 A/B */
  79. status = acpi_hw_register_write(ACPI_REGISTER_PM1_STATUS,
  80. ACPI_BITMASK_ALL_FIXED_STATUS);
  81. if (ACPI_FAILURE(status)) {
  82. goto unlock_and_exit;
  83. }
  84. /* Clear the GPE Bits in all GPE registers in all GPE blocks */
  85. status = acpi_ev_walk_gpe_list(acpi_hw_clear_gpe_block, NULL);
  86. unlock_and_exit:
  87. acpi_os_release_lock(acpi_gbl_hardware_lock, lock_flags);
  88. return_ACPI_STATUS(status);
  89. }
  90. /*******************************************************************************
  91. *
  92. * FUNCTION: acpi_hw_get_register_bit_mask
  93. *
  94. * PARAMETERS: register_id - Index of ACPI Register to access
  95. *
  96. * RETURN: The bitmask to be used when accessing the register
  97. *
  98. * DESCRIPTION: Map register_id into a register bitmask.
  99. *
  100. ******************************************************************************/
  101. struct acpi_bit_register_info *acpi_hw_get_bit_register_info(u32 register_id)
  102. {
  103. ACPI_FUNCTION_ENTRY();
  104. if (register_id > ACPI_BITREG_MAX) {
  105. ACPI_ERROR((AE_INFO, "Invalid BitRegister ID: %X",
  106. register_id));
  107. return (NULL);
  108. }
  109. return (&acpi_gbl_bit_register_info[register_id]);
  110. }
  111. /******************************************************************************
  112. *
  113. * FUNCTION: acpi_hw_write_pm1_control
  114. *
  115. * PARAMETERS: pm1a_control - Value to be written to PM1A control
  116. * pm1b_control - Value to be written to PM1B control
  117. *
  118. * RETURN: Status
  119. *
  120. * DESCRIPTION: Write the PM1 A/B control registers. These registers are
  121. * different than than the PM1 A/B status and enable registers
  122. * in that different values can be written to the A/B registers.
  123. * Most notably, the SLP_TYP bits can be different, as per the
  124. * values returned from the _Sx predefined methods.
  125. *
  126. ******************************************************************************/
  127. acpi_status acpi_hw_write_pm1_control(u32 pm1a_control, u32 pm1b_control)
  128. {
  129. acpi_status status;
  130. ACPI_FUNCTION_TRACE(hw_write_pm1_control);
  131. status = acpi_write(pm1a_control, &acpi_gbl_FADT.xpm1a_control_block);
  132. if (ACPI_FAILURE(status)) {
  133. return_ACPI_STATUS(status);
  134. }
  135. if (acpi_gbl_FADT.xpm1b_control_block.address) {
  136. status =
  137. acpi_write(pm1b_control,
  138. &acpi_gbl_FADT.xpm1b_control_block);
  139. }
  140. return_ACPI_STATUS(status);
  141. }
  142. /******************************************************************************
  143. *
  144. * FUNCTION: acpi_hw_register_read
  145. *
  146. * PARAMETERS: register_id - ACPI Register ID
  147. * return_value - Where the register value is returned
  148. *
  149. * RETURN: Status and the value read.
  150. *
  151. * DESCRIPTION: Read from the specified ACPI register
  152. *
  153. ******************************************************************************/
  154. acpi_status
  155. acpi_hw_register_read(u32 register_id, u32 * return_value)
  156. {
  157. u32 value = 0;
  158. acpi_status status;
  159. ACPI_FUNCTION_TRACE(hw_register_read);
  160. switch (register_id) {
  161. case ACPI_REGISTER_PM1_STATUS: /* PM1 A/B: 16-bit access each */
  162. status = acpi_hw_read_multiple(&value,
  163. &acpi_gbl_xpm1a_status,
  164. &acpi_gbl_xpm1b_status);
  165. break;
  166. case ACPI_REGISTER_PM1_ENABLE: /* PM1 A/B: 16-bit access each */
  167. status = acpi_hw_read_multiple(&value,
  168. &acpi_gbl_xpm1a_enable,
  169. &acpi_gbl_xpm1b_enable);
  170. break;
  171. case ACPI_REGISTER_PM1_CONTROL: /* PM1 A/B: 16-bit access each */
  172. status = acpi_hw_read_multiple(&value,
  173. &acpi_gbl_FADT.
  174. xpm1a_control_block,
  175. &acpi_gbl_FADT.
  176. xpm1b_control_block);
  177. /*
  178. * Zero the write-only bits. From the ACPI specification, "Hardware
  179. * Write-Only Bits": "Upon reads to registers with write-only bits,
  180. * software masks out all write-only bits."
  181. */
  182. value &= ~ACPI_PM1_CONTROL_WRITEONLY_BITS;
  183. break;
  184. case ACPI_REGISTER_PM2_CONTROL: /* 8-bit access */
  185. status = acpi_read(&value, &acpi_gbl_FADT.xpm2_control_block);
  186. break;
  187. case ACPI_REGISTER_PM_TIMER: /* 32-bit access */
  188. status = acpi_read(&value, &acpi_gbl_FADT.xpm_timer_block);
  189. break;
  190. case ACPI_REGISTER_SMI_COMMAND_BLOCK: /* 8-bit access */
  191. status =
  192. acpi_hw_read_port(acpi_gbl_FADT.smi_command, &value, 8);
  193. break;
  194. default:
  195. ACPI_ERROR((AE_INFO, "Unknown Register ID: %X", register_id));
  196. status = AE_BAD_PARAMETER;
  197. break;
  198. }
  199. if (ACPI_SUCCESS(status)) {
  200. *return_value = value;
  201. }
  202. return_ACPI_STATUS(status);
  203. }
  204. /******************************************************************************
  205. *
  206. * FUNCTION: acpi_hw_register_write
  207. *
  208. * PARAMETERS: register_id - ACPI Register ID
  209. * Value - The value to write
  210. *
  211. * RETURN: Status
  212. *
  213. * DESCRIPTION: Write to the specified ACPI register
  214. *
  215. * NOTE: In accordance with the ACPI specification, this function automatically
  216. * preserves the value of the following bits, meaning that these bits cannot be
  217. * changed via this interface:
  218. *
  219. * PM1_CONTROL[0] = SCI_EN
  220. * PM1_CONTROL[9]
  221. * PM1_STATUS[11]
  222. *
  223. * ACPI References:
  224. * 1) Hardware Ignored Bits: When software writes to a register with ignored
  225. * bit fields, it preserves the ignored bit fields
  226. * 2) SCI_EN: OSPM always preserves this bit position
  227. *
  228. ******************************************************************************/
  229. acpi_status acpi_hw_register_write(u32 register_id, u32 value)
  230. {
  231. acpi_status status;
  232. u32 read_value;
  233. ACPI_FUNCTION_TRACE(hw_register_write);
  234. switch (register_id) {
  235. case ACPI_REGISTER_PM1_STATUS: /* PM1 A/B: 16-bit access each */
  236. /*
  237. * Handle the "ignored" bit in PM1 Status. According to the ACPI
  238. * specification, ignored bits are to be preserved when writing.
  239. * Normally, this would mean a read/modify/write sequence. However,
  240. * preserving a bit in the status register is different. Writing a
  241. * one clears the status, and writing a zero preserves the status.
  242. * Therefore, we must always write zero to the ignored bit.
  243. *
  244. * This behavior is clarified in the ACPI 4.0 specification.
  245. */
  246. value &= ~ACPI_PM1_STATUS_PRESERVED_BITS;
  247. status = acpi_hw_write_multiple(value,
  248. &acpi_gbl_xpm1a_status,
  249. &acpi_gbl_xpm1b_status);
  250. break;
  251. case ACPI_REGISTER_PM1_ENABLE: /* PM1 A/B: 16-bit access */
  252. status = acpi_hw_write_multiple(value,
  253. &acpi_gbl_xpm1a_enable,
  254. &acpi_gbl_xpm1b_enable);
  255. break;
  256. case ACPI_REGISTER_PM1_CONTROL: /* PM1 A/B: 16-bit access each */
  257. /*
  258. * Perform a read first to preserve certain bits (per ACPI spec)
  259. * Note: This includes SCI_EN, we never want to change this bit
  260. */
  261. status = acpi_hw_read_multiple(&read_value,
  262. &acpi_gbl_FADT.
  263. xpm1a_control_block,
  264. &acpi_gbl_FADT.
  265. xpm1b_control_block);
  266. if (ACPI_FAILURE(status)) {
  267. goto exit;
  268. }
  269. /* Insert the bits to be preserved */
  270. ACPI_INSERT_BITS(value, ACPI_PM1_CONTROL_PRESERVED_BITS,
  271. read_value);
  272. /* Now we can write the data */
  273. status = acpi_hw_write_multiple(value,
  274. &acpi_gbl_FADT.
  275. xpm1a_control_block,
  276. &acpi_gbl_FADT.
  277. xpm1b_control_block);
  278. break;
  279. case ACPI_REGISTER_PM2_CONTROL: /* 8-bit access */
  280. /*
  281. * For control registers, all reserved bits must be preserved,
  282. * as per the ACPI spec.
  283. */
  284. status =
  285. acpi_read(&read_value, &acpi_gbl_FADT.xpm2_control_block);
  286. if (ACPI_FAILURE(status)) {
  287. goto exit;
  288. }
  289. /* Insert the bits to be preserved */
  290. ACPI_INSERT_BITS(value, ACPI_PM2_CONTROL_PRESERVED_BITS,
  291. read_value);
  292. status = acpi_write(value, &acpi_gbl_FADT.xpm2_control_block);
  293. break;
  294. case ACPI_REGISTER_PM_TIMER: /* 32-bit access */
  295. status = acpi_write(value, &acpi_gbl_FADT.xpm_timer_block);
  296. break;
  297. case ACPI_REGISTER_SMI_COMMAND_BLOCK: /* 8-bit access */
  298. /* SMI_CMD is currently always in IO space */
  299. status =
  300. acpi_hw_write_port(acpi_gbl_FADT.smi_command, value, 8);
  301. break;
  302. default:
  303. ACPI_ERROR((AE_INFO, "Unknown Register ID: %X", register_id));
  304. status = AE_BAD_PARAMETER;
  305. break;
  306. }
  307. exit:
  308. return_ACPI_STATUS(status);
  309. }
  310. /******************************************************************************
  311. *
  312. * FUNCTION: acpi_hw_read_multiple
  313. *
  314. * PARAMETERS: Value - Where the register value is returned
  315. * register_a - First ACPI register (required)
  316. * register_b - Second ACPI register (optional)
  317. *
  318. * RETURN: Status
  319. *
  320. * DESCRIPTION: Read from the specified two-part ACPI register (such as PM1 A/B)
  321. *
  322. ******************************************************************************/
  323. static acpi_status
  324. acpi_hw_read_multiple(u32 *value,
  325. struct acpi_generic_address *register_a,
  326. struct acpi_generic_address *register_b)
  327. {
  328. u32 value_a = 0;
  329. u32 value_b = 0;
  330. acpi_status status;
  331. /* The first register is always required */
  332. status = acpi_read(&value_a, register_a);
  333. if (ACPI_FAILURE(status)) {
  334. return (status);
  335. }
  336. /* Second register is optional */
  337. if (register_b->address) {
  338. status = acpi_read(&value_b, register_b);
  339. if (ACPI_FAILURE(status)) {
  340. return (status);
  341. }
  342. }
  343. /*
  344. * OR the two return values together. No shifting or masking is necessary,
  345. * because of how the PM1 registers are defined in the ACPI specification:
  346. *
  347. * "Although the bits can be split between the two register blocks (each
  348. * register block has a unique pointer within the FADT), the bit positions
  349. * are maintained. The register block with unimplemented bits (that is,
  350. * those implemented in the other register block) always returns zeros,
  351. * and writes have no side effects"
  352. */
  353. *value = (value_a | value_b);
  354. return (AE_OK);
  355. }
  356. /******************************************************************************
  357. *
  358. * FUNCTION: acpi_hw_write_multiple
  359. *
  360. * PARAMETERS: Value - The value to write
  361. * register_a - First ACPI register (required)
  362. * register_b - Second ACPI register (optional)
  363. *
  364. * RETURN: Status
  365. *
  366. * DESCRIPTION: Write to the specified two-part ACPI register (such as PM1 A/B)
  367. *
  368. ******************************************************************************/
  369. static acpi_status
  370. acpi_hw_write_multiple(u32 value,
  371. struct acpi_generic_address *register_a,
  372. struct acpi_generic_address *register_b)
  373. {
  374. acpi_status status;
  375. /* The first register is always required */
  376. status = acpi_write(value, register_a);
  377. if (ACPI_FAILURE(status)) {
  378. return (status);
  379. }
  380. /*
  381. * Second register is optional
  382. *
  383. * No bit shifting or clearing is necessary, because of how the PM1
  384. * registers are defined in the ACPI specification:
  385. *
  386. * "Although the bits can be split between the two register blocks (each
  387. * register block has a unique pointer within the FADT), the bit positions
  388. * are maintained. The register block with unimplemented bits (that is,
  389. * those implemented in the other register block) always returns zeros,
  390. * and writes have no side effects"
  391. */
  392. if (register_b->address) {
  393. status = acpi_write(value, register_b);
  394. }
  395. return (status);
  396. }