time_64.c 3.3 KB

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  1. /*
  2. * "High Precision Event Timer" based timekeeping.
  3. *
  4. * Copyright (c) 1991,1992,1995 Linus Torvalds
  5. * Copyright (c) 1994 Alan Modra
  6. * Copyright (c) 1995 Markus Kuhn
  7. * Copyright (c) 1996 Ingo Molnar
  8. * Copyright (c) 1998 Andrea Arcangeli
  9. * Copyright (c) 2002,2006 Vojtech Pavlik
  10. * Copyright (c) 2003 Andi Kleen
  11. * RTC support code taken from arch/i386/kernel/timers/time_hpet.c
  12. */
  13. #include <linux/clockchips.h>
  14. #include <linux/init.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/module.h>
  17. #include <linux/time.h>
  18. #include <linux/mca.h>
  19. #include <linux/nmi.h>
  20. #include <asm/i8253.h>
  21. #include <asm/hpet.h>
  22. #include <asm/vgtod.h>
  23. #include <asm/time.h>
  24. #include <asm/timer.h>
  25. volatile unsigned long __jiffies __section_jiffies = INITIAL_JIFFIES;
  26. unsigned long profile_pc(struct pt_regs *regs)
  27. {
  28. unsigned long pc = instruction_pointer(regs);
  29. /* Assume the lock function has either no stack frame or a copy
  30. of flags from PUSHF
  31. Eflags always has bits 22 and up cleared unlike kernel addresses. */
  32. if (!user_mode_vm(regs) && in_lock_functions(pc)) {
  33. #ifdef CONFIG_FRAME_POINTER
  34. return *(unsigned long *)(regs->bp + sizeof(long));
  35. #else
  36. unsigned long *sp = (unsigned long *)regs->sp;
  37. if (sp[0] >> 22)
  38. return sp[0];
  39. if (sp[1] >> 22)
  40. return sp[1];
  41. #endif
  42. }
  43. return pc;
  44. }
  45. EXPORT_SYMBOL(profile_pc);
  46. static irqreturn_t timer_interrupt(int irq, void *dev_id)
  47. {
  48. inc_irq_stat(irq0_irqs);
  49. global_clock_event->event_handler(global_clock_event);
  50. #ifdef CONFIG_MCA
  51. if (MCA_bus) {
  52. u8 irq_v = inb_p(0x61); /* read the current state */
  53. outb_p(irq_v|0x80, 0x61); /* reset the IRQ */
  54. }
  55. #endif
  56. return IRQ_HANDLED;
  57. }
  58. /* calibrate_cpu is used on systems with fixed rate TSCs to determine
  59. * processor frequency */
  60. #define TICK_COUNT 100000000
  61. unsigned long __init calibrate_cpu(void)
  62. {
  63. int tsc_start, tsc_now;
  64. int i, no_ctr_free;
  65. unsigned long evntsel3 = 0, pmc3 = 0, pmc_now = 0;
  66. unsigned long flags;
  67. for (i = 0; i < 4; i++)
  68. if (avail_to_resrv_perfctr_nmi_bit(i))
  69. break;
  70. no_ctr_free = (i == 4);
  71. if (no_ctr_free) {
  72. WARN(1, KERN_WARNING "Warning: AMD perfctrs busy ... "
  73. "cpu_khz value may be incorrect.\n");
  74. i = 3;
  75. rdmsrl(MSR_K7_EVNTSEL3, evntsel3);
  76. wrmsrl(MSR_K7_EVNTSEL3, 0);
  77. rdmsrl(MSR_K7_PERFCTR3, pmc3);
  78. } else {
  79. reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i);
  80. reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
  81. }
  82. local_irq_save(flags);
  83. /* start measuring cycles, incrementing from 0 */
  84. wrmsrl(MSR_K7_PERFCTR0 + i, 0);
  85. wrmsrl(MSR_K7_EVNTSEL0 + i, 1 << 22 | 3 << 16 | 0x76);
  86. rdtscl(tsc_start);
  87. do {
  88. rdmsrl(MSR_K7_PERFCTR0 + i, pmc_now);
  89. tsc_now = get_cycles();
  90. } while ((tsc_now - tsc_start) < TICK_COUNT);
  91. local_irq_restore(flags);
  92. if (no_ctr_free) {
  93. wrmsrl(MSR_K7_EVNTSEL3, 0);
  94. wrmsrl(MSR_K7_PERFCTR3, pmc3);
  95. wrmsrl(MSR_K7_EVNTSEL3, evntsel3);
  96. } else {
  97. release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
  98. release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
  99. }
  100. return pmc_now * tsc_khz / (tsc_now - tsc_start);
  101. }
  102. static struct irqaction irq0 = {
  103. .handler = timer_interrupt,
  104. .flags = IRQF_DISABLED | IRQF_IRQPOLL | IRQF_NOBALANCING | IRQF_TIMER,
  105. .name = "timer"
  106. };
  107. void __init hpet_time_init(void)
  108. {
  109. if (!hpet_enable())
  110. setup_pit_timer();
  111. setup_irq(0, &irq0);
  112. }
  113. void __init time_init(void)
  114. {
  115. tsc_init();
  116. late_time_init = choose_time_init();
  117. }