irqinit_64.c 4.5 KB

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  1. #include <linux/linkage.h>
  2. #include <linux/errno.h>
  3. #include <linux/signal.h>
  4. #include <linux/sched.h>
  5. #include <linux/ioport.h>
  6. #include <linux/interrupt.h>
  7. #include <linux/timex.h>
  8. #include <linux/slab.h>
  9. #include <linux/random.h>
  10. #include <linux/init.h>
  11. #include <linux/kernel_stat.h>
  12. #include <linux/sysdev.h>
  13. #include <linux/bitops.h>
  14. #include <linux/acpi.h>
  15. #include <linux/io.h>
  16. #include <linux/delay.h>
  17. #include <asm/atomic.h>
  18. #include <asm/system.h>
  19. #include <asm/hw_irq.h>
  20. #include <asm/pgtable.h>
  21. #include <asm/desc.h>
  22. #include <asm/apic.h>
  23. #include <asm/i8259.h>
  24. /*
  25. * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
  26. * (these are usually mapped to vectors 0x30-0x3f)
  27. */
  28. /*
  29. * The IO-APIC gives us many more interrupt sources. Most of these
  30. * are unused but an SMP system is supposed to have enough memory ...
  31. * sometimes (mostly wrt. hw bugs) we get corrupted vectors all
  32. * across the spectrum, so we really want to be prepared to get all
  33. * of these. Plus, more powerful systems might have more than 64
  34. * IO-APIC registers.
  35. *
  36. * (these are usually mapped into the 0x30-0xff vector range)
  37. */
  38. /*
  39. * IRQ2 is cascade interrupt to second interrupt controller
  40. */
  41. static struct irqaction irq2 = {
  42. .handler = no_action,
  43. .name = "cascade",
  44. };
  45. DEFINE_PER_CPU(vector_irq_t, vector_irq) = {
  46. [0 ... IRQ0_VECTOR - 1] = -1,
  47. [IRQ0_VECTOR] = 0,
  48. [IRQ1_VECTOR] = 1,
  49. [IRQ2_VECTOR] = 2,
  50. [IRQ3_VECTOR] = 3,
  51. [IRQ4_VECTOR] = 4,
  52. [IRQ5_VECTOR] = 5,
  53. [IRQ6_VECTOR] = 6,
  54. [IRQ7_VECTOR] = 7,
  55. [IRQ8_VECTOR] = 8,
  56. [IRQ9_VECTOR] = 9,
  57. [IRQ10_VECTOR] = 10,
  58. [IRQ11_VECTOR] = 11,
  59. [IRQ12_VECTOR] = 12,
  60. [IRQ13_VECTOR] = 13,
  61. [IRQ14_VECTOR] = 14,
  62. [IRQ15_VECTOR] = 15,
  63. [IRQ15_VECTOR + 1 ... NR_VECTORS - 1] = -1
  64. };
  65. int vector_used_by_percpu_irq(unsigned int vector)
  66. {
  67. int cpu;
  68. for_each_online_cpu(cpu) {
  69. if (per_cpu(vector_irq, cpu)[vector] != -1)
  70. return 1;
  71. }
  72. return 0;
  73. }
  74. static void __init init_ISA_irqs(void)
  75. {
  76. int i;
  77. init_bsp_APIC();
  78. init_8259A(0);
  79. for (i = 0; i < NR_IRQS_LEGACY; i++) {
  80. struct irq_desc *desc = irq_to_desc(i);
  81. desc->status = IRQ_DISABLED;
  82. desc->action = NULL;
  83. desc->depth = 1;
  84. /*
  85. * 16 old-style INTA-cycle interrupts:
  86. */
  87. set_irq_chip_and_handler_name(i, &i8259A_chip,
  88. handle_level_irq, "XT");
  89. }
  90. }
  91. void init_IRQ(void) __attribute__((weak, alias("native_init_IRQ")));
  92. static void __init smp_intr_init(void)
  93. {
  94. #ifdef CONFIG_SMP
  95. /*
  96. * The reschedule interrupt is a CPU-to-CPU reschedule-helper
  97. * IPI, driven by wakeup.
  98. */
  99. alloc_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
  100. /* IPIs for invalidation */
  101. alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+0, invalidate_interrupt0);
  102. alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+1, invalidate_interrupt1);
  103. alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+2, invalidate_interrupt2);
  104. alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+3, invalidate_interrupt3);
  105. alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+4, invalidate_interrupt4);
  106. alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+5, invalidate_interrupt5);
  107. alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+6, invalidate_interrupt6);
  108. alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+7, invalidate_interrupt7);
  109. /* IPI for generic function call */
  110. alloc_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
  111. /* IPI for generic single function call */
  112. alloc_intr_gate(CALL_FUNCTION_SINGLE_VECTOR,
  113. call_function_single_interrupt);
  114. /* Low priority IPI to cleanup after moving an irq */
  115. set_intr_gate(IRQ_MOVE_CLEANUP_VECTOR, irq_move_cleanup_interrupt);
  116. set_bit(IRQ_MOVE_CLEANUP_VECTOR, used_vectors);
  117. #endif
  118. }
  119. static void __init apic_intr_init(void)
  120. {
  121. smp_intr_init();
  122. alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
  123. alloc_intr_gate(THRESHOLD_APIC_VECTOR, threshold_interrupt);
  124. /* self generated IPI for local APIC timer */
  125. alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
  126. /* generic IPI for platform specific use */
  127. alloc_intr_gate(GENERIC_INTERRUPT_VECTOR, generic_interrupt);
  128. /* IPI vectors for APIC spurious and error interrupts */
  129. alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
  130. alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
  131. }
  132. void __init native_init_IRQ(void)
  133. {
  134. int i;
  135. init_ISA_irqs();
  136. /*
  137. * Cover the whole vector space, no vector can escape
  138. * us. (some of these will be overridden and become
  139. * 'special' SMP interrupts)
  140. */
  141. for (i = 0; i < (NR_VECTORS - FIRST_EXTERNAL_VECTOR); i++) {
  142. int vector = FIRST_EXTERNAL_VECTOR + i;
  143. if (vector != IA32_SYSCALL_VECTOR)
  144. set_intr_gate(vector, interrupt[i]);
  145. }
  146. apic_intr_init();
  147. if (!acpi_ioapic)
  148. setup_irq(2, &irq2);
  149. }