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arch
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sh
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include
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cpu-sh4
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cpu
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timer.h

timer.h 1.7 KB
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  1. /*
    2. 

  2.  * include/asm-sh/cpu-sh4/timer.h
    3. 

  3.  *
    4. 

  4.  * Copyright (C) 2004 Lineo Solutions, Inc.
    5. 

  5.  *
    6. 

  6.  * This file is subject to the terms and conditions of the GNU General Public
    7. 

  7.  * License.  See the file "COPYING" in the main directory of this archive
    8. 

  8.  * for more details.
    9. 

  9.  */
    10. 

  10. #ifndef __ASM_CPU_SH4_TIMER_H
    11. 

  11. #define __ASM_CPU_SH4_TIMER_H
    12. 

  12. 

  13. /*
    14. 

  14.  * ---------------------------------------------------------------------------
    15. 

  15.  * TMU Common definitions for SH4 processors
    16. 

  16.  *	SH7750S/SH7750R
    17. 

  17.  *	SH7751/SH7751R
    18. 

  18.  *	SH7760
    19. 

  19.  *	SH-X3
    20. 

  20.  * ---------------------------------------------------------------------------
    21. 

  21.  */
    22. 

  22. #ifdef CONFIG_CPU_SUBTYPE_SHX3
    23. 

  23. #define TMU_012_BASE	0xffc10000
    24. 

  24. #define TMU_345_BASE	0xffc20000
    25. 

  25. #else
    26. 

  26. #define TMU_012_BASE	0xffd80000
    27. 

  27. #define TMU_345_BASE	0xfe100000
    28. 

  28. #endif
    29. 

  29. 

  30. #define TMU_TOCR	TMU_012_BASE	/* Not supported on all CPUs */
    31. 

  31. 

  32. #define TMU_012_TSTR	(TMU_012_BASE + 0x04)
    33. 

  33. #define TMU_345_TSTR	(TMU_345_BASE + 0x04)
    34. 

  34. 

  35. #define TMU0_TCOR	(TMU_012_BASE + 0x08)
    36. 

  36. #define TMU0_TCNT	(TMU_012_BASE + 0x0c)
    37. 

  37. #define TMU0_TCR	(TMU_012_BASE + 0x10)
    38. 

  38. 

  39. #define TMU1_TCOR       (TMU_012_BASE + 0x14)
    40. 

  40. #define TMU1_TCNT       (TMU_012_BASE + 0x18)
    41. 

  41. #define TMU1_TCR        (TMU_012_BASE + 0x1c)
    42. 

  42. 

  43. #define TMU2_TCOR       (TMU_012_BASE + 0x20)
    44. 

  44. #define TMU2_TCNT       (TMU_012_BASE + 0x24)
    45. 

  45. #define TMU2_TCR	(TMU_012_BASE + 0x28)
    46. 

  46. #define TMU2_TCPR	(TMU_012_BASE + 0x2c)
    47. 

  47. 

  48. #define TMU3_TCOR	(TMU_345_BASE + 0x08)
    49. 

  49. #define TMU3_TCNT	(TMU_345_BASE + 0x0c)
    50. 

  50. #define TMU3_TCR	(TMU_345_BASE + 0x10)
    51. 

  51. 

  52. #define TMU4_TCOR	(TMU_345_BASE + 0x14)
    53. 

  53. #define TMU4_TCNT	(TMU_345_BASE + 0x18)
    54. 

  54. #define TMU4_TCR	(TMU_345_BASE + 0x1c)
    55. 

  55. 

  56. #define TMU5_TCOR	(TMU_345_BASE + 0x20)
    57. 

  57. #define TMU5_TCNT	(TMU_345_BASE + 0x24)
    58. 

  58. #define TMU5_TCR	(TMU_345_BASE + 0x28)
    59. 

  59. 

  60. #endif /* __ASM_CPU_SH4_TIMER_H */
    61.