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linux-vybrid_pu...
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arch
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sh
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include
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cpu-sh3
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cpu
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timer.h

timer.h 2.0 KB
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  1. /*
    2. 

  2.  * include/asm-sh/cpu-sh3/timer.h
    3. 

  3.  *
    4. 

  4.  * Copyright (C) 2004 Lineo Solutions, Inc.
    5. 

  5.  *
    6. 

  6.  * This file is subject to the terms and conditions of the GNU General Public
    7. 

  7.  * License.  See the file "COPYING" in the main directory of this archive
    8. 

  8.  * for more details.
    9. 

  9.  */
    10. 

  10. #ifndef __ASM_CPU_SH3_TIMER_H
    11. 

  11. #define __ASM_CPU_SH3_TIMER_H
    12. 

  12. 

  13. /*
    14. 

  14.  * ---------------------------------------------------------------------------
    15. 

  15.  * TMU Common definitions for SH3 processors
    16. 

  16.  *	SH7706
    17. 

  17.  *	SH7709S
    18. 

  18.  *	SH7727
    19. 

  19.  *	SH7729R
    20. 

  20.  *	SH7710
    21. 

  21.  *	SH7720
    22. 

  22.  *	SH7710
    23. 

  23.  * ---------------------------------------------------------------------------
    24. 

  24.  */
    25. 

  25. 

  26. #if  !defined(CONFIG_CPU_SUBTYPE_SH7720) && !defined(CONFIG_CPU_SUBTYPE_SH7721)
    27. 

  27. #define TMU_TOCR	0xfffffe90	/* Byte access */
    28. 

  28. #endif
    29. 

  29. 

  30. #if defined(CONFIG_CPU_SUBTYPE_SH7710) || \
    31. 

  31.     defined(CONFIG_CPU_SUBTYPE_SH7720) || \
    32. 

  32.     defined(CONFIG_CPU_SUBTYPE_SH7721)
    33. 

  33. #define TMU_012_TSTR	0xa412fe92	/* Byte access */
    34. 

  34. 

  35. #define TMU0_TCOR	0xa412fe94	/* Long access */
    36. 

  36. #define TMU0_TCNT	0xa412fe98	/* Long access */
    37. 

  37. #define TMU0_TCR	0xa412fe9c	/* Word access */
    38. 

  38. 

  39. #define TMU1_TCOR	0xa412fea0	/* Long access */
    40. 

  40. #define TMU1_TCNT	0xa412fea4	/* Long access */
    41. 

  41. #define TMU1_TCR	0xa412fea8	/* Word access */
    42. 

  42. 

  43. #define TMU2_TCOR	0xa412feac	/* Long access */
    44. 

  44. #define TMU2_TCNT	0xa412feb0	/* Long access */
    45. 

  45. #define TMU2_TCR	0xa412feb4	/* Word access */
    46. 

  46. 

  47. #else
    48. 

  48. #define TMU_012_TSTR	0xfffffe92	/* Byte access */
    49. 

  49. 

  50. #define TMU0_TCOR	0xfffffe94	/* Long access */
    51. 

  51. #define TMU0_TCNT	0xfffffe98	/* Long access */
    52. 

  52. #define TMU0_TCR	0xfffffe9c	/* Word access */
    53. 

  53. 

  54. #define TMU1_TCOR	0xfffffea0	/* Long access */
    55. 

  55. #define TMU1_TCNT	0xfffffea4	/* Long access */
    56. 

  56. #define TMU1_TCR	0xfffffea8	/* Word access */
    57. 

  57. 

  58. #define TMU2_TCOR	0xfffffeac	/* Long access */
    59. 

  59. #define TMU2_TCNT	0xfffffeb0	/* Long access */
    60. 

  60. #define TMU2_TCR	0xfffffeb4	/* Word access */
    61. 

  61. #if !defined(CONFIG_CPU_SUBTYPE_SH7720) && !defined(CONFIG_CPU_SUBTYPE_SH7721)
    62. 

  62. #define TMU2_TCPR2	0xfffffeb8	/* Long access */
    63. 

  63. #endif
    64. 

  64. #endif
    65. 

  65. 

  66. #endif /* __ASM_CPU_SH3_TIMER_H */
    67. 

  67.