slb_low.S 8.2 KB

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  1. /*
  2. * Low-level SLB routines
  3. *
  4. * Copyright (C) 2004 David Gibson <dwg@au.ibm.com>, IBM
  5. *
  6. * Based on earlier C version:
  7. * Dave Engebretsen and Mike Corrigan {engebret|mikejc}@us.ibm.com
  8. * Copyright (c) 2001 Dave Engebretsen
  9. * Copyright (C) 2002 Anton Blanchard <anton@au.ibm.com>, IBM
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License
  13. * as published by the Free Software Foundation; either version
  14. * 2 of the License, or (at your option) any later version.
  15. */
  16. #include <asm/processor.h>
  17. #include <asm/ppc_asm.h>
  18. #include <asm/asm-offsets.h>
  19. #include <asm/cputable.h>
  20. #include <asm/page.h>
  21. #include <asm/mmu.h>
  22. #include <asm/pgtable.h>
  23. #include <asm/firmware.h>
  24. /* void slb_allocate_realmode(unsigned long ea);
  25. *
  26. * Create an SLB entry for the given EA (user or kernel).
  27. * r3 = faulting address, r13 = PACA
  28. * r9, r10, r11 are clobbered by this function
  29. * No other registers are examined or changed.
  30. */
  31. _GLOBAL(slb_allocate_realmode)
  32. /* r3 = faulting address */
  33. srdi r9,r3,60 /* get region */
  34. srdi r10,r3,28 /* get esid */
  35. cmpldi cr7,r9,0xc /* cmp PAGE_OFFSET for later use */
  36. /* r3 = address, r10 = esid, cr7 = <> PAGE_OFFSET */
  37. blt cr7,0f /* user or kernel? */
  38. /* kernel address: proto-VSID = ESID */
  39. /* WARNING - MAGIC: we don't use the VSID 0xfffffffff, but
  40. * this code will generate the protoVSID 0xfffffffff for the
  41. * top segment. That's ok, the scramble below will translate
  42. * it to VSID 0, which is reserved as a bad VSID - one which
  43. * will never have any pages in it. */
  44. /* Check if hitting the linear mapping or some other kernel space
  45. */
  46. bne cr7,1f
  47. /* Linear mapping encoding bits, the "li" instruction below will
  48. * be patched by the kernel at boot
  49. */
  50. _GLOBAL(slb_miss_kernel_load_linear)
  51. li r11,0
  52. BEGIN_FTR_SECTION
  53. b slb_finish_load
  54. END_FTR_SECTION_IFCLR(CPU_FTR_1T_SEGMENT)
  55. b slb_finish_load_1T
  56. 1:
  57. #ifdef CONFIG_SPARSEMEM_VMEMMAP
  58. /* Check virtual memmap region. To be patches at kernel boot */
  59. cmpldi cr0,r9,0xf
  60. bne 1f
  61. _GLOBAL(slb_miss_kernel_load_vmemmap)
  62. li r11,0
  63. b 6f
  64. 1:
  65. #endif /* CONFIG_SPARSEMEM_VMEMMAP */
  66. /* vmalloc/ioremap mapping encoding bits, the "li" instructions below
  67. * will be patched by the kernel at boot
  68. */
  69. BEGIN_FTR_SECTION
  70. /* check whether this is in vmalloc or ioremap space */
  71. clrldi r11,r10,48
  72. cmpldi r11,(VMALLOC_SIZE >> 28) - 1
  73. bgt 5f
  74. lhz r11,PACAVMALLOCSLLP(r13)
  75. b 6f
  76. 5:
  77. END_FTR_SECTION_IFCLR(CPU_FTR_CI_LARGE_PAGE)
  78. _GLOBAL(slb_miss_kernel_load_io)
  79. li r11,0
  80. 6:
  81. BEGIN_FTR_SECTION
  82. b slb_finish_load
  83. END_FTR_SECTION_IFCLR(CPU_FTR_1T_SEGMENT)
  84. b slb_finish_load_1T
  85. 0: /* user address: proto-VSID = context << 15 | ESID. First check
  86. * if the address is within the boundaries of the user region
  87. */
  88. srdi. r9,r10,USER_ESID_BITS
  89. bne- 8f /* invalid ea bits set */
  90. /* when using slices, we extract the psize off the slice bitmaps
  91. * and then we need to get the sllp encoding off the mmu_psize_defs
  92. * array.
  93. *
  94. * XXX This is a bit inefficient especially for the normal case,
  95. * so we should try to implement a fast path for the standard page
  96. * size using the old sllp value so we avoid the array. We cannot
  97. * really do dynamic patching unfortunately as processes might flip
  98. * between 4k and 64k standard page size
  99. */
  100. #ifdef CONFIG_PPC_MM_SLICES
  101. cmpldi r10,16
  102. /* Get the slice index * 4 in r11 and matching slice size mask in r9 */
  103. ld r9,PACALOWSLICESPSIZE(r13)
  104. sldi r11,r10,2
  105. blt 5f
  106. ld r9,PACAHIGHSLICEPSIZE(r13)
  107. srdi r11,r10,(SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT - 2)
  108. andi. r11,r11,0x3c
  109. 5: /* Extract the psize and multiply to get an array offset */
  110. srd r9,r9,r11
  111. andi. r9,r9,0xf
  112. mulli r9,r9,MMUPSIZEDEFSIZE
  113. /* Now get to the array and obtain the sllp
  114. */
  115. ld r11,PACATOC(r13)
  116. ld r11,mmu_psize_defs@got(r11)
  117. add r11,r11,r9
  118. ld r11,MMUPSIZESLLP(r11)
  119. ori r11,r11,SLB_VSID_USER
  120. #else
  121. /* paca context sllp already contains the SLB_VSID_USER bits */
  122. lhz r11,PACACONTEXTSLLP(r13)
  123. #endif /* CONFIG_PPC_MM_SLICES */
  124. ld r9,PACACONTEXTID(r13)
  125. BEGIN_FTR_SECTION
  126. cmpldi r10,0x1000
  127. END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT)
  128. rldimi r10,r9,USER_ESID_BITS,0
  129. BEGIN_FTR_SECTION
  130. bge slb_finish_load_1T
  131. END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT)
  132. b slb_finish_load
  133. 8: /* invalid EA */
  134. li r10,0 /* BAD_VSID */
  135. li r11,SLB_VSID_USER /* flags don't much matter */
  136. b slb_finish_load
  137. #ifdef __DISABLED__
  138. /* void slb_allocate_user(unsigned long ea);
  139. *
  140. * Create an SLB entry for the given EA (user or kernel).
  141. * r3 = faulting address, r13 = PACA
  142. * r9, r10, r11 are clobbered by this function
  143. * No other registers are examined or changed.
  144. *
  145. * It is called with translation enabled in order to be able to walk the
  146. * page tables. This is not currently used.
  147. */
  148. _GLOBAL(slb_allocate_user)
  149. /* r3 = faulting address */
  150. srdi r10,r3,28 /* get esid */
  151. crset 4*cr7+lt /* set "user" flag for later */
  152. /* check if we fit in the range covered by the pagetables*/
  153. srdi. r9,r3,PGTABLE_EADDR_SIZE
  154. crnot 4*cr0+eq,4*cr0+eq
  155. beqlr
  156. /* now we need to get to the page tables in order to get the page
  157. * size encoding from the PMD. In the future, we'll be able to deal
  158. * with 1T segments too by getting the encoding from the PGD instead
  159. */
  160. ld r9,PACAPGDIR(r13)
  161. cmpldi cr0,r9,0
  162. beqlr
  163. rlwinm r11,r10,8,25,28
  164. ldx r9,r9,r11 /* get pgd_t */
  165. cmpldi cr0,r9,0
  166. beqlr
  167. rlwinm r11,r10,3,17,28
  168. ldx r9,r9,r11 /* get pmd_t */
  169. cmpldi cr0,r9,0
  170. beqlr
  171. /* build vsid flags */
  172. andi. r11,r9,SLB_VSID_LLP
  173. ori r11,r11,SLB_VSID_USER
  174. /* get context to calculate proto-VSID */
  175. ld r9,PACACONTEXTID(r13)
  176. rldimi r10,r9,USER_ESID_BITS,0
  177. /* fall through slb_finish_load */
  178. #endif /* __DISABLED__ */
  179. /*
  180. * Finish loading of an SLB entry and return
  181. *
  182. * r3 = EA, r10 = proto-VSID, r11 = flags, clobbers r9, cr7 = <> PAGE_OFFSET
  183. */
  184. slb_finish_load:
  185. ASM_VSID_SCRAMBLE(r10,r9,256M)
  186. rldimi r11,r10,SLB_VSID_SHIFT,16 /* combine VSID and flags */
  187. /* r3 = EA, r11 = VSID data */
  188. /*
  189. * Find a slot, round robin. Previously we tried to find a
  190. * free slot first but that took too long. Unfortunately we
  191. * dont have any LRU information to help us choose a slot.
  192. */
  193. #ifdef CONFIG_PPC_ISERIES
  194. BEGIN_FW_FTR_SECTION
  195. /*
  196. * On iSeries, the "bolted" stack segment can be cast out on
  197. * shared processor switch so we need to check for a miss on
  198. * it and restore it to the right slot.
  199. */
  200. ld r9,PACAKSAVE(r13)
  201. clrrdi r9,r9,28
  202. clrrdi r3,r3,28
  203. li r10,SLB_NUM_BOLTED-1 /* Stack goes in last bolted slot */
  204. cmpld r9,r3
  205. beq 3f
  206. END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
  207. #endif /* CONFIG_PPC_ISERIES */
  208. 7: ld r10,PACASTABRR(r13)
  209. addi r10,r10,1
  210. /* This gets soft patched on boot. */
  211. _GLOBAL(slb_compare_rr_to_size)
  212. cmpldi r10,0
  213. blt+ 4f
  214. li r10,SLB_NUM_BOLTED
  215. 4:
  216. std r10,PACASTABRR(r13)
  217. 3:
  218. rldimi r3,r10,0,36 /* r3= EA[0:35] | entry */
  219. oris r10,r3,SLB_ESID_V@h /* r3 |= SLB_ESID_V */
  220. /* r3 = ESID data, r11 = VSID data */
  221. /*
  222. * No need for an isync before or after this slbmte. The exception
  223. * we enter with and the rfid we exit with are context synchronizing.
  224. */
  225. slbmte r11,r10
  226. /* we're done for kernel addresses */
  227. crclr 4*cr0+eq /* set result to "success" */
  228. bgelr cr7
  229. /* Update the slb cache */
  230. lhz r3,PACASLBCACHEPTR(r13) /* offset = paca->slb_cache_ptr */
  231. cmpldi r3,SLB_CACHE_ENTRIES
  232. bge 1f
  233. /* still room in the slb cache */
  234. sldi r11,r3,1 /* r11 = offset * sizeof(u16) */
  235. rldicl r10,r10,36,28 /* get low 16 bits of the ESID */
  236. add r11,r11,r13 /* r11 = (u16 *)paca + offset */
  237. sth r10,PACASLBCACHE(r11) /* paca->slb_cache[offset] = esid */
  238. addi r3,r3,1 /* offset++ */
  239. b 2f
  240. 1: /* offset >= SLB_CACHE_ENTRIES */
  241. li r3,SLB_CACHE_ENTRIES+1
  242. 2:
  243. sth r3,PACASLBCACHEPTR(r13) /* paca->slb_cache_ptr = offset */
  244. crclr 4*cr0+eq /* set result to "success" */
  245. blr
  246. /*
  247. * Finish loading of a 1T SLB entry (for the kernel linear mapping) and return.
  248. * We assume legacy iSeries will never have 1T segments.
  249. *
  250. * r3 = EA, r10 = proto-VSID, r11 = flags, clobbers r9
  251. */
  252. slb_finish_load_1T:
  253. srdi r10,r10,40-28 /* get 1T ESID */
  254. ASM_VSID_SCRAMBLE(r10,r9,1T)
  255. rldimi r11,r10,SLB_VSID_SHIFT_1T,16 /* combine VSID and flags */
  256. li r10,MMU_SEGSIZE_1T
  257. rldimi r11,r10,SLB_VSID_SSIZE_SHIFT,0 /* insert segment size */
  258. /* r3 = EA, r11 = VSID data */
  259. clrrdi r3,r3,SID_SHIFT_1T /* clear out non-ESID bits */
  260. b 7b