kilauea.dts 9.8 KB

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  1. /*
  2. * Device Tree Source for AMCC Kilauea (405EX)
  3. *
  4. * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
  5. *
  6. * This file is licensed under the terms of the GNU General Public
  7. * License version 2. This program is licensed "as is" without
  8. * any warranty of any kind, whether express or implied.
  9. */
  10. /dts-v1/;
  11. / {
  12. #address-cells = <1>;
  13. #size-cells = <1>;
  14. model = "amcc,kilauea";
  15. compatible = "amcc,kilauea";
  16. dcr-parent = <&{/cpus/cpu@0}>;
  17. aliases {
  18. ethernet0 = &EMAC0;
  19. ethernet1 = &EMAC1;
  20. serial0 = &UART0;
  21. serial1 = &UART1;
  22. };
  23. cpus {
  24. #address-cells = <1>;
  25. #size-cells = <0>;
  26. cpu@0 {
  27. device_type = "cpu";
  28. model = "PowerPC,405EX";
  29. reg = <0x00000000>;
  30. clock-frequency = <0>; /* Filled in by U-Boot */
  31. timebase-frequency = <0>; /* Filled in by U-Boot */
  32. i-cache-line-size = <32>;
  33. d-cache-line-size = <32>;
  34. i-cache-size = <16384>; /* 16 kB */
  35. d-cache-size = <16384>; /* 16 kB */
  36. dcr-controller;
  37. dcr-access-method = "native";
  38. };
  39. };
  40. memory {
  41. device_type = "memory";
  42. reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */
  43. };
  44. UIC0: interrupt-controller {
  45. compatible = "ibm,uic-405ex", "ibm,uic";
  46. interrupt-controller;
  47. cell-index = <0>;
  48. dcr-reg = <0x0c0 0x009>;
  49. #address-cells = <0>;
  50. #size-cells = <0>;
  51. #interrupt-cells = <2>;
  52. };
  53. UIC1: interrupt-controller1 {
  54. compatible = "ibm,uic-405ex","ibm,uic";
  55. interrupt-controller;
  56. cell-index = <1>;
  57. dcr-reg = <0x0d0 0x009>;
  58. #address-cells = <0>;
  59. #size-cells = <0>;
  60. #interrupt-cells = <2>;
  61. interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
  62. interrupt-parent = <&UIC0>;
  63. };
  64. UIC2: interrupt-controller2 {
  65. compatible = "ibm,uic-405ex","ibm,uic";
  66. interrupt-controller;
  67. cell-index = <2>;
  68. dcr-reg = <0x0e0 0x009>;
  69. #address-cells = <0>;
  70. #size-cells = <0>;
  71. #interrupt-cells = <2>;
  72. interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */
  73. interrupt-parent = <&UIC0>;
  74. };
  75. plb {
  76. compatible = "ibm,plb-405ex", "ibm,plb4";
  77. #address-cells = <1>;
  78. #size-cells = <1>;
  79. ranges;
  80. clock-frequency = <0>; /* Filled in by U-Boot */
  81. SDRAM0: memory-controller {
  82. compatible = "ibm,sdram-405ex", "ibm,sdram-4xx-ddr2";
  83. dcr-reg = <0x010 0x002>;
  84. interrupt-parent = <&UIC2>;
  85. interrupts = <0x5 0x4 /* ECC DED Error */
  86. 0x6 0x4>; /* ECC SEC Error */
  87. };
  88. CRYPTO: crypto@ef700000 {
  89. compatible = "amcc,ppc405ex-crypto", "amcc,ppc4xx-crypto";
  90. reg = <0xef700000 0x80400>;
  91. interrupt-parent = <&UIC0>;
  92. interrupts = <0x17 0x2>;
  93. };
  94. MAL0: mcmal {
  95. compatible = "ibm,mcmal-405ex", "ibm,mcmal2";
  96. dcr-reg = <0x180 0x062>;
  97. num-tx-chans = <2>;
  98. num-rx-chans = <2>;
  99. interrupt-parent = <&MAL0>;
  100. interrupts = <0x0 0x1 0x2 0x3 0x4>;
  101. #interrupt-cells = <1>;
  102. #address-cells = <0>;
  103. #size-cells = <0>;
  104. interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
  105. /*RXEOB*/ 0x1 &UIC0 0xb 0x4
  106. /*SERR*/ 0x2 &UIC1 0x0 0x4
  107. /*TXDE*/ 0x3 &UIC1 0x1 0x4
  108. /*RXDE*/ 0x4 &UIC1 0x2 0x4>;
  109. interrupt-map-mask = <0xffffffff>;
  110. };
  111. POB0: opb {
  112. compatible = "ibm,opb-405ex", "ibm,opb";
  113. #address-cells = <1>;
  114. #size-cells = <1>;
  115. ranges = <0x80000000 0x80000000 0x10000000
  116. 0xef600000 0xef600000 0x00a00000
  117. 0xf0000000 0xf0000000 0x10000000>;
  118. dcr-reg = <0x0a0 0x005>;
  119. clock-frequency = <0>; /* Filled in by U-Boot */
  120. EBC0: ebc {
  121. compatible = "ibm,ebc-405ex", "ibm,ebc";
  122. dcr-reg = <0x012 0x002>;
  123. #address-cells = <2>;
  124. #size-cells = <1>;
  125. clock-frequency = <0>; /* Filled in by U-Boot */
  126. /* ranges property is supplied by U-Boot */
  127. interrupts = <0x5 0x1>;
  128. interrupt-parent = <&UIC1>;
  129. nor_flash@0,0 {
  130. compatible = "amd,s29gl512n", "cfi-flash";
  131. bank-width = <2>;
  132. reg = <0x00000000 0x00000000 0x04000000>;
  133. #address-cells = <1>;
  134. #size-cells = <1>;
  135. partition@0 {
  136. label = "kernel";
  137. reg = <0x00000000 0x00200000>;
  138. };
  139. partition@200000 {
  140. label = "root";
  141. reg = <0x00200000 0x00200000>;
  142. };
  143. partition@400000 {
  144. label = "user";
  145. reg = <0x00400000 0x03b60000>;
  146. };
  147. partition@3f60000 {
  148. label = "env";
  149. reg = <0x03f60000 0x00040000>;
  150. };
  151. partition@3fa0000 {
  152. label = "u-boot";
  153. reg = <0x03fa0000 0x00060000>;
  154. };
  155. };
  156. };
  157. UART0: serial@ef600200 {
  158. device_type = "serial";
  159. compatible = "ns16550";
  160. reg = <0xef600200 0x00000008>;
  161. virtual-reg = <0xef600200>;
  162. clock-frequency = <0>; /* Filled in by U-Boot */
  163. current-speed = <0>;
  164. interrupt-parent = <&UIC0>;
  165. interrupts = <0x1a 0x4>;
  166. };
  167. UART1: serial@ef600300 {
  168. device_type = "serial";
  169. compatible = "ns16550";
  170. reg = <0xef600300 0x00000008>;
  171. virtual-reg = <0xef600300>;
  172. clock-frequency = <0>; /* Filled in by U-Boot */
  173. current-speed = <0>;
  174. interrupt-parent = <&UIC0>;
  175. interrupts = <0x1 0x4>;
  176. };
  177. IIC0: i2c@ef600400 {
  178. compatible = "ibm,iic-405ex", "ibm,iic";
  179. reg = <0xef600400 0x00000014>;
  180. interrupt-parent = <&UIC0>;
  181. interrupts = <0x2 0x4>;
  182. };
  183. IIC1: i2c@ef600500 {
  184. compatible = "ibm,iic-405ex", "ibm,iic";
  185. reg = <0xef600500 0x00000014>;
  186. interrupt-parent = <&UIC0>;
  187. interrupts = <0x7 0x4>;
  188. };
  189. RGMII0: emac-rgmii@ef600b00 {
  190. compatible = "ibm,rgmii-405ex", "ibm,rgmii";
  191. reg = <0xef600b00 0x00000104>;
  192. has-mdio;
  193. };
  194. EMAC0: ethernet@ef600900 {
  195. linux,network-index = <0x0>;
  196. device_type = "network";
  197. compatible = "ibm,emac-405ex", "ibm,emac4sync";
  198. interrupt-parent = <&EMAC0>;
  199. interrupts = <0x0 0x1>;
  200. #interrupt-cells = <1>;
  201. #address-cells = <0>;
  202. #size-cells = <0>;
  203. interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4
  204. /*Wake*/ 0x1 &UIC1 0x1d 0x4>;
  205. reg = <0xef600900 0x000000c4>;
  206. local-mac-address = [000000000000]; /* Filled in by U-Boot */
  207. mal-device = <&MAL0>;
  208. mal-tx-channel = <0>;
  209. mal-rx-channel = <0>;
  210. cell-index = <0>;
  211. max-frame-size = <9000>;
  212. rx-fifo-size = <4096>;
  213. tx-fifo-size = <2048>;
  214. phy-mode = "rgmii";
  215. phy-map = <0x00000000>;
  216. rgmii-device = <&RGMII0>;
  217. rgmii-channel = <0>;
  218. has-inverted-stacr-oc;
  219. has-new-stacr-staopc;
  220. };
  221. EMAC1: ethernet@ef600a00 {
  222. linux,network-index = <0x1>;
  223. device_type = "network";
  224. compatible = "ibm,emac-405ex", "ibm,emac4sync";
  225. interrupt-parent = <&EMAC1>;
  226. interrupts = <0x0 0x1>;
  227. #interrupt-cells = <1>;
  228. #address-cells = <0>;
  229. #size-cells = <0>;
  230. interrupt-map = </*Status*/ 0x0 &UIC0 0x19 0x4
  231. /*Wake*/ 0x1 &UIC1 0x1f 0x4>;
  232. reg = <0xef600a00 0x000000c4>;
  233. local-mac-address = [000000000000]; /* Filled in by U-Boot */
  234. mal-device = <&MAL0>;
  235. mal-tx-channel = <1>;
  236. mal-rx-channel = <1>;
  237. cell-index = <1>;
  238. max-frame-size = <9000>;
  239. rx-fifo-size = <4096>;
  240. tx-fifo-size = <2048>;
  241. phy-mode = "rgmii";
  242. phy-map = <0x00000000>;
  243. rgmii-device = <&RGMII0>;
  244. rgmii-channel = <1>;
  245. has-inverted-stacr-oc;
  246. has-new-stacr-staopc;
  247. };
  248. };
  249. PCIE0: pciex@0a0000000 {
  250. device_type = "pci";
  251. #interrupt-cells = <1>;
  252. #size-cells = <2>;
  253. #address-cells = <3>;
  254. compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
  255. primary;
  256. port = <0x0>; /* port number */
  257. reg = <0xa0000000 0x20000000 /* Config space access */
  258. 0xef000000 0x00001000>; /* Registers */
  259. dcr-reg = <0x040 0x020>;
  260. sdr-base = <0x400>;
  261. /* Outbound ranges, one memory and one IO,
  262. * later cannot be changed
  263. */
  264. ranges = <0x02000000 0x00000000 0x80000000 0x90000000 0x00000000 0x08000000
  265. 0x01000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00010000>;
  266. /* Inbound 2GB range starting at 0 */
  267. dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
  268. /* This drives busses 0x00 to 0x3f */
  269. bus-range = <0x0 0x3f>;
  270. /* Legacy interrupts (note the weird polarity, the bridge seems
  271. * to invert PCIe legacy interrupts).
  272. * We are de-swizzling here because the numbers are actually for
  273. * port of the root complex virtual P2P bridge. But I want
  274. * to avoid putting a node for it in the tree, so the numbers
  275. * below are basically de-swizzled numbers.
  276. * The real slot is on idsel 0, so the swizzling is 1:1
  277. */
  278. interrupt-map-mask = <0x0 0x0 0x0 0x7>;
  279. interrupt-map = <
  280. 0x0 0x0 0x0 0x1 &UIC2 0x0 0x4 /* swizzled int A */
  281. 0x0 0x0 0x0 0x2 &UIC2 0x1 0x4 /* swizzled int B */
  282. 0x0 0x0 0x0 0x3 &UIC2 0x2 0x4 /* swizzled int C */
  283. 0x0 0x0 0x0 0x4 &UIC2 0x3 0x4 /* swizzled int D */>;
  284. };
  285. PCIE1: pciex@0c0000000 {
  286. device_type = "pci";
  287. #interrupt-cells = <1>;
  288. #size-cells = <2>;
  289. #address-cells = <3>;
  290. compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
  291. primary;
  292. port = <0x1>; /* port number */
  293. reg = <0xc0000000 0x20000000 /* Config space access */
  294. 0xef001000 0x00001000>; /* Registers */
  295. dcr-reg = <0x060 0x020>;
  296. sdr-base = <0x440>;
  297. /* Outbound ranges, one memory and one IO,
  298. * later cannot be changed
  299. */
  300. ranges = <0x02000000 0x00000000 0x80000000 0x98000000 0x00000000 0x08000000
  301. 0x01000000 0x00000000 0x00000000 0xe0010000 0x00000000 0x00010000>;
  302. /* Inbound 2GB range starting at 0 */
  303. dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
  304. /* This drives busses 0x40 to 0x7f */
  305. bus-range = <0x40 0x7f>;
  306. /* Legacy interrupts (note the weird polarity, the bridge seems
  307. * to invert PCIe legacy interrupts).
  308. * We are de-swizzling here because the numbers are actually for
  309. * port of the root complex virtual P2P bridge. But I want
  310. * to avoid putting a node for it in the tree, so the numbers
  311. * below are basically de-swizzled numbers.
  312. * The real slot is on idsel 0, so the swizzling is 1:1
  313. */
  314. interrupt-map-mask = <0x0 0x0 0x0 0x7>;
  315. interrupt-map = <
  316. 0x0 0x0 0x0 0x1 &UIC2 0xb 0x4 /* swizzled int A */
  317. 0x0 0x0 0x0 0x2 &UIC2 0xc 0x4 /* swizzled int B */
  318. 0x0 0x0 0x0 0x3 &UIC2 0xd 0x4 /* swizzled int C */
  319. 0x0 0x0 0x0 0x4 &UIC2 0xe 0x4 /* swizzled int D */>;
  320. };
  321. };
  322. };