mach-gt64120.h 2.4 KB

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  1. /*
  2. * This is a direct copy of the ev96100.h file, with a global
  3. * search and replace. The numbers are the same.
  4. *
  5. * The reason I'm duplicating this is so that the 64120/96100
  6. * defines won't be confusing in the source code.
  7. */
  8. #ifndef __ASM_MIPS_GT64120_H
  9. #define __ASM_MIPS_GT64120_H
  10. /*
  11. * This is the CPU physical memory map of PPMC Board:
  12. *
  13. * 0x00000000-0x03FFFFFF - 64MB SDRAM (SCS[0]#)
  14. * 0x1C000000-0x1C000000 - LED (CS0)
  15. * 0x1C800000-0x1C800007 - UART 16550 port (CS1)
  16. * 0x1F000000-0x1F000000 - MailBox (CS3)
  17. * 0x1FC00000-0x20000000 - 4MB Flash (BOOT CS)
  18. */
  19. #define WRPPMC_SDRAM_SCS0_BASE 0x00000000
  20. #define WRPPMC_SDRAM_SCS0_SIZE 0x04000000
  21. #define WRPPMC_UART16550_BASE 0x1C800000
  22. #define WRPPMC_UART16550_CLOCK 3686400 /* 3.68MHZ */
  23. #define WRPPMC_LED_BASE 0x1C000000
  24. #define WRPPMC_MBOX_BASE 0x1F000000
  25. #define WRPPMC_BOOTROM_BASE 0x1FC00000
  26. #define WRPPMC_BOOTROM_SIZE 0x00400000 /* 4M Flash */
  27. #define WRPPMC_MIPS_TIMER_IRQ 7 /* MIPS compare/count timer interrupt */
  28. #define WRPPMC_UART16550_IRQ 6
  29. #define WRPPMC_PCI_INTA_IRQ 3
  30. /*
  31. * PCI Bus I/O and Memory resources allocation
  32. *
  33. * NOTE: We only have PCI_0 hose interface
  34. */
  35. #define GT_PCI_MEM_BASE 0x13000000UL
  36. #define GT_PCI_MEM_SIZE 0x02000000UL
  37. #define GT_PCI_IO_BASE 0x11000000UL
  38. #define GT_PCI_IO_SIZE 0x02000000UL
  39. /*
  40. * PCI interrupts will come in on either the INTA or INTD interrupt lines,
  41. * which are mapped to the #2 and #5 interrupt pins of the MIPS. On our
  42. * boards, they all either come in on IntD or they all come in on IntA, they
  43. * aren't mixed. There can be numerous PCI interrupts, so we keep a list of the
  44. * "requested" interrupt numbers and go through the list whenever we get an
  45. * IntA/D.
  46. *
  47. * Interrupts < 8 are directly wired to the processor; PCI INTA is 8 and
  48. * INTD is 11.
  49. */
  50. #define GT_TIMER 4
  51. #define GT_INTA 2
  52. #define GT_INTD 5
  53. #ifndef __ASSEMBLY__
  54. /*
  55. * GT64120 internal register space base address
  56. */
  57. extern unsigned long gt64120_base;
  58. #define GT64120_BASE (gt64120_base)
  59. /* define WRPPMC_EARLY_DEBUG to enable early output something to UART */
  60. #undef WRPPMC_EARLY_DEBUG
  61. #ifdef WRPPMC_EARLY_DEBUG
  62. extern void wrppmc_led_on(int mask);
  63. extern void wrppmc_led_off(int mask);
  64. extern void wrppmc_early_printk(const char *fmt, ...);
  65. #else
  66. #define wrppmc_early_printk(fmt, ...) do {} while (0)
  67. #endif /* WRPPMC_EARLY_DEBUG */
  68. #endif /* __ASSEMBLY__ */
  69. #endif /* __ASM_MIPS_GT64120_H */