smpboot.c 22 KB

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  1. /*
  2. * SMP boot-related support
  3. *
  4. * Copyright (C) 1998-2003, 2005 Hewlett-Packard Co
  5. * David Mosberger-Tang <davidm@hpl.hp.com>
  6. * Copyright (C) 2001, 2004-2005 Intel Corp
  7. * Rohit Seth <rohit.seth@intel.com>
  8. * Suresh Siddha <suresh.b.siddha@intel.com>
  9. * Gordon Jin <gordon.jin@intel.com>
  10. * Ashok Raj <ashok.raj@intel.com>
  11. *
  12. * 01/05/16 Rohit Seth <rohit.seth@intel.com> Moved SMP booting functions from smp.c to here.
  13. * 01/04/27 David Mosberger <davidm@hpl.hp.com> Added ITC synching code.
  14. * 02/07/31 David Mosberger <davidm@hpl.hp.com> Switch over to hotplug-CPU boot-sequence.
  15. * smp_boot_cpus()/smp_commence() is replaced by
  16. * smp_prepare_cpus()/__cpu_up()/smp_cpus_done().
  17. * 04/06/21 Ashok Raj <ashok.raj@intel.com> Added CPU Hotplug Support
  18. * 04/12/26 Jin Gordon <gordon.jin@intel.com>
  19. * 04/12/26 Rohit Seth <rohit.seth@intel.com>
  20. * Add multi-threading and multi-core detection
  21. * 05/01/30 Suresh Siddha <suresh.b.siddha@intel.com>
  22. * Setup cpu_sibling_map and cpu_core_map
  23. */
  24. #include <linux/module.h>
  25. #include <linux/acpi.h>
  26. #include <linux/bootmem.h>
  27. #include <linux/cpu.h>
  28. #include <linux/delay.h>
  29. #include <linux/init.h>
  30. #include <linux/interrupt.h>
  31. #include <linux/irq.h>
  32. #include <linux/kernel.h>
  33. #include <linux/kernel_stat.h>
  34. #include <linux/mm.h>
  35. #include <linux/notifier.h>
  36. #include <linux/smp.h>
  37. #include <linux/spinlock.h>
  38. #include <linux/efi.h>
  39. #include <linux/percpu.h>
  40. #include <linux/bitops.h>
  41. #include <asm/atomic.h>
  42. #include <asm/cache.h>
  43. #include <asm/current.h>
  44. #include <asm/delay.h>
  45. #include <asm/ia32.h>
  46. #include <asm/io.h>
  47. #include <asm/irq.h>
  48. #include <asm/machvec.h>
  49. #include <asm/mca.h>
  50. #include <asm/page.h>
  51. #include <asm/paravirt.h>
  52. #include <asm/pgalloc.h>
  53. #include <asm/pgtable.h>
  54. #include <asm/processor.h>
  55. #include <asm/ptrace.h>
  56. #include <asm/sal.h>
  57. #include <asm/system.h>
  58. #include <asm/tlbflush.h>
  59. #include <asm/unistd.h>
  60. #include <asm/sn/arch.h>
  61. #define SMP_DEBUG 0
  62. #if SMP_DEBUG
  63. #define Dprintk(x...) printk(x)
  64. #else
  65. #define Dprintk(x...)
  66. #endif
  67. #ifdef CONFIG_HOTPLUG_CPU
  68. #ifdef CONFIG_PERMIT_BSP_REMOVE
  69. #define bsp_remove_ok 1
  70. #else
  71. #define bsp_remove_ok 0
  72. #endif
  73. /*
  74. * Store all idle threads, this can be reused instead of creating
  75. * a new thread. Also avoids complicated thread destroy functionality
  76. * for idle threads.
  77. */
  78. struct task_struct *idle_thread_array[NR_CPUS];
  79. /*
  80. * Global array allocated for NR_CPUS at boot time
  81. */
  82. struct sal_to_os_boot sal_boot_rendez_state[NR_CPUS];
  83. /*
  84. * start_ap in head.S uses this to store current booting cpu
  85. * info.
  86. */
  87. struct sal_to_os_boot *sal_state_for_booting_cpu = &sal_boot_rendez_state[0];
  88. #define set_brendez_area(x) (sal_state_for_booting_cpu = &sal_boot_rendez_state[(x)]);
  89. #define get_idle_for_cpu(x) (idle_thread_array[(x)])
  90. #define set_idle_for_cpu(x,p) (idle_thread_array[(x)] = (p))
  91. #else
  92. #define get_idle_for_cpu(x) (NULL)
  93. #define set_idle_for_cpu(x,p)
  94. #define set_brendez_area(x)
  95. #endif
  96. /*
  97. * ITC synchronization related stuff:
  98. */
  99. #define MASTER (0)
  100. #define SLAVE (SMP_CACHE_BYTES/8)
  101. #define NUM_ROUNDS 64 /* magic value */
  102. #define NUM_ITERS 5 /* likewise */
  103. static DEFINE_SPINLOCK(itc_sync_lock);
  104. static volatile unsigned long go[SLAVE + 1];
  105. #define DEBUG_ITC_SYNC 0
  106. extern void start_ap (void);
  107. extern unsigned long ia64_iobase;
  108. struct task_struct *task_for_booting_cpu;
  109. /*
  110. * State for each CPU
  111. */
  112. DEFINE_PER_CPU(int, cpu_state);
  113. cpumask_t cpu_core_map[NR_CPUS] __cacheline_aligned;
  114. EXPORT_SYMBOL(cpu_core_map);
  115. DEFINE_PER_CPU_SHARED_ALIGNED(cpumask_t, cpu_sibling_map);
  116. EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
  117. int smp_num_siblings = 1;
  118. /* which logical CPU number maps to which CPU (physical APIC ID) */
  119. volatile int ia64_cpu_to_sapicid[NR_CPUS];
  120. EXPORT_SYMBOL(ia64_cpu_to_sapicid);
  121. static volatile cpumask_t cpu_callin_map;
  122. struct smp_boot_data smp_boot_data __initdata;
  123. unsigned long ap_wakeup_vector = -1; /* External Int use to wakeup APs */
  124. char __initdata no_int_routing;
  125. unsigned char smp_int_redirect; /* are INT and IPI redirectable by the chipset? */
  126. #ifdef CONFIG_FORCE_CPEI_RETARGET
  127. #define CPEI_OVERRIDE_DEFAULT (1)
  128. #else
  129. #define CPEI_OVERRIDE_DEFAULT (0)
  130. #endif
  131. unsigned int force_cpei_retarget = CPEI_OVERRIDE_DEFAULT;
  132. static int __init
  133. cmdl_force_cpei(char *str)
  134. {
  135. int value=0;
  136. get_option (&str, &value);
  137. force_cpei_retarget = value;
  138. return 1;
  139. }
  140. __setup("force_cpei=", cmdl_force_cpei);
  141. static int __init
  142. nointroute (char *str)
  143. {
  144. no_int_routing = 1;
  145. printk ("no_int_routing on\n");
  146. return 1;
  147. }
  148. __setup("nointroute", nointroute);
  149. static void fix_b0_for_bsp(void)
  150. {
  151. #ifdef CONFIG_HOTPLUG_CPU
  152. int cpuid;
  153. static int fix_bsp_b0 = 1;
  154. cpuid = smp_processor_id();
  155. /*
  156. * Cache the b0 value on the first AP that comes up
  157. */
  158. if (!(fix_bsp_b0 && cpuid))
  159. return;
  160. sal_boot_rendez_state[0].br[0] = sal_boot_rendez_state[cpuid].br[0];
  161. printk ("Fixed BSP b0 value from CPU %d\n", cpuid);
  162. fix_bsp_b0 = 0;
  163. #endif
  164. }
  165. void
  166. sync_master (void *arg)
  167. {
  168. unsigned long flags, i;
  169. go[MASTER] = 0;
  170. local_irq_save(flags);
  171. {
  172. for (i = 0; i < NUM_ROUNDS*NUM_ITERS; ++i) {
  173. while (!go[MASTER])
  174. cpu_relax();
  175. go[MASTER] = 0;
  176. go[SLAVE] = ia64_get_itc();
  177. }
  178. }
  179. local_irq_restore(flags);
  180. }
  181. /*
  182. * Return the number of cycles by which our itc differs from the itc on the master
  183. * (time-keeper) CPU. A positive number indicates our itc is ahead of the master,
  184. * negative that it is behind.
  185. */
  186. static inline long
  187. get_delta (long *rt, long *master)
  188. {
  189. unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
  190. unsigned long tcenter, t0, t1, tm;
  191. long i;
  192. for (i = 0; i < NUM_ITERS; ++i) {
  193. t0 = ia64_get_itc();
  194. go[MASTER] = 1;
  195. while (!(tm = go[SLAVE]))
  196. cpu_relax();
  197. go[SLAVE] = 0;
  198. t1 = ia64_get_itc();
  199. if (t1 - t0 < best_t1 - best_t0)
  200. best_t0 = t0, best_t1 = t1, best_tm = tm;
  201. }
  202. *rt = best_t1 - best_t0;
  203. *master = best_tm - best_t0;
  204. /* average best_t0 and best_t1 without overflow: */
  205. tcenter = (best_t0/2 + best_t1/2);
  206. if (best_t0 % 2 + best_t1 % 2 == 2)
  207. ++tcenter;
  208. return tcenter - best_tm;
  209. }
  210. /*
  211. * Synchronize ar.itc of the current (slave) CPU with the ar.itc of the MASTER CPU
  212. * (normally the time-keeper CPU). We use a closed loop to eliminate the possibility of
  213. * unaccounted-for errors (such as getting a machine check in the middle of a calibration
  214. * step). The basic idea is for the slave to ask the master what itc value it has and to
  215. * read its own itc before and after the master responds. Each iteration gives us three
  216. * timestamps:
  217. *
  218. * slave master
  219. *
  220. * t0 ---\
  221. * ---\
  222. * --->
  223. * tm
  224. * /---
  225. * /---
  226. * t1 <---
  227. *
  228. *
  229. * The goal is to adjust the slave's ar.itc such that tm falls exactly half-way between t0
  230. * and t1. If we achieve this, the clocks are synchronized provided the interconnect
  231. * between the slave and the master is symmetric. Even if the interconnect were
  232. * asymmetric, we would still know that the synchronization error is smaller than the
  233. * roundtrip latency (t0 - t1).
  234. *
  235. * When the interconnect is quiet and symmetric, this lets us synchronize the itc to
  236. * within one or two cycles. However, we can only *guarantee* that the synchronization is
  237. * accurate to within a round-trip time, which is typically in the range of several
  238. * hundred cycles (e.g., ~500 cycles). In practice, this means that the itc's are usually
  239. * almost perfectly synchronized, but we shouldn't assume that the accuracy is much better
  240. * than half a micro second or so.
  241. */
  242. void
  243. ia64_sync_itc (unsigned int master)
  244. {
  245. long i, delta, adj, adjust_latency = 0, done = 0;
  246. unsigned long flags, rt, master_time_stamp, bound;
  247. #if DEBUG_ITC_SYNC
  248. struct {
  249. long rt; /* roundtrip time */
  250. long master; /* master's timestamp */
  251. long diff; /* difference between midpoint and master's timestamp */
  252. long lat; /* estimate of itc adjustment latency */
  253. } t[NUM_ROUNDS];
  254. #endif
  255. /*
  256. * Make sure local timer ticks are disabled while we sync. If
  257. * they were enabled, we'd have to worry about nasty issues
  258. * like setting the ITC ahead of (or a long time before) the
  259. * next scheduled tick.
  260. */
  261. BUG_ON((ia64_get_itv() & (1 << 16)) == 0);
  262. go[MASTER] = 1;
  263. if (smp_call_function_single(master, sync_master, NULL, 0) < 0) {
  264. printk(KERN_ERR "sync_itc: failed to get attention of CPU %u!\n", master);
  265. return;
  266. }
  267. while (go[MASTER])
  268. cpu_relax(); /* wait for master to be ready */
  269. spin_lock_irqsave(&itc_sync_lock, flags);
  270. {
  271. for (i = 0; i < NUM_ROUNDS; ++i) {
  272. delta = get_delta(&rt, &master_time_stamp);
  273. if (delta == 0) {
  274. done = 1; /* let's lock on to this... */
  275. bound = rt;
  276. }
  277. if (!done) {
  278. if (i > 0) {
  279. adjust_latency += -delta;
  280. adj = -delta + adjust_latency/4;
  281. } else
  282. adj = -delta;
  283. ia64_set_itc(ia64_get_itc() + adj);
  284. }
  285. #if DEBUG_ITC_SYNC
  286. t[i].rt = rt;
  287. t[i].master = master_time_stamp;
  288. t[i].diff = delta;
  289. t[i].lat = adjust_latency/4;
  290. #endif
  291. }
  292. }
  293. spin_unlock_irqrestore(&itc_sync_lock, flags);
  294. #if DEBUG_ITC_SYNC
  295. for (i = 0; i < NUM_ROUNDS; ++i)
  296. printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
  297. t[i].rt, t[i].master, t[i].diff, t[i].lat);
  298. #endif
  299. printk(KERN_INFO "CPU %d: synchronized ITC with CPU %u (last diff %ld cycles, "
  300. "maxerr %lu cycles)\n", smp_processor_id(), master, delta, rt);
  301. }
  302. /*
  303. * Ideally sets up per-cpu profiling hooks. Doesn't do much now...
  304. */
  305. static inline void __devinit
  306. smp_setup_percpu_timer (void)
  307. {
  308. }
  309. static void __cpuinit
  310. smp_callin (void)
  311. {
  312. int cpuid, phys_id, itc_master;
  313. struct cpuinfo_ia64 *last_cpuinfo, *this_cpuinfo;
  314. extern void ia64_init_itm(void);
  315. extern volatile int time_keeper_id;
  316. #ifdef CONFIG_PERFMON
  317. extern void pfm_init_percpu(void);
  318. #endif
  319. cpuid = smp_processor_id();
  320. phys_id = hard_smp_processor_id();
  321. itc_master = time_keeper_id;
  322. if (cpu_online(cpuid)) {
  323. printk(KERN_ERR "huh, phys CPU#0x%x, CPU#0x%x already present??\n",
  324. phys_id, cpuid);
  325. BUG();
  326. }
  327. fix_b0_for_bsp();
  328. ipi_call_lock_irq();
  329. spin_lock(&vector_lock);
  330. /* Setup the per cpu irq handling data structures */
  331. __setup_vector_irq(cpuid);
  332. notify_cpu_starting(cpuid);
  333. cpu_set(cpuid, cpu_online_map);
  334. per_cpu(cpu_state, cpuid) = CPU_ONLINE;
  335. spin_unlock(&vector_lock);
  336. ipi_call_unlock_irq();
  337. smp_setup_percpu_timer();
  338. ia64_mca_cmc_vector_setup(); /* Setup vector on AP */
  339. #ifdef CONFIG_PERFMON
  340. pfm_init_percpu();
  341. #endif
  342. local_irq_enable();
  343. if (!(sal_platform_features & IA64_SAL_PLATFORM_FEATURE_ITC_DRIFT)) {
  344. /*
  345. * Synchronize the ITC with the BP. Need to do this after irqs are
  346. * enabled because ia64_sync_itc() calls smp_call_function_single(), which
  347. * calls spin_unlock_bh(), which calls spin_unlock_bh(), which calls
  348. * local_bh_enable(), which bugs out if irqs are not enabled...
  349. */
  350. Dprintk("Going to syncup ITC with ITC Master.\n");
  351. ia64_sync_itc(itc_master);
  352. }
  353. /*
  354. * Get our bogomips.
  355. */
  356. ia64_init_itm();
  357. /*
  358. * Delay calibration can be skipped if new processor is identical to the
  359. * previous processor.
  360. */
  361. last_cpuinfo = cpu_data(cpuid - 1);
  362. this_cpuinfo = local_cpu_data;
  363. if (last_cpuinfo->itc_freq != this_cpuinfo->itc_freq ||
  364. last_cpuinfo->proc_freq != this_cpuinfo->proc_freq ||
  365. last_cpuinfo->features != this_cpuinfo->features ||
  366. last_cpuinfo->revision != this_cpuinfo->revision ||
  367. last_cpuinfo->family != this_cpuinfo->family ||
  368. last_cpuinfo->archrev != this_cpuinfo->archrev ||
  369. last_cpuinfo->model != this_cpuinfo->model)
  370. calibrate_delay();
  371. local_cpu_data->loops_per_jiffy = loops_per_jiffy;
  372. #ifdef CONFIG_IA32_SUPPORT
  373. ia32_gdt_init();
  374. #endif
  375. /*
  376. * Allow the master to continue.
  377. */
  378. cpu_set(cpuid, cpu_callin_map);
  379. Dprintk("Stack on CPU %d at about %p\n",cpuid, &cpuid);
  380. }
  381. /*
  382. * Activate a secondary processor. head.S calls this.
  383. */
  384. int __cpuinit
  385. start_secondary (void *unused)
  386. {
  387. /* Early console may use I/O ports */
  388. ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase));
  389. #ifndef CONFIG_PRINTK_TIME
  390. Dprintk("start_secondary: starting CPU 0x%x\n", hard_smp_processor_id());
  391. #endif
  392. efi_map_pal_code();
  393. cpu_init();
  394. preempt_disable();
  395. smp_callin();
  396. cpu_idle();
  397. return 0;
  398. }
  399. struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
  400. {
  401. return NULL;
  402. }
  403. struct create_idle {
  404. struct work_struct work;
  405. struct task_struct *idle;
  406. struct completion done;
  407. int cpu;
  408. };
  409. void __cpuinit
  410. do_fork_idle(struct work_struct *work)
  411. {
  412. struct create_idle *c_idle =
  413. container_of(work, struct create_idle, work);
  414. c_idle->idle = fork_idle(c_idle->cpu);
  415. complete(&c_idle->done);
  416. }
  417. static int __cpuinit
  418. do_boot_cpu (int sapicid, int cpu)
  419. {
  420. int timeout;
  421. struct create_idle c_idle = {
  422. .work = __WORK_INITIALIZER(c_idle.work, do_fork_idle),
  423. .cpu = cpu,
  424. .done = COMPLETION_INITIALIZER(c_idle.done),
  425. };
  426. c_idle.idle = get_idle_for_cpu(cpu);
  427. if (c_idle.idle) {
  428. init_idle(c_idle.idle, cpu);
  429. goto do_rest;
  430. }
  431. /*
  432. * We can't use kernel_thread since we must avoid to reschedule the child.
  433. */
  434. if (!keventd_up() || current_is_keventd())
  435. c_idle.work.func(&c_idle.work);
  436. else {
  437. schedule_work(&c_idle.work);
  438. wait_for_completion(&c_idle.done);
  439. }
  440. if (IS_ERR(c_idle.idle))
  441. panic("failed fork for CPU %d", cpu);
  442. set_idle_for_cpu(cpu, c_idle.idle);
  443. do_rest:
  444. task_for_booting_cpu = c_idle.idle;
  445. Dprintk("Sending wakeup vector %lu to AP 0x%x/0x%x.\n", ap_wakeup_vector, cpu, sapicid);
  446. set_brendez_area(cpu);
  447. platform_send_ipi(cpu, ap_wakeup_vector, IA64_IPI_DM_INT, 0);
  448. /*
  449. * Wait 10s total for the AP to start
  450. */
  451. Dprintk("Waiting on callin_map ...");
  452. for (timeout = 0; timeout < 100000; timeout++) {
  453. if (cpu_isset(cpu, cpu_callin_map))
  454. break; /* It has booted */
  455. udelay(100);
  456. }
  457. Dprintk("\n");
  458. if (!cpu_isset(cpu, cpu_callin_map)) {
  459. printk(KERN_ERR "Processor 0x%x/0x%x is stuck.\n", cpu, sapicid);
  460. ia64_cpu_to_sapicid[cpu] = -1;
  461. cpu_clear(cpu, cpu_online_map); /* was set in smp_callin() */
  462. return -EINVAL;
  463. }
  464. return 0;
  465. }
  466. static int __init
  467. decay (char *str)
  468. {
  469. int ticks;
  470. get_option (&str, &ticks);
  471. return 1;
  472. }
  473. __setup("decay=", decay);
  474. /*
  475. * Initialize the logical CPU number to SAPICID mapping
  476. */
  477. void __init
  478. smp_build_cpu_map (void)
  479. {
  480. int sapicid, cpu, i;
  481. int boot_cpu_id = hard_smp_processor_id();
  482. for (cpu = 0; cpu < NR_CPUS; cpu++) {
  483. ia64_cpu_to_sapicid[cpu] = -1;
  484. }
  485. ia64_cpu_to_sapicid[0] = boot_cpu_id;
  486. cpus_clear(cpu_present_map);
  487. set_cpu_present(0, true);
  488. set_cpu_possible(0, true);
  489. for (cpu = 1, i = 0; i < smp_boot_data.cpu_count; i++) {
  490. sapicid = smp_boot_data.cpu_phys_id[i];
  491. if (sapicid == boot_cpu_id)
  492. continue;
  493. set_cpu_present(cpu, true);
  494. set_cpu_possible(cpu, true);
  495. ia64_cpu_to_sapicid[cpu] = sapicid;
  496. cpu++;
  497. }
  498. }
  499. /*
  500. * Cycle through the APs sending Wakeup IPIs to boot each.
  501. */
  502. void __init
  503. smp_prepare_cpus (unsigned int max_cpus)
  504. {
  505. int boot_cpu_id = hard_smp_processor_id();
  506. /*
  507. * Initialize the per-CPU profiling counter/multiplier
  508. */
  509. smp_setup_percpu_timer();
  510. /*
  511. * We have the boot CPU online for sure.
  512. */
  513. cpu_set(0, cpu_online_map);
  514. cpu_set(0, cpu_callin_map);
  515. local_cpu_data->loops_per_jiffy = loops_per_jiffy;
  516. ia64_cpu_to_sapicid[0] = boot_cpu_id;
  517. printk(KERN_INFO "Boot processor id 0x%x/0x%x\n", 0, boot_cpu_id);
  518. current_thread_info()->cpu = 0;
  519. /*
  520. * If SMP should be disabled, then really disable it!
  521. */
  522. if (!max_cpus) {
  523. printk(KERN_INFO "SMP mode deactivated.\n");
  524. init_cpu_online(cpumask_of(0));
  525. init_cpu_present(cpumask_of(0));
  526. init_cpu_possible(cpumask_of(0));
  527. return;
  528. }
  529. }
  530. void __devinit smp_prepare_boot_cpu(void)
  531. {
  532. cpu_set(smp_processor_id(), cpu_online_map);
  533. cpu_set(smp_processor_id(), cpu_callin_map);
  534. per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
  535. paravirt_post_smp_prepare_boot_cpu();
  536. }
  537. #ifdef CONFIG_HOTPLUG_CPU
  538. static inline void
  539. clear_cpu_sibling_map(int cpu)
  540. {
  541. int i;
  542. for_each_cpu_mask(i, per_cpu(cpu_sibling_map, cpu))
  543. cpu_clear(cpu, per_cpu(cpu_sibling_map, i));
  544. for_each_cpu_mask(i, cpu_core_map[cpu])
  545. cpu_clear(cpu, cpu_core_map[i]);
  546. per_cpu(cpu_sibling_map, cpu) = cpu_core_map[cpu] = CPU_MASK_NONE;
  547. }
  548. static void
  549. remove_siblinginfo(int cpu)
  550. {
  551. int last = 0;
  552. if (cpu_data(cpu)->threads_per_core == 1 &&
  553. cpu_data(cpu)->cores_per_socket == 1) {
  554. cpu_clear(cpu, cpu_core_map[cpu]);
  555. cpu_clear(cpu, per_cpu(cpu_sibling_map, cpu));
  556. return;
  557. }
  558. last = (cpus_weight(cpu_core_map[cpu]) == 1 ? 1 : 0);
  559. /* remove it from all sibling map's */
  560. clear_cpu_sibling_map(cpu);
  561. }
  562. extern void fixup_irqs(void);
  563. int migrate_platform_irqs(unsigned int cpu)
  564. {
  565. int new_cpei_cpu;
  566. irq_desc_t *desc = NULL;
  567. const struct cpumask *mask;
  568. int retval = 0;
  569. /*
  570. * dont permit CPEI target to removed.
  571. */
  572. if (cpe_vector > 0 && is_cpu_cpei_target(cpu)) {
  573. printk ("CPU (%d) is CPEI Target\n", cpu);
  574. if (can_cpei_retarget()) {
  575. /*
  576. * Now re-target the CPEI to a different processor
  577. */
  578. new_cpei_cpu = any_online_cpu(cpu_online_map);
  579. mask = cpumask_of(new_cpei_cpu);
  580. set_cpei_target_cpu(new_cpei_cpu);
  581. desc = irq_desc + ia64_cpe_irq;
  582. /*
  583. * Switch for now, immediately, we need to do fake intr
  584. * as other interrupts, but need to study CPEI behaviour with
  585. * polling before making changes.
  586. */
  587. if (desc) {
  588. desc->chip->disable(ia64_cpe_irq);
  589. desc->chip->set_affinity(ia64_cpe_irq, mask);
  590. desc->chip->enable(ia64_cpe_irq);
  591. printk ("Re-targetting CPEI to cpu %d\n", new_cpei_cpu);
  592. }
  593. }
  594. if (!desc) {
  595. printk ("Unable to retarget CPEI, offline cpu [%d] failed\n", cpu);
  596. retval = -EBUSY;
  597. }
  598. }
  599. return retval;
  600. }
  601. /* must be called with cpucontrol mutex held */
  602. int __cpu_disable(void)
  603. {
  604. int cpu = smp_processor_id();
  605. /*
  606. * dont permit boot processor for now
  607. */
  608. if (cpu == 0 && !bsp_remove_ok) {
  609. printk ("Your platform does not support removal of BSP\n");
  610. return (-EBUSY);
  611. }
  612. if (ia64_platform_is("sn2")) {
  613. if (!sn_cpu_disable_allowed(cpu))
  614. return -EBUSY;
  615. }
  616. cpu_clear(cpu, cpu_online_map);
  617. if (migrate_platform_irqs(cpu)) {
  618. cpu_set(cpu, cpu_online_map);
  619. return -EBUSY;
  620. }
  621. remove_siblinginfo(cpu);
  622. fixup_irqs();
  623. local_flush_tlb_all();
  624. cpu_clear(cpu, cpu_callin_map);
  625. return 0;
  626. }
  627. void __cpu_die(unsigned int cpu)
  628. {
  629. unsigned int i;
  630. for (i = 0; i < 100; i++) {
  631. /* They ack this in play_dead by setting CPU_DEAD */
  632. if (per_cpu(cpu_state, cpu) == CPU_DEAD)
  633. {
  634. printk ("CPU %d is now offline\n", cpu);
  635. return;
  636. }
  637. msleep(100);
  638. }
  639. printk(KERN_ERR "CPU %u didn't die...\n", cpu);
  640. }
  641. #endif /* CONFIG_HOTPLUG_CPU */
  642. void
  643. smp_cpus_done (unsigned int dummy)
  644. {
  645. int cpu;
  646. unsigned long bogosum = 0;
  647. /*
  648. * Allow the user to impress friends.
  649. */
  650. for_each_online_cpu(cpu) {
  651. bogosum += cpu_data(cpu)->loops_per_jiffy;
  652. }
  653. printk(KERN_INFO "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
  654. (int)num_online_cpus(), bogosum/(500000/HZ), (bogosum/(5000/HZ))%100);
  655. }
  656. static inline void __devinit
  657. set_cpu_sibling_map(int cpu)
  658. {
  659. int i;
  660. for_each_online_cpu(i) {
  661. if ((cpu_data(cpu)->socket_id == cpu_data(i)->socket_id)) {
  662. cpu_set(i, cpu_core_map[cpu]);
  663. cpu_set(cpu, cpu_core_map[i]);
  664. if (cpu_data(cpu)->core_id == cpu_data(i)->core_id) {
  665. cpu_set(i, per_cpu(cpu_sibling_map, cpu));
  666. cpu_set(cpu, per_cpu(cpu_sibling_map, i));
  667. }
  668. }
  669. }
  670. }
  671. int __cpuinit
  672. __cpu_up (unsigned int cpu)
  673. {
  674. int ret;
  675. int sapicid;
  676. sapicid = ia64_cpu_to_sapicid[cpu];
  677. if (sapicid == -1)
  678. return -EINVAL;
  679. /*
  680. * Already booted cpu? not valid anymore since we dont
  681. * do idle loop tightspin anymore.
  682. */
  683. if (cpu_isset(cpu, cpu_callin_map))
  684. return -EINVAL;
  685. per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
  686. /* Processor goes to start_secondary(), sets online flag */
  687. ret = do_boot_cpu(sapicid, cpu);
  688. if (ret < 0)
  689. return ret;
  690. if (cpu_data(cpu)->threads_per_core == 1 &&
  691. cpu_data(cpu)->cores_per_socket == 1) {
  692. cpu_set(cpu, per_cpu(cpu_sibling_map, cpu));
  693. cpu_set(cpu, cpu_core_map[cpu]);
  694. return 0;
  695. }
  696. set_cpu_sibling_map(cpu);
  697. return 0;
  698. }
  699. /*
  700. * Assume that CPUs have been discovered by some platform-dependent interface. For
  701. * SoftSDV/Lion, that would be ACPI.
  702. *
  703. * Setup of the IPI irq handler is done in irq.c:init_IRQ_SMP().
  704. */
  705. void __init
  706. init_smp_config(void)
  707. {
  708. struct fptr {
  709. unsigned long fp;
  710. unsigned long gp;
  711. } *ap_startup;
  712. long sal_ret;
  713. /* Tell SAL where to drop the APs. */
  714. ap_startup = (struct fptr *) start_ap;
  715. sal_ret = ia64_sal_set_vectors(SAL_VECTOR_OS_BOOT_RENDEZ,
  716. ia64_tpa(ap_startup->fp), ia64_tpa(ap_startup->gp), 0, 0, 0, 0);
  717. if (sal_ret < 0)
  718. printk(KERN_ERR "SMP: Can't set SAL AP Boot Rendezvous: %s\n",
  719. ia64_sal_strerror(sal_ret));
  720. }
  721. /*
  722. * identify_siblings(cpu) gets called from identify_cpu. This populates the
  723. * information related to logical execution units in per_cpu_data structure.
  724. */
  725. void __devinit
  726. identify_siblings(struct cpuinfo_ia64 *c)
  727. {
  728. s64 status;
  729. u16 pltid;
  730. pal_logical_to_physical_t info;
  731. status = ia64_pal_logical_to_phys(-1, &info);
  732. if (status != PAL_STATUS_SUCCESS) {
  733. if (status != PAL_STATUS_UNIMPLEMENTED) {
  734. printk(KERN_ERR
  735. "ia64_pal_logical_to_phys failed with %ld\n",
  736. status);
  737. return;
  738. }
  739. info.overview_ppid = 0;
  740. info.overview_cpp = 1;
  741. info.overview_tpc = 1;
  742. }
  743. status = ia64_sal_physical_id_info(&pltid);
  744. if (status != PAL_STATUS_SUCCESS) {
  745. if (status != PAL_STATUS_UNIMPLEMENTED)
  746. printk(KERN_ERR
  747. "ia64_sal_pltid failed with %ld\n",
  748. status);
  749. return;
  750. }
  751. c->socket_id = (pltid << 8) | info.overview_ppid;
  752. if (info.overview_cpp == 1 && info.overview_tpc == 1)
  753. return;
  754. c->cores_per_socket = info.overview_cpp;
  755. c->threads_per_core = info.overview_tpc;
  756. c->num_log = info.overview_num_log;
  757. c->core_id = info.log1_cid;
  758. c->thread_id = info.log1_tid;
  759. }
  760. /*
  761. * returns non zero, if multi-threading is enabled
  762. * on at least one physical package. Due to hotplug cpu
  763. * and (maxcpus=), all threads may not necessarily be enabled
  764. * even though the processor supports multi-threading.
  765. */
  766. int is_multithreading_enabled(void)
  767. {
  768. int i, j;
  769. for_each_present_cpu(i) {
  770. for_each_present_cpu(j) {
  771. if (j == i)
  772. continue;
  773. if ((cpu_data(j)->socket_id == cpu_data(i)->socket_id)) {
  774. if (cpu_data(j)->core_id == cpu_data(i)->core_id)
  775. return 1;
  776. }
  777. }
  778. }
  779. return 0;
  780. }
  781. EXPORT_SYMBOL_GPL(is_multithreading_enabled);