pio.c 10 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472
  1. /*
  2. * Atmel PIO2 Port Multiplexer support
  3. *
  4. * Copyright (C) 2004-2006 Atmel Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/debugfs.h>
  12. #include <linux/fs.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/irq.h>
  15. #include <asm/gpio.h>
  16. #include <asm/io.h>
  17. #include <mach/portmux.h>
  18. #include "pio.h"
  19. #define MAX_NR_PIO_DEVICES 8
  20. struct pio_device {
  21. struct gpio_chip chip;
  22. void __iomem *regs;
  23. const struct platform_device *pdev;
  24. struct clk *clk;
  25. u32 pinmux_mask;
  26. char name[8];
  27. };
  28. static struct pio_device pio_dev[MAX_NR_PIO_DEVICES];
  29. static struct pio_device *gpio_to_pio(unsigned int gpio)
  30. {
  31. struct pio_device *pio;
  32. unsigned int index;
  33. index = gpio >> 5;
  34. if (index >= MAX_NR_PIO_DEVICES)
  35. return NULL;
  36. pio = &pio_dev[index];
  37. if (!pio->regs)
  38. return NULL;
  39. return pio;
  40. }
  41. /* Pin multiplexing API */
  42. static DEFINE_SPINLOCK(pio_lock);
  43. void __init at32_select_periph(unsigned int port, u32 pin_mask,
  44. unsigned int periph, unsigned long flags)
  45. {
  46. struct pio_device *pio;
  47. /* assign and verify pio */
  48. pio = gpio_to_pio(port);
  49. if (unlikely(!pio)) {
  50. printk(KERN_WARNING "pio: invalid port %u\n", port);
  51. goto fail;
  52. }
  53. /* Test if any of the requested pins is already muxed */
  54. spin_lock(&pio_lock);
  55. if (unlikely(pio->pinmux_mask & pin_mask)) {
  56. printk(KERN_WARNING "%s: pin(s) busy (requested 0x%x, busy 0x%x)\n",
  57. pio->name, pin_mask, pio->pinmux_mask & pin_mask);
  58. spin_unlock(&pio_lock);
  59. goto fail;
  60. }
  61. pio->pinmux_mask |= pin_mask;
  62. /* enable pull ups */
  63. pio_writel(pio, PUER, pin_mask);
  64. /* select either peripheral A or B */
  65. if (periph)
  66. pio_writel(pio, BSR, pin_mask);
  67. else
  68. pio_writel(pio, ASR, pin_mask);
  69. /* enable peripheral control */
  70. pio_writel(pio, PDR, pin_mask);
  71. /* Disable pull ups if not requested. */
  72. if (!(flags & AT32_GPIOF_PULLUP))
  73. pio_writel(pio, PUDR, pin_mask);
  74. spin_unlock(&pio_lock);
  75. return;
  76. fail:
  77. dump_stack();
  78. }
  79. void __init at32_select_gpio(unsigned int pin, unsigned long flags)
  80. {
  81. struct pio_device *pio;
  82. unsigned int pin_index = pin & 0x1f;
  83. u32 mask = 1 << pin_index;
  84. pio = gpio_to_pio(pin);
  85. if (unlikely(!pio)) {
  86. printk("pio: invalid pin %u\n", pin);
  87. goto fail;
  88. }
  89. if (unlikely(test_and_set_bit(pin_index, &pio->pinmux_mask))) {
  90. printk("%s: pin %u is busy\n", pio->name, pin_index);
  91. goto fail;
  92. }
  93. if (flags & AT32_GPIOF_OUTPUT) {
  94. if (flags & AT32_GPIOF_HIGH)
  95. pio_writel(pio, SODR, mask);
  96. else
  97. pio_writel(pio, CODR, mask);
  98. if (flags & AT32_GPIOF_MULTIDRV)
  99. pio_writel(pio, MDER, mask);
  100. else
  101. pio_writel(pio, MDDR, mask);
  102. pio_writel(pio, PUDR, mask);
  103. pio_writel(pio, OER, mask);
  104. } else {
  105. if (flags & AT32_GPIOF_PULLUP)
  106. pio_writel(pio, PUER, mask);
  107. else
  108. pio_writel(pio, PUDR, mask);
  109. if (flags & AT32_GPIOF_DEGLITCH)
  110. pio_writel(pio, IFER, mask);
  111. else
  112. pio_writel(pio, IFDR, mask);
  113. pio_writel(pio, ODR, mask);
  114. }
  115. pio_writel(pio, PER, mask);
  116. return;
  117. fail:
  118. dump_stack();
  119. }
  120. /*
  121. * Undo a previous pin reservation. Will not affect the hardware
  122. * configuration.
  123. */
  124. void at32_deselect_pin(unsigned int pin)
  125. {
  126. struct pio_device *pio;
  127. unsigned int pin_index = pin & 0x1f;
  128. pio = gpio_to_pio(pin);
  129. if (unlikely(!pio)) {
  130. printk("pio: invalid pin %u\n", pin);
  131. dump_stack();
  132. return;
  133. }
  134. clear_bit(pin_index, &pio->pinmux_mask);
  135. }
  136. /* Reserve a pin, preventing anyone else from changing its configuration. */
  137. void __init at32_reserve_pin(unsigned int port, u32 pin_mask)
  138. {
  139. struct pio_device *pio;
  140. /* assign and verify pio */
  141. pio = gpio_to_pio(port);
  142. if (unlikely(!pio)) {
  143. printk(KERN_WARNING "pio: invalid port %u\n", port);
  144. goto fail;
  145. }
  146. /* Test if any of the requested pins is already muxed */
  147. spin_lock(&pio_lock);
  148. if (unlikely(pio->pinmux_mask & pin_mask)) {
  149. printk(KERN_WARNING "%s: pin(s) busy (req. 0x%x, busy 0x%x)\n",
  150. pio->name, pin_mask, pio->pinmux_mask & pin_mask);
  151. spin_unlock(&pio_lock);
  152. goto fail;
  153. }
  154. /* Reserve pins */
  155. pio->pinmux_mask |= pin_mask;
  156. spin_unlock(&pio_lock);
  157. return;
  158. fail:
  159. dump_stack();
  160. }
  161. /*--------------------------------------------------------------------------*/
  162. /* GPIO API */
  163. static int direction_input(struct gpio_chip *chip, unsigned offset)
  164. {
  165. struct pio_device *pio = container_of(chip, struct pio_device, chip);
  166. u32 mask = 1 << offset;
  167. if (!(pio_readl(pio, PSR) & mask))
  168. return -EINVAL;
  169. pio_writel(pio, ODR, mask);
  170. return 0;
  171. }
  172. static int gpio_get(struct gpio_chip *chip, unsigned offset)
  173. {
  174. struct pio_device *pio = container_of(chip, struct pio_device, chip);
  175. return (pio_readl(pio, PDSR) >> offset) & 1;
  176. }
  177. static void gpio_set(struct gpio_chip *chip, unsigned offset, int value);
  178. static int direction_output(struct gpio_chip *chip, unsigned offset, int value)
  179. {
  180. struct pio_device *pio = container_of(chip, struct pio_device, chip);
  181. u32 mask = 1 << offset;
  182. if (!(pio_readl(pio, PSR) & mask))
  183. return -EINVAL;
  184. gpio_set(chip, offset, value);
  185. pio_writel(pio, OER, mask);
  186. return 0;
  187. }
  188. static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  189. {
  190. struct pio_device *pio = container_of(chip, struct pio_device, chip);
  191. u32 mask = 1 << offset;
  192. if (value)
  193. pio_writel(pio, SODR, mask);
  194. else
  195. pio_writel(pio, CODR, mask);
  196. }
  197. /*--------------------------------------------------------------------------*/
  198. /* GPIO IRQ support */
  199. static void gpio_irq_mask(unsigned irq)
  200. {
  201. unsigned gpio = irq_to_gpio(irq);
  202. struct pio_device *pio = &pio_dev[gpio >> 5];
  203. pio_writel(pio, IDR, 1 << (gpio & 0x1f));
  204. }
  205. static void gpio_irq_unmask(unsigned irq)
  206. {
  207. unsigned gpio = irq_to_gpio(irq);
  208. struct pio_device *pio = &pio_dev[gpio >> 5];
  209. pio_writel(pio, IER, 1 << (gpio & 0x1f));
  210. }
  211. static int gpio_irq_type(unsigned irq, unsigned type)
  212. {
  213. if (type != IRQ_TYPE_EDGE_BOTH && type != IRQ_TYPE_NONE)
  214. return -EINVAL;
  215. return 0;
  216. }
  217. static struct irq_chip gpio_irqchip = {
  218. .name = "gpio",
  219. .mask = gpio_irq_mask,
  220. .unmask = gpio_irq_unmask,
  221. .set_type = gpio_irq_type,
  222. };
  223. static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
  224. {
  225. struct pio_device *pio = get_irq_chip_data(irq);
  226. unsigned gpio_irq;
  227. gpio_irq = (unsigned) get_irq_data(irq);
  228. for (;;) {
  229. u32 isr;
  230. struct irq_desc *d;
  231. /* ack pending GPIO interrupts */
  232. isr = pio_readl(pio, ISR) & pio_readl(pio, IMR);
  233. if (!isr)
  234. break;
  235. do {
  236. int i;
  237. i = ffs(isr) - 1;
  238. isr &= ~(1 << i);
  239. i += gpio_irq;
  240. d = &irq_desc[i];
  241. d->handle_irq(i, d);
  242. } while (isr);
  243. }
  244. }
  245. static void __init
  246. gpio_irq_setup(struct pio_device *pio, int irq, int gpio_irq)
  247. {
  248. unsigned i;
  249. set_irq_chip_data(irq, pio);
  250. set_irq_data(irq, (void *) gpio_irq);
  251. for (i = 0; i < 32; i++, gpio_irq++) {
  252. set_irq_chip_data(gpio_irq, pio);
  253. set_irq_chip_and_handler(gpio_irq, &gpio_irqchip,
  254. handle_simple_irq);
  255. }
  256. set_irq_chained_handler(irq, gpio_irq_handler);
  257. }
  258. /*--------------------------------------------------------------------------*/
  259. #ifdef CONFIG_DEBUG_FS
  260. #include <linux/seq_file.h>
  261. /*
  262. * This shows more info than the generic gpio dump code:
  263. * pullups, deglitching, open drain drive.
  264. */
  265. static void pio_bank_show(struct seq_file *s, struct gpio_chip *chip)
  266. {
  267. struct pio_device *pio = container_of(chip, struct pio_device, chip);
  268. u32 psr, osr, imr, pdsr, pusr, ifsr, mdsr;
  269. unsigned i;
  270. u32 mask;
  271. char bank;
  272. psr = pio_readl(pio, PSR);
  273. osr = pio_readl(pio, OSR);
  274. imr = pio_readl(pio, IMR);
  275. pdsr = pio_readl(pio, PDSR);
  276. pusr = pio_readl(pio, PUSR);
  277. ifsr = pio_readl(pio, IFSR);
  278. mdsr = pio_readl(pio, MDSR);
  279. bank = 'A' + pio->pdev->id;
  280. for (i = 0, mask = 1; i < 32; i++, mask <<= 1) {
  281. const char *label;
  282. label = gpiochip_is_requested(chip, i);
  283. if (!label && (imr & mask))
  284. label = "[irq]";
  285. if (!label)
  286. continue;
  287. seq_printf(s, " gpio-%-3d P%c%-2d (%-12s) %s %s %s",
  288. chip->base + i, bank, i,
  289. label,
  290. (osr & mask) ? "out" : "in ",
  291. (mask & pdsr) ? "hi" : "lo",
  292. (mask & pusr) ? " " : "up");
  293. if (ifsr & mask)
  294. seq_printf(s, " deglitch");
  295. if ((osr & mdsr) & mask)
  296. seq_printf(s, " open-drain");
  297. if (imr & mask)
  298. seq_printf(s, " irq-%d edge-both",
  299. gpio_to_irq(chip->base + i));
  300. seq_printf(s, "\n");
  301. }
  302. }
  303. #else
  304. #define pio_bank_show NULL
  305. #endif
  306. /*--------------------------------------------------------------------------*/
  307. static int __init pio_probe(struct platform_device *pdev)
  308. {
  309. struct pio_device *pio = NULL;
  310. int irq = platform_get_irq(pdev, 0);
  311. int gpio_irq_base = GPIO_IRQ_BASE + pdev->id * 32;
  312. BUG_ON(pdev->id >= MAX_NR_PIO_DEVICES);
  313. pio = &pio_dev[pdev->id];
  314. BUG_ON(!pio->regs);
  315. pio->chip.label = pio->name;
  316. pio->chip.base = pdev->id * 32;
  317. pio->chip.ngpio = 32;
  318. pio->chip.dev = &pdev->dev;
  319. pio->chip.owner = THIS_MODULE;
  320. pio->chip.direction_input = direction_input;
  321. pio->chip.get = gpio_get;
  322. pio->chip.direction_output = direction_output;
  323. pio->chip.set = gpio_set;
  324. pio->chip.dbg_show = pio_bank_show;
  325. gpiochip_add(&pio->chip);
  326. gpio_irq_setup(pio, irq, gpio_irq_base);
  327. platform_set_drvdata(pdev, pio);
  328. printk(KERN_DEBUG "%s: base 0x%p, irq %d chains %d..%d\n",
  329. pio->name, pio->regs, irq, gpio_irq_base, gpio_irq_base + 31);
  330. return 0;
  331. }
  332. static struct platform_driver pio_driver = {
  333. .driver = {
  334. .name = "pio",
  335. },
  336. };
  337. static int __init pio_init(void)
  338. {
  339. return platform_driver_probe(&pio_driver, pio_probe);
  340. }
  341. postcore_initcall(pio_init);
  342. void __init at32_init_pio(struct platform_device *pdev)
  343. {
  344. struct resource *regs;
  345. struct pio_device *pio;
  346. if (pdev->id > MAX_NR_PIO_DEVICES) {
  347. dev_err(&pdev->dev, "only %d PIO devices supported\n",
  348. MAX_NR_PIO_DEVICES);
  349. return;
  350. }
  351. pio = &pio_dev[pdev->id];
  352. snprintf(pio->name, sizeof(pio->name), "pio%d", pdev->id);
  353. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  354. if (!regs) {
  355. dev_err(&pdev->dev, "no mmio resource defined\n");
  356. return;
  357. }
  358. pio->clk = clk_get(&pdev->dev, "mck");
  359. if (IS_ERR(pio->clk))
  360. /*
  361. * This is a fatal error, but if we continue we might
  362. * be so lucky that we manage to initialize the
  363. * console and display this message...
  364. */
  365. dev_err(&pdev->dev, "no mck clock defined\n");
  366. else
  367. clk_enable(pio->clk);
  368. pio->pdev = pdev;
  369. pio->regs = ioremap(regs->start, regs->end - regs->start + 1);
  370. /* start with irqs disabled and acked */
  371. pio_writel(pio, IDR, ~0UL);
  372. (void) pio_readl(pio, ISR);
  373. }