intc.c 4.5 KB

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  1. /*
  2. * Copyright (C) 2006, 2008 Atmel Corporation
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. */
  8. #include <linux/clk.h>
  9. #include <linux/err.h>
  10. #include <linux/init.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/irq.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/sysdev.h>
  15. #include <asm/io.h>
  16. #include "intc.h"
  17. struct intc {
  18. void __iomem *regs;
  19. struct irq_chip chip;
  20. struct sys_device sysdev;
  21. #ifdef CONFIG_PM
  22. unsigned long suspend_ipr;
  23. unsigned long saved_ipr[64];
  24. #endif
  25. };
  26. extern struct platform_device at32_intc0_device;
  27. /*
  28. * TODO: We may be able to implement mask/unmask by setting IxM flags
  29. * in the status register.
  30. */
  31. static void intc_mask_irq(unsigned int irq)
  32. {
  33. }
  34. static void intc_unmask_irq(unsigned int irq)
  35. {
  36. }
  37. static struct intc intc0 = {
  38. .chip = {
  39. .name = "intc",
  40. .mask = intc_mask_irq,
  41. .unmask = intc_unmask_irq,
  42. },
  43. };
  44. /*
  45. * All interrupts go via intc at some point.
  46. */
  47. asmlinkage void do_IRQ(int level, struct pt_regs *regs)
  48. {
  49. struct irq_desc *desc;
  50. struct pt_regs *old_regs;
  51. unsigned int irq;
  52. unsigned long status_reg;
  53. local_irq_disable();
  54. old_regs = set_irq_regs(regs);
  55. irq_enter();
  56. irq = intc_readl(&intc0, INTCAUSE0 - 4 * level);
  57. desc = irq_desc + irq;
  58. desc->handle_irq(irq, desc);
  59. /*
  60. * Clear all interrupt level masks so that we may handle
  61. * interrupts during softirq processing. If this is a nested
  62. * interrupt, interrupts must stay globally disabled until we
  63. * return.
  64. */
  65. status_reg = sysreg_read(SR);
  66. status_reg &= ~(SYSREG_BIT(I0M) | SYSREG_BIT(I1M)
  67. | SYSREG_BIT(I2M) | SYSREG_BIT(I3M));
  68. sysreg_write(SR, status_reg);
  69. irq_exit();
  70. set_irq_regs(old_regs);
  71. }
  72. void __init init_IRQ(void)
  73. {
  74. extern void _evba(void);
  75. extern void irq_level0(void);
  76. struct resource *regs;
  77. struct clk *pclk;
  78. unsigned int i;
  79. u32 offset, readback;
  80. regs = platform_get_resource(&at32_intc0_device, IORESOURCE_MEM, 0);
  81. if (!regs) {
  82. printk(KERN_EMERG "intc: no mmio resource defined\n");
  83. goto fail;
  84. }
  85. pclk = clk_get(&at32_intc0_device.dev, "pclk");
  86. if (IS_ERR(pclk)) {
  87. printk(KERN_EMERG "intc: no clock defined\n");
  88. goto fail;
  89. }
  90. clk_enable(pclk);
  91. intc0.regs = ioremap(regs->start, regs->end - regs->start + 1);
  92. if (!intc0.regs) {
  93. printk(KERN_EMERG "intc: failed to map registers (0x%08lx)\n",
  94. (unsigned long)regs->start);
  95. goto fail;
  96. }
  97. /*
  98. * Initialize all interrupts to level 0 (lowest priority). The
  99. * priority level may be changed by calling
  100. * irq_set_priority().
  101. *
  102. */
  103. offset = (unsigned long)&irq_level0 - (unsigned long)&_evba;
  104. for (i = 0; i < NR_INTERNAL_IRQS; i++) {
  105. intc_writel(&intc0, INTPR0 + 4 * i, offset);
  106. readback = intc_readl(&intc0, INTPR0 + 4 * i);
  107. if (readback == offset)
  108. set_irq_chip_and_handler(i, &intc0.chip,
  109. handle_simple_irq);
  110. }
  111. /* Unmask all interrupt levels */
  112. sysreg_write(SR, (sysreg_read(SR)
  113. & ~(SR_I3M | SR_I2M | SR_I1M | SR_I0M)));
  114. return;
  115. fail:
  116. panic("Interrupt controller initialization failed!\n");
  117. }
  118. #ifdef CONFIG_PM
  119. void intc_set_suspend_handler(unsigned long offset)
  120. {
  121. intc0.suspend_ipr = offset;
  122. }
  123. static int intc_suspend(struct sys_device *sdev, pm_message_t state)
  124. {
  125. struct intc *intc = container_of(sdev, struct intc, sysdev);
  126. int i;
  127. if (unlikely(!irqs_disabled())) {
  128. pr_err("intc_suspend: called with interrupts enabled\n");
  129. return -EINVAL;
  130. }
  131. if (unlikely(!intc->suspend_ipr)) {
  132. pr_err("intc_suspend: suspend_ipr not initialized\n");
  133. return -EINVAL;
  134. }
  135. for (i = 0; i < 64; i++) {
  136. intc->saved_ipr[i] = intc_readl(intc, INTPR0 + 4 * i);
  137. intc_writel(intc, INTPR0 + 4 * i, intc->suspend_ipr);
  138. }
  139. return 0;
  140. }
  141. static int intc_resume(struct sys_device *sdev)
  142. {
  143. struct intc *intc = container_of(sdev, struct intc, sysdev);
  144. int i;
  145. WARN_ON(!irqs_disabled());
  146. for (i = 0; i < 64; i++)
  147. intc_writel(intc, INTPR0 + 4 * i, intc->saved_ipr[i]);
  148. return 0;
  149. }
  150. #else
  151. #define intc_suspend NULL
  152. #define intc_resume NULL
  153. #endif
  154. static struct sysdev_class intc_class = {
  155. .name = "intc",
  156. .suspend = intc_suspend,
  157. .resume = intc_resume,
  158. };
  159. static int __init intc_init_sysdev(void)
  160. {
  161. int ret;
  162. ret = sysdev_class_register(&intc_class);
  163. if (ret)
  164. return ret;
  165. intc0.sysdev.id = 0;
  166. intc0.sysdev.cls = &intc_class;
  167. ret = sysdev_register(&intc0.sysdev);
  168. return ret;
  169. }
  170. device_initcall(intc_init_sysdev);
  171. unsigned long intc_get_pending(unsigned int group)
  172. {
  173. return intc_readl(&intc0, INTREQ0 + 4 * group);
  174. }
  175. EXPORT_SYMBOL_GPL(intc_get_pending);