setup-sdhci.c 2.8 KB

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  1. /* linux/arch/arm/mach-s3c6410/setup-sdhci.c
  2. *
  3. * Copyright 2008 Simtec Electronics
  4. * Copyright 2008 Simtec Electronics
  5. * Ben Dooks <ben@simtec.co.uk>
  6. * http://armlinux.simtec.co.uk/
  7. *
  8. * S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC)
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/types.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/io.h>
  19. #include <linux/mmc/card.h>
  20. #include <linux/mmc/host.h>
  21. #include <mach/gpio.h>
  22. #include <plat/gpio-cfg.h>
  23. #include <plat/regs-sdhci.h>
  24. #include <plat/sdhci.h>
  25. /* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
  26. char *s3c6410_hsmmc_clksrcs[4] = {
  27. [0] = "hsmmc",
  28. [1] = "hsmmc",
  29. [2] = "mmc_bus",
  30. /* [3] = "48m", - note not succesfully used yet */
  31. };
  32. void s3c6410_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
  33. {
  34. unsigned int gpio;
  35. unsigned int end;
  36. end = S3C64XX_GPG(2 + width);
  37. /* Set all the necessary GPG pins to special-function 0 */
  38. for (gpio = S3C64XX_GPG(0); gpio < end; gpio++) {
  39. s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
  40. s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
  41. }
  42. s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
  43. s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(2));
  44. }
  45. void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
  46. void __iomem *r,
  47. struct mmc_ios *ios,
  48. struct mmc_card *card)
  49. {
  50. u32 ctrl2, ctrl3;
  51. /* don't need to alter anything acording to card-type */
  52. writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4);
  53. ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
  54. ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
  55. ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
  56. S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
  57. S3C_SDHCI_CTRL2_ENFBCLKRX |
  58. S3C_SDHCI_CTRL2_DFCNT_NONE |
  59. S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
  60. if (ios->clock < 25 * 1000000)
  61. ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
  62. S3C_SDHCI_CTRL3_FCSEL2 |
  63. S3C_SDHCI_CTRL3_FCSEL1 |
  64. S3C_SDHCI_CTRL3_FCSEL0);
  65. else
  66. ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
  67. printk(KERN_INFO "%s: CTRL 2=%08x, 3=%08x\n", __func__, ctrl2, ctrl3);
  68. writel(ctrl2, r + S3C_SDHCI_CONTROL2);
  69. writel(ctrl3, r + S3C_SDHCI_CONTROL3);
  70. }
  71. void s3c6410_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
  72. {
  73. unsigned int gpio;
  74. unsigned int end;
  75. end = S3C64XX_GPH(2 + width);
  76. /* Set all the necessary GPG pins to special-function 0 */
  77. for (gpio = S3C64XX_GPH(0); gpio < end; gpio++) {
  78. s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
  79. s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
  80. }
  81. s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
  82. s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(3));
  83. }