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board-pb11mp.h

board-pb11mp.h 8.6 KB
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  1. /*
    2. 

  2.  * arch/arm/mach-realview/include/mach/board-pb11mp.h
    3. 

  3.  *
    4. 

  4.  * Copyright (C) 2008 ARM Limited
    5. 

  5.  *
    6. 

  6.  * This program is free software; you can redistribute it and/or modify
    7. 

  7.  * it under the terms of the GNU General Public License version 2 as
    8. 

  8.  * published by the Free Software Foundation.
    9. 

  9.  *
    10. 

  10.  * This program is distributed in the hope that it will be useful,
    11. 

  11.  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    12. 

  12.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    13. 

  13.  * GNU General Public License for more details.
    14. 

  14.  *
    15. 

  15.  * You should have received a copy of the GNU General Public License
    16. 

  16.  * along with this program; if not, write to the Free Software
    17. 

  17.  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
    18. 

  18.  * MA 02110-1301, USA.
    19. 

  19.  */
    20. 

  20. 

  21. #ifndef __ASM_ARCH_BOARD_PB11MP_H
    22. 

  22. #define __ASM_ARCH_BOARD_PB11MP_H
    23. 

  23. 

  24. #include <mach/platform.h>
    25. 

  25. 

  26. /*
    27. 

  27.  * Peripheral addresses
    28. 

  28.  */
    29. 

  29. #define REALVIEW_PB11MP_UART0_BASE		0x10009000	/* UART 0 */
    30. 

  30. #define REALVIEW_PB11MP_UART1_BASE		0x1000A000	/* UART 1 */
    31. 

  31. #define REALVIEW_PB11MP_UART2_BASE		0x1000B000	/* UART 2 */
    32. 

  32. #define REALVIEW_PB11MP_UART3_BASE		0x1000C000	/* UART 3 */
    33. 

  33. #define REALVIEW_PB11MP_SSP_BASE		0x1000D000	/* Synchronous Serial Port */
    34. 

  34. #define REALVIEW_PB11MP_WATCHDOG0_BASE		0x1000F000	/* Watchdog 0 */
    35. 

  35. #define REALVIEW_PB11MP_WATCHDOG_BASE		0x10010000	/* watchdog interface */
    36. 

  36. #define REALVIEW_PB11MP_TIMER0_1_BASE		0x10011000	/* Timer 0 and 1 */
    37. 

  37. #define REALVIEW_PB11MP_TIMER2_3_BASE		0x10012000	/* Timer 2 and 3 */
    38. 

  38. #define REALVIEW_PB11MP_GPIO0_BASE		0x10013000	/* GPIO port 0 */
    39. 

  39. #define REALVIEW_PB11MP_RTC_BASE		0x10017000	/* Real Time Clock */
    40. 

  40. #define REALVIEW_PB11MP_TIMER4_5_BASE		0x10018000	/* Timer 4/5 */
    41. 

  41. #define REALVIEW_PB11MP_TIMER6_7_BASE		0x10019000	/* Timer 6/7 */
    42. 

  42. #define REALVIEW_PB11MP_SCTL_BASE		0x1001A000	/* System Controller */
    43. 

  43. #define REALVIEW_PB11MP_CLCD_BASE		0x10020000	/* CLCD */
    44. 

  44. #define REALVIEW_PB11MP_ONB_SRAM_BASE		0x10060000	/* On-board SRAM */
    45. 

  45. #define REALVIEW_PB11MP_DMC_BASE		0x100E0000	/* DMC configuration */
    46. 

  46. #define REALVIEW_PB11MP_SMC_BASE		0x100E1000	/* SMC configuration */
    47. 

  47. #define REALVIEW_PB11MP_CAN_BASE		0x100E2000	/* CAN bus */
    48. 

  48. #define REALVIEW_PB11MP_CF_BASE			0x18000000	/* Compact flash */
    49. 

  49. #define REALVIEW_PB11MP_CF_MEM_BASE		0x18003000	/* SMC for Compact flash */
    50. 

  50. #define REALVIEW_PB11MP_GIC_CPU_BASE		0x1E000000	/* Generic interrupt controller CPU interface */
    51. 

  51. #define REALVIEW_PB11MP_FLASH0_BASE		0x40000000
    52. 

  52. #define REALVIEW_PB11MP_FLASH0_SIZE		SZ_64M
    53. 

  53. #define REALVIEW_PB11MP_FLASH1_BASE		0x44000000
    54. 

  54. #define REALVIEW_PB11MP_FLASH1_SIZE		SZ_64M
    55. 

  55. #define REALVIEW_PB11MP_ETH_BASE		0x4E000000	/* Ethernet */
    56. 

  56. #define REALVIEW_PB11MP_USB_BASE		0x4F000000	/* USB */
    57. 

  57. #define REALVIEW_PB11MP_GIC_DIST_BASE		0x1E001000	/* Generic interrupt controller distributor */
    58. 

  58. #define REALVIEW_PB11MP_LT_BASE			0xC0000000	/* Logic Tile expansion */
    59. 

  59. #define REALVIEW_PB11MP_SDRAM6_BASE		0x70000000	/* SDRAM bank 6 256MB */
    60. 

  60. #define REALVIEW_PB11MP_SDRAM7_BASE		0x80000000	/* SDRAM bank 7 256MB */
    61. 

  61. 

  62. #define REALVIEW_PB11MP_SYS_PLD_CTRL1		0x74
    63. 

  63. 

  64. /*
    65. 

  65.  * PB11MPCore PCI regions
    66. 

  66.  */
    67. 

  67. #define REALVIEW_PB11MP_PCI_BASE		0x90040000	/* PCI-X Unit base */
    68. 

  68. #define REALVIEW_PB11MP_PCI_IO_BASE		0x90050000	/* IO Region on AHB */
    69. 

  69. #define REALVIEW_PB11MP_PCI_MEM_BASE		0xA0000000	/* MEM Region on AHB */
    70. 

  70. 

  71. #define REALVIEW_PB11MP_PCI_BASE_SIZE		0x10000		/* 16 Kb */
    72. 

  72. #define REALVIEW_PB11MP_PCI_IO_SIZE		0x1000		/* 4 Kb */
    73. 

  73. #define REALVIEW_PB11MP_PCI_MEM_SIZE		0x20000000	/* 512 MB */
    74. 

  74. 

  75. /*
    76. 

  76.  * Testchip peripheral and fpga gic regions
    77. 

  77.  */
    78. 

  78. #define REALVIEW_TC11MP_SCU_BASE		0x1F000000	/* IRQ, Test chip */
    79. 

  79. #define REALVIEW_TC11MP_GIC_CPU_BASE		0x1F000100	/* Test chip interrupt controller CPU interface */
    80. 

  80. #define REALVIEW_TC11MP_TWD_BASE		0x1F000600
    81. 

  81. #define REALVIEW_TC11MP_GIC_DIST_BASE		0x1F001000	/* Test chip interrupt controller distributor */
    82. 

  82. #define REALVIEW_TC11MP_L220_BASE		0x1F002000	/* L220 registers */
    83. 

  83. 

  84. /*
    85. 

  85.  * Irqs
    86. 

  86.  */
    87. 

  87. #define IRQ_TC11MP_GIC_START			32
    88. 

  88. #define IRQ_PB11MP_GIC_START			64
    89. 

  89. 

  90. /*
    91. 

  91.  * ARM11MPCore test chip interrupt sources (primary GIC on the test chip)
    92. 

  92.  */
    93. 

  93. #define IRQ_TC11MP_AACI		(IRQ_TC11MP_GIC_START + 0)
    94. 

  94. #define IRQ_TC11MP_TIMER0_1	(IRQ_TC11MP_GIC_START + 1)
    95. 

  95. #define IRQ_TC11MP_TIMER2_3	(IRQ_TC11MP_GIC_START + 2)
    96. 

  96. #define IRQ_TC11MP_USB		(IRQ_TC11MP_GIC_START + 3)
    97. 

  97. #define IRQ_TC11MP_UART0	(IRQ_TC11MP_GIC_START + 4)
    98. 

  98. #define IRQ_TC11MP_UART1	(IRQ_TC11MP_GIC_START + 5)
    99. 

  99. #define IRQ_TC11MP_RTC		(IRQ_TC11MP_GIC_START + 6)
    100. 

  100. #define IRQ_TC11MP_KMI0		(IRQ_TC11MP_GIC_START + 7)
    101. 

  101. #define IRQ_TC11MP_KMI1		(IRQ_TC11MP_GIC_START + 8)
    102. 

  102. #define IRQ_TC11MP_ETH		(IRQ_TC11MP_GIC_START + 9)
    103. 

  103. #define IRQ_TC11MP_PB_IRQ1	(IRQ_TC11MP_GIC_START + 10)		/* main GIC */
    104. 

  104. #define IRQ_TC11MP_PB_IRQ2	(IRQ_TC11MP_GIC_START + 11)		/* tile GIC */
    105. 

  105. #define IRQ_TC11MP_PB_FIQ1	(IRQ_TC11MP_GIC_START + 12)		/* main GIC */
    106. 

  106. #define IRQ_TC11MP_PB_FIQ2	(IRQ_TC11MP_GIC_START + 13)		/* tile GIC */
    107. 

  107. #define IRQ_TC11MP_MMCI0A	(IRQ_TC11MP_GIC_START + 14)
    108. 

  108. #define IRQ_TC11MP_MMCI0B	(IRQ_TC11MP_GIC_START + 15)
    109. 

  109. 

  110. #define IRQ_TC11MP_PMU_CPU0	(IRQ_TC11MP_GIC_START + 17)
    111. 

  111. #define IRQ_TC11MP_PMU_CPU1	(IRQ_TC11MP_GIC_START + 18)
    112. 

  112. #define IRQ_TC11MP_PMU_CPU2	(IRQ_TC11MP_GIC_START + 19)
    113. 

  113. #define IRQ_TC11MP_PMU_CPU3	(IRQ_TC11MP_GIC_START + 20)
    114. 

  114. #define IRQ_TC11MP_PMU_SCU0	(IRQ_TC11MP_GIC_START + 21)
    115. 

  115. #define IRQ_TC11MP_PMU_SCU1	(IRQ_TC11MP_GIC_START + 22)
    116. 

  116. #define IRQ_TC11MP_PMU_SCU2	(IRQ_TC11MP_GIC_START + 23)
    117. 

  117. #define IRQ_TC11MP_PMU_SCU3	(IRQ_TC11MP_GIC_START + 24)
    118. 

  118. #define IRQ_TC11MP_PMU_SCU4	(IRQ_TC11MP_GIC_START + 25)
    119. 

  119. #define IRQ_TC11MP_PMU_SCU5	(IRQ_TC11MP_GIC_START + 26)
    120. 

  120. #define IRQ_TC11MP_PMU_SCU6	(IRQ_TC11MP_GIC_START + 27)
    121. 

  121. #define IRQ_TC11MP_PMU_SCU7	(IRQ_TC11MP_GIC_START + 28)
    122. 

  122. 

  123. #define IRQ_TC11MP_L220_EVENT	(IRQ_TC11MP_GIC_START + 29)
    124. 

  124. #define IRQ_TC11MP_L220_SLAVE	(IRQ_TC11MP_GIC_START + 30)
    125. 

  125. #define IRQ_TC11MP_L220_DECODE	(IRQ_TC11MP_GIC_START + 31)
    126. 

  126. 

  127. /*
    128. 

  128.  * RealView PB11MPCore GIC interrupt sources (secondary GIC on the board)
    129. 

  129.  */
    130. 

  130. #define IRQ_PB11MP_WATCHDOG	(IRQ_PB11MP_GIC_START + 0)	/* Watchdog timer */
    131. 

  131. #define IRQ_PB11MP_SOFT		(IRQ_PB11MP_GIC_START + 1)	/* Software interrupt */
    132. 

  132. #define IRQ_PB11MP_COMMRx	(IRQ_PB11MP_GIC_START + 2)	/* Debug Comm Rx interrupt */
    133. 

  133. #define IRQ_PB11MP_COMMTx	(IRQ_PB11MP_GIC_START + 3)	/* Debug Comm Tx interrupt */
    134. 

  134. #define IRQ_PB11MP_GPIO0	(IRQ_PB11MP_GIC_START + 6)	/* GPIO 0 */
    135. 

  135. #define IRQ_PB11MP_GPIO1	(IRQ_PB11MP_GIC_START + 7)	/* GPIO 1 */
    136. 

  136. #define IRQ_PB11MP_GPIO2	(IRQ_PB11MP_GIC_START + 8)	/* GPIO 2 */
    137. 

  137. 								/* 9 reserved */
    138. 

  138. #define IRQ_PB11MP_RTC_GIC1	(IRQ_PB11MP_GIC_START + 10)	/* Real Time Clock */
    139. 

  139. #define IRQ_PB11MP_SSP		(IRQ_PB11MP_GIC_START + 11)	/* Synchronous Serial Port */
    140. 

  140. #define IRQ_PB11MP_UART0_GIC1	(IRQ_PB11MP_GIC_START + 12)	/* UART 0 on development chip */
    141. 

  141. #define IRQ_PB11MP_UART1_GIC1	(IRQ_PB11MP_GIC_START + 13)	/* UART 1 on development chip */
    142. 

  142. #define IRQ_PB11MP_UART2	(IRQ_PB11MP_GIC_START + 14)	/* UART 2 on development chip */
    143. 

  143. #define IRQ_PB11MP_UART3	(IRQ_PB11MP_GIC_START + 15)	/* UART 3 on development chip */
    144. 

  144. #define IRQ_PB11MP_SCI		(IRQ_PB11MP_GIC_START + 16)	/* Smart Card Interface */
    145. 

  145. #define IRQ_PB11MP_MMCI0A_GIC1	(IRQ_PB11MP_GIC_START + 17)	/* Multimedia Card 0A */
    146. 

  146. #define IRQ_PB11MP_MMCI0B_GIC1	(IRQ_PB11MP_GIC_START + 18)	/* Multimedia Card 0B */
    147. 

  147. #define IRQ_PB11MP_AACI_GIC1	(IRQ_PB11MP_GIC_START + 19)	/* Audio Codec */
    148. 

  148. #define IRQ_PB11MP_KMI0_GIC1	(IRQ_PB11MP_GIC_START + 20)	/* Keyboard/Mouse port 0 */
    149. 

  149. #define IRQ_PB11MP_KMI1_GIC1	(IRQ_PB11MP_GIC_START + 21)	/* Keyboard/Mouse port 1 */
    150. 

  150. #define IRQ_PB11MP_CHARLCD	(IRQ_PB11MP_GIC_START + 22)	/* Character LCD */
    151. 

  151. #define IRQ_PB11MP_CLCD		(IRQ_PB11MP_GIC_START + 23)	/* CLCD controller */
    152. 

  152. #define IRQ_PB11MP_DMAC		(IRQ_PB11MP_GIC_START + 24)	/* DMA controller */
    153. 

  153. #define IRQ_PB11MP_PWRFAIL	(IRQ_PB11MP_GIC_START + 25)	/* Power failure */
    154. 

  154. #define IRQ_PB11MP_PISMO	(IRQ_PB11MP_GIC_START + 26)	/* PISMO interface */
    155. 

  155. #define IRQ_PB11MP_DoC		(IRQ_PB11MP_GIC_START + 27)	/* Disk on Chip memory controller */
    156. 

  156. #define IRQ_PB11MP_ETH_GIC1	(IRQ_PB11MP_GIC_START + 28)	/* Ethernet controller */
    157. 

  157. #define IRQ_PB11MP_USB_GIC1	(IRQ_PB11MP_GIC_START + 29)	/* USB controller */
    158. 

  158. #define IRQ_PB11MP_TSPEN	(IRQ_PB11MP_GIC_START + 30)	/* Touchscreen pen */
    159. 

  159. #define IRQ_PB11MP_TSKPAD	(IRQ_PB11MP_GIC_START + 31)	/* Touchscreen keypad */
    160. 

  160. 

  161. #define IRQ_PB11MP_SMC		-1
    162. 

  162. #define IRQ_PB11MP_SCTL		-1
    163. 

  163. 

  164. #define NR_GIC_PB11MP		2
    165. 

  165. 

  166. /*
    167. 

  167.  * Only define NR_IRQS if less than NR_IRQS_PB11MP
    168. 

  168.  */
    169. 

  169. #define NR_IRQS_PB11MP		(IRQ_TC11MP_GIC_START + 96)
    170. 

  170. 

  171. #if defined(CONFIG_MACH_REALVIEW_PB11MP)
    172. 

  172. 

  173. #if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_PB11MP)
    174. 

  174. #undef NR_IRQS
    175. 

  175. #define NR_IRQS			NR_IRQS_PB11MP
    176. 

  176. #endif
    177. 

  177. 

  178. #if !defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_PB11MP)
    179. 

  179. #undef MAX_GIC_NR
    180. 

  180. #define MAX_GIC_NR		NR_GIC_PB11MP
    181. 

  181. #endif
    182. 

  182. 

  183. #endif	/* CONFIG_MACH_REALVIEW_PB11MP */
    184. 

  184. 

  185. #endif	/* __ASM_ARCH_BOARD_PB11MP_H */
    186.